54AC11112 TI | Alldatasheet

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54AC11112, 74AC11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS073A – JUNE 1989 – REVISED APRIL 1993 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Copyright  1993, Texas Instruments Incorporated 2–1

  • Flow-Through Architecture Optimizes PCB Layout
  • Center-Pin VCC and GND Configuration Minimizes High-Speed Switching Noise
  • EPIC  (Enhanced-Performance Implanted CMOS) 1-mm Process
  • 500-mA Typical Latch-Up Immunity at 125°C
  • ESD Protection Exceeds 2000 V, MIL STD-883C Method 3015
  • Package Options Include Plastic Small- Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs

description

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. The 54AC11112 is characterized for operation over the full military temperature range of –55°C to 125°C. The 74AC11112 is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each gate) INPUTS OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H LXXXL H L LXXX H /C0123H /C0123 H H ↓ LL Q O Q O H H ↓ HLH L H H ↓ LHL H H H ↓ H H Toggle H H H X X Q O Q O † This configuration is nonstable; that is, it will not persist when either PRE or CLR returns to its inactive (high) level. 54AC11112 ...J PACKAGE 74AC11112 ...D O R N PACKAGE (TOP VIEW) 54AC11112 . . . FK PACKAGE (TOP VIEW) NC – No internal connection 1PRE GND 2PRE 1CLK 1CLR VCC 2CLR 2CLK 3 2 1 20 19 91 0 1 1 1 2 1 3 2CLK NC 2PRE NC 1PRE 1CLK NC 2Q 2CLR GND NC V 1CLR CC EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

54AC11112, 74AC11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS073A – JUNE 1989 – REVISED APRIL 1993 POST OFFICE BOX 655303 • DALLAS, TEXAS 752652–2 logic symbol† C1 3 S R S R 1PRE 1CLK 1CLR 2PRE 2CLK 2CLR † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. logic diagram, each flip-flop (positive logic) TGTG TG C C C C Q C C PRE J K CLK CLR C C C C Q TG absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

54AC11112, 74AC11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS073A – JUNE 1989 – REVISED APRIL 1993 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–3 recommended operating conditions 54AC11112 74AC11112 UNIT MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 3 5 5.5 3 5 5.5 V VCC = 3 V 2.1 2.1 VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V VCC = 5.5 V 3.85 3.85 VCC = 3 V 0.9 0.9 VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 V VCC = 5.5 V 1.65 1.65 VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 3 V –4 –4 IOH High-level output current VCC = 4.5 V –24 –24 mA VCC = 5.5 V –24 –24 VCC = 3 V 12 12 IOL Low-level output current VCC = 4.5 V 24 24 mA VCC = 5.5 V 24 24 Dt/Dv Input transition rise or fall rate 0 10 0 10 ns/V TA Operating free-air temperature –55 125 –40 85 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C 54AC11112 74AC11112 UNITPARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT 3 V 2.9 2.9 2.9 IOH = – 50 mA 4.5 V 4.4 4.4 4.4 5.5 V 5.4 5.4 5.4 VOH IOH = – 4 mA 3 V 2.58 2.4 2.48 VVOH I2 4 A 4.5 V 3.94 3.7 3.8 V IOH = – 24 mA 5.5 V 4.94 4.7 4.8 IOH = – 50 mA† 5.5 V 3.85 IOH = –75 mA† 5.5 V 3.85 3 V 0.1 0.1 0.1 IOL = 50 mA 4.5 V 0.1 0.1 0.1 5.5 V 0.1 0.1 0.1 VOL IOL = 12 mA 3 V 0.36 0.5 0.44 VVOL IOL =2 4m A 4.5 V 0.36 0.5 0.44 V IOL = 24 mA 5.5 V 0.36 0.5 0.44 IOL = 50 mA† 5.5 V 1.65 IOL = 75 mA† 5.5 V 1.65 II VI = VCC or GND 5.5 V ± 0.1 ±1 ±1 mA ICC VI = VCC or GND, IO = 0 5.5 V 4 80 40 mA C i VI = VCC or GND 5 V 3.5 pF † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.

54AC11112, 74AC11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS073A – JUNE 1989 – REVISED APRIL 1993 POST OFFICE BOX 655303 • DALLAS, TEXAS 752652–4 timing requirements, VCC = 3.3 V ± 0.3 V (see Figure 1) TA = 25°C 54AC11112 74AC11112 UNIT MIN MAX MIN MAX MIN MAX UNIT fclock Clock frequency 0 100 0 70 0 70 MHz t Pulse duration PRE or CLR low 5 5 5 nstw Pulse duration CLK low or CLK high 5 5 5 ns t Setup time before CLK↓ Data high or low 5 5 5 nstsu Setup time before CLK ↓ PRE or CLR inactive 2.5 2.5 2.5 ns th Hold time after CLK↓ 0.5 0.5 0.5 ns timing requirements, VCC = 5 V ± 0.5 V (see Figure 1) TA = 25°C 54AC11112 74AC11112 UNIT MIN MAX MIN MAX MIN MAX UNIT fclock Clock frequency 0 125 0 125 0 125 MHz t Pulse duration PRE or CLR low 4 4 4 nstw Pulse duration CLK low or CLK high 4 4 4 ns t Setup time before CLK↓ Data high or low 3.5 3.5 3.5 nstsu Setup time before CLK ↓ PRE or CLR inactive 2 2 2 ns th Hold time after CLK↓ 1 1 1 ns switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM TO TA = 25°C 54AC11112 74AC11112 UNITPARAMETER (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX UNIT fmax 100 150 100 100 MHz tPLH PRE or CLR Qo rQ ns tPHL ns tPLH CLK Qo rQ ns tPHL CLK Q or Q ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM TO TA = 25°C 54AC11112 74AC11112 UNITPARAMETER (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX UNIT fmax 125 175 125 125 MHz tPLH PRE or CLR Qo rQ ns tPHL ns tPLH CLK Qo rQ ns tPHL CLK Q or Q ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT C pd Power dissipation capacitance per gate C L = 50 pF, f = 1 MHz 37 pF

NOTES: A. C L includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W , tr = 3 ns, tf = 3 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms

54AC11112, 74AC11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS073A – JUNE 1989 – REVISED APRIL 1993 POST OFFICE BOX 655303 • DALLAS, TEXAS 752652–6

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