54ABT652

54ABT652 NSC | Alldatasheet

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n Independent registers for A and B buses n Multiplexed real-time and stored data n A and B output sink capability of 48 mA, source capability of 24 mA n Guaranteed latchup protection n High impedance glitch free bus loading during entire power up and power down cycle n Nondestructive hot insertion capability n Standard Microcircuit Drawing (SMD) 5962-9324201 Ordering Code: Commercial Package Package Description Number 54ABT652J-QML J24A 24-Lead Ceramic Dual-in-line 54ABT652W-QML W24C 24-Lead Cerpack 54ABT652E-QML E28A 28-Lead Ceramic Leadless Chip Carrier, Type C Connection Diagram TRI-STATE® is a registered trademark of National Semiconductor Corporation. Pin Assignment for DIP and Flatpack DS100220-1 August 1998 54ABT652 Octal Transceivers and Registers with TRI-STATE Outputs © 1998 National Semiconductor Corporation DS100220 www.national.com

Connection Diagram (Continued) Pin Assignment for LCC DS100220-48 www.national.com 2

A0–A 7 Data Register A Inputs/TRI-STATE Outputs B0–B 7 Data Register B Inputs/TRI-STATE Outputs CPAB, CPBA Clock Pulse Inputs SAB, SBA Select Inputs OEAB, OEBA Output Enable Inputs Logic Diagram Functional Description In the transceiver mode, data present at the HIGH imped- ance port may be stored in either the A or B register or both. The select (SAB, SBA) controls can multiplex stored and real-time. The examples inFigure 1demonstrate the four fundamental bus-management functions that can be performed with the ’ABT652C. Data on the A or B data bus, or both can be stored in the in- ternal D flip-flop by LOW to HIGH transitions at the appropri- ate Clock Inputs (CPAB, CPBA) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D flip-flops by simultaneously enabling OEAB and OEBA. In this configuration each Output rein- forces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state. DS100220-3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.national.com

Functional Description(Continued) Note A: Real-Time Transfer Bus B to Bus A DS100220-4 OEAB OEBA CPAB CPBA SAB SBA LLXXXL Note C: Storage DS100220-6 OEAB OEBA CPAB CPBA SAB SBA XHNXXX LXXNXX LHNNXX Note B: Real-Time Transfer Bus A to Bus B DS100220-5 OEAB OEBA CPAB CPBA SAB SBA HHXXLX Note D: Transfer Storage Data to A or B DS100220-7 OEAB OEBA CPAB CPBA SAB SBA H L Ho rL Ho rL H H FIGURE 1. www.national.com 4

Functional Description(Continued) Inputs Inputs/Outputs (Note 1) Operating Mode OEAB OEBA CPAB CPBA SAB SBA A 0 thru A7 B 0 thru B7 L H H or L H or L X X Input Input Isolation L H N N X X Store A and B Data X H N H or L X X Input Not Specified Store A, Hold B H H N N X X Input Output Store A in Both Registers L X H or L N X X Not Specified Input Hold A, Store B L L N N X X Output Input Store B in Both Registers L L X X X L Output Input Real-Time B Data to A Bus L L X H or L X H Store B Data to A Bus H H X X L X Input Output Real-Time A Data to B Bus H H H or L X H X Stored A Data to B Bus H L H or L H or L H H Output Output Stored A Data to B Bus and Stored B Data to A Bus H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW to HIGH Clock Transition Note 1:The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW to HIGH transition on the clock inputs. 5 www.national.com

Absolute Maximum Ratings(Note 2) Storage Temperature −65˚C to +150˚C Ambient Temperature under Bias −55˚C to +125˚C Junction Temperature under Bias Ceramic −55˚C to +175˚C V CC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 3) −0.5V to +7.0V Input Current (Note 3) −30 mA to +5.0 mA Voltage Applied to Any Output in the Disable or or Power-Off State −0.5V to +5.5V in the HIGH State −0.5V to V CC Current Applied to Output in LOW State (Max) twice the rated I OL (mA) DC Latchup Source Current −500 mA Over Voltage Latchup (I/O) 10V Recommended Operating Conditions Free Air Ambient Temperature Military −55˚C to +125˚C Supply Voltage Military +4.5V to +5.5V Minimum Input Edge Rate ( ΔV/Δt) Data Input 50 mV/ns Enable Input 20 mV/ns Clock Input 100 mV/ns Note 2:Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3:Either voltage limit or current limit is sufficient to protect inputs.DC Electrical Characteristics Symbol Parameter ABT652 Units V CC Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Recognized HIGH Signal VIL Input LOW Voltage 0.8 V Recognized LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA (Non I/O Pins) VOH Output HIGH 54ABT 2.5 V Min I OH = −3 mA, (An,B n) Voltage 54ABT 2.0 I OH = −24 mA, (An,B n) VOL Output LOW 54ABT 0.55 V Min I OL = 48 mA, (An,B n) Voltage IIH Input HIGH Current 2 µA Max V IN = 2.7V (Non-I/O Pins) (Note 4) VIN = VCC (Non-I/O Pins) IBVI Input HIGH Current 7 µA Max V IN = 7.0V (Non-I/O Pins) Breakdown Test IBVIT Input HIGH Current 100 µA Max V IN = 5.5V (An,B n) Breakdown Test (I/O) IIL Input LOW Current −2 µA Max V IN = 0.5V (Non-I/O Pins) (Note 4) VIN = 0.0V (Non-I/O Pins) IIH +IOZH Output Leakage Current 50 µA 0V–5.5V V OUT = 2.7V (An,B n); OEBA = 2.0V and OEAB = GND = 2.0V IIL +IOZL Output Leakage Current −50 µA 0V–5.5V V OUT = 0.5V (An,B n); OEBA = 2.0V and OEAB = GND = 2.0V IOS Output Short-Circuit Current −50 −180 mA Max V OUT = 0V (An,B n) ICEX Output HIGH Leakage Current 50 µA Max V OUT = VCC (An,B n) ICCH Power Supply Current 250 µA Max All Outputs HIGH ICCL Power Supply Current 30 mA Max All Outputs LOW ICCZ Power Supply Current 250 µA Max Outputs TRI-STATE; All others at VCC or GND ICCT Additional ICC /Input 2.5 mA Max V I = VCC − 2.1V All others at VCC or GND Note 4:Guaranteed but not tested. Note 5:For 8 outputs toggling, ICCD < 1.4 mA/MHz. Note 6:Guaranteed, but not tested. www.national.com 6

Symbol Parameter Max Units V CC Conditions C L = 50 pF, RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL 1.2 V 5.0 T A = 25˚C (Note 7) VOLV Quiet Output Minimum Dynamic VOL -1.8 V 5.0 T A = 25˚C (Note 7) Note 7:Max number of outputs defined as (n).n−1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. 54ABT TA = −55˚C to +125˚C Fig. Symbol Parameter V CC = 4.5V–5.5V Units No. C L = 50 pF Min Max fmax Max Clock Frequency 125 MHz tPLH Propagation Delay 1.4 7.8 ns Figure 5tPHL Clock to Bus 1.2 8.4 tPLH Propagation Delay 1.5 6.7 ns Figure 5tPHL Bus to Bus 1.5 6.7 tPLH Propagation Delay 1.2 6.9 ns Figure 5tPHL SBA or SAB to An to Bn 1.2 7.7 tPZH Enable Time 1.3 5.6 ns Figure tPZL OEBA or OEAB to An or Bn 2.0 7.8 tPHZ Disable Time 1.5 8.2 ns Figure tPLZ OEBA or OEAB to An or Bn 1.5 7.3 AC Operating Requirements 54ABT TA = −55˚C to +125˚C Fig. Symbol Parameter V CC = 4.5V–5.5V Units No. C L = 50 pF Min Max tS(H) Setup Time, HIGH 3.5 ns Figure tS(L) or LOW Bus to Clock tH (H) Hold Time, HIGH 1.5 ns Figure tH (L) or LOW Bus to Clock tW (H) Pulse Width, 4.0 ns Figure tW (L) HIGH or LOW 7 www.national.com

Symbol Parameter Max Units Conditions (TA = 25˚C) C IN Input Capacitance 14.0 pF V CC = 0V (non I/O pins) C I/O(Note 8) I/O Capacitance 19.5 pF V CC = 5.0V (An,B n) Note 8:C I/Ois measured at frequency, f= 1 MHz, per MIL-STD-883D, Method 3012. www.national.com 8

Capacitance(Continued) tPLH vs Temperature (TA ) C L = 50 pF, 1 Output Switching Clock to Bus DS100220-16 tPHL vs Temperature (TA ) C L = 50 pF, 1 Output Switching Clock to Bus DS100220-17 tPLH vs Temperature (TA ) C L = 50 pF, 1 Output Switching Bus to Bus DS100220-18 tPHL vs Temperature (TA ) C L = 50 pF, 1 Output Switching Bus to Bus DS100220-19 tPLH vs Temperature (TA ) C L = 50 pF, 1 Output Switching SBA or SAB to An or Bn DS100220-20 tPHL vs Temperature (TA ) C L = 50 pF, 1 Output Switching SBA or SAB to An or Bn DS100220-21 9 www.national.com

Capacitance(Continued) tPLH vs Load Capacitance

1 Output Switching, TA = 25˚C

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Capacitance(Continued) tPLH vs Load Capacitance

8 Outputs Switching, TA = 25˚C

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Capacitance(Continued) tPZL vs Temperature (TA ) C L = 50 pF, 1 Output Switching DS100220-34 tPLZ vs Temperature (TA ) C L = 50 pF, 1 Output Switching DS100220-35 tPZH vs Temperature (TA ) C L = 50 pF, 1 Output Switching DS100220-36 tPHZ vs Temperature (TA ) C L = 50 pF, 1 Output Switching DS100220-37 tPZH vs Temperature (TA ) C L = 50 pF, 8 Outputs Switching DS100220-38 tPHZ vs Temperature (TA ) C L = 50 pF, 8 Outputs Switching DS100220-39 www.national.com 12

Capacitance(Continued) tPZL vs Temperature (TA ) C L = 50 pF, 8 Outputs Switching DS100220-40 tPLZ vs Temperature (TA ) C L = 50 pF, 8 Outputs Switching DS100220-41 tPZL vs Load Capacitance

8 Outputs Switching

T A = 25˚C DS100220-42 tPZH vs Load Capacitance T A = 25˚C DS100220-43 tPLH and tPHL vs Number Output Switching VCC = 5V, TA = 25˚C, CL = 50 pF Clock to Bus DS100220-44 tPLH and tPHL vs Number Output Switching VCC = 5V, TA = 25˚C, CL = 50 pF Bus to Bus DS100220-45 13 www.national.com

Capacitance(Continued) tPLH and tPHL vs Number Output Switching VCC = 5V, TA = 25˚C, CL = 50 pF SBA or SAB to Anor Bn DS100220-46 www.national.com 14

Physical Dimensionsinches (millimeters) unless otherwise noted 24-Lead Ceramic Dual-in-line 24-Lead Cerpack www.national.com 16

Physical Dimensionsinches (millimeters) unless otherwise noted (Continued) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI- CONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or sys- tems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose fail- ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 28-Lead Ceramic Leadless Chip Carrier, Type C 54ABT652 Octal Transceivers and Registers with TRI-STATE Outputs National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.