54ABT543

54ABT543 NSC | Alldatasheet

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n Back-to-back registers for storage n Bidirectional data path n A and B outputs have current sourcing capability of 24 mA and current sinking capability of 48 mA n Separate controls for data flow in each direction n Guaranteed latchup protection n High impedance glitch free bus loading during entire power up and power down cycle n Nondestructive hot insertion capability n Standard Military Drawing (SMD) 5962-9231401 Ordering Code: Military Package Package Description Number 54ABT543J-QML J24F 24-Lead Ceramic Dual-In-Line 54ABT543W-QML W24C 24-Lead Cerpack 54ABT543E-QML E28A 28-Lead Ceramic Leadless Chip Carrier, Type C Connection Diagrams Pin Assignment for DIP and Flatpak 10021801 Pin Assignment for LCC 10021802 TRI-STATE® is a registered trademark of National Semiconductor Corporation. November 2002 54ABT543 Octal Registered Transceiver with TRI-STATE Outputs © 2002 National Semiconductor Corporation DS100218 www.national.com

OEAB , OEBA Output Enable Inputs LEAB , LEBA Latch Enable Inputs CEAB , CEBA Chip Enable Inputs A0–A7 Side A Inputs or TRI-STATE Outputs B 0–B7 Side B Inputs or TRI-STATE Outputs Functional Description The ’ABT543 contains two sets of D-type latches, with sepa- rate input and output controls for each. For data flow from A to B, for example, the A to B Enable (CEAB ) input must be low in order to enter data from the A port or take data from the B port as indicated in the Data I/O Control Table. With CEAB low, a low signal on (LEAB ) input makes the A to B latches transparent; a subsequent low to high transition of the LEAB line puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both low, the B output buffers are active and reflect the data present on the output of the A latches. Control of data flow from B to A is similar, but using the CEBA , LEBA and OEBA . Data I/O Control Table Inputs Latch Status Output BuffersCEAB LEAB OEAB H X X Latched High Z X H X Latched — L L X Transparent — X X H — High Z L X L — Driving H = High Voltage Level L = Low Voltage Level X = Immaterial Logic Diagram 10021803 54ABT543 www.national.com 2

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature −65˚C to +150˚C Ambient Temperature under Bias −55˚C to +125˚C Junction Temperature under Bias Ceramic −55˚C to +175˚C V CC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Any Output in the Disable or Power-Off State −0.5V to +5.5V in the HIGH State −0.5V to V CC Current Applied to Output in LOW State (Max) twice the rated I OL (mA) DC Latchup Source Current −500 mA Over Voltage Latchup (I/O) 10V Recommended Operating Conditions Free Air Ambient Temperature Military −55˚C to +125˚C Supply Voltage Military +4.5V to +5.5V Minimum Input Edge Rate ( ∆V/∆t) Data Input 50 mV/ns Enable Input 20 mV/ns Clock Input 100 mV/ns Symbol Parameter ABT543 Units V CC Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Recognized HIGH Signal VIL Input LOW Voltage 0.8 V Recognized LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA (Non I/O Pins) VOH Output HIGH Voltage 54ABT 2.5 I OH = −3 mA, (A n,B n) 54ABT 2.0 V Min I OH = −24 mA, (A n,B n) VOL Output LOW Voltage 54ABT 0.55 V Min I OL = 48 mA, (A n,B n) VID Input Leakage Test 4.75 V 0.0 I ID = 1.9 µA, (Non-I/O Pins) All Other Pins Grounded IIH Input HIGH Current 5 µA Max VIN = 2.7V (Non-I/O Pins) (Note 3) VIN =V CC (Non-I/O Pins) IBVI Input HIGH Current Breakdown Test 7 µA Max V IN = 7.0V (Non-I/O Pins) IBVIT Input HIGH Current 100 µA Max V IN = 5.5V (A n,B n) Breakdown Test (I/O) IIL Input LOW Current −5 µA Max VIN = 0.5V (Non-I/O Pins)(Note VIN = 0.0V (Non-I/O Pins) IIH +I OZH Output Leakage Current 50 µA 0V–5.5V V OUT = 2.7V (A n,B n); OEAB or CEAB = 2V IIL +I OZL Output Leakage Current −50 µA 0V–5.5V V OUT = 0.5V (A n,B n); OEAB or CEAB = 2V IOS Output Short-Circuit Current −100 −275 mA Max V OUT =0 V( A n,B n) ICEX Output HIGH Leakage Current 50 µA Max V OUT =V CC (An,B n) IZZ Bus Drainage Test 100 µA 0.0V V OUT = 5.5V (A n,B n); All Others GND ICCLH Power Supply Current 50 µA Max All Outputs HIGH ICCL Power Supply Current 30 mA Max All Outputs LOW ICCZ Power Supply Current 50 µA Max Outputs TRI-STATE All Others at V CC or GND 54ABT543 www.national.com3

Symbol Parameter ABT543 Units V CC Conditions Min Typ Max ICCT Additional ICC/Input 2.5 mA Max V I =V CC − 2.1V All Others at V CC or GND ICCD Dynamic ICC No Load Outputs Open, CEAB (Note 3) 0.18 mA/MHz Max and OEAB = GND,CEBA = VCC, One Bit Toggling, 50% Duty Cycle, (Note 4) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Note 3: Guaranteed but not tested. Note 4: For 8-bit toggling. I CCD < 1.4 mA/MHz. Conditions Symbol Parameter Min Max Units V CC CL = 50 pF, RL = 500Ω VOLP Quiet Output Maximum Dynamic V OL 1.1 V 5.0 T A = 25˚C (Note 5) VOLV Quiet Output Minimum Dynamic V OL -0.45 V 5.0 T A = 25˚C(Note 5) Note 5: Max number of outputs defined as (n) .n−1 data inputs are driven 0V to 3V. One output at LOW. 54ABT TA = −55˚C to +125˚C Fig. Symbol Parameter V CC = 4.5V–5.5V Units No. CL =5 0p F Min Max tPLH Propagation Delay 1.6 6.4 ns Figure tPHL An to Bn or Bn to An 1.6 6.2 tPLH Propagation Delay tPHL LEAB to Bn, LEBA to A n 1.6 6.6 ns Figure OEBA or OEAB to A n or Bn 1.6 6.4 tPZH Enable Time tPZL LEAB to Bn, LEBA to A n 1.3 6.4 ns Figure OEBA or OEAB to A n or Bn 1.8 7.4 tPHZ Disable Time 2.0 7.2 ns Figure tPLZ CEBA or CEAB to A n or Bn 1.5 7.0 54ABT543 www.national.com 4

Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Ceramic Leadless Chip Carrier (L) Order Number 54ABT543E-QML 24-Lead Ceramic Dual-In-Line Package Order Number 54ABT543J-QML 54ABT543 www.national.com7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Ceramic Flatpak Package (F) Order Number 54ABT543W-QML LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com 54ABT543 Octal Registered Transceiver with TRI-STATE Outputs National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the righ t at any time without notice to change said circuitry and specifications.