54ABT373CLMQB

74ABT373 NSC | Alldatasheet

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Technical content

Features

Y TRI-STATE outputs for bus interfacing Y Output sink capability of 64 mA, source capability of 32 mA Y Guaranteed output skew Y Guaranteed multiple output switching specifications Y Output switching specified for both 50 pF and 250 pF loads Y Guaranteed simultaneous switching, noise level and dynamic threshold performance Y Guaranteed latchup protection Y High impedance glitch free bus loading during entire power up and power down Y Nondestructive hot insertion capability Y Standard Military Drawing (SMD) 5962-9321801 Commercial Military Package Package Description Number 74ABT373CSC (Note 1) M20B 20-Lead (0.300× Wide) Molded Small Outline, JEDEC 74ABT373CSJ (Note 1) M20D 20-Lead (0.300× Wide) Molded Small Outline, EIAJ 74ABT373CPC N20B 20-Lead (0.300× Wide) Molded Dual-In-Line 54ABT373J/883 J20A 20-Lead Ceramic Dual-In-Line 74ABT373CMSA (Note 1) MSA20 20-Lead Molded Shrink Small Outline, EIAJ Type II 54ABT373W/883 W20A 20-Lead Cerpack 54ABT373E/883 E20A 20-Lead Ceramic Leadless Chip Carrier, Type C 74ABT373CMTC (Notes 1, 2) MTC20 20-Lead Molded Thin Shrink Small Outline, JEDEC Note 1: Devices also available in 13× reel. Use suffix e SCX, SJX, MSAX, and MTCX. Note 2: Contact factory for package availability. Connection Diagrams Pin Assignment for DIP, SOIC, SSOP and Flatpak TL/F/11547–1 Pin Assignment for LCC TL/F/11547–2 Pin Names

Description

D0–D7 Data Inputs LE Latch Enable Input (Active HIGH) OE Output Enable Input (Active LOW) O0–O7 TRI-STATE Latch Outputs TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

’ABT373 contains eight D-type latches with TRI-STATE output buffers. When the Latch Enable (LE) in- put is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW tran- sition of LE. The TRI-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Truth Table Inputs Output LE OE Dn On H L H H H L L L L L X On (no change) X H X Z H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Z e High Impedance State Logic Diagram TL/F/11547–3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b65§C to a150§C Ambient Temperature under Bias b55§C to a125§C Junction Temperature under Bias Ceramic b55§C to a175§C Plastic b55§C to a150§C VCC Pin Potential to Ground Pin b0.5V to a7.0V Input Voltage (Note 2) b0.5V to a7.0V Input Current (Note 2) b30 mA to a5.0 mA Voltage Applied to Any Output in the Disabled or Power-Off State b0.5V to a5.5V in the HIGH State b0.5V to VCC Current Applied to Output in LOW State (Max) twice the rated IOL (mA) DC Latchup Source Current: OE Pin b150 mA (Across Comm Operating Range) Other Pins b500 mA Over Voltage Latchup (I/O) 10V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Recommended Operating Conditions Free Air Ambient Temperature Military b55§C to a125§C Commercial b40§C to a85§C Supply Voltage Military a4.5V to a5.5V Commercial a4.5V to a5.5V Minimum Input Edge Rate (DV/Dt) Data Input 50 mV/ns Enable Input 20 mV/ns Symbol Parameter ABT373 Units VCC Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Recognized HIGH Signal VIL Input LOW Voltage 0.8 V Recognized LOW Signal VCD Input Clamp Diode Voltage b1.2 V Min IIN e b18 mA VOH Output HIGH Voltage 54ABT/74ABT 2.5 IOH e b3 mA 54ABT 2.0 V Min IOH e b24 mA 74ABT 2.0 IOH e b32 mA VOL Output LOW Voltage 54ABT 0.55 V Min IOL e 48 mA 74ABT 0.55 IOL e 64 mA IIH Input HIGH Current mA Max VIN e 2.7V (Note 2) VIN e VCC IBVI Input HIGH Current Breakdown Test mA Max VIN e 7.0V IIL Input LOW Current mA Max VIN e 0.5V (Note 2) VIN e 0.0V VID Input Leakage Test 4.75 V 0.0 IID e 1.9 mA All Other Pins Grounded IOZH Output Leakage Current mA 0 b 5.5V VOUT e 2.7V; OE e 2.0V IOZL Output Leakage Current b50 mA 0 b 5.5V VOUT e 0.5V; OE e 2.0V IOS Output Short-Circuit Current b100 b275 mA Max VOUT e 0.0V ICEX Output High Leakage Current mA Max VOUT e VCC IZZ Bus Drainage Test 100 mA 0.0 VOUT e 5.5V; All Others GND ICCH Power Supply Current mA Max All Outputs HIGH ICCL Power Supply Current mA Max All Outputs LOW ICCZ Power Supply Current mA Max OE e VCC All Others at VCC or GND ICCT Additional ICC/Input Outputs Enabled 2.5 mA VI e VCC b 2.1V Outputs TRI-STATE 2.5 mA Max Enable Input VI e VCC b 2.1V Outputs TRI-STATE 2.5 mA Data Input VI e VCC b 2.1V All Others at VCC or GND ICCD Dynamic ICC No Load mA/ Max Outputs Open, LE e VCC (Note 2) 0.12 MHz OE e GND, (Note 1) One Bit Toggling, 50% Duty Cycle Note 1: For 8 bits toggling, ICCD k 0.8 mA/MHz. Note 2: Guaranteed, but not tested.

CL e 50 pF, RL e 500X VOLP Quiet Output Maximum Dynamic VOL 0.4 0.8 V 5.0 TA e 25§C (Note 1) VOLV Quiet Output Minimum Dynamic VOL b1.2 b0.8 V 5.0 TA e 25§C (Note 1) VOHV Minimum High Level Dynamic Output Voltage 2.5 3.0 V 5.0 TA e 25§C (Note 3) VIHD Minimum High Level Dynamic Input Voltage 2.0 1.7 V 5.0 TA e 25§C (Note 2) VILD Maximum Low Level Dynamic Input Voltage 0.9 0.6 V 5.0 TA e 25§C (Note 2) Note 1: Max number of outputs defined as (n). n b 1 data inputs are driven 0V to 3V. One output at Low. Guaranteed, but not tested. Note 2: Max number of data inputs (n) switching. n b 1 inputs switching 0V to 3V. Input-under-test switching: 3V to theshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested. Note 3: Max number of outputs defined as (n). n b 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. Symbol Parameter 74ABT 54ABT 74ABT Units TA e a25§C TA e b55§C to a125§C TA e b40§C to a85§C VCC e a5.0V VCC e 4.5V to 5.5V VCC e 4.5V to 5.5V CL e 50 pF CL e 50 pF CL e 50 pF Min Typ Max Min Max Min Max tPLH Propagation Delay 1.9 2.7 4.5 1.0 6.8 1.9 4.5 ns tPHL Dn to On 1.9 2.8 4.5 1.0 7.0 1.9 4.5 tPLH Propagation Delay 2.0 3.1 5.0 1.0 7.7 2.0 5.0 ns tPHL LE to On 2.0 3.0 5.0 1.5 7.7 2.0 5.0 tPZH Output Enable Time 1.5 3.1 5.3 1.0 6.7 1.5 5.3 ns tPZL 1.5 3.1 5.3 1.5 7.2 1.5 5.3 tPHZ Output Disable Time 2.0 3.6 5.4 1.7 8.0 2.0 5.4 ns tPLZ 2.0 3.4 5.4 1.0 7.0 2.0 5.4 AC Operating Requirements Symbol Parameter 74ABT 54ABT 74ABT Units TA e a25§C TA e b55§C to a125§C TA e b40§C to a85§C VCC e a5.0V VCC e 4.5V to 5.5V VCC e 4.5V to 5.5V CL e 50 pF CL e 50 pF CL e 50 pF Min Typ Max Min Max Min Max ftoggle Max Toggle 100 100 MHz Frequency ts(H) Setup Time, HIGH 1.5 2.5 1.5 ns ts(L) or LOW Dn to LE 1.5 2.5 1.5 th(H) Hold Time, HIGH 1.0 2.5 1.0 ns th(L) or LOW Dn to LE 1.0 2.5 1.0 tw(H) Pulse Width, 3.0 3.3 3.0 ns LE HIGH

Extended AC Electrical Characteristics (SOIC package) 74ABT 74ABT 74ABT TA e b40§C to a85§C TA e b40§C to a85§C TA e b40§C to a85§C VCC e 4.5V to 5.5V VCC e 4.5V to 5.5V VCC e 4.5V to 5.5V Symbol Parameter CL e 50 pF CL e 250 pF CL e 250 pF Units

8 Outputs Switching

(Note 5) (Note 4) (Note 6) Min Max Min Max Min Max tPLH Propagation Delay 1.5 5.2 2.0 6.8 2.0 9.0 ns tPHL Dn to On 1.5 5.2 2.0 6.8 2.0 9.0 tPLH Propagation Delay 1.5 5.5 2.0 7.5 2.0 9.5 ns tPHL LE to On 1.5 5.5 2.0 7.5 2.0 9.5 tPZH Output Enable Time 1.5 6.2 2.0 8.0 2.0 10.5 ns tPZL 1.5 6.2 2.0 8.0 2.0 10.5 tPHZ Output Disable Time 1.0 5.5 (Note 7) (Note 7) ns tPZL 1.0 5.5 Note 4: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 5: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in plce of the 50 pF load capacitors in the standard AC load. This specificaiton pertains to single output switching only. Note 6: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 7: The TRI-STATE delay times are dominated by the RC network (500X, 250 pF) on the output and has been excluded from the datasheet. Skew Symbol Parameter 74ABT 74ABT Units TA e b40§C to a85§C TA e b40§C to a85§C VCC e 4.5V–5.5V VCC e 4.5V–5.5V CL e 50 pF CL e 250 pF (Note 3) (Note 4) Max Max tOSHL Pin to Pin Skew 1.0 1.5 ns (Note 1) HL Transitions tOSLH Pin to Pin Skew 1.0 1.5 ns (Note 1) LH Transitions tPS Duty Cycle 1.4 3.5 ns (Note 5) LH–HL Skew tOST Pin to Pin Skew 1.5 3.9 ns (Note 1) LH/HL Transitions tPV Device to Device Skew 2.0 4.0 ns (Note 2) LH/HL Transitions Note 1: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH to LOW (tOSHL), LOW to HIGH (tOSLH), or any combination switching LOW to HIGH and/or HIGH to LOW (tOST). This specification is guaranteed but not tested. Note 2: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. Note 3: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 4: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 5: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.

(TA e 25§C) CIN Input Capacitance pF VCC e 0V COUT (Note 1) Output Capacitance pF VCC e 5.0V Note 1: COUT is measured at frequency f e 1 MHz, per MIL-STD-883B, Method 3012. tPLH vs Temperature (TA) CL e 50 pF, 1 Output Switching Data to Output TL/F/11547–11 tPHL vs Temperature (TA) CL e 50 pF, 1 Output Switching Data to Output TL/F/11547–12 tPZH vs Temperature (TA) CL e 50 pF, 1 Output Switching OE to Output TL/F/11547–13 tPZL vs Temperature (TA) CL e 50 pF, 1 Output Switching OE to Output TL/F/11547–14 tPHZ vs Temperature (TA) CL e 50 pF, 1 Output Switching OE to Output TL/F/11547–15 tPLZ vs Temperature (TA) CL e 50 pF, 1 Output Switching OE to Output TL/F/11547–16 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables.

tSET LOW vs Temperature (TA) CL e 50 pF, 1 Output Switching Data to LE TL/F/11547–17 tSET HIGH vs Temperature (TA) CL e 50 pF, 1 Output Switching Data to LE TL/F/11547–18 tHOLD HIGH vs Temperature (TA) CL e 50 pF, 1 Output Switching Data to LE TL/F/11547–19 tHOLD LOW vs Temperature (TA) CL e 50 pF, 1 Output Switching Data to LE TL/F/11547–20 tPLH vs Temperature (TA) CL e 50 pF, 8 Outputs Switching Data to Output TL/F/11547–21 tPHL vs Temperature (TA) CL e 50 pF, 8 Outputs Switching Data to Output TL/F/11547–22 tPZH vs Temperature (TA) CL e 50 pF, 8 Outputs Switching OE to Output TL/F/11547–23 tPZL vs Temperature (TA) CL e 50 pF, 8 Outputs Switching OE to Output TL/F/11547–24 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables.

tPHZ vs Temperature (TA) CL e 50 pF, 8 Outputs Switching OE to Output TL/F/11547–25 tPLZ vs Temperature (TA) CL e 50 pF, 8 Outputs Switching OE to Output TL/F/11547–26 tPLH vs Load Capacitance TA e 25§C, 1 Output Switching Data to Output TL/F/11547–27 tPHL vs Load Capacitance TA e 25§C, 1 Output Switching Data to Output TL/F/11547–28 tPLH vs Load Capacitance TA e 25§C, 8 Outputs Switching Data to Output TL/F/11547–29 tPHL vs Load Capacitance TA e 25§C, 8 Outputs Switching Data to Output TL/F/11547–30 tPZH vs Load Capacitance TA e 25§C, 8 Outputs Switching OE to Output TL/F/11547–31 tPZL vs Load Capacitance TA e 25§C, 8 Outputs Switching OE to Output TL/F/11547–32 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables.

tPLH vs Temperature (TA) CL e 50 pF, 1 Output Switching LE to Output TL/F/11547–35 tPHL vs Temperature (TA) CL e 50 pF, 1 Output Switching LE to Output TL/F/11547–36 tPLH vs Temperature (TA) CL e 50 pF, 8 Outputs Switching LE to Output TL/F/11547–37 tPHL vs Temperature (TA) CL e 50 pF, 8 Outputs Switching LE to Output TL/F/11547–38 tPLH and tPHL vs Number Outputs Switching CL e 50 pF, TA e 25§C, VCC e 5.0V, Outputs In Phase Data to Output TL/F/11547–33 Typical ICC vs Output Switching Frequency CL e 0 pF, VCC e VIH e 5.5V, LE e GND,

1 Output Switching at 50% Duty Cycle

Data to Output, Transparent Mode with Unused Data Inputs e VIH TL/F/11547–34 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables.

FIGURE 1. Standard AC Test Load

1 MHz

FIGURE 3. Propagation Delay Waveforms for FIGURE 4. Propagation Delay, FIGURE 5. TRI-STATE Output HIGH FIGURE 6. Setup Time, Hold Time

Ordering Information

The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: TL/F/11547–39

Physical Dimensions inches (millimeters) 20-Terminal Ceramic Chip Carrier (L)

Physical Dimensions inches (millimeters) (Continued) 20-Lead Ceramic Dual-In-Line (D) 20-Lead Small Outline Integrated Circuit JEDEC (S)

Physical Dimensions inches (millimeters) (Continued) 20-Lead Small Outline Integrated Circuit EIAJ (SJ) 20-Lead Plastic EIAJ SSOP (MSA)

Physical Dimensions inches (millimeters) (Continued) All dimensions are in millimeters. 20-Lead Molded Thin Shrink Small Outline Package JEDEC (MTC) 20-Lead Plastic Dual-In-Line Package (P)

54ABT/74ABT373 Octal Transparent Latch with TRI-STATE Outputs Physical Dimensions inches (millimeters) (Continued) 20-Lead Ceramic Flatpak (F) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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