ICS544-01 RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: mamiller
  • PDF pages: 8

Technical content

Features

  • Packaged in 8-pin SOIC
  • Pb-free package
  • IDT’s lowest cost clock divider
  • Easy to use with other generators and buffers
  • Input crystal at 16.777216MHz
  • Output clock duty cycle of 45/55
  • Output Enable
  • Advanced, low-power CMOS process
  • Operating voltage of 2.25 V to 3.6 V
  • Does not degrade phase noise - no PLL
  • Available in industrial temperature range Block Diagram Divider and Selection Circuitry /32, /64 /256, /512, CLK1 OEGND VDD 16.777216MHz crystal input Optional tuning capacitors S1, S0 (1:0)

CLOCK DIVIDER CLOCK DIVIDER IDT® CLOCK DIVIDER 2 ICS544-01 REV B 051810 Pin Assignment 8-pin (150 mil) SOIC Clock Divider Table 0 = connect directly to ground 1 = connect directly to VDD Pin Descriptions External Components Series Termination Resistor Ω Ω Ω On chip capacitors connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value (in pf) of these crystal caps equal (C L-12)*2 in this equation, CL=crystal load capacitance in pf. For example, for a crystal with a 16 pF load cap, each external crystal cap would be 8 pF . [(16-12)x2]=8. Decoupling Capacitor As with any high-performance mixed-signal IC, the ICS544-01 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01µF must be connected between VDD and the PCB ground plane. X1/ICLK GND VDD OE CLK S11 S1 S0 CLK 0 0 Input/32 0 1 Input/64

10 I n p u t / 2 5 6

11 I n p u t / 5 1 2

1 X1/ICLK XI Crystal input. 2 X2 Xo Connect to crystal for crystal input and leave open for clock input. 3 GND Power Connect to ground. 4 S0 Input Select 0 for output clock. Connect to GND or VDD, per divider table above. Internal pull-up resistor. 5 CLK Output Clock output per table above. Internal Pull down resistor. 6 OE Input Output Enable.Tri-states output clock when low. Also shuts down the oscillator circuit. Internal pull-up resistor. OE=1 normal operation. 7 VDD Power Connect to 2.25 V to 3.6 V. 8 S1 Input Select 1 for output clock. Connect to GND or VDD, per divider table above. Internal pull-up resistor.

CLOCK DIVIDER CLOCK DIVIDER IDT® CLOCK DIVIDER 3 ICS544-01 REV B 051810 PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. T he 0.01µF decoupling capacitor should be mounted o n the component side of the board as close to the VDD p in as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is le ss cr itical. 2) To minimize EMI, the 33Ω series termination resistor (if needed) should be placed close to the clock output. An optimum layout is one with all components on the same side of the board, minimizing vias through other sig nal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal tr aces should be routed away from the ICS544-01. This include s signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the de vice. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS544-01. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions Item Rating Supply Voltage, VDD 7 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature (commercial) 0 to +70° C Ambient Operating Temperature (industrial) -40 to +85° C Storage Temperature -65 to +150° C Junction Temperature 125° C Soldering Temperature 260° C Parameter Min. Typ. Max. Units Ambient Operating Temperature (commercial) 0 +70 ° C Ambient Operating Temperature (industrial) -40 +85 ° C Power Supply Voltage (measured in respect to GND) 2.25 3.6 V

CLOCK DIVIDER CLOCK DIVIDER IDT® CLOCK DIVIDER 4 ICS544-01 REV B 051810 Unless stated otherwise, VDD = 2.25 V to 3.6 V, CL=15pF ±5%, Ambient Temperature -40° C to +85° C Unless stated otherwise, VDD = 2.25 V to 3.6 V±5%, CL=15pF ±5%, Ambient Temp -40° C to +85° C Thermal Characteristics Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 2.25 3.6 V Input High Voltage V IH S0, S1, OE, ICLK 0.7VDD V Input Low Voltage V IL S0, S1, OE, ICLK 0.3VDD V Output High Voltage V OH IOH = -2 mA VDD-0.4 VDD-0.15 V Output Low Voltage V OL IOL = 2 mA 0.15 0.4 V Operating Supply Current I DD VDD =2.25 V - 2.75 V 0.3 0.6 mA Operating Supply Current I DD VDD= 2.75 V - 3.6 V 0.5 1 mA Standby Current I SB OE=0 10 ua Short Circuit Current I OS ±40 mA Input Capacitance C IN S0, S1, OE 4 pF Nominal Output Impedance Z O at VDD/2 20 Ω Internal Pull-up Resistor Rpup OE, S1, S0 420 k Ω Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency, clock input VDD = 3.3 V 0 16.777216 MHz Output Rise Time t OR 0.1VDD to 0.9VDD 0.2 1 μs Output Fall Time t OF 0.9VDD to 0.1VDD 0.2 1 μs Duty Cycle at VDD/2 45 49 to 51 55 % Output Enable Delay Time t OE OE going high to CLK output valid 2 μs Output Disable Delay Time t OD OE going low to CLK output invalid 2 μs Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air 150 ° C/W θJA 1 m/s air flow 140 ° C/W θJA 3 m/s air flow 120 ° C/W Thermal Resistance Junction to Case θJC 40 ° C/W

CLOCK DIVIDER CLOCK DIVIDER IDT® CLOCK DIVIDER 5 ICS544-01 REV B 051810 Marking Diagram (ICS554M-01LF) Marking Diagram (ICS554MI-01LF) Notes: YYWW is the last two digits of the year and week that the part was assembled. 3. “L ” or “LF” denotes Pb (lead) free package. 4. “I” denotes industrial temperature range. Bo ttom Marking: (origin) Origin = country of origin if not USA. 554M01LF YYWW 554MI01L YYWW

CLOCK DIVIDER CLOCK DIVIDER IDT® CLOCK DIVIDER 6 ICS544-01 REV B 051810 Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping Packaging Package Temperature 544M-01LF 544M01LF Tubes 8-pin SOIC 0 to +70 ° C 544M-01LFT 544M01LF Tape and Reel 8-pin SOIC 0 to +70 ° C 544MI-01LF 544MI01L Tubes 8-pin SOIC -40 to +85 ° C 544MI-01LFT 544MI01L Tape and Reel 8-pin SOIC -40 to +85 ° C INDEX AREA 1 2 D E SEATING PLANE A e - C - B .10 (.004) C C L H h x 45 Millimeters Inches Symbol Min Max Min Max A 1.35 1.75 .0532 .0688 A1 0.10 0.25 .0040 .0098 B 0.33 0.51 .013 .020 C 0.19 0.25 .0075 .0098 D 4.80 5.00 .1890 .1968 E 3.80 4.00 .1497 .1574 e 1.27 BASIC 0.050 BASIC H 5.80 6.20 .2284 .2440 h 0.25 0.50 .010 .020 L 0.40 1.27 .016 .050 α 0° 8° 0° 8°

© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, IC S, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA Corporate Headquarters Integrated Device Technology, Inc. www.idt.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support www.idt.com/go/clockhelp Innovate with IDT and accelerate your future networks. Contact: www.IDT.com ICS544-01 CLOCK DIVIDER CLOCK DIVIDER

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