5420CRZ

EL5120 INTERSIL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 20

Technical content

Features

• 12MHz -3dB Bandwidth
• Supply Voltage = 4.5V to 16.5V
• Low Supply Current (per Amplifier) = 500µA
• High Slew Rate = 10V/µs
• Unity-Gain Stable
• Beyond the Rails Input Capability
• Rail-to-Rail Output Swing
• Ultra-Small Package
• Pb-Free Available (RoHS Compliant)

Applications

• TFT-LCD Drive Circuits
• Electronics Notebooks
• Electronics Games
• Touch-Screen Displays
• Personal Communication Devices
• Personal Digital Assistants (PDA)
• Portable Instrumentation
• Sampling ADC Amplifiers
• Wireless LANs
• Office Automation
• Active Filters
• ADC/DAC Buffer Data Sheet March 4, 2009 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004, 2005, 2007, 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 FN7186.6 March 4, 2009

Ordering Information

TEMP. RANGE (°C) PACKAGE PKG. DWG. # EL5120IWT-T7* K -40 to +85 5 Ld TSOT Tape and Reel MDP0049 EL5120IWT-T7A* K -40 to +85 5 Ld TSOT Tape and Reel MDP0049 EL5120IWTZ-T7* (Note) BKAA -40 to +85 5 Ld TSOT Tape and Reel (Pb-Free) MDP0049 EL5120IWTZ-T7A* (Note) BKAA -40 to +85 5 Ld TSOT Tape and Reel (Pb-Free) MDP0049 EL5220ILZ-T13 *(Note) 20Z -40 to +85 8 Ld DFN Tape and Reel (Pb-Free) L8.2x3 EL5220CY D -40 to +85 8 Ld MSOP MDP0043 EL5220CY-T7 D -40 to +85 8 Ld MSOP Tape and Reel MDP0043 EL5220CY-13 D -40 to +85 8 Ld MSOP Tape and Reel MDP0043 EL5220CYZ (Note) BBAAA -40 to +85 8 Ld MSOP (Pb-Free) MDP0043 EL5220CYZ-T7* (Note) BBAAA -40 to +85 8 Ld MSOP Tape and Reel (Pb-Free) MDP0043 EL5220CYZ-T13* (Note) BBAAA -40 to +85 8 Ld MSOP Tape and Reel (Pb-Free) MDP0043 EL5420CL 5420CL -40 to +85 16 Ld QFN MDP0046 EL5420CL-T7 5420CL -40 to +85 16 Ld QFN Tape and Reel MDP0046 EL5420CL-T13 5420CL -40 to +85 16 Ld QFN Tape and Reel MDP0046 EL5420CLZ (Note) 5420CLZ -40 to +85 16 Ld QFN (Pb-Free) MDP0046 EL5420CLZ-T7* (Note) 5420CLZ -40 to +85 16 Ld QFN Tape and Reel (Pb-Free) MDP0046 EL5420CLZ-T13* (Note) 5420CLZ -40 to +85 16 Ld QFN Tape and Reel (Pb-Free) MDP0046 EL5420CS 5420CS -40 to +85 14 Ld SOIC MDP0027 EL5420CS-T7 5420CS -40 to +85 14 Ld SOIC Tape and Reel MDP0027 EL5420CS-T13 5420CS -40 to +85 14 Ld SOIC Tape and Reel MDP0027 EL5420CSZ (Note) 5420CSZ -40 to +85 14 Ld SOIC (Pb-Free) MDP0027 EL5420CSZ-T7* (Note) 5420CSZ -40 to +85 14 Ld SOIC Tape and Reel (Pb-Free) MDP0027 EL5420CSZ-T13* (Note) 5420CSZ -40 to +85 14 Ld SOIC Tape and Reel (Pb-Free) MDP0027 EL5420CR 5420CR -40 to +85 14 Ld TSSOP MDP0044 EL5420CR-T7* 5420CR -40 to +85 14 Ld TSSOP Tape and Reel MDP0044 EL5420CR-T13* 5420CR -40 to +85 14 Ld TSSOP Tape and Reel MDP0044 EL5420CRZ (Note) 5420CRZ -40 to +85 14 Ld TSSOP (Pb-Free) M14.173 EL5420CRZ-T7* (Note) 5420CRZ -40 to +85 14 Ld TSSOP Tape and Reel (Pb-Free) M14.173 EL5420CRZ-T13* (Note) 5420CRZ -40 to +85 14 Ld TSSOP Tape and Reel (Pb-Free) M14.173 * Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. EL5120, EL5220, EL5420

3 FN7186.6 March 4, 2009 Pinouts EL5420 (16 LD QFN) TOP VIEW VINA- VINA+ VS+ VINB+ VINB- VOUTB VOUTC VINC- NC VOUTA VOUTD NC VIND- VIND+ VS- VINC+ VS+ VIN-VIN+ VS- VOUT VS+ VOUTB VINB- VINB+VS- VINA+ VINA- VOUTA THERMAL PAD EL5220 (8 LD MSOP) TOP VIEW EL5120 (5 LD TSOT) TOP VIEW -+ -+ VOUTD VIND- VIND+ VS- VINC+ VINC- VOUTCVOUTB VINB- VINB+ VS+ VINA+ VINA- VOUTA -+ -+ EL5420 (14 LD TSSOP, SOIC) TOP VIEW VOUTA VINA- VINA+ VS- VS+ VOUTB VINB- VINB+ EL5220 (8 LD DFN) TOP VIEW THERMAL PAD THERMAL PAD CONNECTS TO VS- THERMAL PAD CONNECTS TO VS- EL5120, EL5220, EL5420

4 FN7186.6 March 4, 2009 IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Absolute Maximum Ratings (TA = +25°C) Thermal Information Thermal Resistance (Typical) θ JA (°C/W) http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. Electrical Specifications VS+ = +5V, VS- = -5V, RL = 10kΩ and CL = 10pF to 0V, TA = +25°C, unless otherwise specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT INPUT CHARACTERISTICS VOS Input Offset Voltage V CM = 0V 2 12 mV TCVOS Average Offset Voltage Drift (Note 3) 5 µV/°C IB Input Bias Current V CM = 0V 2 50 nA RIN Input Impedance 1G Ω CIN Input Capacitance 1.35 pF CMIR Common-Mode Input Range -5.5 +5.5 V CMRR Common-Mode Rejection Ratio for V IN from -5.5V to +5.5V 50 70 dB AVOL Open Loop Gain -4.5V ≤ VOUT ≤ +4.5V 75 95 dB OUTPUT CHARACTERISTICS VOL Output Swing Low I L = -5mA -4.92 -4.85 V VOH Output Swing High I L = 5mA 4.85 4.92 V ISC Short Circuit Current ±120 mA IOUT Output Current ±30 mA POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio V S is moved from ±2.25V to ±7.75V 60 80 dB IS Supply Current (Per Amplifier) No load 500 750 µA DYNAMIC PERFORMANCE SR Slew Rate (Note 4) -4.0V ≤ VOUT ≤ +4.0V, 20% to 80% 10 V/µs tS Settling to +0.1% (AV = +1) (A V = +1), VO = 2V step 500 ns BW -3dB Bandwidth R L = 10kΩ, CL = 10pF 12 MHz GBWP Gain-Bandwidth Product R L = 10kΩ, CL = 10pF 8 MHz EL5120, EL5220, EL5420

5 FN7186.6 March 4, 2009 PM Phase Margin R L = 10kΩ, CL = 10pF 50 ° CS Channel Separation f = 5MHz (EL5220 and EL5420 only) 75 dB NOTES: 3. Measured over operating temperature range. 4. Slew rate is measured on rising and falling edges. Electrical Specifications VS+ = +5V, VS- = -5V, RL = 10kΩ and CL = 10pF to 0V, TA = +25°C, unless otherwise specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT Electrical Specifications VS+ = +5V, VS- = 0V, RL = 10kΩ and CL = 10pF to 2.5V, TA = +25°C, unless otherwise specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT INPUT CHARACTERISTICS VOS Input Offset Voltage V CM = 2.5V 2 10 mV TCVOS Average Offset Voltage Drift (Note 5) 5 µV/°C IB Input Bias Current V CM = 2.5V 2 50 nA RIN Input Impedance 1G Ω CIN Input Capacitance 1.35 pF CMIR Common-Mode Input Range -0.5 +5.5 V CMRR Common-Mode Rejection Ratio for V IN from -0.5V to +5.5V 45 66 dB AVOL Open Loop Gain 0.5V ≤ VOUT ≤+ 4.5V 75 95 dB OUTPUT CHARACTERISTICS V OL Output Swing Low I L = -5mA 80 150 mV VOH Output Swing High I L = +5mA 4.85 4.92 V ISC Short Circuit Current ±120 mA IOUT Output Current ±30 mA POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio V S is moved from 4.5V to 15.5V 60 80 dB IS Supply Current (Per Amplifier) No load 500 750 µA DYNAMIC PERFORMANCE SR Slew Rate (Note 6) 1V ≤ VOUT ≤ 4V, 20% to 80% 10 V/µs tS Settling to +0.1% (AV = +1) (A V = +1), VO = 2V step 500 ns BW -3dB Bandwidth R L = 10kΩ, CL = 10pF 12 MHz GBWP Gain-Bandwidth Product R L = 10kΩ, CL = 10pF 8 MHz PM Phase Margin R L = 10kΩ, CL = 10pF 50 ° CS Channel Separation f = 5MHz (EL5220 and EL5420 only) 75 dB NOTES: 5. Measured over operating temperature range. 6. Slew rate is measured on rising and falling edges. EL5120, EL5220, EL5420

6 FN7186.6 March 4, 2009 Electrical Specifications VS+ = +15V, VS- = 0V, RL = 10kΩ and CL = 10pF to 7.5V, TA = +25°C, unless otherwise specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT INPUT CHARACTERISTICS VOS Input Offset Voltage V CM = 7.5V 2 14 mV TCVOS Average Offset Voltage Drift (Note 7) 5 µV/°C IB Input Bias Current V CM = 7.5V 2 50 nA RIN Input Impedance 1G Ω CIN Input Capacitance 1.35 pF CMIR Common-Mode Input Range -0.5 +15.5 V CMRR Common-Mode Rejection Ratio for V IN from -0.5V to +15.5V 53 72 dB AVOL Open Loop Gain 0.5V ≤ VOUT ≤ 14.5V 75 95 dB OUTPUT CHARACTERISTICS VOL Output Swing Low I L = -5mA 80 150 mV VOH Output Swing High I L = +5mA 14.85 14.92 V ISC Short Circuit Current ±120 mA IOUT Output Current ±30 mA POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio V S is moved from 4.5V to 15.5V 60 80 dB IS Supply Current (Per Amplifier) No load 500 750 µA DYNAMIC PERFORMANCE SR Slew Rate (Note 8) 1V ≤ V OUT ≤ 14V, 20% to 80% 10 V/µs tS Settling to +0.1% (AV = +1) (A V = +1), VO = 2V step 500 ns BW -3dB Bandwidth R L = 10kΩ, CL = 10pF 12 MHz GBWP Gain-Bandwidth Product R L = 10kΩ, CL = 10pF 8 MHz PM Phase Margin R L = 10kΩ, CL = 10pF 50 ° CS Channel Separation f = 5MHz (EL5220 and EL5420 only) 75 dB NOTES: 7. Measured over operating temperature range 8. Slew rate is measured on rising and falling edges EL5120, EL5220, EL5420

FIGURE 1. EL5420 INPUT OFFSET VOLTAGE DISTRIBUTION FIGURE 2. EL5420 INPUT OFFSET VOLTAGE DRIFT FIGURE 3. INPUT OFFSET VOLTAGE vs TEMPERATURE FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE FIGURE 5. OUTPUT HIGH VOLTAGE vs TEMPERATURE FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE

10 VS = ±5V

FIGURE 7. OPEN LOOP GAIN vs TEMPERATURE FIGURE 8. SLEW RATE vs TEMPERATURE FIGURE 9. EL5420 SUPPLY CURRENT PER AMPLIFIER vs FIGURE 10. EL5420 SUPPLY CURRENT PER AMPLIFIER vs FIGURE 11. OPEN LOOP GAIN AND PHASE vs FREQUE NCY FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS R L

10.40 VS = ±5V

11 FN7186.6 March 4, 2009 Pin Descriptions EL5120 EL5220 EL5420 PIN NAME PIN FUNCTION EQUIVALENT CIRCUIT 5 LD TSOT

8 LD MSOP,

8 LD DFN

14 LD TSSOP ,

14 LD SOIC

13, 16 NC No Connect IN+ Amplifier Non-Inverting Input (Reference Circuit 1) IN- Amplifier Inverting Input (Reference Circuit 1) OUT Amplifier Output (Reference Circuit 2)

3 VIN+ Amplifier Non-Inverting Input (Reference Circuit 1)

4 VIN- Amplifier Inverting Input (Reference Circuit 1)

1 VOUT Amplifier Output (Reference Circuit 2)

1 1 15 VOUTA Amplifier A Output (Reference Circuit 2) 2 2 1 VINA- Amplifier A Inverting Input (Reference Circuit 1) 3 3 2 VINA+ Amplifier A Non-Inverting Input (Reference Circuit 1) 5 8 4 3 VS+ Positive Power Supply 5 5 4 VINB+ Amplifier B Non-Inverting Input (Reference Circuit 1) 6 6 5 VINB- Amplifier B Inverting Input (Reference Circuit 1) 7 7 6 VOUTB Amplifier B Output (Reference Circuit 2) 8 7 VOUTC Amplifier C Outp ut (Reference Circuit 2) 9 8 VINC- Amplifier C Inverti ng Input (Reference Circuit 1) 10 9 VINC+ Amplifier C Non-Invert ing Input (Reference Circuit 1) 2 4 11 10 VS- Negative Power Supply 12 11 VIND+ Amplifier D Non-Invert ing Input (Reference Circuit 1) 13 12 VIND- Amplifier D Inverti ng Input (Reference Circuit 1) 14 14 VOUTD Amplifier D Ou tput (Reference Circuit 2) VS+ VS- VS+ GND VS- CIRCUIT 1 CIRCUIT 2 EL5120, EL5220, EL5420

• i = 1 to 2 for dual and 1 to 4 for quad S = Total supply voltage
• I SMAX = Maximum supply current per amplifier
• V OUTi = Maximum output voltage of the application
• I LOADi = Load current If we set the two PDMAX equations equal to each other, we can solve for RLOADi to avoid device overheat. Figure 27 provide a convenient way to see if the device will overheat. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. By using the previous equation, it is a simple matter to see if P DMAX exceeds the device's power derating curves. To ensure proper operation, it is important to observe the recommended derating curves in Figure 27. Unused Amplifiers It is recommended that any unused amplifiers in a dual and a quad package be configured as a unity gain follower. The inverting input should be directly connected to the output and the non-inverting input tied to the ground plane. Driving Capacitive Loads The EL5120, EL5220, and EL5420 can drive a wide range of capacitive loads. As load capacitance increases, however, the -3dB bandwidth of the device will decrease and the peaking will increase. The amplifiers drive 10pF loads in parallel with 10kΩ with just 1.5dB of peaking, and 100pF with 6.4dB of peaking. If less peaking is desired in these applications, a small series resistor (usually between 5Ω and 50Ω) can be placed in series with the output. However, this will obviously reduce the gain slightly. Another method of reducing peaking is to add a “snubber” circuit at the output. A snubber is a shunt load consisting of a resistor in series with a capacitor. Values of 150Ω and 10nF are typical. The advantage of a snubber is that it does not draw any DC load current or reduce the gain Power Supply Bypassing and Printed Circuit Board Layout The EL5120, EL5220, and EL5420 can provide gain at high frequency. As with any high-frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to ground, a 0.1µF ceramic capacitor should be placed from VS+ to pin to VS- pin. A 4.7µF tantalum capacitor should then be connected in parallel, placed in the region of the amplifier. One 4.7µF capacitor may be used for multiple devices. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. PDMAX ΣiV S ISMAX VS+( VOUT i) ILOAD i×–+×[]×= (EQ. 2) PDMAX ΣiV S ISMAX VOUT i( VS- ) ILOAD i×–+×[]×= (EQ. 3) 3.0 2.5 2.0 1.5 1.0 0.5 0 2 55 07 5 1 0 0 1 5 0 AMBIENT TEMPERATURE (°C) POWER DISSIPATION (W) 2.27W θJA = 44°C/W QFN16 12585 1.22W 870mW θJA = 115°C/W MSOP8 θJA = 93°C/W TSSOP14 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.08W θJA = 82°C/W SOIC14 1.800W θJA = 55°C/W DFN8

FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT

14 FN7186.6 March 4, 2009 EL5120, EL5220, EL5420 Dual Flat No-Lead Plastic Package (DFN) NX (b) SECTION "C-C" (A1) BOTTOM VIEW A AREA INDEX C C 0.10 0.08 SIDE VIEW 0.15 E A B C0.15 D TOP VIEW CB AREA INDEX NX L E2/2 REF. e N (Nd-1)Xe (DATUM A) (DATUM B) 0.10 87D2 BAM C N-1 PLANE SEATING C A NX b D2/2 NX k FOR EVEN TERMINAL/SIDE TERMINAL TIP CL e L CC L8.2x3

8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

A 0.80 0.90 1.00 - A1 - - 0.05 - A3 0.20 REF - b 0.20 0.25 0.32 5,8 D 2.00 BSC - D2 1.50 1.65 1.75 7,8 E 3.00 BSC - E2 1.65 1.80 1.90 7,8 e 0.50 BSC - k0 . 2 0 - - - L 0.30 0.40 0.50 8 N 8 2 Nd 4 3 Rev. 0 6/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.25mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are prov ided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.

15 FN7186.6 March 4, 2009 EL5120, EL5220, EL5420 Small Outline Package Family (SO) GAUGE PLANE A1 L DETAIL X 4¬¨¬®Ð SEATING PLANE e H b C 0.010 BM CA0.004 C

0.010 BM CA

B D (N/2)1 E1E NN (N/2)+1 A PIN #1 I.D. MARK h X 45¬ A SEE DETAIL ‚Äö c 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL INCHES TOLERANCE NOTESSO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) N 8 14 16 16 20 24 28 Reference - Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M -1994

16 FN7186.6 March 4, 2009 EL5120, EL5220, EL5420 Mini SO Package Family (MSOP) (N/2) (N/2)+1 N PLANE SEATING N LEADS 0.10 C PIN #1 I.D. E1E b DETAIL X 3¬¨¬®Ð GAUGE PLANE SEE DETAIL "X" c A 0.25 A1 L

0.25 C A B

D AM B e C

0.08 C A BM

H MDP0043 MINI SO PACKAGE FAMILY SYMBOL MILLIMETERS TOLERANCE NOTESMSOP8 MSOP10 A1 . 1 0 1 . 1 0 M a x . - A1 0.10 0.10 ±0.05 - A2 0.86 0.86 ±0.09 - c0 . 1 8 0 . 1 8 ± 0 . 0 5 - D 3.00 3.00 ±0.10 1, 3 E4 . 9 0 4 . 9 0 ± 0 . 1 5 - E1 3.00 3.00 ±0.10 2, 3 e0 . 6 5 0 . 5 0 B a s i c - L0 . 5 5 0 . 5 5 ± 0 . 1 5 - L1 0.95 0.95 Basic - N 8 10 Reference - Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994.

17 FN7186.6 March 4, 2009 EL5120, EL5220, EL5420 Thin Shrink Small Outline Package Family (TSSOP) N (N/2)+1 (N/2) TOP VIEW AD 0.20 C B A N/2 LEAD TIPSB E1E

0.25 CABM

H PIN #1 I.D. 0.05 eC 0.10 C N LEADS SIDE VIEW

0.10 CABMb

c SEE DETAIL ‚Äö END VIEW DETAIL X 0¬¨¬®Ðê GAUGE PLANE 0.25 LA1 A SEATING PLANE MDP0044 THIN SHRINK SMALL OUTLINE PACKAGE FAMILY SYMBOL MILLIMETERS TOLERANCE14 LD 16 LD 20 LD 24 LD 28 LD Rev. F 2/07 NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusi ons shall not exceed 0.25mm per side. 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M -1994.

18 FN7186.6 March 4, 2009 EL5120, EL5220, EL5420 QFN (Quad Flat No-Lead) Package Family PIN #1 I.D. MARK (N-2) (N-1) N (N/2) 2X 0.075 TOP VIEW(N/2) NE PIN #1 I.D. (N-2) (N-1) N b L N LEADS BOTTOM VIEW DETAIL X PLANE SEATING N LEADS C SEE DETAIL "X" (L) N LEADS & EXPOSED PAD 0.10 SIDE VIEW

0.10 BAM C

C B A E 0.075 C D (E2) (D2) e 0.08 C C (c) A C MDP0046 QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY (COMPLIANT TO JEDEC MO-220) SYMBOL MILLIMETERS TOLERANCE NOTESQFN44 QFN3 QFN32 c 0.20 0.20 0.20 0.20 Reference - D 7.00 5.00 8.00 5.00 Basic - E 7.00 7.00 8.00 6.00 Basic - e 0.50 0.50 0.80 0.50 Basic - N 44 38 32 32 Reference 4 ND 11 7 8 7 Reference 6 NE 11 12 8 9 Reference 5 SYMBOL MILLIMETERS TOLER- ANCE NOTESQFN28 QFN2 QFN20 QFN16 -0.02 N 28 24 20 20 16 Reference 4 ND 6 5 5 5 4 Reference 6 NE 8 7 5 5 4 Reference 5 Rev 11 2/07 NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Tiebar view shown is a non-functional feature. 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device. 5. NE is the number of terminal s on the “E” side of the package (or Y-direction). 6. ND is the number of terminals on the “D” side of the package (or X-direction). ND = (N/2)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet.

19 FN7186.6 March 4, 2009 EL5120, EL5220, EL5420 N A D E (N/2)21 0.15 DC 0.25 C 2X N/2 TIPSe B ddd M DC A-B b NX 2 3 SEATING PLANE 0.10 C NX 1 3 C D

0.15 A-BC

H c (L1) L 0.25 4¬¨¬®Ð GAUGE PLANE A MDP0049 TSOT PACKAGE FAMILY SYMBOL MILLIMETERS TOLERANCETSOT5 TSOT6 TSOT8 A 1.00 1.00 1.00 Max A1 0.05 0.05 0.05 ±0.05 A2 0.87 0.87 0.87 ±0.03 b 0.38 0.38 0.29 ±0.07 D 2.90 2.90 2.90 Basic E 2.80 2.80 2.80 Basic E1 1.60 1.60 1.60 Basic e 0.95 0.95 0.65 Basic e1 1.90 1.90 1.95 Basic L 0.40 0.40 0.40 ±0.10 L1 0.60 0.60 0.60 Reference ddd 0.20 0.20 0.13 - N 5 6 8 Reference Rev. B 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. 2. Plastic interlead protrusions of 0.15mm maximum per side are not included. 3. This dimension is measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Index area - Pin #1 I.D. will be located within the indicated zone (TSOT6 AND TSOT8 only). 6. TSOT5 version has no center lead (shown as a dashed line).

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7186.6 March 4, 2009 EL5120, EL5220, EL5420 Thin Shrink Small Outline Plastic Packages (TSSOP) α INDEX AREA D N 123 -B- 0.10(0.004) C AM BS e -A- b M -C- A SEATING PLANE 0.10(0.004) c E 0.25(0.010) BM M L 0.25 0.010 GAUGE PLANE NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen- sion at maximum material condition. Minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. (Angles in degrees) 0.05(0.002) M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC

A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.195 0.199 4.95 5.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 N1 4 1 4 7 α 0o 8o 0o 8o - Rev. 2 4/06