SI541 SKYWORKS | Alldatasheet

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Ultra Series™ Crystal Oscillator Si541 Data Sheet Ultra Low Jitter Dual Any-Frequency XO (125 fs), 0.2 to 1500 MHz The Si541 Ultra Series™ oscillator utilizes Skyworks Solutions’ advanced 4th gen- eration DSPLL® technology to provide an ultra-low jitter, low phase noise clock at two selectable frequencies. The device is factory-programmed to provide any two selectable frequencies from 0.2 to 1500 MHz with <1 ppb resolution and maintains exceptionally low jitter for both integer and fractional frequencies across its operating range. The Si541 offers excellent reliability and frequency stability as well as guaranteed aging performance. On-chip power supply filtering provides industry-leading power supply noise rejection, simplifying the task of generating low jitter clocks in noisy systems that use switched-mode power supplies. Offered in industry-standard footprints, the Si541 has a dramatically simplified supply chain that enables Skyworks to ship custom frequency samples 1-2 weeks after receipt of order. Unlike a traditional XO, where a different crystal is required for each out- put frequency, the Si541 uses one simple crystal and a DSPLL IC-based approach to provide the desired output frequencies. This process also guarantees 100% electrical testing of every device. The Si541 is factory-configurable for a wide variety of user specifications, including frequency, output format, and OE pin loca- tion/polarity. Specific configurations are factory-programmed at time of shipment, eliminating the long lead times associated with custom oscillators. KEY FEATURES

  • Available with any two selectable frequencies from 0.2 MHz to 1500 MHz
  • Very low jitter: 125 fs Typ RMS (12 kHz – 20 MHz)
  • Excellent PSNR and supply noise immunity: –80 dBc Typ
  • 7 ppm stability option (-40 to 85 C)
  • 3.3 V, 2.5 V and 1.8 V VDD supply operation from the same part number
  • LVPECL, LVDS, CML, HCSL, CMOS, and Dual CMOS output options
  • 2.5x3.2, 3.2x5, 5x7 mm package options
  • Any custom frequency available with 1-2 week lead times

APPLICATIONS

  • 100G/200G/400G OTN, coherent optics
  • 10G/40G/100G optical ethernet
  • 3G-SDI/12G-SDI/24G-SDI broadcast video
  • Servers, switches, storage, NICs, search acceleration
  • Test and measurement
  • Clock and data recovery
  • FPGA/ASIC clocking Pin Assignments 4GND FS/OE VDD CLK+ CLK- OE/FS (Top View) Pin # Descriptions 1, 2 Selectable via ordering option OE = Output enable; FS = Frequency Select

3 GND = Ground

4 CLK+ = Clock output

5 CLK- = Complementary clock output. Not used for CMOS.

6 VDD = Power supply

OE, Frequency Select (Pin Control) Flexible Formats, 1.8V – 3.3V Operation Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 1 206610A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 27, 2023 1

  1. Ordering Guide The Si541 XO supports a variety of options including frequency, output format, and OE pin location/polarity, as shown in the chart below. Specific device configurations are programmed into the part at time of shipment, and samples are available in 1-2 weeks. Skyworks Solutions provides an online part number configuration utility to simplify this process. Refer to https://www.skywork- sinc.com/Products/Timing-Oscillators to access this tool and for further ordering instructions. A FS Pin Pin 2 Pin 2 Pin 1 Pin 1 - - - - - A C G-AAA541 R Device Revision Tape and Reel Reel R Coil Tape<Blank> OE PolarityOE Pin Active HighPin 1A Active LowPin 1B Active HighPin 2C Active LowPin 2D Frequency Code Description xxxxxx Two unique frequencies can be specified within the supported range of the selected signal format. Either frequency can be assigned to FS=0 or FS=1. A six digit numeric code will be assigned for the specific combination of frequencies. Order OptionVDD RangeSignal Format A2.5, 3.3 V LVPECL B1.8, 2.5, 3.3 V LVDS C1.8, 2.5, 3.3 V CMOS D1.8, 2.5, 3.3 V CML E1.8, 2.5, 3.3 V HCSL F1.8, 2.5, 3.3 V Dual CMOS (In-Phase) Dual Frequency DescriptionXO Series 541 ± 20 ppm Temp Stability A -40 to 85 °C Temperature Grade G± 50 ppm Total Stability 2 B ± 10 ppm ± 25 ppm ± 7 ppmC ± 20 ppm B C X1.8, 2.5, 3.3 V Custom 1 G1.8, 2.5, 3.3 V Dual CMOS (Complementary) H1.8, 2.5, 3.3 V HCSL-Fast Package 5x7 mm 3.2x5 mm 2.5x3.2 mm Notes: 1. Contact Skyworks for non-standard configurations. 2. Total stability includes temp stability, initial accuracy, load pulling, VDD variation, and 20 year aging at 70 °C. 3. Create custom part numbers at https://www.skyworksinc.com/Products/Timing-Oscillators.

1.1 Technical Support

Frequently Asked Questions (FAQ) https://www.skyworksinc.com/products/timing/ultra-series-crystal-oscillators-xo/ si541 Oscillator Phase Noise Lookup Utility https://www.skyworksinc.com/tools/oscillator-phase-noise Quality and Reliability www.skyworksinc.com/quality Development Kits https://www.skyworksinc.com/Products/Timing-Oscillators Si541 Data Sheet • Ordering Guide Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 2 206610A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 27, 2023 2

  1. Electrical Specifications Table 2.1. Electrical Specifications VDD = 1.8 V, 2.5 or 3.3 V ± 5%, TA = –40 to 85 ºC Parameter Symbol Test Condition/Comment Min Typ Max Unit Temperature Range TA –40 — 85 ºC Frequency Range FCLK LVPECL, LVDS, CML 0.2 — 1500 MHz HCSL 0.2 — 400 MHz CMOS, Dual CMOS 0.2 — 250 MHz Supply Voltage VDD 3.3 V 3.135 3.3 3.465 V 2.5 V 2.375 2.5 2.625 V 1.8 V 1.71 1.8 1.89 V Supply Current IDD LVPECL (output enabled) — 100 145 mA LVDS/CML (output enabled) — 75 111 mA HCSL (output enabled) — 80 125 mA HCSL-Fast (output enabled) — 88 137 mA CMOS (output enabled) — 74 108 mA Dual CMOS (output enabled) — 80 125 mA Tristate Hi-Z (output disabled) — 64 100 mA Temperature Stability Frequency stability Grade A –20 — 20 ppm Frequency stability Grade B –10 — 10 ppm Frequency stability Grade C –7 — 7 ppm Total Stability1 FSTAB Frequency stability Grade A –50 — 50 ppm Frequency stability Grade B –25 — 25 ppm Frequency stability Grade C –20 — 20 ppm Rise/Fall Time (20% to 80% VPP) TR/TF LVPECL/LVDS/CML — — 350 ps CMOS / Dual CMOS, (CL = 5 pF) — 0.5 1.5 ns HCSL, FCLK >50 MHz — — 550 ps HCSL-Fast, FCLK >50 MHz — — 275 ps Duty Cycle DC All formats 45 — 55 % Output Enable (OE) Frequency Select (FS)2 VIH 0.7 × VDD — — V VIL — — 0.3 × VDD V TD Output Disable Time, FCLK >10 MHz — — 3 µs TE Output Enable Time, FCLK > 10 MHz — — 20 µs TFS Settling Time after FS Change — — 10 ms Powerup Time tOSC Time from 0.9 × VDD until output fre- quency (FCLK) within spec — — 10 ms Si541 Data Sheet • Electrical Specifications Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 3 206610A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 27, 2023 3

Parameter Symbol Test Condition/Comment Min Typ Max Unit Powerup VDD Ramp Rate VRAMP Fastest VDD ramp allowed on startup — — 100 V/ms LVPECL Output Option3 VOC Mid-level VDD – 1.42 — VDD – 1.25 V VO Swing (diff) 1.1 — 1.9 VPP Mid-level (1.8 V VDD) 0.8 0.9 1.0 V VO Swing (FCLK ≤ 1.4 GHz) 0.6 0.7 0.9 VPP Swing (FCLK > 1.4 GHz) 0.5 0.7 0.9 VPP HCSL Output Option5 HCSL-Fast Output Option5 VOH Output voltage high 660 750 850 mV VOL Output voltage low –150 0 150 mV VC Crossing voltage 250 350 550 mV CML Output Option (AC-Coupled) VO Swing (diff) 0.6 0.8 1.0 VPP CMOS Output Option VOH IOH = 8/6/4 mA for 3.3/2.5/1.8 V VDD 0.85 × VDD — — V VOL IOL = 8/6/4 mA for 3.3/2.5/1.8 V VDD — — 0.15 × VDD V Notes: 1. Total Stability includes temperature stability, initial accuracy, load pulling, VDD variation, and aging for 20 yrs at 70 ºC. 2. OE includes a 50 kΩ pull-up to VDD for OE active high. Includes a 50 kΩ pull-down to GND for OE active low. FS includes a 50 kΩ pull-up to VDD. 3. 50 Ω to VDD – 2.0 V. Additional DC current from the output driver will flow through the 50Ω resistors, resulting in a shift in common mode voltage. The measurements in this table have accounted for this. 4. Rterm = 100 Ω (differential). 5. 50 Ω to GND. Table 2.2. Clock Output Phase Jitter and PSNR VDD = 1.8 V, 2.5 or 3.3 V ± 5%, TA = –40 to 85 ºC Parameter Symbol Test Condition/Comment Min Typ Max Unit Phase Jitter (RMS, 12kHz - 20MHz)1 2.5 x 3.2 mm, 3.2 x 5 mm, FCLK ≥ 100 MHz ϕJ Differential Formats — 125 200 fs CMOS, Dual CMOS — 200 — fs Phase Jitter (RMS, 12kHz - 20MHz)1 5 x 7 mm, FCLK ≥ 100 MHz Differential Formats — 150 200 fs CMOS, Dual CMOS — 200 — fs Spurs Induced by External Power Supply Noise, 50 mVpp Ripple. LVDS 156.25 MHz Output PSNR 100 kHz sine wave — -83 — dBc 200 kHz sine wave — -83 — 500 kHz sine wave — -82 —

1 MHz sine wave — -85 —

Note: 1. Guaranteed by characterization. Jitter inclusive of any spurs. Si541 Data Sheet • Electrical Specifications Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 4 206610A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 27, 2023 4

Table 2.3. 3.2 x 5 mm Clock Output Phase Noise (Typical, 50ppm Total Stability Option) Offset Frequency (f) 156.25 MHz LVDS 200 MHz LVDS 644.53125 MHz LVDS Unit

100 Hz –110 –107 –99

1 kHz –121 –120 –109 10 kHz –132 –130 –121 100 kHz –139 –137 –127

1 MHz –151 –149 –138

10 MHz –160 –161 –155

20 MHz –161 –162 –157

Offset Frequency (f) 156.25 MHz LVPECL

200 MHz

644.53125 MHz

100 Hz –113 –110 –100

1 kHz –123 –120 –110 10 kHz –133 –130 –119 100 kHz –139 –137 –127

10 MHz –162 –166 –156

20 MHz –163 –167 –157

Phase jitter measured with Agilent E5052 using a differential-to-single ended converter (balun or buffer). Measurements collected for >700 commonly used frequencies. Phase noise plots for specific frequencies are available using our free, online Oscillator Phase Noise Lookup Tool at https://www.skyworksinc.com/Products/Timing-Oscillators. Figure 2.1. Phase Jitter vs. Output Frequency Si541 Data Sheet • Electrical Specifications Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 5 206610A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 27, 2023 5

Table 2.4. Environmental Compliance and Package Information Parameter Test Condition Mechanical Shock MIL-STD-883, Method 2002 Mechanical Vibration MIL-STD-883, Method 2007 Solderability MIL-STD-883, Method 2003 Gross and Fine Leak MIL-STD-883, Method 1014 Resistance to Solder Heat MIL-STD-883, Method 2036 Moisture Sensitivity Level (MSL): 3.2 x 5, 5 x 7 packages 1 Moisture Sensitivity Level (MSL): 2.5 x 3.2 package 2 Note: 1. For additional product information not listed in the data sheet (e.g. RoHS Certifications, MDDS data, qualification data, REACH Declarations, ECCN codes, etc.), refer to our "Corporate Request For Information" portal found here: www.skyworksinc.com/qual- ity. Table 2.5. Thermal Conditions Max Junction Temperature = 125° C Package Parameter Symbol Test Condition Value Unit 2.5 x 3.2 mm 6-pin DFN Thermal Resistance Junction to Ambient ΘJA Still Air, 85 °C 80 ºC/W Thermal Parameter Junction to Board ΨJB Still Air, 85 °C 39 ºC/W Thermal Parameter Junction to Top Center ΨJT Still Air, 85 °C 17 ºC/W 3.2 × 5 mm 6-pin CLCC Thermal Resistance Junction to Ambient ΘJA Still Air, 85 °C 55 ºC/W Thermal Parameter Junction to Board ΨJB Still Air, 85 °C 20 ºC/W Thermal Parameter Junction to Top Center ΨJT Still Air, 85 °C 20 ºC/W 5 × 7 mm 6-pin CLCC Thermal Resistance Junction to Ambient ΘJA Still Air, 85 °C 53 ºC/W Thermal Parameter Junction to Board ΨJB Still Air, 85 °C 26 ºC/W Thermal Parameter Junction to Top Center ΨJT Still Air, 85 °C 26 ºC/W Note: 1. Based on PCB Dimensions: 4.5" x 7", PCB Thickness: 1.6 mm, Number of Cu Layers: 4. Si541 Data Sheet • Electrical Specifications Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 6 206610A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 27, 2023 6

Table 2.6. Absolute Maximum Ratings1 Parameter Symbol Rating Unit Maximum Operating Temp. TAMAX 95 ºC Storage Temperature TS –55 to 125 ºC Supply Voltage VDD –0.5 to 3.8 ºC Input Voltage VIN –0.5 to VDD + 0.3 V ESD HBM (JESD22-A114) HBM 2.0 kV Solder Temperature2 TPEAK 260 ºC Solder Time at TPEAK2 TP 20–40 sec Notes: 1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. 2. The device is compliant with JEDEC J-STD-020. Si541 Data Sheet • Electrical Specifications Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 7 206610A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 27, 2023 7

  1. Dual CMOS Buffer Dual CMOS output format ordering options support either complementary or in-phase signals for two identical frequency outputs. This feature enables replacement of multiple XOs with a single Si541 device. Complementary Outputs In-Phase Outputs Figure 3.1. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Outputs Si541 Data Sheet • Dual CMOS Buffer Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 8 206610A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 27, 2023 8
  1. Recommended Output Terminations The output drivers support both AC-coupled and DC-coupled terminations as shown in figures below. CLK- LVPECL Receiver (3.3V, 2.5V)VDD Si54x 50 Ω CLK+ 50 Ω Rp Rp VDD R1 R1 R2 R2 CLK- LVPECL Receiver (3.3V, 2.5V)VDD Si54x 50 Ω CLK+ 50 Ω VDD R1 R1 R2 R2 AC-Coupled LVPECL – Thevenin Termination DC-Coupled LVPECL – Thevenin Termination CLK- LVPECL Receiver 50 Ω CLK+ 50 Ω Rp Rp 50 Ω R1 R2 50 Ω VDD VTT Si54x (3.3V, 2.5V)VDD CLK- LVPECL Receiver 50 Ω CLK+ 50 Ω 50 Ω 50 Ω VDD – 2.0V Si54x (3.3V, 2.5V)VDD AC-Coupled LVPECL - 50 Ω w/VTT Bias DC-Coupled LVPECL - 50 Ω w/VTT Bias Figure 4.1. LVPECL Output Terminations AC Coupled LVPECL Termination Resistor Values VDD R1 R2 Rp 3.3 V 82.5 Ω 127 Ω 130 Ω 2.5 V 62.5 Ω 250 Ω 90 Ω DC Coupled LVPECL Termination Resistor Values VDD R1 R2 3.3 V 127 Ω 82.5 Ω 2.5 V 250 Ω 62.5 Ω Si541 Data Sheet • Recommended Output Terminations Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 9 206610A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 27, 2023 9
  1. Package Outline

5.1 Package Outline (5×7 mm)

The figure below illustrates the package details for the 5×7 mm Si541. The table below lists the values for the dimensions shown in the illustration. Figure 5.1. Si541 (5×7 mm) Outline Diagram Table 5.1. Package Diagram Dimensions (mm) Dimension Min Nom Max Dimension Min Nom Max b 1.30 1.40 1.50 R 0.70 REF c 0.50 0.60 0.70 aaa 0.15 D 5.00 BSC bbb 0.15 D1 4.30 4.40 4.50 ccc 0.08 e 2.54 BSC ddd 0.10 E 7.00 BSC eee 0.05 E1 6.10 6.20 6.30 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. Si541 Data Sheet • Package Outline Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 11 206610A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 27, 2023 11

5.2 Package Outline (3.2×5 mm) The figure below illustrates the package details for the 3.2×5 mm Si541. The table below lists the values for the dimensions shown in the illustration. Figure 5.2. Si541 (3.2×5 mm) Outline Diagram Table 5.2. Package Diagram Dimensions (mm) Dimension Min Nom Max A 1.06 1.17 1.33 b 0.54 0.64 0.74 c 0.35 0.45 0.55 D 3.20 BSC D1 2.55 2.60 2.65 e 1.27 BSC E 5.00 BSC E1 4.35 4.40 4.45 H 0.45 0.55 0.65 L 0.80 0.90 1.00 L1 0.05 0.10 0.15 p 1.36 1.46 1.56 R 0.32 REF aaa 0.15 bbb 0.15 ccc 0.08 ddd 0.10 eee 0.05 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. Si541 Data Sheet • Package Outline Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 12 206610A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 27, 2023 12

5.3 Package Outline (2.5x3.2 mm) The figure below illustrates the package details for the 2.5x3.2 mm Si541. The table below lists the values for the dimensions shown in the illustration. Figure 5.3. Si541 (2.5×3.2 mm) Outline Diagram Table 5.3. Package Diagram Dimensions (mm) Dimension Min Nom Max A 0.85 0.90 1.00 A1 0.36 REF A2 0.53 REF W 0.55 0.60 0.65 D 3.2 BSC E 2.5 BSC e 1.10 BSC L 0.65 0.70 0.75 n 5 D1 2.2 BSC E1 1.589 BSC aaa 0.10 bbb 0.10 ddd 0.08 Notes: 1. The dimensions in parentheses are reference. 2. All dimensions in millimeters (mm). 3. Dimensioning and Tolerancing per ANSI Y14.5M-1994. Si541 Data Sheet • Package Outline Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 13 206610A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 27, 2023 13

  1. PCB Land Pattern

6.1 PCB Land Pattern (5×7 mm)

The figure below illustrates the 5×7 mm PCB land pattern for the Si541. The table below lists the values for the dimensions shown in the illustration. Figure 6.1. Si541 (5×7 mm) PCB Land Pattern Table 6.1. PCB Land Pattern Dimensions (mm) Dimension (mm) C1 4.20 E 2.54 X1 1.55 Y1 1.95 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Si541 Data Sheet • PCB Land Pattern Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 14 206610A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 27, 2023 14

6.2 PCB Land Pattern (3.2×5 mm) The figure below illustrates the 3.2×5.0 mm PCB land pattern for the Si541. The table below lists the values for the dimensions shown in the illustration. Figure 6.2. Si541 (3.2×5 mm) PCB Land Pattern Table 6.2. PCB Land Pattern Dimensions (mm) Dimension (mm) C1 2.60 E 1.27 X1 0.80 Y1 1.70 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Si541 Data Sheet • PCB Land Pattern Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 15 206610A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 27, 2023 15

6.3 PCB Land Pattern (2.5×3.2 mm) The figure below illustrates the 2.5×3.2 mm PCB land pattern for the Si541. The table below lists the values for the dimensions shown in the illustration. Figure 6.3. Si541 (2.5×3.2 mm) PCB Land Pattern Table 6.3. PCB Land Pattern Dimensions (mm) Dimension Description Value (mm) X1 Width - leads on long sides 0.85 Y1 Height - leads on long sides 0.7 D1 Pitch in X directions of XLY1 leads 1.639 E1 Lead pitch XLY1 leads 1.10 Notes: The following notes and stencil design are shared as recommendations only. A customer or user may find it necessary to use different parameters and fine-tune their SMT process as required for their application and tooling. General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 0.8:1 for the pads. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Si541 Data Sheet • PCB Land Pattern Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 16 206610A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 27, 2023 16

  1. Top Marking (5x7 and 3.2x5 Packages) The figure below illustrates the mark specification for the Si541. The table below lists the line information. Figure 7.1. Mark Specification Table 7.1. Si541 Top Mark Description Line Position Description 1 1–8 "Si541", xxx = Ordering Option 1, Option 2, Option 3 (e.g. Si541AAA) 2 1–6 Frequency Code (6-digit custom code as described in the Ordering Guide)

3 Trace Code

Position 1 Pin 1 orientation mark (dot) Position 2 Product Revision (C) Position 3–5 Tiny Trace Code (3 alphanumeric characters per assembly release instructions) Position 6–7 Year (last two digits of the year), to be assigned by assembly site (ex: 2017 = 17) Position 8–9 Calendar Work Week number (1–53), to be assigned by assembly site Si541 Data Sheet • Top Marking (5x7 and 3.2x5 Packages) Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 17 206610A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 27, 2023 17

  1. Top Marking (2.5x3.2 Package) The figure below illustrates the mark specification for the Si541 2.5x3.2 package sizes. The table below lists the line information. B C C C C C T T TTTT Y Y W W Figure 8.1. Mark Specification Table 8.1. Si541 Top Mark Description Line Position Description 1 1–6 B = Si541, CCCCC = Custom Mark Code

2 Trace Code

1–6 Six-digit trace code per assembly release instructions

3 Position 1 Pin 1 orientation mark (dot)

Position 2–3 Year (last two digits of the year), to be assigned by assembly site (exp: 2017 = 17) Position 4–5 Calendar Work Week number (1–53), to be assigned by assembly site Si541 Data Sheet • Top Marking (2.5x3.2 Package) Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 18 206610A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 27, 2023 18

  1. Revision History Revision 206610A May, 2023
  • Updated Min and Nom package diagram dimensions specs in 5.3 Package Outline (2.5x3.2 mm). Revision 1.3 June 2021
  • Updated Ordering Guide and topmark for RevC silicon
  • Added HCSL-Fast (faster tR/tF) ordering option
  • Updated Table 2.1, Powerup VDD Ramp Rate Revision 1.2 September 2020
  • Updated Table 2.1, Powerup VDD Ramp Rate and LVDS Swing Revision 1.1 November 2019
  • Added 2.5x3.2 mm package option. Revision 1.0 July 2018
  • Added 20 ppm total stability option. Revision 0.75 March 2018
  • Added 25 ppm total stability option. Revision 0.71 December 11, 2017
  • Added 5x7 package and land pattern. Revision 0.7 June 27, 2017
  • Initial release. Si541 Data Sheet • Revision History Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 19 206610A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 27, 2023 19

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