74198 ETC1 | Alldatasheet
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| foe ee -ep ~~~ F | CONNECTION DIAGRAM | j PINOUT A i 8-BIT R/L SHIFT REGISTER So [2a} vi DESCRIPTION — The '198 features synchronous parallel load, hold, shift 2 “ right and shift left modes, as determined by the Select (So, Si) inputs. State snl} fz} ss ! changes are initiated by the rising edge of the clock. An asynchronous Master Poli] [zo Reset (MA) input overrides all other inputs and clears the register. The "198 oof] —_ j is useful for serial-serial, serial-parallel, parallel-serial and parallel-parallel : register transfers. Ey 2lor af Fa} Ps : Pr [i].05 i © PARALLEL IN/PARALLEL OUT © SYNCHRONOUS PARALLEL LOAD ofa pzles © SHIFT RIGHT AND SHIFT LEFT CAPABILITY sf] FaJos © ASYNCHRONOUS OVERRIDING CLEAR ota = ! ORDERING CODE: See Section 9 orl plo COMMERCIAL GRADE| MILITARY GRADE onolet eer : PIN PKG 1 PKGS Voc = $5.0 V #5%, Voc = +5.0 V +10%, F OUT! = TA =0°C to 470°C "| Ta =-55°C to +126°C | TYPE Plastic ; [ape [| , Ceramic DIP) 74198DC 54198DM | on | Ri Flatpak y F| i ‘| 74198FC 54198FM i INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions i 54/74 (ULL.) PIN NAMES DESCRIPTION HIGHILOW So, S1 Mode Select Inputs 1.0/1.0 Po—Pr Parallel! Data Inputs 1.0/1.0 j Ds Serial Data Input (Shift Right) 1.0/1.0 i Ost Serial Data Input (Shift Left 1.0/1.0 cP Clock Pulse Input (Active Rising Edge 4.0/1.0 : MA Asynchronous Master Reset Input (Active LOW) 1.0/1.0 Qo — a7 Flip-flop Outputs 20/10 j LOGIC SYMBOL i 209.5 7 918 M719 2 2 Den Po PY PrP) Pe PS Pe Pr Ost i ‘ 0 ! 2a—|s i nw—ter MI_Qo Q1 2 03 Q4 Os Os O7 Veo = Pin 24 ’ GND = Pin 12 134 6 68 10 14 16 18 20 ‘
1537 E-02 4305 41 PE
FUNCTIONAL DESCRIPTION — The '198 contains eight edge-triggered D-type flip-flops and the interstage 4 gating required to perform synchronous parallel load, shift right, and shift left operations. Serial data enters at 4 Dsr for shift right and at Dst for shift left operations. Paralie! data is applied to the Po —P7 inputs. State ; changes are initiated by the rising edge of the clock. The Dsr, Ds_ and Po — P7 inputs can change when the clock is in either state, provided only that the recommended setup and hold times are observed. The operating mode is determined by So and Si, as shown in the Mode Select Table. Clocking of the flip-flopsis Inhibited when both So and S1 are LOW. To avoid inadvertently clocking the register, the Select inputs should only be changed while CP is HIGH, A LOWsignal on MR overrides all other inputs and forces the outputs LOW. : MODE SELECT TABLE | INPUTS 1 MR CP So’ Si* L x |X x Asynchronous Reset; Outputs = LOW
4 H}| S| H H Parallel Load; Prh—=Qn
4d H/T] L H Shift Right; Osa —= Qo, Qo —™Q), etc. H/ sr} He Shift Lett; Ds. —~Q7, Q7 —=Qs, etc. 3
4 H] xXPefpe Hold 3
“Select inputs should be changed only while CP Is HIGH H = HIGH Voltago Love! L = LOW Voltage Level X = Immaterial i | LOGIC DIAGRAM ¢ Dsa Po Py Pe Ps Pe Ps Pe Pr Ds i Sop Fe—hH A ot o t etH aa : spe He et rt — TU HH ae ir eor | 0 VOO/00U O0G DOU 099 NOU O99 HOU E U U V) U U , U U 4 | op. D D [1] me II TI am I~] TI mm-p—_| [PPP eee ee — — a a — t—4 ! Qa a @ Qy 7 Qs Qs ay i
7-SO-0F-05 _ 198 |
4 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) , J
SYMBOL PARAMETER UNITS: CONDITIONS lec | Power Supply Current ne Veo = Maxi So, $1 = 45 V AC CHARACTERISTICS: Vcc = +5.0 V, Ta = +25°C (See Section 3 for waveforms and load configurations) |
4 SYMBOL PARAMETER Ci = 15 pF UNITS CONDITIONS
' Ri = 4009 | fmax Maximum Shift Frequency [2 iS (| Figs. 9-1, 3-8 a | tun Propagation Delay — | {Jeu - | cP to Q Figs. 3-1, 3-8 I Propagation Delay 4 ae 4 tPHL MR to Qn Figs, 3-1, 3-16 4 AC OPERATING REQUIREMENTS: Vcc = +5.0 V, Ta = +25°C § SYMBOL PARAMETER oe ax UNITS CONDITIONS ts (HD Setup Time HIGH or LOW : & Pn, Dst, Ds to CP . | th (U Pn, Dst, Osr to CP Fig. 3-6 | . ts (H) Setup Time HIGH or LOW t(D So or Si to CP th (H) Hold Time HIGH or LOW hi So or $1 to CP | 1339 E=04 wor FLIPS IK