54195 NSC | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 3

Technical content

! , NATIONAL SEMICOND {LOGIC} O2E D Jp esouee 0063930 tb | 195 =4 b- 07-050 4 CONNECTION DIAGRAM PINOUT A ; 54LS/74LS195A am [vee UNIVERSAL 4-BIT SHIFT REGISTER eB elo KB] [74] a: Po [4] [13] 2 . PG] fizjas Po [i] mea DESCRIPTION —The '195 is a high speed 4-bit shift register offering typical | shift frequencies of 50 MHz. It is useful for a wide variety of register and eo [7| al cr counting applications. The ‘195 is pin and functionally identical to the 9300, | cno[s] [a] Pe 93L00 and 93H00. * TYPICAL SHIFT RIGHT FREQUENCY OF 50 MHz ('LS195A) LOGIC SYMBOL ' * ASYNCHRONOUS MASTER RESET | « J, K INPUTS TO FIRST STAGE ‘ * FULLY SYNCHRONOUS SERIAL OR PARALLEL DATA TRANSFERS case? j ORDERING CODE: See Section 9 a—fy PE Po Pt Pe Ps pin | COMMERCIAL GRADE] MILITARY GRADE | 4 | Je 2 }O— 11 PKGS | gy] Yoo = +8.0 V 45%, Veo = +5.0V 10%, | type MR Qo O12 3 Ta=0°C to+70°C | Ta= -55°C to +125°C = Plastic 115 14:13:12 | [SET [reve [Toe] Ceramic | 4 | 74195DC, 74LS195ADC |54195DM, 54LS195A0M Vec = Pin 16 DIP (D) G " i i ind = Pin 8 Fatpak TA195FC, 74LS195AFC |54195FM, S4LS195AFM INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions j 54/74 (UL) S4/TALS (ULL.) PIN NAMES DESCRIPTION HIGHTLOW HIGHLOW F PE Parallel Enable Input (Active LOW) 1.0/1.0 0.5/0.25 | Po—Ps Parallel Data Inputs 1.0/1.0 0.5/0.25 J First Stage J Input (Active HIGH) 1.0/1.0 0.5/0.25 K First Stage K Input (Active LOW) 1.0/1.0 0.5/0.25 i ce Clock Pulse input (Active Rising Edge) 1.0/1.0 0.5/0.25 MA Asynchronous Master Reset Input 4.0/1.0 0.5/0.25 (Active LOW) Qo—Qa Parallel Outputs 20/10 10/5.0 ! (2.5) : tory Complementary Last Stage Output 20/10 10/5.0 : (Active LOW) (2.5)

44 LI PG 12

| 13528 © p-07 208 SH/PS™

. io ~ : fot : i, NATIONAL SEMICOND {LOGIC} O2— D | 6501122 00635931 4 | T¥6-0g9-05 199 x FUNCTIONAL DESCRIPTION — The Logic Diagram and Truth Table indicate the functional characteristics of : #] the '195 4-bit shift register. The device is useful in a wide variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds. The '195 has two primary modes of operation, shift right(Qo— Qi) and parallel load, which are controlled by the state of the Parallel Enable (PE) input. When the PE inputis HIGH, serial data enters the first flip-flop Qo via the J and K inputs and is shifted one bit in the direction Qo-> Qi» Q2—> Qs following each LOW-to-HIGH clock transition. The JK inputs provide the flexibility of the JK type input for special applications, and the simple D | type input for general applications by tying the two pins together. When the PE input is LOW, the'195 appearsas four common clocked D flip-flops. The data on the parallel inputs Po, P1, P2, P3 is transferred to the respective Qo, G1, Q2, Qs outputs following the LOW-to-HIGH clock transition. Shift left operation (Q3—Q2) can be | achieved by tying the Qn outputs to-the Pn - 1 inputs and holding the PE input LOW. Allserial and parallel data transfers are synchronous, occuring after each LOW-to-HIGH clock transition. Since the ‘195 utilizes edge-triggering, there is no restriction on the activity of the J, K, Pn and PE inputs for togic operation— except for the setup and release time requirements. A LOW on the asynchronous Master Reset (MP) Input sets all Q outputs LOW, independent of any other input condition. fa | MODE SELECT TABLE | : OPERATING MODES INPUTS OUTPUTS a MR PE JK Pn| Qo Qi Q2 Q3 Os it

5 Asynchronous Reset Lx x x xfLe_ Loe eH

Fi Shift, Set First Stage H ho h h X}H qo a a a Shift, Reset FirstStage | H h | | X|L ao a a q Shift, Toggle First Stage} H h h 1! XJ] Go qo qi qe Ge Shift, Retain First Stage |H oh 1! h X] qo qo ai qe qe Parallel Load H | XX pn] po _pi_pe ps Be H= HIGH Voltage Level L = LOW Voltage Level X = Immaterial F 1= LOW voltage level one satup time prior to the LOW to HIGH clock transition. h= HIGH voltage level one setup time prior to the LOW to HIGH clock transition. e i pa (qn) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to. | the LOW to HIGH clock transition. { LOGIC DIAGRAM | Fes RP ms Pa a cd | v y 191s res Ul * 2 ; 3 i | ) Co oO or 030) 1329 p-08 4-297 S f/PS- Lye

NATIONAL SEMICOND {LOGIC} O2E D Jesonee 0063932 0 I

195 T- Yb -0F-05 F

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) SYMBOL PARAMETER UNITS CONDITIONS | | Voc = Max, PE= Gnd loo Power Supply Current 21 | mA | J, K. Pn, MA=4.5V cps AC CHARACTERISTICS: Vcc = +5.0 V, Ta = +25°C (See Section 3 for wavetorms and load configurations) sama | sa/7aLs SYMBOL PARAMETER OL =15 pF|C.=15 pF| UNITS CONDITIONS RL = 400 0) tun Propagation Delay at ter CPtoQn 24 te Propagation Delay,MRtoQn | 30 | 26 | __ns__‘| Figs. 3-1, 3-16 ] AC OPERATING REQUIREMENTS: Vcc = +5.0 V, Ta = +25°C K SYMBOL PARAMETER UNITS CONDITIONS bi Setup Time HIGH or LOW &) 4, K or Pn to CP . th J, K or Pn to CP Fig, 9:6 i (HD Setup Time HIGH or LOW | tb PE to CP : tn(H) | Hold Time HIGH or LOW ! trib PE to CP i ; tw(H) GP Pulse Width HIGH [is [iw | ns | Fin oe i — 4-298 GS I/IGFIR 1330 0-09 ot ;