74178 ETC1 | Alldatasheet
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“ CONNECTION DIAGRAM ZL. PINOUT A fot 54/74178 9/5 4-BIT SHIFT REGISTER 2) a [74] vec Po[2| [ia] Pe os [3] [ia] Ps Qo [4] [17] se oe] [io] a3 ae] [Ss] Pe en) [s] a2 LOGIC SYMBOL DESCRIPTION — The '178 features synchronous parallel or serial entry and parallel outputs. The flip-flops are fully edge-triggered, with state changes initiated by a HIGH-to-LOW transition of the clock. Parallel Enable and Serial Enable inputs are used to select Load, Shift and Hold modes of opera- 9 2 4 13 12 tion. The '178 is the 14-pin version of the 179. For detail specifications, please refer to the '179 data sheet. PE PsP; Ps Ps 3 Ds 5 ho ORDERING CODE: See Section 9 u—tse COMMERCIAL GRADE] MILITARY GRADE | py, Qo: a2 ae PKGS Voc = +5.0 V +5%, Veo = +5.0V #10% | type Ta = 0°C to +70°C Ta = -55°C to +125°C 4 6 8 10 Plastic DIP (P) ee ee ce . Ceramic DIP (D) | * [prec seraom | | Voc = Pin 14 Fl GND = Pin 7 INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions 54/74 (U.L.) PIN NAMES: DESCRIPTION HIGH/LOW PE Parallel Enable Input 1.0/1.0 Po — P3 Parallel Data Inputs 1.0/1.0 Ds Serial Data Input 1.0/1.0 SE Shift Enable Input 1.0/1.0 cp Clock Pulse Input (Active Falling Edge) 1.0/1.0 Qo—Q3 Flip-flop Outputs 20/10 4-262 .
FUNCTIONAL DESCRIPTION — The ‘178 contains four D-type edge-triggered flip-flops and sufficient inter- stage logic to perform parallel load, shift right or hold operations. All state changes are initiated by a HIGH- to-LOW transition of the clock. A HIGH signal on the Shift Enable (SE) input prevents parallel loading and per- mits aright shift each time the clock makes a negative transition. When the SE inputis LOW, the signal applied to the Parallel Enable (PE) input determines whether the circuit is in a paraliel load or a hold mode, as shownin the Mode Select Table. The SE, PE, Ds and Pn inputs can change when the clock is in either state, provided only that the recommended setup and hold times are observed. MODE SELECT TABLE INPUTS _ RESPONSE [ve] oF] H | x [AL | Right snitt. Ds; Go ay, ete. L H kL Parallel load Ph» —® Qn. L L x Hold H= HIGH Votage Level CS Low vonage Level X= Immaterial LOGIC DIAGRAM Po Py Pe Ps "bebe | «—ptp— TT a a, a a 4-263