54167DM

54167 FAIRCHILD | Alldatasheet

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/ PINOUT A Li DO sarrater 220! SYNCHRONOUS DECADE RATE MULTIPLIER nel pslve< s [2] me sf] [74] So ms [4] [13] MA Cag fale, ov [6] [ii] ce ita [ale DESCRIPTION — The "167 contains asynchronous decade counter andfour | SNL paler decoding gates that serve to gate the clock through to the output at a sub- multiple of the clock frequency. The output pulse rate, relative to the clock 4 frequency, is determined by signals applied to the Select (So— So) inputs. Both true and complement outputs are available, along with an enable input | —————————— for each. A Count Enable input and a Terminal Count output are provided LOGIC SYMBOL for cascading two or more packages. Asynchronous Master Reset and Master Set inputs prevent counting and clear the counter or set it to maximum, respectively. 44is2 3 MS 6 8, 8: So ORDERING CODE: See Section 9 Noyce o—lcr COMMERCIAL GRADE| MILITARY GRADE w—ole, telo—7 PKGS Voc = +5.0 V +5%, Voc = +5.0 V #10%, we TaA=0°C to +70°C | Ta =-55°C to +125°C Ma __ 92 oe Plastic IP (>) La | merece | sd | * vs Ceramic Vec = Pin 16 Flatpak 74167FC 84167FM INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions 54/74 (U.L.) PIN NAMES DESCRIPTION eon, So —S3 Rate Select Inputs 1.0/1.0 & Oz Enable Input (Active Low 1.0/1.0 Ey Oy Enable Input 1.0/1.0 cE Count Enable Input (Active LOW 4.0/1.0 cP Clock Pulse input (Active Rising Edge) 2.0/2.0 Ms Asynchronous Master Set Input (Active HIGH) (Set to 9) 1.0/1.0 MR Asynchronous Master Reset Input (Active HIGH) 1.0/1.0 Oz Gated Clock Output (Active LOW) 10/10 Ov Complement Output (Active HIGH) 10/10 TC Terminal Count Output (Active LOW 10/10 4-233

__ CLOCK _ mR GE Ez Sa Se S: So | PULSES|Ey| Oy Oz TC | NOTES HIxPH]x x x x x falc a 1 cfefeye eee to |H}L OH 2 cfefe}eou ua wo JH] a 14 2 cefefef}e ue we wo JH] 2 2 2 cfefefeou Hou 1 jH|3s 3 2 cfefefe wee wo fH] 4 4 2 cfefefo Hod to H|5 5 2 cfefevo wae 10 |H|6 6 2 cfefetuo nw nH wo |H}7 7 2 cfefefH oe ece to |H|s 6 2 cfefeyH cou aw to |H]}9 9 2 cfefceyH cae to |H|a 2 2,3 cfefeyH oc HH to |H|}9 9 2.3 cfefefH woe to |H|e 6 2,3 cfelcjH Hea 10 |H}9 9 2.3 cfejeyH HAL to JH|8 8 2.3 cfejc}H HOH A 10 JH|9 9 2,3 ee) to jc} 9 4 1. This is a simplified illustration of the clear function. CP and Ez also affect the logic level of Oy and Oz. A'LOW signel on Er wil cause Ov fo remain HIGH, 2 ech rate llusirated assumes So--So are constant throughtout the cycle: however, these ilusta- fiona (n no way prohibit verable-rate operation

4 Trove input conations exceed the range of the decade rate Select inputs

& Ev een be used to mnibit output Or H= HIGH Voitage Level C= {ow voltage Level X= tmmateriel PULSE PATTERN TABLE Sa_S2 $1 So | m| Oz PULSE PATTERN cotoLt MW | aftitto0tdiidd L L HL 2);1101111011 Lou HH | 3ft1010110914 Low LL | 4fto101t101014 L HOL H 6/1010010101 L oH HL | 6{1000110001 L oH HH | 7/1000010001 H L L L 8/0000100001 H Lt tH | 9{0000000001 = HIGH Voltage Level CE Low voltage Leve! 4-235

FUNCTIONAL DESCRIPTION — The ‘167 contains four JK flip-flops connected as a synchronous decade counter with a count sequence of 0-1-2-3-4-8-9-10-11-12. A LOW signal on the Count Enable(CB) input permits Counting, with all state changes initiated simultaneously by the rising edge of the clock. When the count reaches maximum (12) the Terminal Count (TC) output goes LOW if CE is LOW. A HIGH signal on Master Reset (MR) clears the flip-flops and prevents counting, although output pulses can still occur if the clock is running, Ez is LOW and Ss is HIGH. A HIGH signal on Master Set (MS) prevents counting and sets the counter to 12, the only state in which no output pulses can occur. The flip-flop outputs are decoded by a 4-wide AND-OR-INVERT gate. Each AND gate also contains the buffered and inverted CP and Z-enable (Ez) functions, as well as one of the Select (So —Sa) inputs. The Z output Oz is normally HIGH and goes LOW when CP and Ez are LOWand any of the AND gates has its other inputs HIGH. The AND gates are enabled at different times and different rates relative to the clock. For example, the gate to which So is connected is enabled only when the counter is in state five, assuming that So is HIGH. Thus, during one complete cycle of the counter (10 clocks) the So gate can contribute only pulse to the output rate. The S1 gate is enabled twice per cycle, the Sz gate four times per cycle (etc.). The output pulse rate thus depends on the clock rate and which of the So — So inputs are HIGH, as expressed in the following formula. fout =m * fin where m = S3 © 23 + Sz © 22 +S; #21 + So # 20 Thus by appropriate choice of signals applied to the So — So inputs, the output pulse rate can range from 1/10 to 9/10. of the clock rate. The select codes, m values and Oz pulse pattern are shown in the Pulse Pattern Table. In the Oz pattern, each column represents a clock period, with the state-12 column on the right. A one indicates that the Oz output will be HIGH during that entire clock period, while azero indicates that Oz will be LOW when the clock is LOW during that period. Note that the output pulses are evenly spaced only when m is one or two, assuming that the clock frequency is constant, and that no output pulses can occur in state 12 of the counter. The Y output Oy is the complement of Oz and is thus normally LOW. A LOW signal on the Y-enable input Ey disables Oy. To expand the multiplier to 2-digit rate select, two packages can be cascaded as shown in Figure a. Both circuits operate from the basic clock, with the TC output of the first acting to enable both counting and the ‘output pulses of the second package. Thus the second counter advances at only 1/10 the rate of the first anda full cycle ofthe two counters combined requires 100 clocks. Output pulses contributed by the second counter ‘occur only when the first counter is in state 12. All output pulses are opposite in phase to the clock mse tse enase Bo 8) 82 8 Bo 81 S27 S dfce ce ref + -—ler cH Py i ar de: ev oz oy four crock in Fig. a Cascading tor 2-Digit Rate Select 4-236

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) emeor | ramaweren ee | conormmons los Output Short Circuit Current | -18 55 | = mA_—s|s Vcc = Max Vec = Max; MS = Gnd AC CHARACTERISTICS: Vcc = +5.0 V, Ta = +25°C (See Section 3 for waveforms and load configurations) SYMBOL CL = 15 pF CONDITIONS RL = 4001 a tee Propagation Delay PHL CP to TI tPLH Propagation Delay tPHL Ez to Oy tPHL Ey to Oy Figs $1, 94 tPLH Propagation Delay tPHL Sn to Oz tPLH Propagation Delay tPHL CP to Oy {PL Propagation Delay tPHL Ez to Oz tPHL Sn to Oy Figs. 3:1,3-5 tPLH Propagation Delay (PHL CP to Oz tPLH Propagation Delay tPHL CE to TC Propagation Delay ten MS to TC 27 Propagation Delay . bial MR to Ov Figs. 3-1, 3-16 Propagation Delay 4-237 @— 900469? 0293053 574

AC OPERATING REQUIREMENTS: Vcc = +5.0 V, Ta = 25°C symBoL PARAMETER ee ons | CONDITIONS SE to OP ing f= | = | t ib = ees, TE to CP Rising Fig. b Hold Time HIGH he CE to CP Rising ° tw CP-10 Lom SE to OF Faling | 0 wom] ns | t(D — : 0 tw CP-10 CE to CP Falling Fig. ¢ Hold Time LOW mw CE to CP Falling | = re | om | Inhibit Time HIGH 7 ton | CE to cP Fating pe fee a Ve m tefl) tty tinn¢H) oP Vn = 15 twcP Fig. b ae Vn to( ky to(L) oP Vn =18¥ wee a Fig. c 4-238