54161

54161 NSC | Alldatasheet

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: 2 National > . i Semiconductor a ry a 54161/DM54161A/DM74161A DM54163A/DM74163A Synchronous 4-Bit Counters General Description These synchronous, presettable counters feature an inter- _ put is connected to the clear input to synchronously clear nal carry look-ahead for application in high-speed counting _ the counter to all low outputs. Low-to-high transitions at the designs. The 161A and 163A are 4-bit binary counters. The _clear input of the 163A are also permissible, regardless of carry output is decoded by means of a NOR gate, thus pre- _the logic levels on the clock, enable, or load inputs. venting spikes during the normal counting mode of opera- The carry look-ahead circuitry provides for cascading coun- tion. Synchronous operation is provided by having all flip- ters for n-bit synchronous applications without additional flops clocked simultaneously so that the outputs change co- gating. Instrumental in accomplishing this function are two incident with each other when so instructed by the count- count-enable inputs and a ripple carry output. Both count- enable inputs and internal gating. This mode of operation enable inputs (P and T) must be high to count, and input T is eliminates the output counting spikes which are normally —_feq forward to enable the ripple carry output. The ripple car- associated with asynchronous (ripple clock) counters. A ry output thus enabled will produce a high-level output pulse buffered clock input triggers the four flip-flops on the rising with a duration approximately equal to the high-level portion (positive-going) edge of the clock input waveform. of the Qa output. This high-level overflow ripple carry pulse Thess counters are fully programmable; that is, the outputs —_can be used to enable successive cascaded stages. High- may be preset to either level. As presetting is synchronous, _to-low-level transitions at the enable P or T inputs of the setting up a low level at the load input disables the counter 161A through 163A may occur, regardless of the logic tevel and causes the outputs to agree with the setup data after on the clock the next clock pulse. regardless of the levels of the enable input. Low-to-high transitions at the load input of the 161A Features and 163A are perfectly acceptable, regardless of the logic Synchronously programmable levels on the clock or enable inputs. The clear function for internal look-ahead for fast counting the 1614 is asynchronous; and a low level at the clear inpul 3 C for mbit din sets all four of the flip-flop outputs low, regardless of the Ty output for n-bit cascading levels of clock, Icad, or enable inputs. The clear function for ™ Synchronous counting the 163A is synchronous; and a low level at the clear input Load control line sets all four of the flip-flop outputs low after the next clock ™ Diode-clamped inputs pulse, regardless of the levels of the enable inputs. This m Alternate Military/Aerospace device (54161) is avail- synchronous clear allows the count length to be mositied able. Contact a National Semiconductor Sales Office/ easily, as decoding the maximum count desired can be ac- Distributor for specifications. complished with one external NAND gate. The gate out- Connection Diagram Dual-In-Line Package RIPPLE: OUTPUTS CARRY 9 “+ _ ENABLE. Yoo OUTPUT % % QO % | LOAD 16 15 14 13 12 WY 10 9 1 2 3 4 5 6 7 8 4 | CLEAR CLOCK A 8 c D ENABLE = GND DATA INPUTS , TUF /6551~1 Order Number 54161DMQB, 54161FMQB, DM54161AJ, DM54161AW, DM54163AJ, DM54163AW, DM74161AN or DM74163AN See NS Package Number J16A, N1GE or W16A. 4-159

8 Absolute Maximum Ratings (note)

© | If Milltary/Aerospace specified devices are required, Note: The “Absolute Maximum Ratings” are those values << | please contact the National Semiconductor Sales beyond which the safety of the device cannot be guaran- & | Office/Distributors for availability and specifications. teed. The device should not be operated at these limits. The aa Supply Voltage ~v parametric values defined in the “Electrical: Characteristics” Input Voltage 5.5V ‘eb are not ood Ona bie fescue a nite Operating Free Air Temperature Range the conditions for actual pick operation. DMS54 and 54 —55°C to + 125°C DM74 OC to +70°C Storage Temperature Range —65°C to + 150°C Recommended Operating Conditions | win [Nom [max | win | Nom | Max_| Voc | Suepyvotige | 4s | 5 | 58 | ars | os | 525 |v Via___| High tovotinputvotage | 2 | Te Vi__| townovetinputvottage | | | ow Tf oe lon [| Highteveloutputcurent ||| oe | || -08 | ma lo | towteveloupurcurent | TT te TT tema forx | Glock Frequency (Noes) || | as | oo ||| Me w Pusowisth | Glock | 2s | | dT ows | UT notes) | ow | ao fT me TT teu Seuptime | daa | ao [| rf am | Note) | enabler | oe [Tf ow TT, [tos of os | Ts | tu | Howtimewotos | oo ST TT to Te Tr__| FroeirOperating Temperature | -s5 | | as | o [| wm |

Electrical Characteristics

Over recommended operating free air temperature range (unless otherwise noted) wrt | ree | crete | ome | ay |e | te Voltage Vit = Max, Vin = Min Vor Low Level Output Voc = Min, lo. = Max [eno | veecmutcwer || oe |e | eee eee TT Input Voltage tm High Level Input Voc = Max [enabiot | | | wo | Current Wa 2av ee ee he Low Level Input Vor = Max | enabiot | | | -32 | | otmers | | 16 | 4-160

a Electrical Characteristics > Over recommended operating free air temperature range (unless otherwise noted) (Continued) e Typ 2 ry Symbol Parameter | contnone || (Note 1) ums 5 loon Supply Curent Voo=mex | owes | [se fs Ty lect Supply Curent Voo=max [owes [7 [ee [aT winOuputsiow | ote) owe [ [es [tor | Note 1: All typicals are at Voc = 5V, Ta = 25°C. Note 2: Not more than one output should be shorted at a time. Note 3: Iccx is measured with the LOAD high, then again with the LOAD low, with all inputs high and all outputs open. Note 4: loci is measured with the CLOCK high, then again with the CLOCK input low, with all inputs low and all outputs open. Note §: Applies to "163A which has synchronous clear inputs, Note 6: Ta = 25°C and Voc = 5V. Switching Characteristics at voc = sv and T, = 25°C (See Section 1 for Test Waveforms and Output Load) ‘Symbol From (Input) Ry = 4000, C, = 15 pF Units recoup) [wn [| “nn Frown) a Mie Frequency teu Propagation Delay Time Clock to 27 hs Low to High Level Output Ripple Carry tPHL Propagation Delay Time Clock to ns High to Low Level Output Ripple Carry tPLH Propagation Delay Time Clock ns Low to High Level Output (Load High) to Q tex Propagation Delay Time Clock hs High to Low Level Output (Load High) to Q tpLH Propagation Delay Time Clock a1 ns Low to High Level Output (Load Low) toQ tpHL Propagation Delay Time Clock 32 ns High to Low Level Output (Load Low) toQ te Propagation Delay Time Enable T to 16 ns Low to High Level Output Ripple Carry tPHL Propagation Delay Time Enable T to ns High to Low Level Output Ripple Carry tPHL Propagation Delay Time Clear (Note 7) ns High to Low Level Output toQ Note 7: Propagation delay for clearing is measured from the clear input for the 161A or trom the clock input transition for the 163A, 4-161

©| Logic Diagrams < 161A oe oon 7) a HDS, | len (4) OR a 7] tt Wiese Db: T ; (3) ne HN — f+ - iit. (6) | ro | >o + CLEAR [ee Dot 4-162

Logic Diagrams (continued) 2 e 163A Fa > r> cLock @ Hl = et Hees [o> aoe” 7) We D | { ° | Cl> CLOCK 7 i L ‘ o> P= Poot: LoaD ‘CLEAR: rel a: Sal eed (10) (free ia ci> cLock catac © ttt line a Hes Lt — DATAD © cate) a [is=d=>. J curaR mes 4 4-163

©| Logic Diagrams (continued) e = 161A, 163A Synchronous Binary Counters o syn = Typical Clear, Preset, Count and Inhibit Sequences aur (ASYNCHRONOUS) CLEAR 163A (ASYNCHRONOUS) LOAD A EIIIIIIIIIIIIIIIIIDIIIIIIIIIII IE. paral ® Swe wenn nrc cewcec cee rccccccccenas INPUTS ee www ewww ewww neem e eee eccees € Be wcccccccw ccc cccccceccccnnensces > STITIDIDIIIIIDIIIIIIIIIIIIIIIIITS cLock 161A Lock 165A ENABLE P ENABLE T O%LIIIZ Qrcosle OUTPUTS: emeeee Comeces 0222222 RIPPLE CARRY OUTPUT 12 [13 14 15 0 1 2 COUNT INHIBIT ———-> CLEAR PRESET TUF /6551-5 4-164

a Parameter Measurement information > ‘Switching Time Waveforms hed tw (cLocx) > 3.0v ——— clock INPUT Veer Veer Veer ov foun \\ ‘PHL (WEASURE AT tys 1) (MEASURE AT tye 2) Vou ‘OUTPUT Vou tpn tru \\ (MEASURE AT tus 4) (MEASURE AT tye 9) ‘ow ourPuT ¥, v, % | | il iad Vou. teu foun (MEASURE AT tys g) (MEASURE AT tys 4) Vou v o PHL (MEASURE AT ths 19 tun y OR tye1¢) (NOTE B) (MEASURE AT tys g) on You fue ten (MEASURE AT tus 10 You OR tye 46) (NOTE 8) RIPPLE CARRY VRer VRer OUTPUT yo 2 TUF /6551-6 Note A: The input pulses are supplied by generators having the following characteristics: PRR < 1 MHz, duty cycle < 50%, Zoyr = 50M. For 161A and 163A, t < 10 ns, < 10 ns. Vary PRR to measure fax. Note B: Outputs Qp and carry are tested at tn+ 1g for 161A, 163A where tn is the bit ime when all outputs are low. Note C: For 161A and 163A, VagF = 1.5V. 4-165

© | Parameter Measurement Information (continued) e o Switching Time Waveforms ha 3.0¥ CLOCK INPUT 161A Veer“ Yrer YRer W—| sow 1 Mect00n) R ger Vrer Veer VRer iad /| ‘serve 3.0. ———" wecuear) LOAD Veer INPUT h—| 3.0V a ‘sewur OATA INPUTS y ‘A,B, © AND D REF ov, t You mu Q OUTPUTS . ¥, 161A ef REF Ty ENABLE P OR ENABLE T | | | er “eer ov. — | te Vou Vou I= tserup 3.0¥ CLOCK INPUT 163A, VReF Yrer Veer ov___ y toa —| trun ‘OH Q OUTPUTS 163A Vrer VRer Vou true —l te (MEASURE AT tug OR tyg4) TUF/6551-7 Note A: The input pulses are supplied by generators having the following characteristics: PRR < 1 MHz, duty cycle < 50%, Zour = 50M. For 161A and 163A, | < 10 ns, ty < 10 ns. Vary PAR to measure fyax. Note B: Enable P and enable T setup times are measured at tn +o- Note C: For 161A and 163A, Ver = 1.5V. 4-166