EL5111_07 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Pb-free plus anneal available (RoHS compliant)
  • 60MHz -3dB bandwidth
  • Supply voltage = 4.5V to 16.5V
  • Low supply current (per amplifier) = 2.5mA
  • High slew rate = 75V/µs
  • Unity-gain stable
  • Beyond the rails input capability
  • Rail-to-rail output swing
  • ±180mA output short current

Applications

  • TFT-LCD panels
  • V COM amplifiers
  • Drivers for A-to-D converters
  • Data acquisition
  • Video processing
  • Audio processing
  • Active filters
  • Test equipment
  • Battery-powered applications
  • Portable equipment Pinouts EL5111 (8 LD HMSOP) TOP VIEW NC VS+ VOUT NCVS- VIN+ VIN- NC EL5111 (5 LD TSOT) TOP VIEW VIN+ VS- VOUT VIN- VS+ EL5211 (8 LD HMSOP) TOP VIEW VS+ VOUTB VINB- VINB+VS- VINA+ VINA- VOUTA EL5411 (14 LD HTSSOP) TOP VIEW VS-VS+ VINB+ VINB- VOUTB VINA+ VINA- VOUTA VINC+ VINC- VOUTC VIND+ VIND- VOUTD Data Sheet January 10, 2007 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

Ordering Information

PART NUMBER PART MARKING TAPE & REEL PACKAGE PKG. DWG. # EL5111IWT-T7 8 7” (3k pcs) 5 Ld TSOT MDP0049 EL5111IWT-T7A 8 7” (250 pcs) 5 Ld TSOT MDP0049 EL5111IWTZ-T7 (Note) BAAG 7” (3k pcs) 5 Ld TSOT (Pb-free) MDP0049 EL5111IWTZ-T7A (Note) BAAG 7” (250 pcs) 5 Ld TSOT (Pb-free) MDP0049 EL5111IYE 7 - 8 Ld HMSOP MDP0050 EL5111IYE-T7 7 7” 8 Ld HMSOP MDP0050 EL5111IYE-T13 7 13” 8 Ld HMSOP MDP0050 EL5111IYEZ (Note) BAAJA - 8 Ld HMSOP (Pb-free) MDP0050 EL5111IYEZ-T7 (Note) BAAJA 7” 8 Ld HMSOP (Pb-free) MDP0050 EL5111IYEZ-T13 (Note) BAAJA 13” 8 Ld HMSOP (Pb-free) MDP0050 EL5211IYE 9 - 8 Ld HMSOP MDP0050 EL5211IYE-T7 9 7” 8 Ld HMSOP MDP0050 EL5211IYE-T13 9 13” 8 Ld HMSOP MDP0050 EL5211IYEZ (Note) BAATA - 8 Ld HMSOP (Pb-free) MDP0050 EL5211IYEZ-T7 (Note) BAATA 7” 8 Ld HMSOP (Pb-free) MDP0050 EL5211IYEZ-T13 (Note) BAATA 13” 8 Ld HMSOP (Pb-free) MDP0050 EL5211AIYEZ (Note) BBLAA - 8 Ld HMSOP (Pb-free) MDP0050 EL5211AIYEZ-T7 (Note) BBLAA 7” 8 Ld HMSOP (Pb-free) MDP0050 EL5211AIYEZ-T13 (Note) BBLAA 13” 8 Ld HMSOP (Pb-free) MDP0050 EL5411IRE 5411IRE - 14 Ld HTSSOP MDP0048 EL5411IRE-T7 5411IRE 7” 14 Ld HTSSOP MDP0048 EL5411IRE-T13 5411IRE 13” 14 Ld HTSSOP MDP0048 EL5411IREZ (Note) 5411IREZ - 14 Ld HTSSOP (Pb-free) MDP0048 EL5411IREZ-T7 (Note) 5411IREZ 7” 14 Ld HTSSOP (Pb-free) MDP0048 EL5411IREZ-T13 (Note) 5411IREZ 13” 14 Ld HTSSOP (Pb-free) MDP0048 EL5411IR 5411IR - 14 Ld TSSOP MDP0044 EL5411IR-T7 5411IR 7” 14 Ld TSSOP MDP0044 EL5411IR-T13 5411IR 13” 14 Ld TSSOP MDP0044 EL5411IRZ (Note) 5411IRZ - 14 Ld TSSOP (Pb-free) M14.173 EL5411IRZ-T7 (Note) 5411IRZ 7” 14 Ld TSSOP (Pb-free) M14.173 EL5411IRZ-T13 (Note) 5411IRZ 13” 14 Ld TSSOP (Pb-free) M14.173 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN7119.5 January 10, 2007 EL5111, EL5211, EL5411

Absolute Maximum Ratings (TA = +25°C) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 3 FN7119.5 January 10, 2007 IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications VS+ = +5V, VS- = -5V, RL = 1kΩ to 0V, TA = +25°C, Unless Otherwise Specified PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 0V 3 15 mV TCVOS Average Offset Voltage Drift (Note 1) 7 µV/°C IB Input Bias Current VCM = 0V 2 60 nA RIN Input Impedance 1 GΩ CIN Input Capacitance 2 pF CMIR Common-Mode Input Range -5.5 +5.5 V CMRR Common-Mode Rejection Ratio for VIN from -5.5V to 5.5V 50 70 dB AVOL Open-Loop Gain -4.5V ≤ VOUT ≤ 4.5V 62 70 dB OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA -4.92 -4.85 V VOH Output Swing High IL = 5mA 4.85 4.92 V ISC Short-Circuit Current ±180 mA IOUT Output Current ±65 mA POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from ±2.25V to ±7.75V 60 80 dB IS Supply Current No load (EL5111) 2.5 4.5 mA No load (EL5211) 5 7.5 mA No load (EL5411) 10 15 mA DYNAMIC PERFORMANCE SR Slew Rate (Note 2) -4.0V ≤ VOUT ≤ 4.0V, 20% to 80% 75 V/µs tS Settling to +0.1% (AV = +1) (AV = +1), VO = 2V step 80 ns BW -3dB Bandwidth 60 MHz GBWP Gain-Bandwidth Product 32 MHz PM Phase Margin 50 ° CS Channel Separation f = 5MHz (EL5211 and EL5411 only) 110 dB dG Differential Gain (Note 3) RF = RG = 1kΩ and VOUT = 1.4V 0.17 % dP Differential Phase (Note 3) RF = RG = 1kΩ and VOUT = 1.4V 0.24 ° NOTES: 1. Measured over operating temperature range. 2. Slew rate is measured on rising and falling edges. 3. NTSC signal generator used. EL5111, EL5211, EL5411

Electrical Specifications VS+ = +5V, VS- = 0V, RL = 1kΩ to 2.5V, TA = +25°C, Unless Otherwise Specified PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 2.5V 3 15 mV TCVOS Average Offset Voltage Drift (Note 4) 7 µV/°C IB Input Bias Current VCM = 2.5V 2 60 nA RIN Input Impedance 1 GΩ CIN Input Capacitance 2 pF CMIR Common-Mode Input Range -0.5 +5.5 V CMRR Common-Mode Rejection Ratio for VIN from -0.5V to 5.5V 45 66 dB AVOL Open-Loop Gain 0.5V ≤ VOUT ≤ 4.5V 62 70 dB OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA 80 150 mV VOH Output Swing High IL = 5mA 4.85 4.92 V ISC Short-circuit Current ±180 mA IOUT Output Current ±65 mA POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from 4.5V to 15.5V 60 80 dB IS Supply Current No load (EL5111) 2.5 4.5 mA No load (EL5211) 5 7.5 mA No load (EL5411) 10 15 mA DYNAMIC PERFORMANCE SR Slew Rate (Note 5) 1V ≤ VOUT ≤ 4V, 20% to 80% 75 V/µs tS Settling to +0.1% (AV = +1) (AV = +1), VO = 2V step 80 ns BW -3dB Bandwidth 60 MHz GBWP Gain-Bandwidth Product 32 MHz PM Phase Margin 50 ° CS Channel Separation f = 5MHz (EL5211 and EL5411 only) 110 dB dG Differential Gain (Note 6) RF = RG = 1kΩ and VOUT = 1.4V 0.17 % dP Differential Phase (Note 6) RF = RG = 1kΩ and VOUT = 1.4V 0.24 ° NOTES: 4. Measured over operating temperature range. 5. Slew rate is measured on rising and falling edges. 6. NTSC signal generator used. 4 FN7119.5 January 10, 2007 EL5111, EL5211, EL5411

Electrical Specifications VS+ = +15V, VS- = 0V, RL = 1kΩ to 7.5V, TA = +25°C, Unless Otherwise Specified PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 7.5V 3 15 mV TCVOS Average Offset Voltage Drift (Note 7) 7 µV/°C IB Input Bias Current VCM = 7.5V 2 60 nA RIN Input Impedance 1 GΩ CIN Input Capacitance 2 pF CMIR Common-Mode Input Range -0.5 +15.5 V CMRR Common-Mode Rejection Ratio for VIN from -0.5V to 15.5V 53 72 dB AVOL Open-Loop Gain 0.5V ≤ VOUT ≤ 14.5V 62 70 dB OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA 80 150 mV VOH Output Swing High IL = 5mA 14.85 14.92 V ISC Short-circuit Current ±180 mA IOUT Output Current ±65 mA POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from 4.5V to 15.5V 60 80 dB IS Supply Current No load (EL5111) 2.5 4.5 mA No load (EL5211) 5 7.5 mA No load (EL5411) 10 15 mA DYNAMIC PERFORMANCE SR Slew Rate (Note 8) 1V ≤ VOUT ≤ 14V, 20% to 80% 75 V/µs tS Settling to +0.1% (AV = +1) (AV = +1), VO = 2V step 80 ns BW -3dB Bandwidth 60 MHz GBWP Gain-Bandwidth Product 32 MHz PM Phase Margin 50 ° CS Channel Separation f = 5MHz (EL5211 and EL5411 only) 110 dB dG Differential Gain (Note 9) RF = RG = 1kΩ and VOUT = 1.4V 0.16 % dP Differential Phase (Note 9) RF = RG = 1kΩ and VOUT = 1.4V 0.22 ° NOTES: 7. Measured over operating temperature range 8. Slew rate is measured on rising and falling edges 9. NTSC signal generator used 5 FN7119.5 January 10, 2007 EL5111, EL5211, EL5411

10 FN7119.5 January 10, 2007 FIGURE 25. 50ns/DIV 1V STEP VS=±5V TA=+25°C AV=1 RL=1kΩ LARGE SIGNAL TRANSIENT RESPONSE FIGURE 26. 50ns/DIV 100mV STEP VS=±5V TA=+25°C AV=1 RL=1kΩ SMALL SIGNAL TRANSIENT RESPONSE Pin Descriptions EL5111 (TSOT-5) EL5111 (HMSOP8) EL5211 (HMSOP8) EL5411 ( HTSSOP14) NAME FUNCTION EQUIVALENT CIRCUIT 1 6 1 1 VOUTA Amplifier A output VS+ GND VS- CIRCUIT 1 4 2 2 2 VINA- Amplifier A inverting input VS+ VS- CIRCUIT 2 3 3 3 3 VINA+ Amplifier A non-inverting input (Reference Circuit 2) 5 7 8 4 VS+ Positive power supply 5 5 VINB+ Amplifier B non-inverting input (Reference Circuit 2) 6 6 VINB- Amplifier B inverting input (Reference Circuit 2) 7 7 VOUTB Amplifier B output (Reference Circuit 1)

8 VOUTC Amplifier C output (Reference Circuit 1)

9 VINC- Amplifier C inverting input (Reference Circuit 2)

10 VINC+ Amplifier C non-inverting input (Reference Circuit 2)

2 4 4 11 VS- Negative power supply

12 VIND+ Amplifier D non-inverting input (Reference Circuit 2)

13 VIND- Amplifier D inverting input (Reference Circuit 2)

14 VOUTD Amplifier D output (Reference Circuit 1)

1, 5, 8 NC Not connected Typical Performance Curves (Continued) EL5111, EL5211, EL5411

14 FN7119.5 January 10, 2007 EL5111, EL5211, EL5411 Thin Shrink Small Outline Package Family (TSSOP) N (N/2)+1 (N/2) TOP VIEW AD 0.20 C B A N/2 LEAD TIPSB E1E

0.25 CABM

H PIN #1 I.D. 0.05 eC 0.10 C N LEADS SIDE VIEW

0.10 CABMb

c SEE DETAIL “X” END VIEW DETAIL X 0° - 8° GAUGE PLANE 0.25 LA1 A SEATING PLANE MDP0044 THIN SHRINK SMALL OUTLINE PACKAGE FAMILY SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE Rev. E 12/02 NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M -1994.

15 FN7119.5 January 10, 2007 HTSSOP (Heat-Sink TSSOP) Family N (N/2)+1 (N/2) TOP VIEW AD 0.20 C B A N/2 LEAD TIPSB E1E H PIN #1 I.D. 0.05 eC 0.10 C N LEADS SIDE VIEW c SEE DETAIL “X” END VIEW DETAIL X 0° - 8° GAUGE PLANE 0.25 LA1 A SEATING PLANE BOTTOM VIEW EXPOSED THERMAL PAD MDP0048 HTSSOP (Heat-Sink TSSOP) Family SYMBOL 14 LD 20 LD 24 LD 28 LD 38 LD TOLERANCE N 1 42 02 42 83 8R e f e r e n c e Rev. 2 12/03 NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. 3. Dimensions “D” and “E1” are measured at Datum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M -1994. EL5111, EL5211, EL5411

16 FN7119.5 January 10, 2007 EL5111, EL5211, EL5411 N A D E (N/2)21 0.15 DC 0.25 C 2X N/2 TIPSe B ddd M DC A-B b NX 2 3 SEATING PLANE 0.10 C NX 1 3 C D

0.15 A-BC

H c (L1) L 0.25 4° ±4° GAUGE PLANE A MDP0049 TSOT PACKAGE FAMILY SYMBOL TSOT5 TSOT6 TSOT8 TOLERANCE A 1.00 1.00 1.00 Max A1 0.05 0.05 0.05 ±0.05 A2 0.87 0.87 0.87 ±0.03 b 0.38 0.38 0.29 ±0.07 D 2.90 2.90 2.90 Basic E 2.80 2.80 2.80 Basic E1 1.60 1.60 1.60 Basic e 0.95 0.95 0.65 Basic e1 1.90 1.90 1.95 Basic L 0.40 0.40 0.40 ±0.10 L1 0.60 0.60 0.60 Reference ddd 0.20 0.20 0.13 - N 5 6 8 Reference Rev. A 12/02 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. 2. Plastic interlead protrusions of 0.15mm maximum per side are not included. 3. This dimension is measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Index area - Pin #1 I.D. will be located within the indicated zone (TSOT6 AND TSOT8 only). 6. TSOT5 version has no center lead (shown as a dashed line).

17 FN7119.5 January 10, 2007 EL5111, EL5211, EL5411 HMSOP (Heat-Sink MSOP) Package Family (N/2) (N/2)+1 N PLANE SEATING N LEADS 0.10 C PIN #1 I.D. E b DETAIL X3° ±3° GAUGE PLANE SEE DETAIL "X" c A 0.25 A1L

0.25 C A B

D A M B e C

0.08 C A BM

H END VIEW SIDE VIEW TOP VIEW BOTTOM VIEW EXPOSED THERMAL PAD MDP0050 HMSOP (HEAT-SINK MSOP) PACKAGE FAMILY SYMBOL HMSOP8 HMSOP10 TOLERANCE NOTES A1 . 0 0 1 . 0 0 M a x . - A2 0.86 0.86 ±0.09 - c0 . 1 5 0 . 1 5 ± 0 . 0 5 - D 3.00 3.00 ±0.10 1, 3 D1 1.85 1.85 Reference - E4 . 9 0 4 . 9 0 ± 0 . 1 5 - E1 3.00 3.00 ±0.10 2, 3 E2 1.73 1.73 Reference - e0 . 6 5 0 . 5 0 B a s i c - L0 . 5 5 0 . 5 5 ± 0 . 1 5 - L1 0.95 0.95 Basic - N 8 10 Reference - Rev. 0 10/03 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7119.5 January 10, 2007 EL5111, EL5211, EL5411 Thin Shrink Small Outline Plastic Packages (TSSOP) α INDEX AREA D N 123 -B- 0.10(0.004) C AM BS e -A- b M -C- A SEATING PLANE 0.10(0.004) c E 0.25(0.010) BM M L 0.25 0.010 GAUGE PLANE NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen- sion at maximum material condition. Minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIME TER. Converted inch dimensions are not necessarily exact. (Angles in degrees) 0.05(0.002) M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC

A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.195 0.199 4.95 5.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 N1 4 1 4 7 α 0o 8o 0o 8o - Rev. 2 4/06