EL5102_06 INTERSIL | Alldatasheet

Document overview

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  • PDF pages: 17

Technical content

Features

  • Operates off 3V, 5V, or ±5V applications
  • Power-down to 0µA (EL5x02)
  • -3dB bandwidth = 400MHz
  • ±0.1dB bandwidth = 50MHz
  • Low supply current = 5mA
  • Slew rate = 3500V/µs
  • Low offset voltage = 5mV max
  • Output current = 140mA VOL = 2000
  • Diff gain/phase = 0.01%/0.01°
  • Pb-Free plus anneal available (RoHS compliant)

Applications

  • Video amplifiers
  • PCMCIA applications
  • A / D d r i v e r s
  • Line drivers
  • Portable computers
  • High speed communications
  • RGB applications
  • Broadcast equipment
  • Active filtering Data Sheet June 23, 2006

2 FN7331.6 June 23, 2006

Ordering Information

TAPE & REEL PKG. DWG. # EL5102IS 5102IS 8 Ld SOIC - MDP0027 EL5102IS-T7 5102IS 8 Ld SOIC 7” MDP0027 EL5102IS-T13 5102IS 8 Ld SOIC 13” MDP0027 EL5102ISZ (See Note) 5102ISZ 8 Ld SOIC (Pb-free) - MDP0027 EL5102ISZ-T7 (See Note) 5102ISZ 8 Ld SOIC (Pb-free) 7” MDP0027 EL5102ISZ-T13 (See Note) 5102ISZ 8 Ld SOIC (Pb-free) 13” MDP0027 EL5102IW-T7 q 6 Ld SOT-23 7” (3K pcs) MDP0038 EL5102IW-T7A q 6 Ld SOT-23 7” (250 pcs) MDP0038 EL5102IWZ-T7 (See Note) BBSA 6 Ld SOT-23 (Pb-free) (3K pcs) MDP0038 EL5102IWZ-T7A (See Note) BBSA 6 Ld SOT-23 (Pb-free) (250 pcs) MDP0038 EL5103IC-T7 B 5 Ld SC-70 7” (3K pcs) P5.049 EL5103IC-T7A B 5 Ld SC-70 7” (250 pcs) P5.049 EL5103IW-T7 g 5 Ld SOT-23 7” (3K pcs) MDP0038 EL5103IWZ-T7 BBTA 5 Ld SOT-23 (Pb-free) (3K pcs) MDP0038 EL5103IWZ-T7A BBTA 5 Ld SOT-23 (Pb-free) (250 pcs) MDP0038 EL5202IY BRAAA 10 Ld MSOP - MDP0043 EL5202IY-T7 BRAAA 10 Ld MSOP 7” MDP0043 EL5202IY-T13 BRAAA 10 Ld MSOP 13” MDP0043 EL5202IYZ (See Note) BAAAD 10 Ld MSOP (Pb-free) - MDP0043 EL5202IYZ-T7 (See Note) BAAAD 10 Ld MSOP (Pb-free) 7” MDP0043 EL5202IYZ-T13 (See Note) BAAAD 10 Ld MSOP (Pb-free) 13” MDP0043 EL5203IS 5203IS 8 Ld SOIC - MDP0027 EL5203IS-T7 5203IS 8 Ld SOIC 7” MDP0027 EL5203IS-T13 5203IS 8 Ld SOIC 13” MDP0027 EL5203ISZ (See Note) 5203ISZ 8 Ld SOIC (Pb-free) - MDP0027 EL5203ISZ-T7 (See Note) 5203ISZ 8 Ld SOIC (Pb-free) 7” MDP0027 EL5203ISZ-T13 (See Note) 5203ISZ 8 Ld SOIC (Pb-free) 13” MDP0027 EL5203IY BSAAA 8 Ld MSOP - MDP0043 EL5203IY-T7 BSAAA 8 Ld MSOP 7” MDP0043 EL5203IY-T13 BSAAA 8 Ld MSOP 13” MDP0043 EL5203IYZ (See Note) BAAAE 8 Ld MSOP (Pb-free) - MDP0043 EL5203IYZ-T7 (See Note) BAAAE 8 Ld MSOP (Pb-free) 7” MDP0043 EL5203IYZ-T13 (See Note) BAAAE 8 Ld MSOP (Pb-free) 13” MDP0043 EL5302IU 5302IU 16 Ld QSOP - MDP0040 EL5302IU-T7 5302IU 16 Ld QSOP 7” MDP0040 EL5302IU-T13 5302IU 16 Ld QSOP 13” MDP0040 EL5302IUZ (See Note) 5302IUZ 16 Ld QSOP (Pb-free) - MDP0040 EL5302IUZ-T7 (See Note) 5302IUZ 16 Ld QSOP (Pb-free) 7” MDP0040 EL5302IUZ-T13 (See Note) 5302IUZ 16 Ld QSOP (Pb-free) 13” MDP0040 NOTE: Intersil Pb-free plus anneal pr oducts employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 Ordering Information (Continued) PART NUMBER PART MARKING PACKAGE TAPE & REEL PKG. DWG. # EL5102, EL5103, EL5202, EL5203, EL5302

3 FN7331.6 June 23, 2006 Pinouts EL5102 (6 LD SOT-23) TOP VIEW EL5103 (5 LD SOT-23) TOP VIEW EL5102 (8 LD SOIC) TOP VIEW EL5203 (8 LD SOIC, MSOP) TOP VIEW EL5202 (10 LD MSOP) TOP VIEW EL5302 (16 LD QSOP) TOP VIEW OUT VS- IN+ VS+ CE IN- VS+OUT IN-IN+ VS- CE VS+ OUT NC NC IN- IN+ VS- OUTA INA- INA+ VS- VS+ OUTB INB- INB+ 5 6 OUT IN- IN+ VS- VS+ OUT IN- IN+ CE CE 8 9 INA+ CEA VS- CEB INA- OUTA VS+ OUTB INB+ NC CEC INC+ INB- NC OUTC INC- EL5102, EL5103, EL5202, EL5203, EL5302

4 FN7331.6 June 23, 2006 Absolute Maximum Ratings (TA = 25°C) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. U nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT VOS Offset Voltage EL5102, EL5103, EL5202, EL5203 1 5 mV EL5302 2 8 mV TCVOS Offset Voltage Temperature Coefficient Measured from T MIN to TMAX 10 µV/°C IB Input Bias Current V IN = 0V -12 2 12 µA IOS Input Offset Current V IN = 0V -8 1 8 µA TCIOS Input Bias Current Temperature Coefficient Measured from TMIN to TMAX 50 nA/°C PSRR Power Supply Rejection Ratio V S = ±4.75V to ±5.25V -70 -80 dB CMRR Common Mode Rejection Ratio V CM = -3V to 3.0V -60 -80 dB CMIR Common Mode Input Range Guaranteed by CMRR test -3 ±3.3 3 V RIN Input Resistance Common mode 200 400 k Ω CIN Input Capacitance SO package 1 pF IS,ON Supply Current - Enabled per amplifier 4.6 5.2 5.8 mA IS,OFF Supply Current - Shut-down per amplifier V S++ 1 0 + 2 5 µ A VS-- 2 5 7 - 1 µ A AVOL Open Loop Gain V OUT = ±2.5V, RL = 1kΩ to GND 58 66 dB VOUT = ±2.5V, RL = 150Ω to GND 60 dB VOUT Output Voltage Swing R L = 1kΩ to GND ±3.5 ±3.9 V RL = 150Ω to GND ±3.4 ±3.7 V IOUT Output Current A V = 1, RL = 10Ω to 0V ±80 ±150 mA VCE-ON CE Pin Voltage for Power-up (V S+)-5 (V S+)-3 V VCE-OFF CE Pin Voltage for Shut-down (V S+)-1 V S+V IEN-ON Pin Current - Enabled CE = 0V -1 0 +1 µA IEN-OFF Pin Current - Disabled CE = +5V 1 14 25 µA EL5102, EL5103, EL5202, EL5203, EL5302

5 FN7331.6 June 23, 2006 Closed Loop AC Electrical Specifications VS+ = +5V, VS- = -5V, TA = 25°C, VENABLE = +5V, AV = +1, RF = 0Ω, RL = 150Ω to GND pin, unless otherwise specified. (Note 1) PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT BW -3dB Bandwidth (V OUT = 400mVP-P)A V = 1, RF = 0Ω 400 MHz SR Slew Rate A V = +2, RL = 100Ω, VOUT = -3V to +3V 1100 2200 5000 V/µs RL = 500Ω, VOUT = -3V to +3V 4000 V/µs tR,tF Rise Time, Fall Time ±0.1V step 2.8 ns OS Overshoot ±0.1V step 10 % tS 0.1% Settling Time V S = ±5V, RL = 500Ω, AV = 1, VOUT = ±3V 20 ns dG Differential Gain (Note 2) A V = 2, RF = 1kΩ 0.01 % dP Differential Phase (Note 2) A V = 2, RF = 1kΩ 0.01 ° eN Input Noise Voltage f = 10kHz 12 nV/ √Hz iN Input Noise Current f = 10kHz 11 pA/ √Hz tDIS Disable Time (Note 3) 50 ns tEN Enable Time (Note 3) 25 ns NOTES: 1. All AC tests are performed on a “warmed up” part, except slew rate, which is pulse tested. 3. Disable/Enable time is defined as the time from when the logic signal is applied to the ENABLE pin to when the supply current has reached half its final value. EL5102, EL5103, EL5202, EL5203, EL5302

13 FN7331.6 June 23, 2006 N A D E 321 0.15 DC 0.20 C 2Xe B 0.20 M DC A-B b NX 2 3 SEATING PLANE 0.10 C NX 1 3 C D

0.15 A-BC

H c (L1) L 0.25 0° +3°-0° GAUGE PLANE A MDP0038 SOT-23 PACKAGE FAMILY SYMBOL SOT23-5 SOT23-6 TOLERANCE A 1.45 1.45 MAX A1 0.10 0.10 ±0.05 A2 1.14 1.14 ±0.15 b 0.40 0.40 ±0.05 c 0.14 0.14 ±0.06 D 2.90 2.90 Basic E 2.80 2.80 Basic E1 1.60 1.60 Basic e 0.95 0.95 Basic e1 1.90 1.90 Basic L 0.45 0.45 ±0.10 L1 0.60 0.60 Reference N 5 6 Reference Rev. E 3/00 NOTES: 1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only). 6. SOT23-5 version has no center lead (shown as a dashed line). EL5102, EL5103, EL5202, EL5203, EL5302

14 FN7331.6 June 23, 2006 EL5102, EL5103, EL5202, EL5203, EL5302 Quarter Size Outline Plastic Packages Family (QSOP)

0.010 C A B

1 (N/2) (N/2)+1N PIN #1 I.D. MARK b 0.004 C c A SEE DETAIL "X" 4°±4° GAUGE PLANE 0.010 LA1 D B H C e A

0.007 C A B

QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES A 0.068 0.068 0.068 Max. - A1 0.006 0.006 0.006 ±0.002 - A2 0.056 0.056 0.056 ±0.004 - b 0.010 0.010 0.010 ±0.002 - c 0.008 0.008 0.008 ±0.001 - D 0.193 0.341 0.390 ±0.004 1, 3 E 0.236 0.236 0.236 ±0.008 - E1 0.154 0.154 0.154 ±0.004 2, 3 e 0.025 0.025 0.025 Basic - L 0.025 0.025 0.025 ±0.009 - L1 0.041 0.041 0.041 Basic - N 16 24 28 Reference - Rev. E 3/01 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994.

15 FN7331.6 June 23, 2006 EL5102, EL5103, EL5202, EL5203, EL5302 Mini SO Package Family (MSOP) (N/2) (N/2)+1 N PLANE SEATING N LEADS 0.10 C PIN #1 I.D. E1E b DETAIL X 3° ±3° GAUGE PLANE SEE DETAIL "X" c A 0.25 A1 L

0.25 C A B

D AM B e C

0.08 C A BM

H MDP0043 MINI SO PACKAGE FAMILY SYMBOL MSOP8 MSOP10 TOLERANCE NOTES A1 . 1 0 1 . 1 0 M a x . - A1 0.10 0.10 ±0.05 - A2 0.86 0.86 ±0.09 - c0 . 1 8 0 . 1 8 ± 0 . 0 5 - D 3.00 3.00 ±0.10 1, 3 E4 . 9 0 4 . 9 0 ± 0 . 1 5 - E1 3.00 3.00 ±0.10 2, 3 e0 . 6 5 0 . 5 0 B a s i c - L0 . 5 5 0 . 5 5 ± 0 . 1 5 - L1 0.95 0.95 Basic - N 8 10 Reference - Rev. C 6/99 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994.

16 FN7331.6 June 23, 2006 EL5102, EL5103, EL5202, EL5203, EL5302 Small Outline Package Family (SO) GAUGE PLANE A1 L DETAIL X 4° ±4° SEATING PLANE e H b C 0.010 BM CA0.004 C

0.010 BM CA

B D (N/2)1 E1E NN (N/2)+1 A PIN #1 I.D. MARK h X 45° A SEE DETAIL “X” c 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES N 8 14 16 16 20 24 28 Reference - Rev. L 2/01 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M -1994

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7331.6 June 23, 2006 EL5102, EL5103, EL5202, EL5203, EL5302 Small Outline Transistor Plastic Packages (SC70-5) D E E1CL C CL e b CL A2A A1 CL 0.20 (0.008) M 0.10 (0.004) C C -C- SEATING PLANE 12 3 VIEW C VIEW C L R 4X θ1 4X θ1 GAUGE PLANE SEATING α L2C PLANE c BASE METAL WITH b1PLATING b P5.049

5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE

A 0.031 0.043 0.80 1.10 - A1 0.000 0.004 0.00 0.10 - A2 0.031 0.039 0.80 1.00 - b 0.006 0.012 0.15 0.30 - b1 0.006 0.010 0.15 0.25 c 0.003 0.009 0.08 0.22 6 c1 0.003 0.009 0.08 0.20 6 D 0.073 0.085 1.85 2.15 3 E 0.071 0.094 1.80 2.40 - E1 0.045 0.053 1.15 1.35 3 e 0.0256 Ref 0.65 Ref - e1 0.0512 Ref 1.30 Ref - L 0.010 0.018 0.26 0.46 4 L1 0.017 Ref. 0.420 Ref. - L2 0.006 BSC 0.15 BSC α 0o 8o 0o 8o - N5 5 5 R 0.004 - 0.10 - R1 0.004 0.010 0.15 0.25 Rev. 2 9/03 NOTES: 1. Dimensioning and tolerances per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC70 and JEDEC MO-203AA. 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. 4. Footlength L measured at reference to gauge plane. 5. “N” is the number of terminal positions. 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIME TER. Converted inch dimen- sions are for reference only.