ICS514 IDT | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 7

Technical content

Features

  • Packaged as 8-pin SOIC or die
  • Pb (lead) free package
  • IDT’s lowest cost PLL clock plus reference
  • Produces common computer frequencies
  • Input crystal frequency typically 14.3182 MHz
  • Output clock frequencies up to 66.66 MHz from a

14.3182 MHz crystal or input clock

  • Low jitter of 50 ps (one sigma)
  • Compatible with all popular CPUs
  • Duty cycle of 45/55
  • Custom frequencies available
  • Operating voltage of 3.3 V to 5.5 V
  • Power-down mode turns off chip
  • 25 mA drive capability at TTL levels
  • Advanced, low-power CMOS process Block Diagram CLK PLL Clock Synthesis and Control Circuitry

14.31818 MHz crystal

S1:0 X1/ICLK Optional crystal capacitors REF

LOCO™ PLL CLOCK GENERA TOR CLOCK MULTIPLIER IDT™ / ICS™ LOCO™ PLL CLOCK GENERATOR 2 ICS514 REV G 051310 Pin Assignment Clock Decoding Table (MHz) with 14.31818 MHz Crystal or Clock Input 0 = connect directly to ground 1 = connect directly to VDD M = leave unconnected (floating) CLK and REF stop low in power-down state Pin Descriptions Notes: 1. With S1 = S0 = 0, the internal PLL is turned off and the CLK outputs stops low. The crystal oscillator and REF output are still active. 2. With a clock input, the phase relationship between the input and the output clocks can change each time the device is powered on. If a fixed phase relationship is required, use the ICS571 or other zero delay multipliers. X1/ICLK VDD GND REF CLK X21 8-pin (150 mil) SOIC S1 S0 CLK Multiplier Accuracy 0 0 Power-down CLK — — 0 1 25 1.746 1 ppm M 0 33.33 2.328 0.008% M 1 40 2.794 1 ppm 1 0 50 3.492 1 ppm 1 1 66.66 4.656 0.008% Pin Number Pin Name Pin Type Pin Description 1 XI/ICLK Input Crystal connection to a 14.31818 MHz crystal or clock input. 2 VDD Power Connect to +3.3 V or +5 V. 3 GND Power Connect to ground. 4 REF Output Reference 14.31818 MHz crys tal oscillator buffered clock output. 5 CLK Output Clock output per table above. 6 S0 Tri-level Input Select 0 for output clock. Connect to GND or VDD or float. See table above. 7 S1 Tri-level Input Select 1 for output clock. Connect to GND or VDD or float. See table above. 8 X2 Output Crystal connection to a 14.31818 MHz crystal. Leave unconnected for clock input.

LOCO™ PLL CLOCK GENERATOR CLOCK MULTIPLIER IDT™ / ICS™ LOCO™ PLL CLOCK GENERATOR 3 ICS514 REV G 051310 External Components Decoupling Capacitor As with any high-performance mixed-signal IC, the ICS514 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01µF must be connected between VDD and the GND. It must be connected close to the ICS514 to minimize lead inductance. No external power supply filtering is required for the ICS514. Series Termination Resistor A 33Ω terminating resistor can be used next to the CLK and REF pins for trace lengths over one inch. Crystal Load Capacitors The total on-chip capacitance is approximately 12 pF . A parallel resonant, fundamental mode crystal should be used. The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal capacitors, if needed, must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal (C L -12 pF)*2. In this equation, CL= crystal load capacitance in pF . Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 8 pF [(16-12) x 2 = 8]. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS514. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7 V All Inputs and Outputs (referenced to GND) -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70 ° C Storage Temperature -65 to +150 ° C Soldering Temperature 260 ° C

LOCO™ PLL CLOCK GENERATOR CLOCK MULTIPLIER IDT™ / ICS™ LOCO™ PLL CLOCK GENERATOR 4 ICS514 REV G 051310 Recommended Operation Conditions VDD=5.0 V ±5% , Ambient temperature 0 to +70° C, unless stated otherwise VDD = 5.0 V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise Parameter Min. Typ. Max. Units Ambient Operating Temperature 0 +70 ° C Power Supply Voltage (measured in respect to GND) +3.0 +5.5 V Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.0 5.5 V Input High Voltage, ICLK only V IH ICLK (pin 1) (VDD/2)+1 VDD/2 V Input Low Voltage, ICLK only V IL ICLK (pin 1) VDD/2 (VDD/2)-1 V Input High Voltage V IH S0 2.0 V Input Low Voltage V IL S0 0.8 V Input High Voltage V IH S1 VDD-0.5 V Input Mid Voltage V IM S1 VDD/2 V Input Low Voltage V IL S1 0.5 V Output High Voltage V OH IOH = -25 mA 2.4 V Output Low Voltage V OL IOL = 25 mA 0.4 V IDD Operating Supply Current No load, 66.66 MHz 20 mA IDD Power-down Supply Current, 3.3 V S1=S0=0 1.5 mA Short Circuit Current CLK output + 70 mA On-Chip Pull-up Resistor Pin 6 270 k Ω Input Capacitance, S1, S0 Pins 6, 7 4 pF Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency, crystal input F IN 5 14.31818 27 MHz Input Frequency, clock input F IN 2 14.31818 50 MHz Output Frequency, VDD = 4.5 to 5.5 V F OUT 14 66.66 140 MHz Output Frequency, VDD = 3.0 to 3.6 V F OUT 14 66.66 100 MHz Output Clock Rise Time t OR 0.8 to 2.0 V 1 ns Output Clock Fall Time t OF 2.0 to 8.0 V 1 ns Output Clock Duty Cycle t OD 1.5 V,up to 140 MHz 45 49-51 55 %

LOCO™ PLL CLOCK GENERATOR CLOCK MULTIPLIER IDT™ / ICS™ LOCO™ PLL CLOCK GENERATOR 5 ICS514 REV G 051310 Thermal Characteristics Marking Diagram Notes: 2. YYWW is the last two digits of the year and the week. 3. “LF” designates Pb (lead) fee package. Power-up time, from PD to outputs stable 51 0 m s Power-down time, from running to PD state 50 ns Absolute Clock Period Jitter t ja Deviation from mean +160 ps One Sigma Clock Period Jitter t js 50 ps Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air 150 ° C/W θJA 1 m/s air flow 140 ° C/W θJA 3 m/s air flow 120 ° C/W Thermal Resistance Junction to Case θJC 40 ° C/W Parameter Symbol Conditions Min. Typ. Max. Units 514MLF YYWW

LOCO™ PLL CLOCK GENERATOR CLOCK MULTIPLIER IDT™ / ICS™ LOCO™ PLL CLOCK GENERATOR 6 ICS514 REV G 051310 Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

“LF” denotes Pb (lead) free package. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping Packaging Package Temperature 514MLF 514MLF Tubes 8-pin SOIC 0 to +70 ° C 514MLFT 514MLF Tape and Reel 8-pin SOIC 0 to +70 ° C INDEX AREA 1 2 D E SEATING PLANE A e - C - B .10 (.004) C C L H h x 45 Millimeters Inches Symbol Min Max Min Max A 1.35 1.75 .0532 .0688 A1 0.10 0.25 .0040 .0098 B 0 . 3 30 . 5 1. 0 1 3. 0 2 0 C 0.19 0.25 .0075 .0098 D 4.80 5.00 .1890 .1968 E 3.80 4.00 .1497 .1574 e 1.27 BASIC 0.050 BASIC H 5.80 6.20 .2284 .2440 h 0 . 2 50 . 5 0. 0 1 0. 0 2 0 L 0 . 4 01 . 2 7. 0 1 6. 0 5 0 α 0° 8° 0° 8°

© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA Corporate Headquarters Integrated Device Technology, Inc. www.idt.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support www.idt.com/go/clockhelp Innovate with IDT and accelerate your future networks. Contact: www.IDT.com ICS514 LOCO™ PLL CLOCK GENERATOR CLOCK MULTIPLIER