512M-DDR1-AS4C64M8D1 ALSC | Alldatasheet
Document overview
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Technical content
-1- Rev.1.0 May 2015
Revision History
Rev 1.0 Preliminary datasheet DĂLJ201ϱ Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice AS4C64M8D1-66pin TSOPII and 60-ball TFBGA PACKAGE
Features
- Fast clock rate: 250/200MHz
- Differential Clock CK & CK
- Bi-directional DQS
- DLL enable/disable by EMRS
- Fully synchronous operation
- Internal pipeline architecture
- Four internal banks, 16M x 8-bit for each bank
- Programmable Mode and Extended Mode registers - CAS Latency: 2, 2.5, 3 - Burst length: 2, 4, 8 - Burst Type: Sequential & Interleave d
- Individual byte write mask control
- DM Write Latency = 0
- Auto Refresh and Self Refresh
- 8192 refresh cycles / 64ms
- Precharge & active power down
- Power supplies: VDD & VDDQ = 2.5V ± 0.2V
- Operating Temperature: - Commercial (0~70 °C) - Industrial (-40~85°C)
- Interface: SSTL_2 I/O Interface
- Package: 66 Pin TSOP II, 0.65mm pin pitch - Pb and Halogen free
- Package: 60-Ball, 8x13x1.2 mm (max) TFBGA - Pb free and Halogen Free 512M DDR1-AS4C64M8D1 Confidential -2- Rev.1.0 May 2015
The 512Mb DDR SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 512 Mbits. result in a device particularly well suited to high performance main memory and graphics applications. Table 1. Ordering Information
Figure 2. Block Diagram
Table 2. Pin Details entry to the Power Down and Self Refresh modes. BankPrecharge command is being applied. switched to the idle state after the precharge operation. asserting WE "HIGH" or “LOW”. data, centered in write data. Used to capture write data. Data Bus: Data Input/output.
VDDQ Supply DQ Power: 2.5V ± 0.2V. Provide isolated power to DQs for improved noise immunity. VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. VREF Supply SSTL_2 reference Voltage NC - No Connect: These pins should be left u nconnected. 512M DDR1-AS4C64M8D1 Confidential -7- Rev.1.0 May 2015
shows the truth table for the operation commands. Table 3. Truth Table (Note (1), (2))
- CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
- These are states of bank designated by B A signal.
- Device state is 2, 4, and 8 burst operation.
default value of the Mode Register is not defined; therefore the Mode Register must be written by the user. specific codes for various burst lengths, burst types and CAS latencies. Table 4. Mode Register Bitmap
0 MRS 1 0 1 Reserved 1 0 1 Reserved
- Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2, 4,
Table 5. Burst Length
- Addressing Mode Select Field (A3) The Addressing Mode can be one of two modes, either Interleave Mode or Sequential Mode. Both Sequential Mode and Interleave Mode support b urst length of 2, 4 and 8.
Table 6. Addressing Mode
0 Sequential
1 Interleave
- Burst Definition, Addressing Sequence of Sequential and Interleave Mode
Table 7. Burst Address ordering
2 X X 0 0, 1 0, 1
- CAS Latency Field (A6~A4) This field specifies the number of clock cycles from the assertio n of the Read command to the first read data. The minimum whole value of CAS Latency depends on the frequency of CK. The minimum whole value satisfying the following formula must be programmed into this field. t CAC(min) ≤ CAS Latency X tCK
Table 8. CAS Latency
- Test Mode field (A8~A7) These two bits are used to enter the tes t mode and must be programmed to "00" in normal operation.
Table 9. Test Mode
- ( BA0, BA1)
Table 10. MRS/EMRS normal, or weak. Two clock cycles are required to complete the write operation in the extended mode register. for EMRS. Refer to the table for specific codes. Table 11. Extended Mode Register Bitmap
0 MRS 0 Full 0 Enable
1 EMRS 1 Weak 1 Disable
Table 12. Absolute Maximum Rating Note : All voltages are referenced to VSS. Table 14. Capacitance (VDD = 2.5V, f = 1MHz, TA = 25 ° C)
Parameter & Test Condition Symbol -5 Unit Max. inputs changing once every two clock cycles.
Table 16. Electrical Characteristics and Recommended A.C.Operating Condition Symbol Parameter -5 Unit Note Min. Max.
1) Enables on-chip refresh and address counters. transitioning from HIGH to LOW at this time, depending on t DQSS. this parameter, but system performanc e (bus turnaround) will degrade accordingly. 6) For command/address and CK & CK slew rate ≧ 1.0V/ns. 7) A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
Table 18. SSTL _2 Interface Figure 3. SSTL_2 A.C. Test Load up must be performed in the following sequence. "NOP" state and maintain CKE “LOW”. 2) Start clock and maintain stable condition for minimum 200 µs. 4) Issue a “Precharge All” command. 6) Issue MRS – reset DLL. (An additional 200 clock cycles are required to lock the DLL). 7) Precharge all banks of the device. 8) Issue two or more Auto Refresh commands. 9) Issue MRS – with A8 to low to initialize the mode register.
Figure 4. Activating a Specific Row in a Specific Bank
Figure 7. Read Burst Required CAS Latencies (CL=2)
Read Burst Required CAS Latencies (CL=3) DO n CK CK COMMAND READ NOP NOP NOP NOP NOP Bank A, Col nADDRESS DQS DQ CL=3 Don’t Care DO n=Data Out from column n Burst Length=4 3 subsequent elements of Data Out appear in the programmed order following DO n 512M DDR1-AS4C64M8D1 Confidential -20- Rev.1.0 May 2015
Figure 8. Consecutive Read Bursts Required CAS Latencies (CL=2)
Consecutive Read Bursts Required CAS Latencies (CL=2.5) DO o CK CK COMMAND READ NOP READ NOP NOP NOP Bank, Col nADDRESS DQS DQ CL=2.5 Don’t Care Bank, Col o DO n (or o)=Data Out from column n (or column o) Burst Length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first) 3 subsequent elements of Data Out appear in the programmed order following DO n 3 (or 7) subsequent elements of Data Out appear in the programmed order following DO o Read commands shown must be to the same device DO n 512M DDR1-AS4C64M8D1 Confidential -22- Rev.1.0 May 2015
o CK CK COMMAND READ NOP READ NOP NOP NOP Bank, Col nADDRESS DQS DQ CL=3 Don’t Care Bank, Col o DO n (or o)=Data Out from column n (or column o) Burst Length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first) 3 subsequent elements of Data Out appear in the programmed order following DO n 3 (or 7) subsequent elements of Data Out appear in the programmed order following DO o Read commands shown must be to the same device DO n Consecutive Read Bursts Required CAS Latencies (CL=3) 512M DDR1-AS4C64M8D1 Confidential -23- Rev.1.0 May 2015
Figure 9. Non-Consecutive Read Bursts Required CAS Latencies (CL=2)
Non-Consecutive Read Bursts Required CAS Latencies (CL=3) CK CK COMMAND READ NOP NOP READ NOP NOP Bank, Col nADDRESS DQS DQ CL=3 Don’t Care Bank, Col o NOP DO n (or o)=Data Out from column n (or column o) Burst Length=4 3 subsequent elements of Data Out appear in the programmed order following DO n (and following DO o) DO o DO n 512M DDR1-AS4C64M8D1 Confidential -25- Rev.1.0 May 2015
Figure 10. Random Read Accesses Required CAS Latencies (CL=2) DO n, etc. =Data Out from column n, etc.
Random Read Accesses Required CAS Latencies (CL=2.5) DO p DO DO o DO DO CK CK COMMAND READ READ READ READ NOP NOP Bank, Col nADDRESS DQS DQ CL=2.5 Don’t Care Bank, Col o Bank, Col p Bank, Col q DO n, etc. =Data Out from column n, etc. n ' , etc. =the next Data Out following DO n, etc. according to the programmed burst order Burst Length=2,4 or 8 in cases shown. If burst of 4 or 8, the burst is interrupted Reads are to active rows in any banks DO n Random Read Accesses Required CAS Latencies (CL=3) DO p DO DO o DO CK CK COMMAND READ READ READ READ NOP NOP Bank, Col nADDRESS DQS DQ CL=3 Don’t Care Bank, Col o Bank, Col p Bank, Col q DO n, etc. =Data Out from column n, etc. n ' , etc. =the next Data Out following DO n, etc. according to the programmed burst order Burst Length=2,4 or 8 in cases shown. If burst of 4 or 8, the burst is interrupted Reads are to active rows in any banks DO n 512M DDR1-AS4C64M8D1 Confidential -27- Rev.1.0 May 2015
Figure 11. Terminating a Read Burst Required CAS Latencies (CL=2)
COMMAND READ NOP BST NOP NOP NOP Bank A, Col nADDRESS DQS DQ CL=3 Don’t Care DO n = Data Out from column n Cases shown are bursts of 8 terminated after 4 data elements 3 subsequent elements of Data Out appear in the programmed order following DO n DO n Terminating a Read Burst Required CAS Latencies (CL=3) 512M DDR1-AS4C64M8D1 Confidential -29- Rev.1.0 May 2015
Figure 12. Read to Write Required CAS Latencies (CL=2)
COMMAND READ BST NOP NOP WRITE NOP Bank, Col nADDRESS DQS DQ CL=2.5 Don’t Care min tDQSS DI o DM Bank, Col o DO n (or o)= Data Out from column n (or column o) Burst Length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the BST command shown can be NOP) 1 subsequent element of Data Out appears in the programmed order following DO n Data in elements are applied following DI o in the programmed order DO n Read to Write Required CAS Latencies (CL=2.5) 512M DDR1-AS4C64M8D1 Confidential -31- Rev.1.0 May 2015
Read to Write Required CAS Latencies (CL=3) CK CK COMMAND READ BST NOP NOP WRITE NOP Bank, Col nADDRESS DQS DQ CL=3 Don’t Care Bank, Col o min tDQSS DI o DM DO n (or o)= Data Out from column n (or column o) Burst Length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the BST command shown can be NOP) 1 subsequent element of Data Out appears in the programmed order following DO n Data in elements are applied following DI o in the programmed order DO n 512M DDR1-AS4C64M8D1 Confidential -32- Rev.1.0 May 2015
Figure 13. Read to Precharge Required CAS Latencies (CL=2)
COMMAND READ NOP PRE NOP NOP ACT Bank A, Col nADDRESS DQS DQ CL=2.5 Don’t Care Bank (a or all) Bank A, Row tRP DO n = Data Out from column n Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8 3 subsequent elements of Data Out appear in the programmed order following DO n Precharge may be applied at (BL/2) tCK after the READ command Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks The Active command may be applied if tRC has been met DO n Read to Precharge Required CAS Latencies (CL=2.5) 512M DDR1-AS4C64M8D1 Confidential -34- Rev.1.0 May 2015
COMMAND READ NOP PRE NOP NOP ACT Bank A, Col nADDRESS DQS DQ CL=3 Don’t Care Bank (a or all) Bank A, Row tRP DO n = Data Out from column n Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8 3 subsequent elements of Data Out appear in the programmed order following DO n Precharge may be applied at (BL/2) tCK after the READ command Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks The Active command may be applied if tRC has been met DO n Read to Precharge Required CAS Latencies (CL=3) 512M DDR1-AS4C64M8D1 Confidential -35- Rev.1.0 May 2015
Figure 14. Write Command
Figure 15. Write Max DQSS
Figure 16. Write Min DQSS
Figure 17. Write Burst Nom, Min, and Max tDQSS
Figure 18. Write to Write Max tDQSS DI n , etc. = Data In for column n,etc.
Figure 19. Write to Write Max tDQSS, Non Consecutive DI n, etc. = Data In for column n, etc.
Figure 20. Random Write Cycles Max tDQSS DI n, etc. = Data In for column n, etc.
Figure 21. Write to Read Max tDQSS Non Interrupting DI n, etc. = Data In for column n, etc.
Figure 22. Write to Read Max tDQSS Interrupting DI n, etc. = Data In for column n, etc.
Figure 23. Write to Read Max tDQSS, ODD Number of Data, Interrupting
Figure 24. Write to Precharge Max tDQSS, NON- Interrupting
Figure 25. Write to Precharge Max tDQSS, Interrupting
Figure 26. Write to Precharge Max tDQSS ODD Number of Data Interrupting
Figure 27. Precharge Command
Figure 28. Power-Down Figure 29. Clock Frequency Change in Precharge
200 Clocks
Figure 32. Initialize and Mode Register Sets
Figure 33. Power Down Mode then the Power-Down mode shown is active Power Down.
Figure 34. Auto Refresh Mode
Figure 35. Self Refresh Mode required before a READ command can be applied.
Figure 36. Read without Auto Precharge
Figure 37. Read with Auto Precharge
Figure 38. Bank Read Access
Figure 39. Write without Auto Precharge
Figure 40. Write with Auto Precharge
Figure 41. Bank Write Access
Figure 42. Write DM Operation
Figure 43. 66 Pin TSOP II Package Outline Drawing Information
Figure 44. BGA 60ball package Outline Drawing Information
-65- Rev.1.0 May 2015 Alliance Memory, Inc.
511 Taylor Way,
San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved © Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. PART NUMBERING SYSTEM AS4C 64M8D1 T/B C/I N DRAM 64M8=64Mx8 D1=''51 =200MHz B = FBGA C=Commercial (0¡ C70¡ C) I=Industrial (-40¡ C85¡ C) Indicates Pb and Halogen Free T = TSOPII