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an unshielded environment, with proper PCB design choices. techniques, including board layout and stack-up issues. ards, all results are applicable to both standards. techniques are outside of the scope of this application note. Figure 1. Example of iCoupler Device Families

Rev. 0 | Page 2 of 20 TABLE OF CONTENTS

REVISION HISTORY

4/11—Revision 0: Initial Version

Rev. 0 | Page 5 of 20 SOURCES OF CONDUCTED NOISE Large currents and frequencies also generate conducted noise on the ground and power planes. This can be addressed with the same techniques for radiated emissions because the causes and remedies for both types of EMI can be improved with the same PCB ground and power structures. The inability of the bypass capacitors and ground/power planes to provide adequate high frequency current to the iCoupler device causes V DD noise. The iCoupler isolator transmits data across the transformer in bursts of 1 ns pulses with an ampli- tude of 70 mA. An ideal bypass capacitor of 100 nF should be adequate to supply the ac component of the current. However, bypass capacitors are not ideal and may connect to the ground or power planes through an inductive via. In addition, a large distance between ground and power planes creates a large inductance between them, which restricts the ability to supply current quickly. These factors may contribute to a large fraction of a volt of high frequency noise on the V DD plane.

requirements of the design, including cost and performance. Input-to-Output Stitching section.

  • Input-to-output ground plane stitching
  • Edge guarding
  • Interplane capacitive bypass
  • Power control (3.3 V operation) Circuit boards with test structures were prepared to evaluate each of these EMI mitigation techniques using the ADuM140x. The layout of each board was varied as little as possible to allow meaningful comparison of results. Testing was conducted at an EMI test facility under standard conditions for CISPR 22 Class B certification. Results are shown in Figure 14 to Figure 17 and summarized in Table 4 to Table 7. INPUT-TO-OUTPUT STITCHING When current flows along PCB traces, an image charge follows along the ground plane beneath the trace. If the trace crosses a gap in the ground plane, the image charge cannot follow along. This creates differential currents and voltages in the PCB, leading to radiated and conducted emissions. The solution is to provide a path for the image charge to follow the signal. Standard prac- tice is to place a stitching capacitor in proximity to the signal across the split in the ground plane (see “PCB Design for Real- World EMI Control” in the References section). This same technique works to minimize radiation between ground planes due to the operation of iCoupler isolators. There are at least three options to form a stitching capacitance.
  • A safety rated capacitor applied across the barrier.
  • Ground and power planes on an interior layer can be extended into the isolation gap of the PCB to form an overlapping stitching capacitor.
  • A floating metal plane can span the gap between the isolated and nonisolated sides on an interior layer, as shown in Figure 8. Each option has advantages and disadvantages in effectiveness and area required to implement. Note that, for medical applica- tions, the total isolation capacitance allowed between isolated ground and earth ground may only be as large as 10 pF to 20 pF. Safety Stitching Capacitor Stitching capacitance can be implemented with a simple ceramic capacitor across the isolation barrier. Capacitors with guaran- teed creepage, clearance, and withstand voltage can be obtained from most major capacitor manufacturers. These safety rated capacitors come in several grades depending on their intended use. The Y2 grade is used in line-to-ground applications where there is danger of electric shock and is the recommended safety capacitor type for a stitching capacitor in a safety rated applica- tion. This type of capacitor is available in surface-mount and radial leaded disk versions. See Table 1 for a list of some Y2 grade safety capacitors. Because safety capacitors are discrete components, they must be attached to the PCB with pads or through holes. This adds para- sitic inductance in series with the capacitor, on top of its intrinsic inductance. It also localizes the stitching capacitor, requiring currents to flow to the capacitor, which can create asymmetrical image charge paths and added noise. These discrete capacitors are effective at frequencies up to 200 MHz. Above 200 MHz, capacitance built into the PCB layers can be very effective. Capacitance Built Into the PCB The PCB itself can be designed to create a stitching capacitor structure in several ways. A capacitor is formed when two planes in a PCB overlap. This type of capacitor has some very useful properties in that the inductance of the parallel plate capacitor formed is extremely low, and the capacitance is distributed over a relatively large area. These structures must be constructed on internal layers of a PCB. The surface layers have minimum creepage and clearance requirements; therefore, it is not practical to use surface layers for this type of structure.

Table 1. Safety Capacitors Type/Size Value (pF) Manufacturer Part No.

supply noise can be dramatically reduced.

4 LAYER: 4 MIL SPACING GND

2 LAYER: NO GND AND PWR PLANES

Figure 13. VDD Voltage Noise for Different PCB Layouts

3.3 V OPERATION

3.3 V supplies are used instead of 5 V supplies. Figure 14. Peak Emissions at Frequencies of 30 MHz to 230 MHz at 1 Mbps to secondary side stitching capacitance and guard options. Figure 15. Peak Emissions at Frequencies of 230 MHz to 1000 MHz at 1 Mbps Figure 16. Peak Emissions at Frequencies of 30 MHz to 230 MHz at 10 Mbps Figure 17. Peak Emissions at Frequencies of 230 MHz to 1000 MHz at

10 Mbps Rate for Stitching Capacitance and Guard Options

  • Use a minimum stack-up of four layers.
  • Make the GND layer as close as possible to the VDD layer to maximize the bypass capacitance value.
  • All vias in the power path should be as large as practical. Small vias have high inductance and generate noise. Using multiple small vias is not as effective in reducing via induc- tance as a single large via because the bulk of the current goes through the closest via, even if multiple paths are present.

Figure 18. Critical Distances in PCB design

  • Be careful to route signal lines over a single reference plane. It is vital to maintain the image charge path so that image charges do not travel by circuitous routes to meet with the original signal on another plane.
  • Do not route high speed lines close to the edges of the PCB.
  • Routing data or power off boards, especially through cables, can introduce an additional radiation concern. Feed- through filter capacitors or similar filter structures can be used to minimize cable radiation. In the case of the IEC 60950 standard in PCBs, there is no minimum specification for distance through the insulation for functional or basic insulation standards. Thus, the designer has a great deal of flexibility in board layout. Materials such as FR4 must be thick enough to withstand the required overvoltage for the life of the product. MEETING ISOLATION STANDARDS Most of the techniques described in this application note do not affect board isolation, with the exception of the stitching capaci- tor. When stitching is implemented with a safety capacitor, the capacitor has rated working and transient voltages, as well as specified creepage and clearance. This makes the safety capaci- tor relatively easy to deal with from a certification point of view. However, its performance as an EMI suppression element is limited. If reinforced insulation is required, a minimum distance of 0.4 mm (about 16 mil) of insulation along a bonded surface, such as the gap between copper structures on an internal PCB layer or directly through the insulation from layer to layer, must be maintained in most cases. In addition, there can be type testing requirements for circuit boards unless multiple layers of insulation are used between active structures. Although this requirement necessitates careful board design and possibly more than four layers, it should not be burdensome if taken into account at the start of a design. The PCB stitching capacitor by its nature is most effective when conductors are located as close to each other as possible. For maximum performance from these elements, it is necessary to push the internal spacing requirements as far as possible, while maintaining safety. The limits of internal spacing depend heavily on the standard that the system is built for. Different standards can have completely different approaches to PCB construction. Capacitive coupling across the isolation barrier allows ac leakage and transients to couple from one ground plane to the other. Although 300 pF seems small, high voltage, high speed transients can inject significant currents across the barrier through this capacitance. Take this into account if the applica- tion is to be subjected to these environments. Certification agencies treat the surface layers of a multilayer PCB differently from interior layers. The surface has creepage and clearance requirements that are driven by air ionization and voltage breakdown along dirty surfaces. Interior layers are treated as solid insulation or permanently cemented joints between solid insulation.

Table 3. Comparison of Isolation Creepage in Isolation Standards

that passes CISPR 22 Class B certification was chosen. levels, a few EMI reduction techniques can be employed. Figure 19. CISPR 22 and FCC Limits Normalized to 10 m Antenna Distance exceeds Class B by 2 dBμV/m. niques in various board layouts and displayed in Table 5. 10 dB and more than meets the emissions limits for Class B. Table 4. CISPR 22 Class A and Class B Emission Limits, Standard 4-Layer PCB, Four Channels at 1 Mbps

3.3 V VDD, 30 MHz

3.3 V VDD, 230 MHz

5 V VDD, 30 MHz

5 V VDD, 230 MHz

Table 5. Techniques to Reduce Emissions, 4-Layer PCB with added Stitching Capacitance, Four Channels at 1 Mbps

Table 6. CISPR 22 Class A and Class B Emission Limits, Standard 4-Layer PCB, Four Channels at 10 Mbps Table 7. Techniques to Reduce Emissions, 4-Layer PCB with Added Stitching Capacitance, Four Channels at 10 Mbps helps reduce the emissions levels. 5 dBμV/m to 6 dBμV/m of emissions reduction. plane, as well as the spacing between ground and power planes. ing because that structure is too subtle to be shown in this view. possible, regardless of which plane is used to implement them. Figure 20. Capacitive Stitching and Via Fence Techniques of ground and power used to make the stitching capacitance.

Rev. 0 | Page 14 of 20 CONCLUSIONS Each method outlined in this application note addresses specific radiation sources and can be combined with the other techniques described to achieve the desired reductions in the associated emissions. Test boards easily meet CISPR 22 Class B standards with no external shielding by utilizing stitching capacitance and edge fencing. In addition, use of interplane decoupling capacitance in the ground and power planes yields a very quiet environment for precision measurement applications. While this application note relies on data collected on the four-channel ADuM140x devices, the techniques are applicable across the iCoupler data isolator portfolio. For additional information on how to suppress EMI in isoPower integrated, isolated power products, refer to the AN-0971 Application Note, Control of Radiated Emissions With isoPower Devices. Where low ac leakage is required, as in some medical applica- tions, stitching capacitance may not be a viable solution. In other applications, there may be concern about stitching capacitance coupling noise from the high noise side to the low noise side. In this case, the use of interplane capacitance bypass and edge guarding with power and ground fills may help reduce the conducted noise. In applications where stitching capacitance cannot be used and other techniques are not effective, grounded metalized chassis enclosures may be the most practical solution for minimizing emissions.

Rev. 0 | Page 19 of 20 REFERENCES Archambeault, Bruce R. and James Drewniak. 2002. PCB Design for Real-World EMI Control. Boston: Kluwer Academic Publishers. Gisin, Franz and Zorica Pantic-Tanner. 2001. “Minimizing EMI Caused by Radially Propagating Waves Inside High Speed Digital Logic PCBs. ” Telecommunications in Modern Satellite, Cable and Broadcasting Service. Nis, Yugoslavia.

Rev. 0 | Page 20 of 20 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. AN09713-0-4/11(0)