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P9221-R_17 IDT | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 35

Technical content

Datasheet sections

• 8.1 LDO – Low Dropout Regulators
• 8.2 Setting the Output Voltage – VOSET
• 8.3 SINK Pin
• 8.4 Rectifier Voltage – VRECT
• 8.5 Over-Current Limit – ILIM
• 8.6 Interrupt Function – INT
• 8.7 Enable Pin – EN
• 8.8 Thermal Protection
• 8.9 External Temperature Sensing – TS
• 8.10 Alignment Guide – ALIGNX and ALIGNY
• 8.11 Received Power Packet Offset and Gain Calibration – RPPO and RPPG
• 8.12 Advanced Foreign Object Detection (FOD)
• 9.1 Modulation/Communication
• 9.2 Bit Encoding Scheme for ASK
• 9.3 Byte Encoding for ASK
• 9.4 Packet Structure
• 10.1 Selection Phase or Startup
• 10.2 Ping Phase (Digital Ping)
• 10.3 Identification and Configuration Phase
• 10.4 Negotiation Phase
• 10.5 Calibration Phase
• 10.6 Power Transfer Phase
• 12.1 Power Dissipation and Thermal Requirements
• 12.2 Recommended Coils
• 12.3 Typical Application Schematic
• 12.4 Bill of Materials (BOM)

Features

 Single-chip solution supporting up to 15W applications  WPC-1.2.3 compliant  Patented over-voltage protection clamp eliminating external capacitors  87% peak DC-to-DC efficiency with P9242-R TX  Proprietary coil alignment guide  Full synchronous rectifier with low RDS(ON) switches  Programmable output voltage: 9V and 12V  Embedded 32-bit ARM® Cortex®-M0 processor  Dedicated remote temperature sensing  Power transfer LED indicator  Programmable current limit  Active-low enable pin for electrical on/off  Open-drain interrupt flag  Supports I2C interface  0 to +85°C ambient operating temperature range  52-WLCSP (2.64  3.94 mm; 0.4mm pitch) Typical Application Circuit AC1 COMM1 BST1 AC2 COMM2 BST2 VRECT OUT VSET ILIM RPPO RPPG SDA SCL INT VDD5V GND Programming Resistors LS P9221-R THM ALIGNX ALIGNY VDD18 CS COUT

Figure 1. Pin Assignments Table 1. Pin Descriptions A2 ALIGNX I AC input for coil alignment guide. If not used, connect to GND through a 10kΩ resistor. A3 SCL I I2C clock pin. Open-drain output. Connect a 5.1kΩ resistor to VDD18 pin.

© 2017 Integrated Device Technology, Inc. 6 April 4, 2017 Pins Name Type Function A5 RPPG I Received power packet gain (RPPG) calibration pin for foreign object detection (FOD) tuning. Connect this pin to the center tap of a resistor divider to set the gain of the FOD. The FOD is disabled by connecting the center tap of two 10kΩ resistors to VDD18 pin and GND. A6 COMM2 O Open-drain output used to communicate with the transmitter. Connect a 47nF capacitor from AC2 to COMM2. B1 RSV4 Reserved for internal use. Do not connect. B2 ALIGNY I AC input for coil alignment guide. If not used, connect to GND through a 10KΩ resistor. B3 SDA I/O I2C data pin. Open-drain output. Connect a 5.1kΩ resistor to VDD18 pin. B4 ILIM I Programmable over-current limit pin. Connect this pin to the center tap of a resistor divider to set the current limit. For more information about the current limit function, see section 8.5. B5 EN̅̅̅̅ I Active-LOW enable pin. Pulling this pin to logic HIGH forces the device into Shut Down Mode. When connected to logic LOW, the device is enabled. Do not leave this pin floating. B6 RSV5 Reserved for internal use. Do not connect. C1, C6, J1, J2, J3,J4,J5,J6 GND GND Ground. C2 SINK O Open-drain output for controlling the rectifier clamp. Connect a 36Ω resistor from this pin to the VRECT pin. C3 INT̅̅̅̅ O Interrupt flag pin. This is an open-drain output that signals fault interrupts. It is pulled LOW if any of these faults exists: an over-voltage is detected, an over-current condition is detected, the die temperature exceeds 140°C, or an external over-temperature condition is detected on the TS pin. It is also asserted LOW when EN is HIGH. Connect to VDD18 through a 10kΩ resistor. See section 8.6 for additional conditions affecting the interrupt flag. C4 RPPO O Received power packet offset (RPPO) calibration pin for FOD tuning. Connect to the center tap of the resistor divider to set the offset of the FOD. The FOD is disabled by connecting the center tap of two 10kΩ resistors to VDD18 pin and GND. C5 DEN I Reserved. Must connect a 10kΩ resistor to the VDD18 pin. D1, D2, D3, D4, D5, D6 OUT O Regulated output voltage pin. Connect three 10μF capacitors from this pin to GND. The default voltage is set to 12V when the VOSET pin is pulled up to VDD18 pin through a 10kΩ resister. For more information about VOSET, see section 8.2. E1, E2, E5, E6 F2, F3, F4, F5 VRECT O Output voltage of the synchronous rectifier bridge. Connect three 10μF capacitors from this pin to GND. The rectifier voltage dynamically changes as the load changes. For more information, see the typical waveforms in section 6. F1 VDD5V O Internal 5V regulator output voltage for internal use. Connect a 1μF capacitor from this pin to ground. Do not load the pin. F6 VDD18 O Internal 1.8V regulator output voltage. Connect a 1μF capacitor from this pin to ground. Do not load the pin. G1 BST1 O Boost capacitor for driving the high-side switch of the internal rectifier. Connect a 15nF capacitor from the AC1 pin to BST1. G2, H1, H2, AC1 I AC input power. Connect to the resonant capacitor (CS). G3 RSV3 I Reserved pins. Must be connected to GND.

© 2017 Integrated Device Technology, Inc. 7 April 4, 2017 Pins Name Type Function G4 RSV1 Reserved for internal use. Do not connect. G5, H5, H6 AC2 I AC input power. Connect to the Rx coil (LS). G6 BST2 O Boost capacitor for driving the high-side switch of the internal rectifier. Connect a 15nF capacitor from the AC2 pin to BST2. H3 RSV2 Reserved pins. Must be connected to GND. H4 TS I Remote temperature sensor for over-temperature shutdown. Connect to the NTC thermistor network. If not used, connect to VDD18 pin through the 10kΩ resistor.

specification is not implied. Exposure to absolute maximum rating conditions for extended periods might affect reliability. Table 2. Absolute Maximum Ratings are not used in the application. [b] All voltages are referred to ground unless otherwise noted. functionality or reliability of the product. Table 3. ESD Information

Table 4. Package Thermal Information Note: This thermal rating was calculated on a JEDEC 51 standard 4-layer board with dimensions 76.2 x 114.3 mm in still air conditions. result in excessive die temperature, and the device will enter thermal shutdown.

1. Electrical Characteristics

Table 5. Electrical Characteristics Note: VRECT = 5.5V; COUT = 4.7μF, EN̅̅̅̅ = LOW, unless otherwise noted. TJ = 0C to 125C; typical values are at 25°C.

© 2017 Integrated Device Technology, Inc. 10 April 4, 2017 Symbol Description Conditions Min Typical Max Units VDD5V Voltage VVDD5V VDD5V Pin Output Voltage[a] IVDD5V = 10mA, CVDD5V = 1µF 4.5 5 5.5 V Low Drop-Out (LDO) Regulator IOUT_MAX Maximum Output Current 1.25 A VOUT_12V 12V Output Voltage VOSET > 1.5V, VRECT=12.3V 12 V VOUT_9V 9V Output Voltage 0.7V < VOSET < 1.2V, VRECT=9.3V 9 V Analog to Digital Converter N Resolution 12 Bit fSAMPLE Sampling Rate 67.5 kSa/s Channel Number of Channels 8 VIN,FS Full-Scale Input Voltage 2.1 V EN̅̅̅̅ pin VIH Input Threshold HIGH 1.4 V VIL Input Threshold LOW 0.25 V IIL Input Current LOW VEN¯¯ = 0V -1 1 μA IIH Input Current HIGH VEN¯¯ = 5V 2.5 μA VOSET, ILIM, TS, RPPO, RPPG IIL Input Current LOW VVOSET, VILIM, VTS, VRPPO, VRPPG = 0V -1 1 µA IIH Input Current HIGH VVOSET, VILIM, VTS, VRPPO, VRPPG = 1.8V -1 1 µA ALIGNX, ALIGNY and INT̅̅̅̅ pins ILKG Input Leakage Current VALIGNX, VALIGNY, VINT = 0V and 5V -1 1 µA VOL Output Logic LOW IOL = 8mA 0.36 V I2C Interface – SCL, SDA VIL Input Threshold LOW 0.7 V VIH Input Threshold HIGH 1.4 V ILKG Input Leakage Current VSCL, VSDA = 0V and 5V -1 1 µA VOL Output Logic LOW IOL = 8mA 0.36 V fSCL Clock Frequency 400 kHz tHD,STA Hold Time (Repeated) for START Condition 0.6 µs tHD:DAT Data Hold Time 0 ns tLOW Clock Low Period 1.3 µs tHIGH Clock High Period 0.6 µs

© 2017 Integrated Device Technology, Inc. 11 April 4, 2017 Symbol Description Conditions Min Typical Max Units tSU:STA Set-up Time for Repeated START Condition 0.6 µs tBUF Bus Free Time Between STOP and START Condition 1.3 µs CB Capacitive Load for each Bus Line 150 pF CI SCL, SDA Input Capacitance 5 pF Thermal Shutdown TSD Thermal Shutdown Rising[b] 140 °C Falling 120 °C [a] Do not externally load. For internal biasing only. [b] If the die temperature exceeds 130°C, the Thermal_SHTDN_Status flag is set and an end power transfer (EPT) packet is sent (see Table 11).

Figure 17. Functional Block Diagram

the WPC-1.2.2 communication protocol. load current increases. The internal temperature is continuously monitored to ensure proper operation. transmitter, the P9221-R is a complete wireless power system solution.

8.1 LDO – Low Dropout Regulators

connect a minimum of 30µF ceramic capacitance to the OUT pin. placed as close as possible to the pins.

8.2 Setting the Output Voltage – VOSET

R34 are summarized in Table 6. Table 6. Setting the Output Voltage

10 OPEN 12 Enable

© 2017 Integrated Device Technology, Inc. 17 April 4, 2017

8.3 SINK Pin

The P9221-R has an internal automatic DC clamping to protect the device in the event of high voltage transients. The VRECT node must be connected to the SINK pin at all times using a 36Ω resistor with a greater than ¼ W rating.

8.4 Rectifier Voltage – VRECT

The P9221-R uses a high‐efficiency synchronous rectifier to convert the AC signal from the coil to a DC signal on the VRECT pin. During startup, the rectifier operates as a passive diode bridge. Once the voltage on V RECT exceeds the under-voltage lock-out level (UVLO; see Table 5), the rectifier will switch into full synchronous bridge rectifier mode . A total capacitance of 30μF is recommended to minimize the output voltage ripple.

8.5 Over-Current Limit – ILIM

The P9221-R has a programmable current limit function for protecting the device in the event of an over-current or short-circuit fault condition. When the output current exceeds the programmed threshold, the P9221-R will limit the load current by reducing the output voltage. The current limit should be set to 130% of the target maximum output current. See the ILIM pin description in Table 1 for further information. The P9221 -R provides an open -drain, active -LOW interrupt output pin. It is asserted LOW when EN is HIGH or any of the following fault conditions have been triggered: the die temperature exceeds 140°C, the external thermistor measurement exceeds the threshold (see section 8.9), or an over-current (OC) or over-voltage (OV) condition is detected. During normal operation, the INT pin is pulled HIGH. This pin can be connected to the interrupt pin of a microcontroller. The source of the trigger for the interrupt is available in the I2C interrupt register (see Table 12). The P9221-R can be disabled by applying a logic HIGH to the EN pin. When the EN pin is pulled HIGH, the device is in Shut Down Mode. Connecting the enable pin to logic LOW activates the device.

8.8 Thermal Protection

The P9221-R integrates thermal shutdown circuitry to prevent damage resulting from excessive thermal stress that may be encountered under fault conditions. This circuitry will shut down or reset the P9221-R if the die temperature exceeds 140°C.

8.9 External Temperature Sensing – TS

The P9221-R has a temperature sensor input, TS, which can be used to monitor an external temperature by using a thermistor. The built-in comparator’s reference voltage was chosen to be 0.6V in the P9221-R, and it is used for monitoring the voltage level on the TS pin as described by Equation 1. VTS=VVDD18× NTC R+NTC Equation 1 Where NTC is the thermistor’ s resistance and R is the pull -up resistor connected to VDD18 pin. The over–temperature shutdown is tr igged when the TS pin voltage is lower than 0.6V; for more information, see Figure 24.

© 2017 Integrated Device Technology, Inc. 18 April 4, 2017

8.10 Alignment Guide – ALIGNX and ALIGNY

This feature is used to provide directional information regarding the transmit coil and receive coil alignment while the wireless charger is in normal operation mode. Sensing coils (see the basic application circuit on the first page) are placed on the wireless power receiver side between the power RX coil and power TX coil. Special design enables the sensing coils to output zero voltage wh en the alignment is optimum while misalignment between the transmitter and receiver coils will result in a voltage on the sensing coils. These signals are internally rectified, filtered, and passed through the ADC providing quantitative information on the amount of misalignment. The higher the signal is, the more the coils are misaligned. Furthermore, the signal magnitude on ALIGNX and ALIGNY provides directional information by measuring the phase between the input power AC signal and horizontal and vertical alignment signals. Once the signal passes through the ADC, the alignment information is represented by two 8-bit signed numbers, which can be read from the Alignment X Value and Alignment Y Value I2C registers defined in Table 21 and Table 22 respectively, which indicate the misalignment direction and magnitude. The application processor can provide 2D visual graphic s that suggest how much the power coils are misaligned in each direction and can suggest that the user move the device on the TX pad for the best alignment to improve the power transferred and reduce the charging time.

8.11 Received Power Packet Offset and Gain Calibration – RPPO and RPPG

The received power packet offset (RPPO) and received power packet gain (RPPG) calibrations have dedicated pins for tuning foreign object detection (FOD). The offset calibration can be tuned by the voltage level of RPPO to a value between 0.1V to 2.1 V, which corresponds to a power offset range of 1.54W to 2.34W. The gain can be modified by setting the voltage level of the RPPG pin. The range of the control gain is To disable the FOD, the voltage on both RPPO and RPPG must be set to 0.1V. Neither pin should be floating. If FOD is not required, the RPPG and RPPO must be set to 0.9V, which defaults to gain = 1 and offset = 0.

8.12 Advanced Foreign Object Detection (FOD)

When metallic objects are exposed to an alternating magnetic field, eddy currents cause such objects to heat up. Examples of such parasitic metal objects are coins, keys, paper clips, etc. The amount of heating depends on the strength of the coupled magnetic field, as well as on the characteristics of the object, such as its resistivity, size, and shape. In a wireless power transfer system, the heating manifests itself as a power loss, and therefore a reduction in power-transfer efficiency. Moreover, if no appropriate measures are taken, the heating could be sufficient that the foreign object could become heated to an undesirable temperature. During the power transfer phase, the receiver periodically will communicate to the transmitter the amount of power received by means of a received power packet. The transmitter will compare this power with the amount of power transmitted during the same time period. If there is a significant unexplained loss of power, then the transmitter will shut off power delivery because a possible foreign object might be absorbing too much energy. For a WPC system to perform this function with sufficient accuracy, both the transmitter and receiver must account for and compensate for all of their known losses. Such losses could be due to resistive losses or nearby metals that are part of the transmitter or receiver, etc. Because the system accurately measures it s power and accounts for all known losses, it can thereby detect foreign objects because they cause an unknown loss. The WPC specification requires that a power receiver must report to the power transmitter its received power (PPR) in a received- power packet (RPP). The maximum value of the received power accuracy 𝑃Δ depends on the maximum power of the power receiver as defined in Table 7. The power receiver must determine its PPR with an accuracy of ± 𝑃Δ, and report its received power as P RECEIVED = PPR + 𝑃Δ. This means that the reported received power is always greater than or equal to the transmitted power (P PT) if there is no foreign object (FO) present on the interface surface.

Table 7. Maximum Estimated Power Loss The compensation algorithm includes values that are programmable via either the I 2C interface or OTP ( one-time programm able) bits. sensed when the received power is different than the expected system power.

9.1 Modulation/Communication

The wireless medium power charging system uses two-way communication: receiver-to-transmitter and transmitter-to receiver. (ASK) modulation using internal switches to connect external capacitors from AC1 and AC2 to ground (see Figure 17) with a bit rate of 2Kbps. power transmitter detects this as a modulation of coil current/voltage to receive the packets. protocol with the power transmitter. than the operating frequency during FSK communication. transmitter communication packet. The frequency deviation is calculated using Equation 2. is the internal oscillator responsible for counting the period of the power transfer signal. sending 512 consecutive fMOD or fOP cycles. Figure 18. Example of Differential Bi-phase Decoding for FSK Figure 19. Example of Asynchronous Serial Byte Format for FSK

9.2 Bit Encoding Scheme for ASK

Figure 20. Bit Encoding Scheme

9.3 Byte Encoding for ASK

Each byte in the communication packet comprises 11 bits in an asynchronous serial format, as shown in Figure 21. Figure 21. Byte Encoding Scheme Each byte has a start bit, 8 data bits, a parity bit, and a single stop bit.

9.4 Packet Structure

Figure 22. Communication Packet Structure

1. WPC Mode Characteristics

the Base line Power Profile, as shown in Figure 23. Figure 23. WPC Power Transfer Phases Flowchart

10.1 Selection Phase or Startup

signal. This measurement signal should not wake up a power receiver that is positioned on the interface surface.

10.2 Ping Phase (Digital Ping)

are turned on, and microcontroller’s startup is initiated enabling the WPC communication protocol. of the power transfer, maintaining the power signal output.

© 2017 Integrated Device Technology, Inc. 23 April 4, 2017

10.3 Identification and Configuration Phase

The identification and configuration phase is the part of the protocol that the power transmitter executes in order to identify the power receiver and establish a default power transfer contract. This protocol extends the digital ping in order to enable the power receiver to communicate the relevant information. In this phase, the power receiver identifies itself and provides information for a default power transfer contract:  It sends the configuration packet.  If the power transmitter does not acknowledge the request (does not transmit FSK modulation), the power receiver will assume 5W output power.

10.4 Negotiation Phase

In the negotiation phase, the power receiver negotiates changes to the default power transfer contract. In addition, the power receiver verifies that the power transmitter has not detected a foreign object.

10.5 Calibration Phase

In the calibration phase, the power receiver provides information that the power transmitter can use to improve its ability to detect foreign objects during power transfer.

10.6 Power Transfer Phase

In this phase, the P9221-R controls the power transfer by means of the following control data packets:  Control Error Packets  Received Power Packet (RPP, FOD related)  End Power Transfer (EPT) Packet Once the “identification and configuration” phase is completed, the transmitter initiates the power transfer mode . The P9221-R control circuit measures the rectifier voltage and sends error packets to the transmitter to adjust the rectifier voltage to the level requi red to maximize the efficiency of the linear regulator and to send to the transmitter the actual received power packet for foreign object detection (FOD) to guarantee safe, efficient power transfer. In the event of an EPT issued by the application, the P92 21-R turns off the LDO and continuously send s EPT packets until the transmitter removes the power and the rectified voltage on the receiver side drops below the UVLO threshold.

all the internally accessible registers contained within the P9221-R. The default I2 C slave address is 61HEX. Table 8. Device Identification Register Table 9. Firmware Major Revision Table 10. Firmware Minor Revision Table 11. Status Registers 34HEX [7] Vout_Status R 0BIN “0” output voltage is off. 34HEX [2] Thermal_SHTDN_Status R 0BIN “0” indicates no over-temperature condition exists. sends an end power transfer (EPT) packet to the transmitter.

Table 12. Interrupt Status Registers 36HEX [7] INT_Vout_Status R 0BIN “0” output voltage has not changed. 36HEX [2] INT_OVER_TEMP_Status R 0BIN “1” indicates over-temperature condition exists. 36HEX [1] INT_VRECT_OV_ Status R 0BIN “1” indicates rectifier over-voltage condition exists. 36HEX [0] INT_OC_Limit_Status R 0 “1” indicates current limit has been exceeded. INT pin will be pulled down indicating an interrupt event has occurred. Table 13. Interrupt Enable Registers 38HEX [7] Vout_CHGN_INTR_EN RW 0BIN “0” disables the interrupt. 38HEX [2] OVER_TEMP_INT_EN R 0BIN “0” disables the interrupt. 38HEX [1] VRECT_OV_INT_EN RW 0BIN “0” disables the interrupt. 38HEX [0] OC_Limit_INT_EN RW 0BIN “0” disables the interrupt. Table 14. Battery Charge Status [a] Firmware only forwards the data from the application processor to transmitter.

Table 15. End Power Transfer The application processor initiates the end power transfer (EPT). 3BHEX [7:0] EPT_Code R/W 00HEX EPT_Code sent to transmitter. Table 16. Read Register – Output Voltage 3CHEX [7:0] ADC_VOUT [7:0] R 00HEX 8 LSB of VOUT ADC value. 3DHEX [7:4] Reserved R 0HEX Reserved. 3DHEX [3:0] ADC_VOUT [11:8] R 0HEX 4 MSB of VOUT ADC value. Table 17. Read Register – VRECT Voltage 40HEX [7:0] ADC_VRECT [7:0] R – 8 LSB of VRECT ADC value. 41HEX [3:0] ADC_VRECT [11:8] R – 4 MSB of VRECT ADC value. Table 18. Read Register – IOUT Current 44HEX [7:0] RX_IOUT [7:0] RHEX – 8 LSB of IOUT. Output current in mA.

Table 19. Read Register – Die Temperature 444 – 273 where ADC_Die_Temp = 12 bits from ADC_Die_Temp_H and ADC_Die_Temp_L. 46HEX [7:0] ADC_Die_Temp_L R - 8 LSB of current die temperature in °C. 47HEX [3:0] ADC_Die_Temp_H R - 4 MSB of current die temperature in °C. Table 20. Read Register – Operating Frequency 48HEX [7:0] OP_FREQ[7:0] R - 8 LSB AC signal frequency on the coil. 49HEX [7:0] OP_FREQ[15:8] R - 8 MSB AC signal frequency on the coil. Table 21. Alignment X Value Register coil in the X-direction. The value is application-specific. Table 22. Alignment Y Value Register coil in the Y-direction. The value is application-specific.

Table 23. Command Register 4EHEX [7:6] Reserved R 0HEX Reserved.

12.1 Power Dissipation and Thermal Requirements

the overall thermal resistivity and therefore the board’s heat-sinking efficiency.  Improving the power dissipation capability of the PCB design and improving the thermal coupling of the component to the PCB.  Introducing airflow into the system. (AHG52) is nominally θ JA=47°C/W with 8 th ermal vias. Operation is specified to a maximum steady -state ambient temperature (T A) of 85°C. characteristics specified by the JEDEC 51 standard.

12.2 Recommended Coils

Table 24. Recommended Coil Manufacturers

12.3 Typical Application Schematic

Figure 24. P9221-R Typical Application Schematic

12.4 Bill of Materials (BOM)

Table 25. P9221-R MM Evaluation Kit V2.1 Bill of Materials

1 AC2T, VDD5V, VPP18,

16 PTH_TP Test Pad

2 AC2, LC 2 NP Test Point

3 C1, C2, C3, C5 4 100nF/5

8 C10, C11, C21, C22,

9 C12 1 NP CAP CER 10UF 25V X5R 0603 CL10A106MA8NRNC 603

10 C18 1 NP CAP CER 1UF 10V X5R 0402 GRM155R61A105KE15D 402

11 C20 1 1uF CAP CER 1UF 10V X5R 0402 GRM155R61A105KE15D 402

14 D1 1 LED LED GREEN CLEAR 0603 SMD 150060GS75000 0603_diode

16 GND1, VRECT, VOUT,

5 Test

17 L1 1 RX coil AMOTECH, Rx Power Coil ASC-504060E00-S00 10MIL_35PAD

18 J1 1 NP HEADER_1X5_0P1PITCH60P42D 68002-205HLF header_1x5_0p1Pitch60p42d

19 RTS 1 NP

21 R2 1 36 RES SMD 36 OHM 5% 1/2W 0805 ERJ-P06J360V 805

24 R15, R16 2 10K RES SMD 10KOHM 1% 1/10W 0603 RC0603FR-0710KL 603

25 R17, R19, R23, R27,

26 R18, R22, ,R33 3 NP RES SMD 10K OHM 5% 1/10W 0402 ERJ-2GEJ103X 402

28 U1 1 P9221-R Wireless power receiver P9221-R csp52_2p64x3p94_0p4mm

29 U2 1 NP IC EEPROM 128KBIT 400KHZ 8TDFN 24AA128T-I/MNY TDFN08

Figure 25. Package Outline Drawing

1. Recommended Land Pattern

Figure 26. AHG52 52-WLCSP Land Pattern

© 2017 Integrated Device Technology, Inc. 34 April 4, 2017 15. Special Notes: AHG52 WLCSP-52 Package Assembly Unopened dry packaged parts have a one-year shelf life. The HIC indicator card for newly-opened dry packaged parts should be checked. If there is any moisture content, the parts must be baked for a minimum of 8 hours at 125˚C within 24 hours of the assembly reflow process. 16. Marking Diagram IDT P9221 YYWW $-R 1. Line 1 company name. 2. Truncated part number. 3. “YYWW” is the last digit of the year and week that the part was assembled. is the lot sequential code. 4. “$” denotes mark code, -R is part of the device part number 17. Ordering Information Orderable Part Number Description and Package MSL Rating Shipping Packaging Ambient Temperature P9221-RAHGI8 P9221-R Wireless Power Receiver for 15W MSL1 Tape and reel 0°C to +85°C P9221-R-EVK P9221-R-EVK Evaluation Board

© 2017 Integrated Device Technology, Inc. 35 April 4, 2017 18. Revision History Revision Date Description of Change April 4, 2017  Update to WPC-1.2.3 compliant  Update for I2C slave address = 61HEX  Update for device identification register  Update for firmware revision number register  Updates for Table 13 and Table 16.  Update for recommended coil part number and related entry in BOM.  Update for disclaimer  Addition of R9221-R Evaluation Kit order code  Minor edits December 16, 2016 Preliminary release. Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.IDT.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the ri ght to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performanc e specifications and operating parameters of the described products are determined in an independent state and are not guaran teed to perform the same way when installed in customer products. The information contained herein is provided without representati on or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non -infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life suppor t systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, wri tten agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. Fo r datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . All contents of this document are copyright of Integrated Device Technology, Inc. All rights reserved.