DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

  • Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 17

Technical content

Datasheet sections

  • 1.1 Pin Assignments
  • 1.2 Pin Descriptions
  • 2.1 Absolute Maximum Ratings
  • 2.2 Thermal Information
  • 2.3 Recommended Operating Conditions
  • 2.4 Electrical Specifications
  • 5.1 Evaluation Board Photos
  • 5.2 Evaluation Board Schematic
  • 5.3 Evaluation Board Operation

Features

■ Frequency: 10.7 – 12.75 GHz ■ Gain: 19.5dB ■ Noise Figure: 1.4dB ■ Output P1dB: -7dBm ■ Power Consumption: 12.5mW/ch ■ Channel Isolation: 37dB minimum ■ Supply Voltage: 0.9 – 1.0V ■ Common bias control input ■ Compact size for planar integration on λ/2 grid ■ 2.7 × 2.7 × 0.9 mm, 23-pin BGA ■ -40°C to +85°C ambient operating temperature range Note: Performance is typical at 11.7GHz. See the Specifications and Typical Performance Characteristics sections for more details.

Applications

■ Electronically Steered Phased Array Antennas (ESAs) ■ Aerospace, Maritime, and Satcom-on-the-move (SOTM) ■ Ku-Band SATCOM Terminals ■ Communication, Electronic Warfare (EW) and Radar Systems RFO1 [2] CH1 CH2 VDD2 VDD1 IREF RFI1 [1] RFO2 [4] RFI2 [3] F6921

1.1 Pin Assignments

Figure 2. Pin Assignments for 2.7 × 2.7 mm 23-pin FCBGA Package – Top View

1.2 Pin Descriptions

GND Ground – DC and RF ground. A3 VDD1 Power Input Positive supply voltage input for channel 1. E3 VDD2 Power Input Positive supply voltage input for channel 2. B1 RFI1 Analog Input Channel 1 RF input port. D1 RFI2 Analog Input Channel 2 RF input port. B5 RFO1 Analog Output Channel 1 RF output port. D5 RFO2 Analog Output Channel 2 RF output port.

X0010170 Rev.1.0 Apr 8, 2021 Page 5 2. Specifications Exposure of the device to parameter values outside of the range listed below may reduce the operating lifetime and adversely and permanently alter the device characteristics. Furthermore, functional operation at or near absolute maximum ratings is not implied.

2.1 Absolute Maximum Ratings

Parameter Symbol Conditions Minimum Maximum Units Supply Voltage VDD -0.3 1.2 V Reference Current IREF 0 250 μA Input RF Pin DC Voltage VDC_RFI -0.3 1.0 V Output RF Pin DC Voltage VDC_RFO -0.3 1.2 V RF Input Power PIN VDD = 1.0V, VSWR<2:1 0 dBm Junction Temperature TJ 125 °C ESD – Human Body Model VHBM JS-001-2012 750 V ESD – Charged Device Model VCDM JESD22-C101 250 V

2.2 Thermal Information

Parameter Symbol Value Units Theta JB. Junction to board. θJB 14 °C/W Theta JC. Junction to case. (case top) θJC 108 °C/W Theta JA. Junction to ambient. θJA 47 °C/W Storage Temperature TSTOR -40 to +150 °C Lead Temperature (soldering, 30s) TLEAD 260 °C

X0010170 Rev.1.0 Apr 8, 2021 Page 6

2.3 Recommended Operating Conditions

Parameter Symbol Minimum Typical Maximum Units RF Frequency Range fRF 10.7 12.75 GHz Power Supply Voltage VDD 0.9 0.95 1.0 V Reference Bias Current at -40°C IREF 43 50 58 μA Reference Bias Current at +25°C 102 120 138 μA Reference Bias Current at +85°C 156 184 212 μA Ambient Temperature TA -40 85 °C RF Pin Load Impedance ZRF 50 Ω

2.4 Electrical Specifications

Specifications apply when operated at TAMB = 25°C. 2.4.1. DC Electrical Specifications Parameter Symbol Conditions Minimum Typical Maximum Units Supply Current, Per Channel IDD VDD = 0.95V, IREF = 120μA 13 mA Supply Current, Idle-state [1] IDD_IDLE IIREF = 0μA 1 μA 1. IREF pin may be grounded or floating to achieve idle-state.

X0010170 Rev.1.0 Apr 8, 2021 Page 7 2.4.2. RF Electrical Specifications Unless stated otherwise, all specifications are for VDD = 0.95V, IREF = 120μA, TAMB = 25°C, ZS = ZL = 50Ω, fRF = 11.7GHz. Parameter Symbol Condition Minimum Typical Maximum Units Gain G 19.5 dB Gain Flatness vs. Frequency GVAR_FREQ fRF = 10.7 – 12.75 GHz 0.9 dB Within any 250MHz 0.16 dB Noise Figure NF 1.4 dB Output 1dB Compression Point OP1dB -7 dBm Output 3rd Order Intercept Point OIP3 Pin = -35 dBm/tone, Δf = 1MHz 2 dBm Input Return Loss IRL 22 dB Output Return Loss ORL 12 dB Reverse Isolation ISO 35 dB Channel-to-channel Isolation ISOCH-CH fRF = 10.7 – 12.75 GHz 37 dB

5.1 Evaluation Board Photos

Figure 14. Evaluation Board - Top View Figure 15. Evaluation Board - Bottom View

5.2 Evaluation Board Schematic

Figure 16. Evaluation Board - Schematic Table 1. Bill of Material (BOM)

X0010170 Rev.1.0 Apr 8, 2021 Page 13

5.3 Evaluation Board Operation

This section provides basic information on operating the F6921 evaluation board. For more information about the evaluation board, see the F69xx Evaluation Board Manual on the F6921 product page. 5.3.1. Single Power Supply Operation Connect the positive and negative outputs of a power supply (VDD) to J11. In addition, connect the positive output of the VDD supply to TP1. While there are two IREF pins on the F6921 device (which are individually accessible via TP1 and TP2 on the evaluation board), these pins (A4 and E4) are internally connected to the same node on the IC, simultaneously controlling the bias of channels 1 and 2. Set the power supply to 0.95V and enable the power supply output. Monitor the VDD supply output current to confirm the nominal bias point is set correctly (approximately 24mA). 5.3.2. Independent VDD and IREF Bias Control 5.3.2.1. Two Voltage Sources Connect the positive and negative outputs of a power supply (VDD) to J11. In addition, connect the positive output of a second supply (VREF) to TP1 and the negative output to the negative output of the VDD supply. Set both power supplies to 0.95V and enable the power supply outputs. Monitor the IDD of the VDD supply to confirm the nominal bias point is set correctly (approximately 24mA). 5.3.2.2. Voltage Source and Current Source Connect the positive and negative outputs of a power supply (VDD) to J11. In addition, connect an independent current supply (IREF) to TP1 and the ground of the current supply to the negative terminal of the VDD supply. Set VDD to 0.95V, IREF to 120μA and enable the power supply outputs. Monitor the IDD of the VDD supply to confirm the nominal bias point is set correctly (approximately 24mA).

X0010170 Rev.1.0 Apr 8, 2021 Page 14 6. Package Outline Drawings The package outline drawings are located at the end of this document and are accessible from the Renesas website (see Ordering Information for POD links). The package information is the most current data available and is subject to change without revision of this document. 7. Marking Diagram  Lines 1 and 2: Renesas part number  Line 3:

  • # is the device step
  • YW is the last digit of the year and workweek code
  • $ is the lot sequential code and mark location code 8. Ordering Information Orderable Part Number Package MSL Rating Carrier Type Temperature F6921AVRI 2.7 × 2.7 × 0.9 mm 23-BGA 3 Tray -40°C to +85°C F6921AVRI8 2.7 × 2.7 × 0.9 mm 23-BGA 3 Reel -40°C to +85°C F6921EVB F6921 Evaluation Board 9. Revision History Revision Date Description 1.0 Apr 8, 2021 Initial release. Final Datasheet. IDTF69 21AVRI #YW$ Top view (ball side down)

nXØb nxØb © Integrated Device Technology, Inc.

© Integrated Device Technology, Inc. Package Revision HistoryRev No.Date CreatedDescriptionDec. 6, 2018Rev 00Initial Release

TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com Contact Information For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) © 2020 Renesas Electronics Corporation. All rights reserved.