50029Z

HA-5002_06 INTERSIL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 14

Technical content

Features

 Monolithic Construction  Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

 Line Driver  Data Acquistion  110MHz Buffer  Radara Cable Driver  High Power Current Booster  High Power Current Source  Sample and Holds  Video Products

Ordering Information

TEMP. RANGE (°C) PACKAGE PKG. DWG. # HA2-5002-2 HA2-5002-2 -55 to 125 8 Pin Metal Can T8.C HA2-5002-5 HA2-5002-5 0 to 75 8 Pin Metal Can T8.C HA3-5002-5 HA3-5002-5 0 to 75 8 Ld PDIP E8.3 HA3-5002-5Z (Note) HA3-5002-5Z 0 to 75 8 Ld PDIP* (Pb-free) E8.3 HA4P5002-5 HA4P5002-5 0 to 75 20 Ld PLCC N20.35 HA4P5002-5Z (Note) HA4P5002-5Z 0 to 75 20 Ld PLCC (Pb-free) N20.35 HA9P5002-5 50025 0 to 75 8 Ld SOIC M8.15 HA9P5002-5Z (Note) 50025Z 0 to 75 8 Ld SOIC (Pb-free) M8.15 HA9P5002-9 50029 -40 to 85 8 Ld SOIC M8.15 HA9P5002-9Z (Note) 50029Z -40 to 85 8 Ld SOIC (Pb-free) M8.15 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. March 8, 2006 FN2921.11Data Sheet CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003-2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.

2 FN2921.11 March 8, 2006 Pinouts HA-5002 (PDIP, SOIC) TOP VIEW HA-5002 (PLCC) TOP VIEW HA-5002 (METAL CAN) TOP VIEW NOTE: Case Voltage = Floating OUT V2+ NC V1- V1+ V2- NC IN 193 2 201 9 10 11 12 13 V2- NC NC NC NC NC IN NC V1- NC V2+ NC NC NC NC NC V1+ NC OUT NC IN V2-V2+ OUT V1+ NC V1- NC HA-5002

3 FN2921.11 March 8, 2006 Absolute Maximum Ratings Thermal Information Operating Conditions Temperature Range Thermal Resistance (Typical, Note 2)θ JA (°C/W) θJC (°C/W) (PLCC and SOIC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Maximum power dissipation, including load conditions, must be designed to maintain the maximum junction temperature below 175°C for the can packages, and below 150°C for the plastic packages. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical SpecificationsVSUPPL Y = ±12V to ±15V, RS = 50Ω, RL = 1kΩ, CL = 10pF , Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP (°C) UNITSMIN TYP MAX MIN TYP MAX INPUT CHARACTERISTICS Offset Voltage 25 - 5 20 - 5 20 mV Full - 10 30 - 10 30 mV Average Offset Voltage Drift Full - 30 - - 30 - µV/°C Bias Current 25 - 2 7 - 2 7 µA Full - 3.4 10 - 2.4 10 µA Input Resistance Full 1.5 3 - 1.5 3 - M Ω Input Noise Voltage 10Hz-1MHz 25 - 18 - - 18 - µVP-P TRANSFER CHARACTERISTICS Voltage Gain (VOUT = ±10V) R L = 50Ω 25 - 0.900 - - 0.900 - V/V R L = 100Ω 25 - 0.971 - - 0.971 - V/V R L = 1kΩ 25 - 0.995 - - 0.995 - V/V R L = 1kΩ Full 0.980 - - 0.980 - - V/V -3dB Bandwidth V IN = 1VP-P 25 - 110 - - 110 - MHz AC Current Gain 25 - 40 - - 40 - A/mA OUTPUT CHARACTERISTICS Output Voltage Swing R L = 100Ω 25 ±10 ±10.7 - ±10 ±11.2 - V R L = 1kΩ, VS = ±15V Full ±10 ±13.5 - ±10 ±13.9 - V R L = 1kΩ, VS = ±12V Full ±10 ±10.5 - ±10 ±10.5 - V Output Current V IN = ±10V, RL = 40Ω 25 - 220 - - 220 - mA Output Resistance Full - 3 10 - 3 10 Ω Harmonic Distortion V IN = 1VRMS , f = 10kHz 25 - <0.005 - - <0.005 - % TRANSIENT RESPONSE Full Power Bandwidth (Note 3) 25 - 20.7 - - 20.7 - MHz Rise Time 25 - 3.6 - - 3.6 - ns Propagation Delay 25 - 2 - - 2 - ns Overshoot 25 - 30 - - 30 - % Slew Rate 25 1.0 1.3 - 1.0 1.3 - V/ns Settling Time To 0.1% 25 - 50 - - 50 - ns HA-5002

FIGURE 1. LARGE AND SM ALL SIGNAL RESPONSE

5 FN2921.11 March 8, 2006 Schematic Diagram

Application Information

The wide bandwidth of the HA-5002 necessitates that high frequency circuit layout procedures be followed. Failure to follow these guidelines can result in marginal performance. Probably the most crucial of the RF/video layout rules is the use of a ground plane. A ground plane provides isolation and minimizes distributed circuit capacitance and inductance which will degrade high frequency performance. Other considerations are proper power supply bypassing and keeping the input and output connections as short as possible which minimizes distributed capacitance and reduces board space. Power Supply Decoupling For optimal device performance, it is recommended that the positive and negative power supplies be bypassed with capacitors to ground. Ceramic capacitors ranging in value from 0.01 to 0.1µF will minimize high frequency variations in supply voltage, while low frequency bypassing requires LARGE SIGNAL WAVEFORMS LARGE SIGNAL WAVEFORMS Test Circuit and Waveforms (Continued) VOUT VIN R S = 50Ω, RL = 100Ω VOUT VIN R S = 50Ω, RL = 1kΩ R 9 R 10 Q 25 Q 9 Q 10 R 5 Q 11 Q 15 Q 23 R 7 Q 21 Q 22 Q 24 Q 27 Q 26 R 8 Q 20 Q 18 Q 3 R 4 R 1 Q 7 Q 4 Q 8 R 6 R 3R 12 Q 16 Q 14 Q 13 R 2 R N3 R 11 Q 5 Q 6 Q 12 R N1 Q 19 R N2 V1- V2- OUT V2+ V1+ Q 1 Q 2 IN Q 17 HA-5002

capacitor is dependent on frequency. slight reductions in slew rate and bandwidth. generally yields the best results. FIGURE 2. MAXIMUM POWER DISSIPATION vs TEMPERATURE

10 FN2921.11 March 8, 2006 Metallization Mask Layout HA-5002 V1- IN OUT V2+ V1+ (ALT) V1- (ALT) V2- V1+ HA-5002

11 FN2921.11 March 8, 2006 HA-5002 Dual-In-Line Plastic Packages (PDIP) CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L A 1 -A- 0.010 (0.25) C AM BS NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protru- sions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be per- pendicular to datum . 7. eB and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). eA -C- E8.3 (JEDEC MS-001-BA ISSUE D)

8 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.355 0.400 9.01 10.16 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - e A 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N8 8 9 Rev. 0 12/93

12 FN2921.11 March 8, 2006 Metal Can Packages (Can) NOTES: 1. (All leads) Øb applies between L1 and L2. Øb1 applies between L2 and 0.500 from the reference plane. Diameter is uncontrolled in L1 and beyond 0.500 from the reference plane. 2. Measured from maximum diameter of the product. α is the basic spacing from the centerline of the tab to terminal 1 and β is the basic spacing of each lead or lead position (N -1 places) from α, looking at the bottom of the package. 4. N is the maximum number of terminal positions. 5. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 6. Controlling dimension: INCH. Øb ØD2 Ø e k1 k βØb1 BASE AND SEATING PLANE F Q ØD ØD1 REFERENCE PLANE L A α Øb2Øb1 BASE METAL LEAD FINISH SECTION A-A A A N CL T8.C MIL-STD-1835 MACY1-X8 (A1)

8 LEAD METAL CAN PACKAGE

A 0.165 0.185 4.19 4.70 - Øb 0.016 0.019 0.41 0.48 1 Øb1 0.016 0.021 0.41 0.53 1 Øb2 0.016 0.024 0.41 0.61 - ØD 0.335 0.375 8.51 9.40 - ØD1 0.305 0.335 7.75 8.51 - ØD2 0.110 0.160 2.79 4.06 - e 0.200 BSC 5.08 BSC - e1 0.100 BSC 2.54 BSC - F - 0.040 - 1.02 - k 0.027 0.034 0.69 0.86 - k1 0.027 0.045 0.69 1.14 2 L 0.500 0.750 12.70 19.05 1 L1 - 0.050 - 1.27 1 L2 0.250 - 6.35 - 1 Q 0.010 0.045 0.25 1.14 - α 45o BSC 45 o BSC 3 β 45o BSC 45 o BSC 3 N8 8 4 Rev. 0 5/18/94 HA-5002

13 FN2921.11 March 8, 2006 HA-5002 Plastic Leaded Chip Carrier Packages (PLCC) A SEATING PLANE 0.020 (0.51) MIN VIEW “A” D2/E2 0.025 (0.64) 0.045 (1.14)R 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP EE1 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER CL D 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) MIN 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN VIEW “A” TYP. 0.004 (0.10)C -C- D2/E2 CL NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. -C- N20.35 (JEDEC MS-018AA ISSUE A)

20 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.385 0.395 9.78 10.03 - D1 0.350 0.356 8.89 9.04 3 D2 0.141 0.169 3.59 4.29 4, 5 E 0.385 0.395 9.78 10.03 - E1 0.350 0.356 8.89 9.04 3 E2 0.141 0.169 3.59 4.29 4, 5 N2 0 2 0 6 Rev. 2 11/97

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN2921.11 March 8, 2006 HA-5002 Small Outline Plastic Packages (SOIC) INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45° C H 0.25(0.010) BM M α NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N8 8 7 α 0° 8° 0° 8° - Rev. 1 6/05