49FCT3805BQG8 IDT | Alldatasheet

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3.3V CMOS BUFFER/CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE MAY 2010 2005 Integrated Device Technology, Inc. DSC 6879/-c IDT49FCT3805B COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS BUFFER/CLOCK DRIVER DESCRIPTION: The FCT3805B is a 3.3 volt, non-inverting clock driver built using advanced dual metal CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its own output enable control. The device has a "heartbeat" monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The FCT3805B offers low capacitance inputs with hysteresis. The FCT3805B is designed for high speed clock distribution where signal quality and skew are critical. The FCT3805B also allows single point-to-point transmission line driving in applications such as address distribution, where one signal must be distributed to multiple recievers with low skew and high signal quality. For more information on using the FCT3805B with two different input frequencies on bank A and B, please see AN-236. FUNCTIONAL BLOCK DIAGRAM

5 OA1 - OA5

FEATURES:

  • 0.5 MICRON CMOS Technology
  • Guaranteed low skew < 500ps (max.)
  • Very low duty cycle distortion < 1.0ns (max.)
  • Very low CMOS power levels
  • TTL compatible inputs and outputs
  • Inputs can be driven from 3.3V or 5V components
  • Two independent output banks with 3-state control
  • 1:5 fanout per bank
  • "Heartbeat" monitor output CC = 3.3V ± 0.3V
  • Available in SSOP, SOIC, and QSOP packages The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE IDT49FCT3805B 3.3V CMOS BUFFER/CLOCK DRIVER ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Max Unit VTERM(2) Terminal Voltage with Respect to GND –0.5 to +4.6 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to +7 V VTERM(4) Terminal Voltage with Respect to GND –0.5 to V CC+0.5 V TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –60 to +60 mA NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. V CC terminals. 3. Input terminals. 4. Outputs and I/O terminals. CAPACITANCE (TA = +25OC, f = 1.0MHz) Symbol Parameter(1) Conditions Typ. Max. Unit CIN Input Capacitance V IN = 0V 4.5 6 pF COUT Output Capacitance V OUT = 0V 5.5 8 pF NOTE: 1. This parameter is measured at characterization but not tested. PIN DESCRIPTION Pin Names Description OEA, OEB 3-State Output Enable Inputs (Active LOW) INA, IN B Clock Inputs OAn, OBn Clock Outputs MON Monitor Output FUNCTION TABLE (1) Inputs Outputs OEA, OEB INA, INB OAn, OBn MON LLL L LHH H HLZ L HH Z H NOTE: 1. H = HIGH L = LOW Z = High-Impedance

3.3V CMOS BUFFER/CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified Commercial: TA = 0°C to +70°C, Industrial: TA = -40°C to +85°C, VCC = 3.3V ± 0.3V Symbol Parameter Test Conditions(1) Min. Typ. Max. Unit VIH Input HIGH Level (Input pins) Guaranteed Logic HIGH Level 2 — 5.5 V Input HIGH Level (I/O pins) 2 — V CC + 0.5 VIL Input LOW Level (Input and I/O pins) Guaranteed Logic LOW Level –0.5 — 0.8 V IIH Input HIGH Current (Input pins) V CC = Max. V I = 5.5V — — ±1 Input HIGH Current (I/O pins) V I = VCC —— ±1µ A IIL Input LOW Current (Input pins) V CC = Max. V I = GND — — ±1 Input LOW Current (I/O pins) V I = GND — — ±1 IOZH High Impedence Output Current V CC = Max. V O = VCC —— ±1µ A IOZL (3-State Output Pins) V O = GND — — ±1 VIK Clamp Diode Voltage V CC = Min., IIN = –18mA — –0.7 –1.2 V IODH Output HIGH Current V CC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) –36 –60 –110 mA IODL Output LOW Current V CC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) 50 90 200 m A VOH Output HIGH Voltage V CC = Min. I OH = –0.1mA V CC–0.2 — — VIN = VIH or VIL IOH = –8mA 2.4 (5) 3—V VOL Output LOW Voltage V CC = Min. I OL = 0.1mA — — 0.2 VIN = VIH or VIL IOL = 16mA — 0.2 0.4 V IOL = 24mA — 0.3 0.5 IOFF Input Power Off Leakage V CC = 0V, VIN = 4.5V — — ±1µ A IOS Short Circuit Current(4) VCC = Max., V O = GND(3) –60 –135 –240 mA VH Input Hysteresis — — 150 — mV ICCL Quiescent Power Supply Current V CC = Max. — 0.1 10 µA ICCH VIN = GND or VCC ICCZ NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable dev ice type. 2. Typical values are at Vcc = 3.3V, +25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. V OH = Vcc - 0.6V at rated current.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE IDT49FCT3805B 3.3V CMOS BUFFER/CLOCK DRIVER NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable dev ice type. 2. Typical values are at V CC = 3.3V, +25°C ambient. 3. Per TTL driven input (V IN = VCC -0.6V); all other inputs at V CC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 5. Values for these conditions are examples of the I C formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fONO) ICC = Quiescent Current (I CCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input (V IN = VCC -0.6V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at D H ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fO = Output Frequency NO = Number of Outputs at f O All currents are in milliamps and all frequencies are in megahertz. POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit ∆ICC Quiescent Power Supply Current V CC = Max. — 10 30 µA TTL Inputs HIGH V IN = VCC –0.6V(3) ICCD Dynamic Power Supply Current(4) VCC = Max. V IN = VCC — 0.035 0.06 mA/MHz Outputs Open V IN = GND OEA = OEB = GND Per Output Toggling 50% Duty Cycle IC Total Power Supply Current(6) VCC = Max. V IN = VCC — 0.9 1.6 Outputs Open V IN = GND fO = 25MHz 50% Duty Cycle V IN = VCC –0.6V — 0.9 1.6 OEA = OEB = VCC VIN = GND Mon. Output Toggling V CC = Max. V IN = VCC —2 0 3 3 (5) mA Outputs Open V IN = GND fO = 50MHz 50% Duty Cycle V IN = VCC –0.6V — 20 33 (5) OEA = OEB = GND V IN = GND Eleven Outputs Toggling

3.3V CMOS BUFFER/CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE NOTES: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. t PLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested. SWITCHING CHARACTERISTICS OVER OPERATING RANGE (3,4) Commercial Industrial Symbol Parameter Conditions (1) Min.(2) Max. Unit tPLH Propagation Delay C L = 50pF 1.5 5 1.5 5.2 ns tPHL INA to OAn, INB to OBn R L = 500Ω tR Output Rise Time — 2 — 2 ns tF Output Fall Time — 2 — 2 ns tSK(O) Output skew: skew between outputs of all banks of — 0.5 — 0.6 ns same package (inputs tied together) tSK(P) Pulse skew: skew between opposite transitions — 1 — 1 ns of same output (|tPHL -– tPLH|) tSK(T) Package skew: skew between outputs of different — 1.2 — 1.2 ns packages at same power supply voltage, temperature, package type and speed grade tPZL Output Enable Time 1.5 6 1.5 6 ns tPZH OEA to OAn, OEB to OBn tPLZ Output Disable Time 1.5 5 1.5 5 ns tPHZ OEA to OAn, OEB to OBn

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE IDT49FCT3805B 3.3V CMOS BUFFER/CLOCK DRIVER D.U.T. VIN VOUT VCC RT Pulse Generator 50pF 500 500 GND CONTROL INPUT OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH 1.5V 3.5V SWITCH CLOSED SWITCH OPEN VOL VOH0.3V 0.3V tPLZtPZL tPZH tPHZ 3.5V 1.5V 1.5V ENABLE DISABLE VOH tPLH tPHL VOL 1.5V 1.5V tR tF 2.0V 0.8V INPUT OUTPUT tPLH tPHL VOH 1.5V 1.5V VOL tSK(p) = |tPHL - tPLH| INPUT OUTPUT tPLH1 OUTPUT 1 OUTPUT 2 tSK(o) tPLH2 VOH 1.5V 1.5V VOL VOH 1.5V VOL INPUT tPHL1 tPHL2 tSK(o) tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1| INPUT tPLH1 PACKAGE 1 OUTPUT tSK(t) tPLH2 VOH 1.5V 1.5V VOL VOH 1.5V VOL tPHL1 tPHL2 tSK(t) tSK(t) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1| PACKAGE 2 OUTPUT Package Delay TEST CIRCUITS AND WAVEFORMS Pulse Skew - tSK(P) Test Circuits for All Outputs DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to Z OUT of the Pulse Generator. Test Switch Disable LOW 6V Enable LOW Disable HIGH GND Enable HIGH SWITCH POSITION Output Skew - t SK(X) Output Skew - t SK(O) Package Skew - tSK(T) NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: f ≤ 1.0MHz; t F ≤ 2.5ns; t R ≤ 2.5ns

3.3V CMOS BUFFER/CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

ORDERING INFORMATION

X Package 3805B Non-Inverting 3.3V Buffer/Clock Driver SO SOG PY PYG Q QG Small Outline IC SOIC - Green Shrink Small Outline IC SSOP - Green Quarter-size Small Outline IC QSOP - Green Blank I Commercial (0°C to +70°C) Industrial (-40°C to +85°C) XXXX X Package CORPORATE HEADQUARTERS for SALES: for Tech Support: 6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 clockhelp@idt.com San Jose, CA 95138 fax: 408-284-2775 www.idt.com