48SWTQFN-EP

Maxim Integrated Produc...

3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output 2019

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MAX9288_V01 MAXIM | Alldatasheet

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Technical content

The MAX9288/MAX9290 gigabit multimedia serial link (GMSL) deserializers receive data from a GMSL serializer over 50Ω coax or 100Ω shielded twisted-pair (STP) cable and output deserialized data on the CSI-2 outputs. The MAX9290 has HDCP content protection but other - wise is the same as the MAX9288. The deserializers pair with any GMSL serializer capable of coax output. When programmed for STP input, they are backward compatible with any GMSL serializer. The audio channel supports L-PCM I 2S stereo and up to eight channels of L-PCM in TDM mode. Sample rates of 32kHz to 192kHz are supported with sample depth up to 32 bits. The embedded control channel operates at 9.6kbps to 1Mbps in UART-to-UART and UART-to-I 2C modes, and up to 1Mbps in I 2C-to-I2C mode. Using the control channel, a µC can program serializer, deserializer, and peripheral device registers at any time, independent of video timing, and manage HDCP operation (MAX9290). Two GPIO ports are included, allowing display power- up and switching of the backlight, among other uses. A continuously sampled GPI input supports touch-screen controller interrupt requests in display applications. For use with longer cables, the deserializers have a pro - grammable cable equalizer. The serial input meets ISO 10605 and IEC 61000-4-2 ESD standards. The GMSL supply is 3.0V to 3.6V, the MIPI CSI-2 supply is 1.7V to 1.9V, and the I/O supply is 1.7V to 3.6V. The devices are available in lead(Pb)-free, 48-pin, 7mm x 7mm TQFN and SWTQFN packages with exposed pad and 0.5mm lead pitch.

Applications

High-Resolution Automotive Navigation
Rear-Seat Infotainment
Megapixel Camera Systems Benefits and Features
Ideal for High-Definition Video Applications
4-Lane CSI-2 Output with Up to 1Gbps Per Lane
Works with Low-Cost 50Ω Coax Cable and FAKRA Connectors or 100Ω STP
104MHz High-Bandwidth Mode Supports 1920 x 720p/60Hz Display with 24-Bit Color
Equalization Allows 15m Cable at Full Speed
Up to 192kHz Sample Rate and 32-Bit Sample Depth For 7.1 Channel HD Audio
Audio Clock from Audio Source or Audio Sink
Color Lookup Table for Gamma Correction
CNTL0–CNTL3 Control Outputs for HDMI/MHL
Multiple Data Rates for System Flexibility
Up to 3.12Gbps Serial-Bit Rate
6.25MHz to 104MHz Pixel Clock
9.6kbps to 1Mbps Control Channel in UART, Mixed UART/I2C, or I2C Mode with Clock-Stretch Capability
Reduces EMI and Shielding Requirements
Tracks Spread Spectrum on Input
High-Immunity Mode for Maximum Control- Channel Noise Rejection
Peripheral Features for System Power-Up and Verification
Built-In PRBS Tester for BER Testing of the Serial Link
Programmable Choice of 8 Default Device Addresses
Two Dedicated GPIO Ports
Dedicated “Up/Down” GPI for Touch-Screen Interrupt and Other Uses
Remote/Local Wake-Up from Sleep Mode
Meets Rigorous Automotive and Industrial Requirements
-40°C to +105°C Operating Temperature
±8kV Contact and ±12kV Air ISO 10605 and IEC 61000-4-2 ESD Protection Ordering Information appears at end of data sheet. 19-6916; Rev 5; 8/19 MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output Click here for production status of specific part numbers. Simplified Diagram µC GMSL SERIALIZER MAX9288 MAX9290 VIDEO/AUDIO I2C 720p DISPLAY CSI-2 VIDEO/ AUDIO I2C EVALUATION KIT AVAILABLE

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 2 TABLE OF CONTENTS Interfacing Command-Byte-Only I 2C Devices

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 3 TABLE OF CONTENTS (continued)

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 4 TABLE OF CONTENTS (continued)

Table 17. Startup, HDCP Authentication, and Normal Operation (Deserializer is Not a Repeater)—First Table 20. HDCP Authentication and Normal Operation (One Repeater, Two µCs)—First and Second

(Note 1) Continuous Power Dissipation (TA = +70°C) TQFN/SWTQFN (derate 40mW/°C above +70°C) ....3200mW TQFN/SWTQFN to PCB ground (GND), T A = -40°C to +105°C, unless otherwise noted. Typical values are at V AVDD18 = VDVDD18 = VIOVDD = 1.8V, VAVDD3 = 3.3V, TA = +25°C.) (Note 3) Note 1: EP connected to PCB ground. MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 8 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SINGLE-ENDED INPUTS (ADD_, I2CSEL, PWDN, MS, GPI, DRS, EQS, CDS, HIM, SCK, WS) High-Level Input Voltage VIH1 0.65 x VIOVDD V Low-Level Input Voltage VIL1 0.35 x VIOVDD V Input Current IIN1 VIN = 0V to VIOVDD -20 +20 µA THREE-LEVEL LOGIC INPUTS (BWS, CX/TP) High-Level Input Voltage VIH 0.7 x VIOVDD V Low-Level Input Voltage VIL 0.3 x VIOVDD V Mid-Level Input Current IINM (Note 4) -10 +10 µA Input Current IIN -150 +150 µA SINGLE-ENDED OUTPUTS (WS, SCK, SD, CNTL_, INTOUT) High-Level Output Voltage VOH1 IOUT = -2mA DCS = 0 VIOVDD - 0.3 V DCS = 1 VIOVDD - 0.2 Low-Level Output Voltage VOL1 IOUT = 2mA DCS = 0 0.3 VDCS = 1 0.2 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Thermal Characteristics (Note 2) Absolute Maximum Ratings Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

to PCB ground (GND), T A = -40°C to +105°C, unless otherwise noted. Typical values are at V AVDD18 = VDVDD18 = VIOVDD = 1.8V, VAVDD3 = VIOVDD = 3.3V, TA = +25°C.) MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 9 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Short-Circuit Current IOS VO = 0V, DCS = 0 VIOVDD = 3.0V to 3.6V 15 25 39 mAVIOVDD = 1.7V to 1.9V 3 7 15 VO = 0V, DCS = 1 VIOVDD = 3.0V to 3.6V 20 35 63 VIOVDD = 1.7V to 1.9V 5 10 21 MIPI HIGH-SPEED DIFFERENTIAL OUTPUT PORTS (DOUT0–DOUT3_, CLK_) (Note 3) Transmit Static Common-Mode Voltage VCMTX 150 200 250 mV VCMTX Mismatch When Output is Differential 1 or 0 |ΔVCMT(1,0)| 5 mV Transmit Differential Voltage |VOD| 140 200 270 mV VOD Mismatch When Output is Differential 1 or 0 |ΔVOD| 14 mV Output High Voltage VOHHS 360 mV Single-Ended Output Impedance ZOS 40 50 62.5 Ω Single-Ended Output Impedance Mismatch ΔZOS Mismatch of the single-ended output impedance at both DOUT_+ and DOUT_- pins for both differential 1 and 0 10 % MIPI LOW-SPEED SINGLE-ENDED OUTPUT PORTS (DOUT0–DOUT3_, CLK_) Thevenin Output High Level VOH 1.05 1.2 1.3 V Thevenin Output Low Level VOL -50 +50 mV Output Impedance of Low Power Transmitter ZOLP 110 Ω OPEN-DRAIN INPUT/OUTPUT (GPIO0, GPIO1, RX/SDA, TX/SCL, ERR, LOCK, LFLT) High-Level Input Voltage VIH2 0.7 x VIOVDD V Low-Level Input Voltage VIL2 0.3 x VIOVDD V Input Current IIN2 (Note 5) RX/SDA, TX/SCL -100 +5 µALOCK, ERR, GPIO_, LFLT -80 +5 Low-Level Output Voltage VOL2 IOUT = 3mA VIOVDD = 1.7V to 1.9V 0.4 V VIOVDD = 3.0V to 3.6V 0.3 Input Capacitance CIN Each pin (Note 6) 10 pF LINE-FAULT DETECTION INPUT (LMN0, LMN1) Short-to-GND Threshold VTG Figure 1 0.3 V Normal Threshold VTN Figure 1 0.57 1.07 V Open Threshold VTO Figure 1 1.45 VIO + 0.06 V Open Input Voltage VIO Figure 1 1.49 1.75 V

to PCB ground (GND), T A = -40°C to +105°C, unless otherwise noted. Typical values are at V AVDD18 = VDVDD18 = VIOVDD = 1.8V, VAVDD3 = 3.3V, TA = +25°C.) (Note 3) MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 11 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLY Total Supply Current (AVDD_ + DVDD_ + IOVDD) (Note 7) (Worst-Case-Pattern, Figure 5) IWCS BWS = low, fPCLKOUT = 16.6MHz, 1 MIPI lane, RGB666 AVDD3 97 131 mA DVDD18 28 38 IOVDD 0.3 2 AVDD18 21 33 Total 146 197 BWS = low, fPCLKOUT = 33.3MHz, 1 MIPI lanes, RGB666 AVDD3 99 134 DVDD18 45 62 IOVDD 0.3 2 AVDD18 25 34 Total 170 227 BWS = low, fPCLKOUT = 66.6MHz, 2 MIPI lanes, RGB666 AVDD3 103 140 DVDD18 69 94 IOVDD 0.3 2 AVDD18 29 39 Total 201 270 BWS = low, fPCLKOUT = 104MHz, 2 MIPI lanes, RGB666 AVDD3 112 152 DVDD18 100 139 IOVDD 0.3 2 AVDD18 46 63 Total 259 351 BWS = mid, fPCLKOUT = 36.6MHz, 1 MIPI lanes, RGB888 AVDD3 100 136 DVDD18 51 70 IOVDD 0.3 2 AVDD18 27 36 Total 178 236 BWS = mid, fPCLKOUT = 104MHz, 2 MIPI lanes, RGB888 AVDD3 112 153 DVDD18 123 169 IOVDD 0.3 2 AVDD18 55 75 Total 290 394 Sleep-Mode Supply Current ICCS 44 120 µA Power-Down Current ICCZ PWDN = GND 12 75 µA ESD PROTECTION IN+, IN- (Note 8) VESD Human Body Model, RD = 1.5kΩ, CS = 100pF ±8 kVIEC 61000-4-2, RD = 330Ω, CS = 150pF Contact discharge ±8 Air discharge ±12 ISO 10605, RD = 2kΩ, CS = 330pF Contact discharge ±8 Air discharge ±20 All Other Pins (Note 9) VESD Human Body Model, RD = 1.5kΩ, CS = 100pF ±2.5 kV

to PCB ground (GND), T A = -40°C to +105°C, unless otherwise noted. Typical values are at V AVDD18 = VDVDD18 = VIOVDD = 1.8V, VAVDD3 = 3.3V, TA = +25°C.) MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 14 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Audio Skew Relative to Video tASK Video and audio synchronized 3 x tWS 4 x tWS µs SCK, SD, WS Rise-and-Fall Time tR, tF 20% to 80% CL = 10pF, DCS = 1 0.3 3.1 nsCL = 5pF, DCS = 0 0.4 3.8 SD, WS Valid Time Before SCK (2-Channel I2S) tDVB1 tSCK = 1/fSCK, Figure 12 0.20 x tSCK 0.5 x tSCK ns SD, WS Valid Time After SCK (2-Channel I2S) tDVA1 tSCK = 1/fSCK, Figure 12 0.20 x tSCK 0.5 x tSCK ns SD, WS Valid Time Before SCK (8-Channel TDM) tDVB2 tSCK = 1/fSCK, Figure 12 0.20 x tSCK 0.5 x tSCK ns SD, WS Valid Time After SCK (8-Channel TDM) tDVA2 tSCK = 1/fSCK, Figure 12 0.20 x tSCK 0.5 x tSCK ns HIGH-SPEED DIFFERENTAIL OUTPUT PORTS (DOUT0_–DOUT3_, CLK_) (Note 10) 20% to 80% Rise Time and Fall Time tR, tF Bit rate ≤ 1Gbps 0.3 UI 100 ps Data-to-Clock Skew tSKW -0.15 +0.15 UI UI Instantaneous UIINS 1 12.5 ns Common-Level Variation Above 450MHz ΔVCM 15 mVRMS Common-Level Variation Between 50MHz to 450MHz 25 mVPEAK LOW-SPEED DIFFERENTIAL OUTPUT PORTS (DOUT0_–DOUT3_, CLK_) (Note 10) 15% to 85% Rise Time and Fall Time tRLP/tFLP 25 ns 30% to 85% Rise Time and Fall Time Transition from HS to LP tREOP 35 ns GENERAL CSI-2 TIMING SPECIFICATIONS (Note 10, Figure 13) Start of Transmission: Clock Prepare Time tCLK- PREPARE Time that the transmitter drives the clock lane LP-00 line state immediately before HS-0 line state starting the HS transition 38 95 ns End of Transmission: Clock Trail Time tCLK-TRAIL Time that the transmitter drives the HS-0 state after the last payload clock bit of a HS transmission burst 60 ns Clock Start of Transmission Time tCLK- PREPARE + tCLK- ZERO tCLK-PREPARE + time that the transmitter drives the HS-0 state prior to starting the clock 300 ns

to PCB ground (GND), T A = -40°C to +105°C, unless otherwise noted. Typical values are at V AVDD18 = VDVDD18 = VIOVDD = 1.8V, VAVDD3 = 3.3V, TA = +25°C.) Note 3: Limits are 100% production tested at TA = +105°C. Limits over the operating temperature range are guaranteed by design and characterization, unless otherwise noted. Note 4: To provide a mid level, leave the input open, or, if driven, put driver in high impedance. High-impedance leakage current must be less than ±10µA. Note 5: I IN_ min due to voltage drop across the internal pullup resistor. Note 6: Not production tested. Guaranteed by design. Note 7: HDCP enabled (MAX9290 only). IOVDD current is not production tested. For the MAX9288 (or when HDCP is disabled on the MAX9290), subtract the HDCP supply current, as shown in Table 25. Note 8: Specified pin to ground. Note 9: Specified pin to all supply/ground. Note 10: Not production tested, guaranteed by characterization. Note 11: Measured in serial link bit times. Bit time = 1/(30 x f PIXEL) for BWS = 0 or open. Bit time = 1/(40 x f PIXEL) for BWS = 1. MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 15 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Clock End of Transmission Time tEOT Transmitted time interval from the start of tHS-TRAIL or tCLK-TRAIL to start of the LP-11 state following a HS burst 105ns + 12 x UI ns HS Exit Time tHS-EXIT Time that the transmitter drivesLP-11 following a HS burst 100 ns Start of Transmission: Data Prepare Time tHS- PREPARE Time that the transmitter drives the data lane LP-00 line state immediately before the HS-0 line state starting the HS transmission 40ns + 4 x UI 85ns + 6 x UI ns Start of Transition Time tHS- PREPARE + tHS- ZERO tHS-PREPARE + time that the transmitter drives the HS-0 state prior to transmitting the sync sequence 145ns + 10 x UI ns End of Transmission: Data Trail Time tHS-TRAIL Time that the transmitter drives the flipped differential state after last payload data bit of a HS transmission burst Max(8 x UI, 60ns + 4 x UI) ns LP Transmit Time tLPTX Transmitted length of any low-power state period 50 ns

(VAVDD18 = VDVDD18 = VIOVDD = 1.8V, VAVDD3 = 3.3V, TA = +25°C, unless otherwise noted.) MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output Maxim Integrated │ 16 www.maximintegrated.com 100 120 140 160 180 200 220 240 260 15 30 45 60 75 90 105 SUPPLY CURRENT (mA) PCLK FREQUENCY (MHz) SUPPLY CURRENT vs. PIXEL CLOCK FREQUENCY (BWS = OPEN) toc02 PRBS ON, COAX MODE, RGB888, HDCP ON

2 CHANNELS

SUPPLY CURRENT (mA) PCLK FREQUENCY (MHz) SUPPLY CURRENT vs. PIXEL CLOCK FREQUENCY (BWS = HIGH) toc03 PRBS ON, COAX MODE, RGB888, HDCP ON 5 15 25 35 45 55 65 75 85 95 105 SUPPLY CURRENT (mA) PCLK FREQUENCY (MHz) SUPPLY CURRENT vs. PIXEL CLOCK FREQUENCY (BWS = LOW) toc01 PRBS ON, COAX MODE, RGB666, HDCP ON 5 15 25 35 45 55 65 75 85 95 105 SUPPLY CURRENT (mA) PCLK FREQUENCY (MHz) SUPPLY CURRENT vs. PIXEL CLOCK FREQUENCY (BWS = LOW) toc04 PRBS ON, COAX MODE, RGB666, HDCP ON

4 CHANNELS

SUPPLY CURRENT (mA) PCLK FREQUENCY (MHz) SUPPLY CURRENT vs. PIXEL CLOCK FREQUENCY (BWS = HIGH) toc06 PRBS ON, COAX MODE, RGB888, HDCP ON SUPPLY CURRENT (mA) PCLK FREQUENCY (MHz) SUPPLY CURRENT vs. PIXEL CLOCK FREQUENCY (BWS = OPEN) toc05 PRBS ON, COAX MODE, RGB888, HDCP ON PIXEL CLOCK FREQUENCY (MHz) CABLE LENGTH (m) MAXIMUM PIXEL CLOCK FREQUENCY vs. COAX CABLE LENGTH (BER ≤ 10-10) toc07 BER CAN BE AS LOW AS 10-12 FOR CABLE LENGTHS LESS THAN 15m OPTIMUM PE/EQ NO PE, 10.7dB EQ NO PE/EQ Typical Operating Characteristics

(VAVDD18 = VDVDD18 = VIOVDD = 1.8V, VAVDD3 = 3.3V, TA = +25°C, unless otherwise noted.) MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output Maxim Integrated │ 17 www.maximintegrated.com 100mV/div toc09 2ns/div MIPI CLOCK EYE PATTERN 80Mbps 100mV/div toc10 200ps/div MIPI CLOCK EYE PATTERN 1000Mbps 100 120 0 5 10 15 20 PIXEL CLOCK FREQUENCY (MHz) CABLE LENGTH (m) MAXIMUM PIXEL CLOCK FREQUENCY vs. STP CABLE LENGTH (BER ≤ 10-9) toc08 BER CAN BE AS LOW AS 10-12 FOR CABLE LENGTHS LESS THAN 12m OPTIMUM PE/EQ NO PE, 10.7dB EQ NO PE/EQ 6dB PE, 10.7dB EQ 100mV/div toc11 2ns/div MIPI DATA EYE PATTERN 80Mbps 500mV/div toc13 50ns/div MIPI SOT 100mV/div toc12 200ps/div MIPI DATA EYE PATTERN 1000Mbps 500mV/div toc14 50ns/div MIPI EOT Typical Operating Characteristics (continued)

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 18 PIN NAME FUNCTION 1 INTOUT A/V Status Register Interrupt Output. Indicates new data in the A/V status registers. INTOUT is reset when the A/V status registers are read. 2 GPI General-Purpose Input with Internal Pulldown to EP. The serializer GPO (or INT) output follows GPI. 3 I2CSEL I2C Select. Control channel interface protocol select input with internal pulldown to EP. Set I2CSEL = high to select I2C interface. Set I2CSEL = low to select UART interface.

4 GPIO0 Open-Drain, General-Purpose Input/Output, with Internal 60kΩ Pullup to IOVDD

5 BWS

Three-Level Bus Width Select Input. Set BWS to the same level on both sides of the serial link. Set BWS = low, with 6kΩ (max) pulldown for 24-bit mode. Set BWS = high, with 6kΩ (max) pullup to IOVDD for 32-bit mode. Set BWS = open for high-bandwidth mode. 6, 47 AVDD3 3.3V Analog Power Supply. Bypass AVDD3 to EP with 0.1µF and 0.001µF capacitors as close as possible to the device with the smaller capacitor closest to AVDD3.

7 IN+ Noninverting Coax/Twisted-Pair Serial Input

8 IN- Inverting Coax/Twisted-Pair Serial Input

(7mm x 7mm x 0.75mm) CONNECT EP TO GROUND PLANE EP* MAX9288 MAX9290 TOP VIEW RX/SDA + TX/SCL PWDN WS SCK SD ADD2/CNTL2 HIM/CNTL1 IOVDD CDS DVDD18 RSVD 1 2 3 4 5 6 7 8 9 10 11 12 CX/TP AVDD3 LMN1 LMN0 LFLT IOVDD DRS ERR LOCK ADD0/CNTL0 ADD1/CNTL3 DVDD18 EQS GPIO1 DVDD18 MS IN- IN+ AVDD3 BWS GPIO0 I2CSEL GPI INTOUT 36 35 34 33 32 31 30 29 28 27 26 25 AVDD18 DOUT3+ DOUT3- DOUT2+ DOUT2- CLK+ CLK- DOUT1+ DOUT1- DOUT0+ DOUT0- AVDD18 Pin Description Pin Configuration

possible to the device with the smaller value capacitor closest to DVDD18.

11 GPIO1 Open-Drain, General-Purpose Input/Output, with Internal 60kΩ Pullup to IOVDD

12 EQS

13 RX/SDA

RX: Input of the deserializer’s UART. SDA: Data input/output of the deserializer’s I2C Master/Slave.

14 TX/SCL

TX: Output of the deserializer’s UART. SCL: Clock input/output of the deserializer’s I2C Master/Slave. mode to reduce power consumption. externally (system provided clock).

17 SCK

externally (system provided clock). control/data output. Encrypted when HDCP is enabled.

19 ADD2/CNTL2

CNTL2 output automatically after power-up. Table 1. Connect ADD2/CNTL2 to IOVDD with a 30kΩ resistor to set high or leave open to set low. GMSL serializer’s CNTL2 or DIN28 input.

20 HIM/CNTL1

CNTL2 output automatically after power-up. the serializer must be set to the same value. GMSL serializer’s CNTL1, DIN27, or RES input. capacitors as close as possible to the device with the smallest value capacitor closest to IOVDD.

22 CDS

serializer. Set CDS = high when the control channel master µC is connected at the deserializer. possible to the device with the smaller capacitor closest to AVDD18.

38 ADD1/CNTL3

CNTL3 output automatically after power-up. Table 1. Connect ADD1/CNTL3 to IOVDD with a 30kΩ resistor to set high or leave open to set low. CNTL3: Used only in high-bandwidth mode (BWS = open.

39 ADD0/CNTL0

CNTL0 output automatically after power-up. ADD0: Bit value is latched at power-up or when resuming from power-down mode (PWDN = low). See Table 1. Connect ADD0/CNTL0 to IOVDD with a 30kΩ resistor to set high or leave open to set low. CNTL0: Used only in high-bandwidth mode (BWS = open).

40 LOCK

an incorrect serial-word-boundary alignment. LOCK is high when PWDN = low. pullup to IOVDD. ERR is high when PWDN is low.

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 21 PIN NAME FUNCTION

42 DRS

Data-Rate Select Input. DRS is latched upon power-up or when PWDN transitions low-to-high. Set DRS high for pixel clock rates below 16.66MHz (BWS = low), 12.5MHz (BWS = high), or 36.66MHz (BWS = open). Set DRS = low for faster pixel clock rates. 44 LFLT Active-Low Open-Drain Line-Fault Output. LFLT has a 60kΩ internal pullup to IOVDD. LFLT = low indicates a line fault. LFLT is high when PWDN = low.

45 LMN0 Line Fault Monitor Input 0 (See Figure 1)

46 LMN1 Line Fault Monitor Input 1 (See Figure 1)

48 CX/TP Three-Level Coax/Twisted Pair Select Input. Use 6kΩ (max) pullup to IOVDD or pulldown resistor for setting CX/TP = high or low. See Table 12 for function. — EP Exposed Pad. EP is internally connected to device ground. MUST connect EP to the PCB ground plane through an array of vias for proper thermal and electrical performance. SERIAL TO PARALLEL FIFO PARALLEL TO CSI-2 I2S/TDM TX RGB VS DE HS RGB CNTL[3:0] (9B10B) CLK± DOUT0± DOUT1± DOUT2± DOUT3± PWDN BWS REVERSE CONTROL CHANNEL VIDEO MAX9288 MAX9290 IN+ IN- CLKDIV HDCP DECRYPT VS DE HS HDCP DECRYPT HDCP KEYS CDRPLL HDCP CONTROL FCC ACB SD WS SCK CML RX AND EQ ADD[2:0] 8B/10B DECODE/ DESCRAMBLE (MAX9290 ONLY) CONTROL (9B10B) SYNC UART/I2C TX/ SCL RX/ SDA GPIO_GPI I2CSEL ADD0/CNTL0, HIM/CNTL1, ADD2/CNTL2, ADD1/CNTL3 DATA DESCRIPTION REGISTERS INTOUT CONTROL CX/TP ADD[2:0], HIM CDS EQS MS PLL Pin Description (continued) Functional Diagram

Figure 1. Line Fault

Figure 5. Worst-Case Pattern Output Figure 6. I2C Timing Parameters

GMSL SERIALIZER INPUT SIGNAL
VS STARTS LOW AND REMAINS HIGH
REGISTER SETTING DETERMINES IF DE OR HS IS USED

2000 PCLK CYCLES

200 PCLK

protection (HDCP), while the MAX9288 does not. 27-bit high-bandwidth mode, or 78MHz in 32-bit mode. stereo and up to eight channels of L-PCM in TDM mode. cable length and enhances link reliability. while bypass mode uses a user-defined UART protocol. I2C allows half-duplex communication. 4-2 ESD protection standards. devices hold the device addresses. Figure 13. MIPI Output Timing Parameters

Figure 14. 24-Bit Mode Serial Data Format Figure 15. 32-Bit Mode Serial Data Format MAX9290 NOTE: ONLY DOUT[17:0] AND AUDIO HAVE HDCP ENCRYPTION.

24 BITS

DE/VS/HS MUST BE SET AT DOUT[20:18]. MAX9290 NOTE: ONLY DOUT[17:0], DOUT[26:21], AND AUDIO HAVE HDCP ENCRYPTION.

32 BITS

26 CNTL1 CNTL2

Figure 16. High-Bandwidth Mode Serial-Data Format Figure 17. Transmitting a Frame from GMSL to MIPI

27 BITS

26 WS SCK SD RX/

VS/HS MUST BE SET AT DOUT[20:18]. MAX9290 NOTE: ONLY DOUT[17:0], DOUT[26:21] AND ACB HAVE HDCP ENCRYPTION.

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 31 Figure 18. RGB565 Output

8 BITS 16 BITS 8 BITS

DESCRIPTION

SYNCHRONIZATION SHORT PACKET DATA TYPES GENERIC SHORT PACKET DATA TYPES GENERIC LONG PACKET DATA TYPES (TYPE 0X12 USED FOR EMBEDDED AUDIO YUV DATA USER DEFINED BYTE BASED DATA RESERVED RGB DATA RAW DATA

1 OF 4 CHANNEL

8 BITS 8 BITS

NO INPUT WHEN BWS = LOW B1[4:0] R1[4:0] N 2N CONTROLS FS & FE AND PACKET START/END WRD 1 WRD 2 WRD 3 WRD 4 WORD (WC – 2) WORD (WC -1) WORD WCWORD (WC – 3) MSBLSB MSBLSB MSBLSB HS

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 32 Figure 19. RGB666 Output SYNCHRONIZATION SHORT PACKET DATA TYPES GENERIC SHORT PACKET DATA TYPES GENERIC LONG PACKET DATA TYPES (TYPE 0X12 USED FOR EMBEDDED AUDIO YUV DATA USER DEFINED BYTE BASED DATA RESERVED RGB DATA RAW DATA 1 2.25 18 LINE START LINE STOP HS VS DER-0 R-1 R-4 G-0 G-1 G-5 B-0 B-1 B-4 RES RES *PIXEL COUNT NEEDS TO BE A MULTIPLE OF 4 WORD 1 WORD 2 WORD 3 WORD 4 WORD (WC) - 2 WORD (WC) -1 WORD WCWORD (WC) - 3 N* 9/4 X N MSBLSB MSBLSB MSBLSB

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 33 Figure 20. RGB888 Output SYNCHRONIZATION SHORT PACKET DATA TYPES GENERIC SHORT PACKET DATA TYPES GENERIC LONG PACKET DATA TYPES (TYPE 0X12 USED FOR EMBEDDED AUDIO YUV DATA USER DEFINED BYTE BASED DATA RESERVED RGB DATA RAW DATA START LINE STOPWRD 1 WRD 2 WRD 3 WRD 4 WRD WC- 2 WRD WC -1 WRD WCWRD WC - 4WRD 5 WRD 6 WRD WC - 5 WRD WC - 3 G-0 G-1 G-2 G-3 G-4 G-5 G-6 G-7 R-0 R-1 R-2 R-3 R-4 R-5 R-6 R-7 *VESA AND oLDI DEFINE NAMING CONVENTIONS WITH REGARDS TO MSB AND LSB. THE GMSL TO MIPI MAPPING IS SHOWN IN THE TABLE TO THE RIGHT. WORD COUNT PIXEL BYTES BITS 1 3 24 N 3N OLDI = 0 (VESA) R7 (MSB) OLDI = 1 (oDLI) R0 (LSB) R5 (MSB) R6 (LSB) GMSL BIT NAME MIPI BIT NAME R7 (MSB) R0 (LSB)

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 34 Figure 21. YUV422 8-Bit (Muxed) Output SYNCHRONIZATION SHORT PACKET DATA TYPES GENERIC SHORT PACKET DATA TYPES GENERIC LONG PACKET DATA TYPES (TYPE 0X12 USED FOR EMBEDDED AUDIO YUV DATA USER DEFINED BYTE BASED DATA RESERVED RGB DATA RAW DATA

1 OF 4 CHANNEL SELECT

WRD WC- 2 WRD WC -1 WRD WCWRD WC - 3 HS VS DE DOUT18 /HS DOUT19 /VS DOUT20 /DE DOUT21 DOUT26 RES RES DOUT17 RES NO INPUT WHEN BWS = LOW DOUT0 DOUT1 CR-0 CR-1 CR-7 DOUT7 DOUT8 HS VS DE DOUT18 /HS DOUT19 /VS DOUT20 /DE DOUT21 DOUT26 RES RES DOUT17 RES CONTROLS FS & FE AND PACKET START/END DOUT0 DOUT1 DOUT7 DOUT8 HS VS DE DOUT18 /HS DOUT19 /VS DOUT20 /DE DOUT21 DOUT26 RES RES DOUT17 RES DOUT0 DOUT1 DOUT7 DOUT8 Y-0 Y-1 Y-7 HS VS DE DOUT18 /HS DOUT19 /VS DOUT20 /DE DOUT21 DOUT26 RES RES DOUT17 RES Y-0 Y-1 Y-7 RES RES RES RES CB-7 CB-6 CB-5 CB-4 CB-3 CB-2 CB-1 CB-0 Y-7 Y-6 Y-5 Y-4 Y-3 Y-2 Y-1 Y-0 CR-7 CR-6 CR-5 CR-4 CR-3 CR-2 CR-1 CR-0 WRD 1 WRD 2 WRD 3 WRD 4

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 35 Figure 22. YUV422 10-Bit (Muxed) Output SYNCHRONIZATION SHORT PACKET DATA TYPES GENERIC SHORT PACKET DATA TYPES GENERIC LONG PACKET DATA TYPES (TYPE 0X12 USED FOR EMBEDDED AUDIO YUV DATA USER DEFINED BYTE BASED DATA RESERVED RGB DATA RAW DATA 1 2.5 20 LINE START LINE STOP N* 2.5N WRD WC- 2 WRD WC -1 WRD WCWRD WC - 3 HS VS DE DOUT18 /HS DOUT19 /VS DOUT20 /DE DOUT21 DOUT26 RES RES DOUT17 RES NO INPUT WHEN BWS = LOW DOUT0 DOUT1 CR-0 CR-1 CR-2 DOUT2 DOUT10 HS VS DE DOUT18 /HS DOUT19 /VS DOUT20 /DE DOUT21 DOUT26 RES RES DOUT17 RES CONTROLS FS & FE AND PACKET START/END DOUT2 DOUT10 HS VS DE DOUT18 /HS DOUT19 /VS DOUT20 /DE DOUT21 DOUT26 RES RES DOUT17 RES DOUT2 DOUT10 Y-0 Y-1 Y-2 HS VS DE DOUT18 /HS DOUT19 /VS DOUT20 /DE DOUT21 DOUT26 RES RES DOUT17 RES Y-2 RES RES RES RES DOUT9 CB-9 DOUT9 CR-9 DOUT9 DOUT9 Y-9 Y-9 LSB LSB WRD WC - 4 *PIXEL COUNT NEEDS TO BE A MULTIPLE OF 2 Y-8 Y-9Y-2 Y-3 Y-4 Y-5 Y-6 Y-7 CR-8 CR-9 CR-2 CR-3 CR-4 CR-5 CR-6 CR-7 CB-8 CB-9CB-2 CB-3 CB-4 CB-5 CB-6 CB-7 Y2-0 Y2-1 CR2-0 CR2-1 Y1-0 Y1-1 CB1-0 CB1-1 Y-0 Y-1 WRD 1 WRD 2 WRD 3 WRD 4 WRD 5 DOUT0 DOUT1 DOUT0 DOUT1

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 36 Figure 23. YUV422 8-Bit Output SYNCHRONIZATION SHORT PACKET DATA TYPES GENERIC SHORT PACKET DATA TYPES GENERIC LONG PACKET DATA TYPES (TYPE 0X12 USED FOR EMBEDDED AUDIO YUV DATA USER DEFINED BYTE BASED DATA RESERVED RGB DATA RAW DATA

1 OF 4

WRD WC- 2 WRD WC -1 WRD WCWRD WC - 3 HS VS DE DOUT 18/HS DOUT 19/VS DOUT 20/DE DOUT DOUT RES RES DOUT DOUT RES RES NO INPUT WHEN BWS = LOW DOUT DOUT CR-0 CR-1 CR-7 DOUT DOUT DOUT DOUT Y-0 Y-1 Y-7 HS VS DE DOUT 18/HS DOUT 19/VS DOUT 20/DE DOUT DOUT RES RES DOUT DOUT RES RES CONTROLS FS & FE AND PACKET START/END CB-7 CB-6 CB-5 CB-4 CB-3 CB-2 CB-1 CB-0 CR-7 CR-6 CR-5 CR-4 CR-3 CR-2 CR-1 CR-0 Y-7 Y-6 Y-5 Y-4 Y-3 Y-2 Y-1 Y-0 WRD 1 WRD 2 WRD 3 WRD 4

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 37 Figure 24. YUV422 10-Bit Output SYNCHRONIZATION SHORT PACKET DATA TYPES GENERIC SHORT PACKET DATA TYPES GENERIC LONG PACKET DATA TYPES (TYPE 0X12 USED FOR EMBEDDED AUDIO YUV DATA USER DEFINED BYTE BASED DATA RESERVED RGB DATA RAW DATA 1 2.5 20 LINE START LINE STOP N* 2.5N WRD WC- 2 WRD WC -1 WRD WCWRD WC - 3 HS VS DE DOUT 18/HS DOUT 19/VS DOUT 20/DE DOUT DOUT RES RES CR-0 CR-1 CR-2 CONTROLS FS & FE AND PACKET START/END DOUT DOUT DOUT HS VS DE DOUT 18/HS DOUT 19/VS DOUT 20/DE DOUT DOUT DOUT Y-0 Y-1 Y-2 DOUT CB-9 CR-9 DOUT DOUT Y-7 LSB LSB WRD WC - 4 *PIXEL COUNT NEEDS TO BE A MULTIPLE OF 2 DOUT Y-8 DOUT Y-9 Y-0 Y-1 Y-2 Y-7 DOUT DOUT DOUT DOUT DOUT DOUT RES RES DOUT Y-8 DOUT Y-9 Y-8 Y-9Y-2 Y-3 Y-4 Y-5 Y-6 Y-7 CR-8 CR-9 CR-2 CR-3 CR-4 CR-5 CR-6 CR-7 CB-8 CB-9CB-2 CB-3 CB-4 CB-5 CB-6 CB-7 WRD 1 WRD 2 WRD 3 WRD 4 WRD 5

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 38 Figure 25. YUV422 12-Bit Output SYNCHRONIZATION SHORT PACKET DATA TYPES GENERIC SHORT PACKET DATA TYPES GENERIC LONG PACKET DATA TYPES (TYPE 0X12 USED FOR EMBEDDED AUDIO YUV DATA YUV 422 12-BIT = 0x30 RESERVED RGB DATA RAW DATA WRD WC- 2 WRD WC -1 WCWC - 3 CB-8 CB-9 CB-10 CB-11CB-4 CB-5 CB-6 CB-7 HS VS DE DOUT18 /HS DOUT19 /VS DOUT20 /DE DOUT26 CONTROLS FS & FE AND PACKET START/END DOUT12 DOUT13 DOUT14 Y-0 Y-1 Y-2 DOUT11 CB-11 DOUT17 Y-5 LSB WRD WC- 4 DOUT21 Y-6 DOUT3 CB-3 CB-4 DOUT4 DOUT15 DOUT16 Y-3 Y-4 Y-11 DOUT0 DOUT1 CR-0 CR-1 CR-2 DOUT2 HS VS DE DOUT18 /HS DOUT19 /VS DOUT20 /DE DOUT26DOUT12 DOUT13 DOUT14 Y-0 Y-1 Y-2 DOUT11 CR-11 DOUT17 Y-5 DOUT21 Y-6 DOUT3 CR-3 CR-4 DOUT4 DOUT15 DOUT16 Y-3 Y-4 Y-11 LSB LSB LSB WRD WC - 4 CB-1 CB-0 Y-1 Y-0 Y-8 Y-9 Y-10 Y-11Y-4 Y-5 Y-6 Y-7 CR-8 CR-9 CR-10 CR-11 CR-4 CR-5 CR-6 CR-7 CR-3 CR-2 Y-3 Y-2 CR-1 CR-0 Y-1 Y-0 WRD 1 WRD 2 WRD 3 WRD 4 WRD 5 WRD 6

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 39 Figure 26. RAW 8-Bit (Double Load) Output SYNCHRONIZATION SHORT PACKET DATA TYPES GENERIC SHORT PACKET DATA TYPES GENERIC LONG PACKET DATA TYPES (TYPE 0x12 USED FOR EMBEDDED AUDIO YUV DATA USER DEFINED BYTE BASED DATA RESERVED RGB DATA RAW DATA N* N WRD 1 WRD 2 WRD 3 WRD 4 WRD WC- 2 WRD WC -1 WRD WCWRD WC - 3 DOUT21 DOUT26 RES RES NO INPUT WHEN BWS = LOW RESRES P3[7:0] P4[7:0] *PIXEL COUNT NEEDS TO BE A MULTIPLE OF 2 PA-7 PA-6 PA-5 PA-4 PA-3 PA-2 PA-1 PA-0 PB-7 PB-6 PB-5 PB-4 PB-3 PB-2 PB-1 PB-0

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 40 Figure 27. RAW 10-Bit (Double Load) Output SYNCHRONIZATION SHORT PACKET DATA TYPES GENERIC SHORT PACKET DATA TYPES GENERIC LONG PACKET DATA TYPES (TYPE 0X12 USED FOR EMBEDDED AUDIO YUV DATA USER DEFINED BYTE BASED DATA RESERVED RGB DATA RAW DATA WORD COUNT PIXEL BYTES BITS 1 1.25 10 N* 1.25N *PIXEL COUNT NEEDS TO BE A MULTIPLE OF 4 PB-8 PB-9 PB-2 PB-3 PB-4 PB-5 PB-6 PB-7 PA-8 PA-9 PA-2 PA-3 PA-4 PA-5 PA-6 PA-7 WRD 1 WRD 2 WRD 3 WRD 4 WRD 5

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 41 Figure 28. RAW 12-Bit (Double Load) Output SYNCHRONIZATION SHORT PACKET DATA TYPES GENERIC SHORT PACKET DATA TYPES GENERIC LONG PACKET DATA TYPES (TYPE 0X12 USED FOR EMBEDDED AUDIO YUV DATA USER DEFINED BYTE BASED DATA RESERVED RGB DATA RAW DATA 1 1.5 12 LINE START LINE STOP N* 1.5N WRD 4 WRD WC- 2 WRD WC -1 WCWC - 3 CONTROLS FS & FE AND PACKET START/END DOUT11 PA-11 WRD 5 LSB WRD WC- 4 *PIXEL COUNT NEEDS TO BE A MULTIPLE OF 2 DOUT3 PA-3 PA-4 DOUT4 LSB LSB LSB WRD 6 WRD WC - 4 HS VS DE DOUT18 /HS DOUT19 /VS DOUT20 /DE DOUT26DOUT12 DOUT13 DOUT14 PB-0 PB-1 PB-2 DOUT17 PB-5 DOUT21 PB-6 DOUT15 DOUT16 PB-3 PB-4 PB-11 PA-7 PA-6 PA-5 PA-4 PA-11 PA-10 PA-9 PA-8 PB-3 PB-2 PA-3 PA-2 PB-1 PB-0 PA-1 PA-0 PB-7 PB-6 PB-5 PB-4 PB-11 PB-10 PB-9 PB-8 WRD 1 WRD 2 WRD 3

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 42 Figure 29. RAW 8-Bit Output SYNCHRONIZATION SHORT PACKET DATA TYPES GENERIC SHORT PACKET DATA TYPES GENERIC LONG PACKET DATA TYPES (TYPE 0X12 USED FOR EMBEDDED AUDIO YUV DATA USER DEFINED BYTE BASED DATA RESERVED RGB DATA RAW DATA WRD 1 WRD 2 WRD 3 WRD 4 WRD WC- 2 WRD WC -1 WRD WCWRD WC - 4WRD WC - 5 WRD WC - 3 P-7 P-6 P-5 P-4 P-3 P-2 P-1 P-0 HS VS DE CONTROLS FS & FE AND PACKET START/END DOUT 18/HS DOUT 19/VS DOUT 20/DE DOUT DOUT DOUT RES RES NO INPUT WHEN BWS = LOW RESRES

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 43 Figure 30. RAW 10-Bit Output SYNCHRONIZATION SHORT PACKET DATA TYPES GENERIC SHORT PACKET DATA TYPES GENERIC LONG PACKET DATA TYPES (TYPE 0X12 USED FOR EMBEDDED AUDIO YUV DATA USER DEFINED BYTE BASED DATA RESERVED RGB DATA RAW DATA 1 1.25 10 LINE START LINE STOP N* 1.25N WRD 1 WRD 2 WRD 3 WRD 4 WRD WC- 2 WRD WC -1 WRD WCWRD WC - 3WRD 5 LSB LSB WRD WC - 4 P-8 P-9 P-2 P-3 P-4 P-5 P-6 P-7 *PIXEL COUNT NEEDS TO BE A MULTIPLE OF 4

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 44 Figure 31. RAW 12-Bit Output SYNCHRONIZATION SHORT PACKET DATA TYPES GENERIC SHORT PACKET DATA TYPES GENERIC LONG PACKET DATA TYPES (TYPE 0x12 USED FOR EMBEDDED AUDIO YUV DATA USER DEFINED BYTE BASED DATA RESERVED RGB DATA RAW DATA 1 1.5 12 LINE START LINE STOP N* 1.5N WRD WC- 2 WRD WC -1 WCWC - 3 P-7 P-6 P-5 P-4 P-11 P-10 P-9 P-8 HS VS DE DOUT 18/HS DOUT 19/VS DOUT 20/DE CONTROLS FS & FE AND PACKET START/END DOUT P-11 WRD 5 LSB WRD WC- 4 *PIXEL COUNT NEEDS TO BE A MULTIPLE OF 2 DOUT P-3 P-4 DOUT DOUT DOUT P-0 P-1 P-2 DOUT HS VS DE DOUT 18/HS DOUT 19/VS DOUT 20/DE DOUT P-11 DOUT P-3 P-4 DOUT LSB LSB LSB WRD 6 WRD WC - 4 DOUT DOUT RES RES NO INPUT WHEN BWS = LOW DOUT DOUT RES RES DOUT DOUT RES RES DOUT DOUT RES RES P-7 P-6 P-5 P-4 P-11 P-10 P-9 P-8 P2-3 P2-2 P1-3 P1-2 P2-1 P2-0 P1-1 P1-0 WRD 1 WRD 2 WRD 3 WRD 4

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 45 Figure 32. RAW 14-Bit Output SYNCHRONIZATION SHORT PACKET DATA TYPES GENERIC SHORT PACKET DATA TYPES GENERIC LONG PACKET DATA TYPES (TYPE 0x12 USED FOR EMBEDDED AUDIO YUV DATA USER DEFINED BYTE BASED DATA RESERVED RGB DATA RAW DATA 1 1.75 14 LINE START LINE STOP N* 1.75N WRD 1 WRD 2 WRD 3 WRD 4 WRD 5 WORD (WC – 6) TO (WC – 3) P-13 P-6 P-7 *PIXEL COUNT NEEDS TO BE A MULTIPLE OF 4 MSBLSB P4[5:0]P1[5:0] P3[5:0]P2[5:0] P(N-3) TO P(N) LSBP(N-3) TO P(N) MSB WORD (WC – 2) TO WC WRD 6 WRD 7 DOUT6 P-6 DOUT6 P-6 DOUT6 DOUT6 P-6 P-6 DOUT13 P-13 DOUT13 P-13 DOUT13 DOUT13 P-13 P-13 RES RES RES

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 46 Figure 33. User-Defined 24-Bit Output SYNCHRONIZATION SHORT PACKET DATA TYPES GENERIC SHORT PACKET DATA TYPES GENERIC LONG PACKET DATA TYPES (TYPE 0X12 USED FOR EMBEDDED AUDIO YUV DATA USER DEFINED 24-BIT = 0x30 RESERVED RGB DATA RAW DATA WRD 1 WRD 2 WRD 3 WRD 4 WRD WC- 2 WRD WC-1 WRD WCWRD WC-4WRD 5 WRD 6 WRD WC-5 WRD WC-3 UB-0 UB-1 UB-2 UB-3 UB-4 UB-5 UB-6 UB-7 UA-0 UA-1 UA-2 UA-3 UA-4 UA-5 UA-6 UA-7 UC-0 UC-1 UC-2 UC-3 UC-4 UC-5 UC-6 UC-7

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 47 Figure 34. User-Defined 24-Bit Output SYNCHRONIZATION SHORT PACKET DATA TYPES GENERIC SHORT PACKET DATA TYPES GENERIC LONG PACKET DATA TYPES (TYPE 0x12 USED FOR EMBEDDED AUDIO YUV DATA USER DEFINED BYTE BASED DATA (USER DEFINED 8-BIT = 0x31) RESERVED RGB DATA RAW DATA WRD 1 WRD 2 WRD 3 WRD 4 WRD WC- 2 WRD WC -1 WRD WCWRD WC - 4WRD WC - 5 WRD WC - 3 U-7 U-6 U-5 U-4 U-3 U-2 U-1 U-0 HS VS DE CONTROLS FS & FE AND PACKET START/END DOUT 18/HS DOUT 19/VS DOUT 20/DE DOUT DOUT DOUT RES RES NO INPUT WHEN BWS = LOW RESRES

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 48 Auto Pixel-Per-Line Feature For proper operation, the device requires the information of number of pixels in DE high period. Program the pixel count into registers 0x61 and 0x62. Alternatively, the device can automatically count the number of pixels in DE high period. Setting the AUTOPPL bit high enables this function. In this mode, the device counts the number of pixels in every DE high period and compares the result with the number of pixels in the previous DE high period. If both numbers are within ±4 pixels of each other, the deserializer accepts this count as valid count and uses the number to pack - etize the video data. An AUTOPPL error is issued only when the current pixel count does not match the previous pixel count. An invalid count (±5 or more pixels) stops the packet transmission and issues an AUTOPPL error. This allows the device to tolerate some noise while alerting the user of an error. Table 2 Video Output Map (RGB and YUV) 1. Refer to the GMSL serializer data sheet for details. 2. YUV defaults to muxed input mode (Cb, Y0, Cr, Y1). Set INPUTBW = 1 to use normal input mode (CBY0, CrY1). 3. Data type available when BWS = high or open, only. *VESA/oLDI bits are mapped to MIPI according to OLDI bit (D4 or register 0x60). Set oLDI bit low when using VESA input or high when using an oLDI input. oLDI defines bits [5:0] as MSB and bits [6:7] as LSB. **12-bit YUV422 sent using CSI-2 user-defined data type (0x30). The output byte sequence is CB[11:4], Y0[11:4], [CB[3:0], Y0[3:0]], GMSL INPUT BITS1 RGB YUV4222 666 565 8883* 8-BIT MUXED 10-BIT MUXED 8-BIT 10-BIT3 12-BIT3** DIN0 R0 R0 R0 Y/Cb/Cr0 Y/Cb/Cr0 Cb/Cr0 Cb/Cr0 Cb/Cr0 DIN1 R1 R1 R1 Y/Cb/Cr1 Y/Cb/Cr1 Cb/Cr1 Cb/Cr1 Cb/Cr1 DIN2 R2 R2 R2 Y/Cb/Cr2 Y/Cb/Cr2 Cb/Cr2 Cb/Cr2 Cb/Cr2 DIN3 R3 R3 R3 Y/Cb/Cr3 Y/Cb/Cr3 Cb/Cr3 Cb/Cr3 Cb/Cr3 DIN4 R4 R4 R4 Y/Cb/Cr4 Y/Cb/Cr4 Cb/Cr4 Cb/Cr4 Cb/Cr4 DIN5 R5 G0 R5 Y/Cb/Cr5 Y/Cb/Cr5 Cb/Cr5 Cb/Cr5 Cb/Cr5 DIN6 G0 G1 G0 Y/Cb/Cr6 Y/Cb/Cr6 Cb/Cr6 Cb/Cr6 Cb/Cr6 DIN7 G1 G2 G1 Y/Cb/Cr7 Y/Cb/Cr7 Cb/Cr7 Cb/Cr7 Cb/Cr7 DIN8 G2 G3 G2 — Y/Cb/Cr8 Y0 Cb/Cr8 Cb/Cr8 DIN9 G3 G4 G3 — Y/Cb/Cr9 Y1 Cb/Cr9 Cb/Cr9 DIN10 G4 G5 G4 — — Y2 Y0 Cb/Cr10 DIN11 G5 B0 G5 — — Y3 Y1 Cb/Cr11 DIN12 B0 B1 B0 — — Y4 Y2 Y0 DIN13 B1 B2 B1 — — Y5 Y3 Y1 DIN14 B2 B3 B2 — — Y6 Y4 Y2 DIN15 B3 B4 B3 — — Y7 Y5 Y3 DIN16 B4 — B4 — — — Y6 Y4 DIN17 B5 — B5 — — — Y7 Y5 DIN18 HS HS HS HS HS HS HS HS DIN19 VS VS VS VS VS VS VS VS DIN20 DE DE DE DE DE DE DE DE

clock transmitter pulls the line to stop state (LP-11). serial input, the MIPI CSI-2 output, and the data bit width. Table 3. Video Output Map (RAW and User Defined)

Refer to the GMSL serializer data sheet for details.
RAW datatype defaults to single load. Set INPUTBW = 1 to use double input mode (output sequence PA0, PB0, PA1, PB1).
Data type available when BWS = high or open, only.

to set the GMSL pixel clock frequency range ( Table 5). pixel clock frequency range of 12.5MHz to 104MHz. DETREN = 0 on the deserializer when DE is not periodic. format is shown in Figure 35. and SCK edges is programmable. examples of acceptable input formats. Figure 35. Audio Channel Input Format

16 TO 256 BITS

Table 5. GMSL Data-Rate Selection Table Table 4. Control Output Map Note: See the High-Bandwidth Mode section for details on timing requirements. *Outputs used only when the respective color lookup tables are enabled. **Not encrypted when HDCP is enabled (MAX9290 only). Table 6. Input Pixel Clock Range (MHz)

Table 6. Input Pixel Clock Range (MHz) (continued)

12 RAW12

14 RAW14

18 RGB666

1 Do not

2 Do not

3 Do not

4 Do not

Table 7. Output CSI-2 Data Rate Range (Mbps)

Table 7. Output CSI-2 Data Rate Range (Mbps) (continued)

Table 8. Maximum Audio WS Frequency (kHz) for Various Pixel Clock Frequencies +Max WS rate is greater than 192kHz. *DRS = 0 pixel clock frequency is equal to 2x the DRS = 1 pixel clock frequency.

Figure 36. 8-Channel TDM (24-Bit Samples, Padded with Zeros) Figure 37. 6-Channel TDM (24-Bit Samples, No Padding) Figure 38. Stereo I2S (24-Bit Samples, Padded with Zeros)

32 SCK

256 SCK

24 SCK

144 SCK

The output format is shown in Figure 40. rising edge. WS and SCK polarity is programmable. MCLK and set CNTL2 or CNTL0 as a control output. (0x15 D1) to output WS from MCLK. during FIFO underflow when no audio data is available. output all zeroes during underflow. stopping the forward serial link. Figure 39. Stereo I2S (16-Bit Samples, No Padding)

16 SCK

START condition to a STOP condition. section for more information. Table 9. fSRC Settings Figure 40. Audio Channel Output Format

8 TO 32 BITS 256 BITS

in base mode between the µC and the serializer/deserializer. SYNC byte to synchronize with the host UART’s data rate. starting to send a new packet. Figure 41. GMSL UART Protocol for Base Mode Figure 42. GMSL UART Data Format for Base Mode Figure 43. SYNC Byte (0x79) Figure 44. ACK Byte (0xC3)

1 UART FRAME

bit rate is the same as the UART bit rate. the first byte in the data stream is the register address. GPO/GPI Control section for GPI functionality limitations. longer than 100µs if GPI control is used. Figure 45. Format Conversion Between GMSL UART and I 2C with Register Address (I2CMETHOD = 0)

bidirectional communication between master and slave(s). lines operate as both an input and an open-drain output. more data bytes, and finally a STOP condition. Figure 46. Format Conversion Between GMSL UART and I 2C without Register Address (I2CMETHOD = 1)

NACK, the device stops sending valid data. must be set according to the local-side I 2C bit rate. Supported remote-side bit rates can be found in Table 10. by setting the I2CSLVSH register settings on both sides. Figure 53. Format for I2C Read Table 10. I2C Bit-Rate Ranges

translated broadcast address. stores the GPI input state. GPO is low after power-up. rupt an I2C/UART command in progress. further compensate cable attenuation at high frequencies. create the most reliable link for a given cable. against bit errors in HS/VS/DE link bits. factory for devices compatible with 75Ω cables). Table 11. Cable Equalizer Boost Levels

CX/TP determine the power-up state of the serial input. active, along with the default device address ( Table 12). the address location stored in the LUTADDR register. bytes field in I2C-to-I2C modes. field in UART packet, when reading a 256-byte data block.

If LUT translation is enabled, each 8-bit pretranslation

to look up the corresponding (translated) 8-bit color value. Table 13. Pixel Data Format Table 12. Configuration Input Map High Coax+ input. 7-bit device address is XXXXXX0 (bin). Mid Coax- input. 7-bit device address is XXXXXX1 (bin).

(write 0x08 to register 0x7C). 2) Write contents of red LUT with a single write packet. of bytes used in the previous step. 0 (write 0x00 to register 0x7C). Figure 56. LUT Dataflow

control-channel communication. 00 when the serial bit rate is larger than 2GBps. By default, high-immunity mode uses a 500kbps bit rate. fast high-immunity mode (Table 15). command from a remote µC using the control channel. matically sets its SLEEP register bit to 0. I2CSEL, DRS, EQS, HIM/CNTL1, and BWS are latched. Table 14. Reverse Control-Channel Modes Table 15. Fast High-Immunity Mode Requirements Fast high-immunity mode requires DRS = 0.

1 Fast high-immunity mode 1000

called configuration link in the absence of a clock input. and attempts to lock when SEREN = 1. channel becomes unavailable for 2ms after power-up. Table 16. Startup Procedure for Image-Sensing Applications (CDS = High, Figure 58)

2 Writes deserializer configuration bits

Writes serializer configuration bits. a dummy acknowledge) if not locked. Configuration changed from default settings. serial link to be established (~3ms).

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 73 High-Bandwidth Digital Content Protection (HDCP) Note: The explanation of HDCP operation in this data sheet is provided as a guide for general understanding. Implementation of HDCP in a product must meet the requirements given in the HDCP System v1.3 Amendment for GMSL, which is available from DCP. HDCP has two main phases of operation, authentication and the link integrity check. The µC starts authentica - tion by writing to the START_AUTHENTICATION bit in the GMSL serializer. The GMSL serializer generates a 64-bit random number. The host µC first reads the 64-bit random number from the GMSL serializer and writes it to the deserializer. The µC then reads the GMSL serial - izer public key selection vector (AKSV) and writes it to the deserializer. The µC then reads the deserializer KSV (BKSV) and writes it to the GMSL serializer. The µC begins checking BKSV against the revocation list. Using the cipher, the GMSL serializer and deserializer calculate a 16-bit response value, R0 and R0’, respectively. The GMSL amendment for HDCP reduces the 100ms mini - mum wait time allowed for the receiver to generate R0’ (specified in HDCP rev 1.3) to 128 pixel clock cycles in the GMSL amendment. There are two response-value comparison modes, internal comparison and µC comparison. Set EN_INT_COMP = 1 to select internal comparison mode. Set EN_INT_COMP = 0 to select µC comparison mode. In internal compari - son mode, the µC reads the deserializer response R0’ and writes it to the GMSL serializer. The GMSL serializer compares R0’ to its internally generated response value R0, and sets R0_RI_MATCHED. In µC comparison mode, the µC reads and compares the R0/R0’ values from the GMSL serializer/deserializer. During response-value generation and comparison, the host µC checks for a valid BKSV (having 20 1s and 20 0s is also reported in BKSV_INVALID) and checks BKSV against the revocation list. If BKSV is not on the list and the response values match, the host authenticates the link. If the response values do not match, the µC resam - ples the response values (as described in HDCP rev 1.3, Appendix C). If resampling fails, the µC restarts authen - tication by setting the RESET_HDCP bit in the GMSL serializer. If BKSV appears on the revocation list, the host cannot transmit data that requires protection. The host knows when the link is authenticated and decides when to output data requiring protection. The µC performs a link integrity check every 128 frames or every 2s ±0.5s. The GMSL serializer/deserializer generate response values every 128 frames. These values are compared internally (internal comparison mode) or can be compared in the host µC. In addition, the GMSL serializer/deserializer provide response values for the enhanced link verification. Enhanced link verification is an optional method of link verification for faster detection of loss-of-synchronization. For this option, the GMSL serializer and deserializer generate 8-bit enhanced link-verification response values (PJ and PJ’) every 16 frames. The host must detect three consecutive PJ/PJ’ mismatches before resampling. Encryption Enable The GMSL link transfers either encrypted or nonen - crypted data. To encrypt data, the host µC sets the encryption enable (ENCRYPTION_ENABLE) bit in both the GMSL serializer and deserializer. The µC must set ENCRYPTION_ENABLE in the same VSYNC cycle in both the GMSL serializer and deserializer (no internal VSYNC falling edges between the two writes). The same timing applies when clearing ENCRYPTION_ENABLE to disable encryption. Note: ENCRYPTION_ENABLE enables/disables encryp - tion on the GMSL irrespective of the content. To comply with HDCP, the µC must not allow content requiring encryption to cross the GMSL unencrypted. The µC must complete the authentication process before enabling encryption. In addition, encryption must be dis - abled before starting a new authentication session. Synchronization of Encryption The video vertical sync (VSYNC) synchronizes the start of encryption. Once encryption has started, the GMSL generates a new encryption key for each frame and each line, with the internal falling edge of VSYNC and HSYNC. Rekeying is transparent to data and does not disrupt the encryption of video or audio data. Repeater Support The GMSL serializer/deserializer include features to build an HDCP repeater. An HDCP repeater receives and decrypts HDCP content and then encrypts and transmits on one or more downstream links. A repeater can also use decrypted HDCP content (e.g., to display on a screen). To support HDCP repeater-authentication protocol, the deserializer has a REPEATER register bit. This register bit must be set to 1 by a µC (most likely on the repeater module). Both the GMSL serializer and deserializer use SHA-1 hash-value calculation over the assembled KSV lists. HDCP GMSL links support a maximum of 15 receiv- ers (total number including the ones in repeater modules).

when it assembles the KSV list. (refer to the HDCP 1.3 Amendment for GMSL for details). a new authentication attempt. ment for HDCP to be in full compliance. Table 17. Startup, HDCP Authentication, and Normal Operation (Deserializer is Not a outputs low-value content A/V data.

4 Reads the locked bit of the deserializer and

5 Optionally writes a random-number seed to

7 Reads AN and AKSV from the GMSL serializer

8 Reads the BKSV and REPEATER bit from the

deserializer and writes to the GMSL serializer.

VSYNC_DET bit in the GMSL serializer). Revocation list and continues if it is not. Authentication can be restarted if it fails.

13 Starts transmission of A/V content that needs

high-value content A/V data.

Table 18. Link Integrity Check (Normal)—Performed Every 128 Frames After Encryption register every 128 VSYNC cycles.

3 Every 128 video frames (VSYNC cycles) or

RI is not stable, go back to step 5.

7 If RI matches RI’, the link integrity check is

inputs (such as blue or informative screen).

9 Writes 0 to the ENCRYPTION_ENABLE bit of

the GMSL serializer and deserializer.

Table 19. Optional Enhanced Link Integrity Check—Performed Every 16 Frames After register every 16 VSYNC cycles.

3 Every 16 video frames, reads PJ from the

4 If PJ matches PJ’, the enhanced link integrity

A/V data input of the GMSL serializer.

6 Writes 0 to the ENCRYPTION_ENABLE bit of

the GMSL serializer and deserializer.

µCs. Table 20 summarizes the authentication operation. receiver and invoke an interrupt to notify upstream µCs. Figure 57. State Diagram (CDS = High) Figure 58. Example Network with One Repeater and Two µCs (Tx = GMSL Serializer’s, Rx = Deserializer’s)

0 SLEEP

Table 20. HDCP Authentication and Normal Operation (One Repeater, Two µCs)—First blue or informative screen). mask A/V data input of TX_B1.

6 Optionally, writes a random

(see steps 6–10 in Table 17). protection is not transmitted.

received and bit is read as 1. the BINFO register of RX_R1. is 1, then authentication fails.

4) HDCP repeater’s µC resets the AUTH_STARTED bit. is enabled/disabled by an upstream µC. (0x04, D5) in the serializer and then in the deserializer. deserializer and then in the serializer. the deserializers lose lock and stop the error counter. and DECERR are reset to 0x00.

18 Starts transmission of A/V

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 83 Auto Error Reset The default method to reset errors is to read the respec - tive error registers in the deserializers (0x0D and 0x0E). Auto error reset clears the error counters DECERR and the ERR output ~1µs after ERR goes low. Auto error reset is disabled on power-up. Enable auto error reset through AUTORST (0x06, D5). Auto error reset does not run when the device is in PRBS test mode. Dual µC Control Usually systems have one microcontroller to run the control channel, located on the serializer side for display applications or on the deserializer side for image-sensing applications. However, a µC can reside on each side simultaneously and trade off running the control channel. In this case, each µC can communicate with the serializer and deserializer and any peripheral devices. Contention occurs if both µCs attempt to use the control channel at the same time. It is up to the user to prevent this contention by implementing a higher level protocol. In addition, the control channel does not provide arbitration between I 2C masters on both sides of the link. An acknowledge frame is not generated when communication fails due to contention. If communication across the serial link is not required, the µCs can disable the forward and reverse control channel using the FWDCCEN and REVCCEN bits (0x04, D[1:0]) in the serializer/deserializer. Communication across the serial link is stopped and contention between µCs cannot occur. As an example of dual µC use in an image-sensing appli- cation, the serializer can be in sleep mode and waiting for wake-up by µC on the deserializer side. After wake- up, the serializer-side µC assumes master control of the serializer’s registers. Changing the Clock Frequency It is recommended that the serial link be enabled after the video clock (f pixel) and the control-channel clock (f UART/ fI2C) are stable. When changing the clock frequency, stop the video clock for 5µs, apply the clock at the new frequency, then restart the serial link or toggle SEREN. On-the-fly changes in clock frequency are possible if the new frequency is immediately stable and without glitches. The reverse control channel remains unavailable for 500µs after serial link start or stop. When using the UART interface, limit on-the-fly changes in f UART to factors of less than 3.5 at a time to ensure that the device recognizes the UART sync pattern. For example, when lowering the UART frequency from 1Mbps to 100kbps, first send data at 333kbps then at 100kbps for reduction ratios of 3 and 3.333, respectively. Spread-Spectrum Clock Tracking Using a spread-spectrum clock source can reduce EMI/ EMC on the serial and MIPI data. The deserializer can track a spread-spectrum signal from the serializer. Use a spread < ±1% for CSI-2 output rates ≤ 400MHz. Use a spread < ±0.5% for CSI-2 output rates > 400MHz. Fast Detection of Loss-of-Synchronization A measure of link quality is the recovery time from loss- of-synchronization. The host can be quickly notified of loss-of-lock by connecting the deserializer’s LOCK out - put to the GPI input. If other sources use the GPI input, such as a touch-screen controller, the µC can implement a routine to distinguish between interrupts from loss- of-sync and normal interrupts. Reverse control-channel communication does not require an active forward link to operate and accurately tracks the LOCK status of the GMSL link. LOCK asserts for video link only and not for the configuration link. Providing a Frame Sync (Camera Applications) The GPI/GPO provide a simple solution for camera applications that require a frame sync signal from the ECU (e.g., surround-view systems). Connect the ECU frame sync signal to the GPI input, and connect GPO output to the camera frame sync input. GPI/GPO has a typical delay of 275µs. Skew between multiple GPI/ GPO channels is typically 115µs. If a lower skew signal is required, connect the camera’s frame sync input to one of the deserializer’s GPIOs and use an I 2C broadcast write command to change the GPIO output state. This has a maximum skew of 1.5µs, independent from the used I 2C bit rate. Software Programming of the Device Addresses The serializers and deserializers have programmable device addresses. This allows multiple GMSL devices, along with I2C peripherals, to coexist on the same control channel. The serializer device address is in register 0x00 of each device, while the deserializer device address is in register 0x01 of each device. To change a device address, first write to the device whose address changes (register 0x00 of the serializer for serializer device address change, or register 0x01 of the deserializer for deserializer device address change). Then write the same address into the corresponding register on the other device (register 0x00 of the deserializer for serializer device address change, or register 0x01 of the serializer for deserializer device address change).

state logic to drive the three-level logic input. CFGBLOCK to make registers 0x00 to 0x1F as read only. are removed or until PWDN is low. key. The NVM is qualified for automotive applications. (0x06, D3 and D1) set the output state of the GPIOs. threshold voltages are referenced to the serializer ground. vary and cross one of the fault-detection thresholds. Table 21. MAX9288/MAX9290 Feature Compatibility HDCP (MAX9290 only) If feature not supported in serializer, must not be turned on in the MAX9290. High-bandwidth mode If feature not supported in serializer, must only use 24-bit and 32-bit modes. I2C-to-I2C If feature not supported in serializer, must use UART-to-I2C or UART-to-UART. 50Ω in series to VDD and set the reverse control channel amplitude to 100mV. High-immunity control channel If feature not supported in serializer, must use the legacy reverse control-channel mode. I2S encoding If feature not supported in serializer, must disable I2S in the MAX9288/MAX9290.

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 85 For the fault-detection circuit, select the resistor’s power rating to handle a short to the battery. In coax mode, leave the unused line-fault inputs unconnected. To detect the short-together case, refer to Application Note 4709: GMSL Line-Fault Detection . Table 23 lists the mapping for line fault types Internal Input Pulldowns The control and configuration inputs (except three-level inputs) include a pulldown resistor to GND. External pulldown resistors are not needed. Choosing I2C/UART Pullup Resistors I2C and UART open-drain lines require a pullup resistor to provide a logic-high level. There are tradeoffs between power dissipation and speed, and a compromise may be required when choosing pullup resistor values. Every device connected to the bus introduces some capacitance even when the device is not in operation. I 2C specifies 300ns rise times (30% to 70%) for fast mode, which is defined for data rates up to 400kbps (see the I 2C specifications in the AC Electrical Characteristics table for details). To meet the fast-mode rise-time requirement, choose the pullup resistors so that rise time t R = 0.85 x R PULLUP x CBUS < 300ns. The waveforms are not recognized if the transition time becomes too slow. The device supports I2C/UART rates up to 1Mbps. AC-Coupling AC-coupling isolates the receiver from DC voltages up to the voltage rating of the capacitor. Capacitors at the serializer output and at the deserializer input are needed for proper link operation and to provide protection if either end of the cable is shorted to a battery. AC-coupling blocks low-frequency ground shifts and low-frequency common-mode noise. Selection of AC-Coupling Capacitors Voltage droop and the digital sum variation (DSV) of transmitted symbols cause signal transitions to start from different voltage levels. Because the transition time is fixed, starting the signal transition from different voltage levels causes timing jitter. The time constant for an AC-coupled link needs to be chosen to reduce droop and jitter to an acceptable level. The RC network for an AC-coupled link consists of the CML/coax receiver termination resistor (RTR), the CML/coax driver termination resistor (R TD), and the series AC-coupling capacitors (C). The RC time constant for four equal-value series capacitors is (C x (RTD + RTR))/4. RTD and RTR are required to match the transmission line impedance (usually 100Ω differential, 50Ω single ended). This leaves the capacitor selection to change the system time constant. Use at 0.22μF (using power over coax or legacy reverse control channel), 47nF (using high-immunity reverse control channel without power over coax), or larger high-frequency surface- mount ceramic capacitors, with sufficient voltage rating to withstand a short to battery, to pass the lower speed reverse control-channel signal. Use capacitors with a case size less than 3.2mm x 1.6mm to have lower parasitic effects to the high-speed signal. Power-Supply Circuits and Bypassing The deserializers use an AVDD18 and DVDD18 of 1.7V to 1.9V and an AVDD3 of 3.0V to 3.6V. All single-ended inputs and outputs except for the serial input derive power from an IOVDD of 1.7V to 3.6V that scale with IOVDD. Proper voltage-supply bypassing is essential for high- frequency circuit stability. Power-Supply Table Power-supply currents shown in the DC Electrical Characteristics table is measured at V IOVDD = 3.6V. If using a different IOVDD voltage, the IOVDD worst-case supply current will vary. HDCP operation (MAX9290 only) draws additional current. This is shown in Table 24. Cables and Connectors Interconnect for CML typically has a differential impedance of 100Ω. Use cables and connectors that have matched differential impedance to minimize imped - ance discontinuities. Coax cables typically have a characteristic impedance of 50Ω, contact the factory for 75Ω operation). Table 24 lists the suggested cables and connectors used in the GMSL link. Board Layout Separate LVCMOS logic signals and CML/coax high- speed signals to prevent crosstalk. Use a four-layer PCB with separate layers for power, ground, CML/coax, and LVCMOS logic signals. Layout PCB traces close to each other for a 100Ω differential characteristic impedance for STP. The trace dimensions depend on the type of trace used (microstrip or stripline). Note that two 50Ω PCB traces do not have 100Ω differential impedance when brought close together—the impedance goes down when the traces are brought closer. Use a 50Ω trace for the single-ended output when driving coax. Route the PCB traces for differential CML channel in parallel to maintain the differential characteristic imped - ance. Avoid vias. Keep PCB traces that make up a differential pair equal length to avoid skew within the differential pair.

Table 22. Line-Fault Mapping Table 23. Additional Supply Current from HDCP (MAX9290 Only) Table 24. Suggested Connectors and Cables for GMSL

00 Negative cable wire shorted to supply voltage

01 Negative cable wire shorted to ground

10 Normal operation

11 Negative cable wire disconnected

00 Positive cable wire shorted to supply voltage

01 Positive cable wire shorted to ground

11 Positive cable wire disconnected

Table 25. Register Table

0 Normal operation

01 Registers 0x00 to 0x1F and 0x60 to 0x67 are

0 WS, SCK configured as output (deserializer-

1 WS, SCK configured as input (system-sourced

(Read only)1 LOCK output is high.

0 Normal mode (power-up default value depends

on CDS and MS pin value at power-up).

1 Activate sleep mode (power-up default value

depends on CDS and MS pin value at power-up).

00 Local control channel uses I2C when

0101 Local control channel uses UART when

10, 11 Local control channel disabled.

0 Disable reverse control channel to serializer

1 Enable reverse control channel to serializer

0 Disable forward control channel from serializer

1 Enable forward control channel from serializer

Table 25. Register Table (continued)

0 I2C conversion sends the register address

when converting UART-to-I2C. D4 PDEQ 0 Enable equalizer. 01 Disable equalizer. 0000 2.1dB equalizer-boost gain. 0001 2.8dB equalizer-boost gain. 0010 3.4dB equalizer-boost gain. 0011 4.2dB equalizer-boost gain. 0101 6.2dB equalizer-boost gain. 0110 7dB equalizer-boost gain. 0111 8.2dB equalizer-boost gain. 1000 9.4dB equalizer-boost gain. 1010 11.7dB equalizer-boost gain. 1011 13dB equalizer-boost gain.

0 Device uses standard PRBS test.

0 Do not automatically reset error registers and

1 Automatically reset DECERR register 1µs after

0 Enable GPI-to-GPO signal transmission to

1 Disable GPI-to-GPO signal transmission to

(Read only)1 GPI input is high. (Read only)1 GPIO1 input is high. (Read only)1 GPIO0 input is high.

00 D18/D19 assigned to HS/VS .

01 D14/D15 assigned to HS/VS (for use with the

0 Automatic pixel count disabled. 1 Automatic pixel count enabled.

0 High-immunity reverse channel mode uses

1 High-immunity reverse channel mode uses

0 MCLK derived from PCLKOUT. See Table 9. 1 MCLK derived from internal oscillator. override the DRS bit setting). override the DRS bit setting). 0 Normal parallel output driver current. 1 Boosted parallel output driver current.

0 INTOUT pin output controlled by INTOUT bit

0 Disable HS/VS tracking (power-up default value

depends on state of BWS input value at power-up).

1 Enable HS/VS tracking (power-up default value

depends on state of BWS input value at power-up).

0 Disable DE tracking (power-up default value

depends on state of BWS input value at power-up).

1 Enable DE tracking (power-up default value

depends on state of BWS input value at power-up). 0 Partial periodic HS/VS and DE tracking. 1 Partial and full periodic HS/VS and DE tracking. 0 MCLK output operates normally. 1 WS is output from MCLK (MCLK mirrors WS). 0 MCLK output on DOUT28/CNTL2. 1 MCLK output on ADD0/CNTL0.

0 Acknowledge not generated when forward

1 I2C to I2C-slave generates local acknowledge

when forward channel is not available. 00 352ns/117ns I2C setup/hold time. 01 469ns/234ns I2C setup/hold time. 10 938ns/352ns I2C setup/hold time. 11 1046ns/469ns I2C setup/hold time. 011 105kbps (typ) I2C to I2C-master bit-rate setting. 100 173kbps (typ) I2C to I2C-master bit-rate setting. 101 339kbps (typ) I2C to I2C-master bit-rate setting. 110 533kbps (typ) I2C to I2C-master bit-rate setting. 111 837kbps (typ) I2C to I2C-master bit-rate setting. 00 64µs (typ) I2C to I2C-slave remote timeout. 01 256µs (typ) I2C to I2C-slave remote timeout. 10 1024µs (typ) I2C to I2C-slave remote timeout. 11 No I2C to I2C-slave remote timeout.

0 Audio FIFO repeats last audio word when FIFO

1 Audio FIFO outputs all zeroes when FIFO is

D1 INVSCK 0 Do not invert SCK at output. 01 Invert SCK at output. D0 INVWS 0 Do not invert WS at output. 01 Invert WS at output.

D4 CAPS 0 Not HDCP capable (MAX9288). (Read only)1 HDCP capable (MAX9290). 00 CSI-2 outputs with ID as virtual channel 0. 0001 CSI-2 outputs with ID as virtual channel 1. 10 CSI-2 outputs with ID as virtual channel 2. 11 CSI-2 outputs with ID as virtual channel 3.

0 RGB888 uses VESA format

1 RGB888 uses oLDI format

0000 CSI-2 output uses RGB888 (Power-on

0001 CSI-2 output uses RGB565. 0010 CSI-2 output uses RGB666. 0011 CSI-2 output uses YUV 422 8-bit. 0100 CSI-2 output uses YUV 422 10-bit. 0101 CSI-2 output uses RAW8. 0110 CSI-2 output uses RAW10. 0111 CSI-2 output uses RAW12. 1000 CSI-2 output uses RAW14. 1001 CSI-2 output uses user defined generic 24-bit (0x30). 1010 CSI-2 output uses user defined YUV422 12-bit (0x30). 1011 CSI-2 output uses user defined generic 8-bit (0x31).

00 Drive clock lane LP00 for 64ns before starting

01 Drive clock lane LP00 for 72ns before starting

10 Drive clock lane LP00 for 80ns before starting

11 Drive clock lane LP00 for 88ns before starting

00 Drive HS0 state for 360ns + 16-24UI before

01 Drive HS0 state for 720ns + 16-24UI before

00 Drive data lane LP00 for 64ns +4UI before

0001 Drive data lane LP00 for 72ns + 4UI before

00 Drive HS0 state for 160ns + 24 - 32UI before

transmitting the sync sequence.

01 Drive HS0 state for 176ns + 24 - 32UI before

transmitting the sync sequence.

10 Drive HS0 state for 200ns + 24 - 32UI before

transmitting the sync sequence.

11 Drive HS0 state for 240ns + 24 - 32UI before

transmitting the sync sequence.

00 Drive HSTRAIL state for 64ns + 8UI after the

last payload data bit of a HS transmission burst.

01 Drive HSTRAIL state for 80ns + 8UI after the

last payload data bit of a HS transmission burst.

10 Drive HSTRAIL state for 96ns + 8UI after the

last payload data bit of a HS transmission burst.

11 Drive HSTRAIL state for 120ns + 8UI after the

last payload data bit of a HS transmission burst. 01 128ns LPTX period length. 10 192ns LPTX period length. 1 HS input is the DE source. 01 Data lanes D0, D1 enabled. 10 Data lanes D0–D2 enabled. 11 Data lanes D0–D3 enabled.

00 Data-byte 3 maps to lane 0 (data mapping

1101 Data-byte 3 maps to lane 1. 10 Data-byte 3 maps to lane 2. 11 Data-byte 3 maps to lane 3.

00 Data byte 2 maps to lane 0 (data mapping

1001 Data byte 2 maps to lane 1. 10 Data byte 2 maps to lane 2. 11 Data byte 2 maps to lane 3.

00 Data byte 1 maps to lane 0 (data mapping

0101 Data byte 1 maps to lane 1.

10 Data byte 1 maps to lane 2

11 Data byte 1 maps to lane 3.

00 Data byte 0 maps to lane 0 (data mapping

0001 Data byte 0 maps to lane 1. 10 Data byte 0 maps to lane 2. 11 Data byte 0 maps to lane 3. 00 Negative cable wire shorted to supply voltage. 01 Negative cable wire shorted to ground. 11 Negative cable wire disconnected. 00 Positive cable wire shorted to supply voltage. 01 Positive cable wire shorted to ground. 11 Positive cable wire disconnected.

(Read only)1 Pixels-per-line error detected. Read to clear.

0 MAX9271/MAX9273-compatible PRBS test not

1 MAX9271/MAX9273-compatible PRBS test

(Read only)1 DE tracking locked. (Read only)1 VS tracking locked. (Read only)1 HS tracking locked. 0 Disable LUT write and read. 1 Enable LUT write and read.

Table 26. HDCP Register Table (MAX9290 Only)

1 = Set to one if device is a repeater. 0 = Set to zero if device is not a repeater.

MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 102 Note: All devices operate over the -40°C to +105°C temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. /V Denotes an automotive-qualified part. SW = Side-wettable package. *EP = Exposed pad. **Future product―contact factory for availability. †HDCP parts require registration with Digital Content Protection, LLC. PART PIN-PACKAGE HDCP MAX9288GTM+ 48 TQFN-EP* No MAX9288GTM/V+ 48 TQFN-EP* No MAX9288GTM/VY+ 48 SWTQFN-EP* No MAX9290GTM+ 48 TQFN-EP* Yes† MAX9290GTM/V+ 48 TQFN-EP* Yes† MAX9290GTM/VY+** 48 SWTQFN-EP* Yes† PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.

48 TQFN-EP T4877+4 21-0144 90-0130

48 SWTQFN-EP T4877Y+4 21-100045 90-0130

NOTE: NOT ALL PULLUP/PULLDOWN RESISTORS ARE SHOWN. SEE PIN DESCRIPTION FOR DETAILS. CAMERA APPLICATION SENSOR DIN0–DIN26 PCLKIN RX/SDA TX/SCL GPO OUT+ OUT- 49.9Ω 1.8V CONF0– CONF3 RGB888 FSYNC I2C SENSOR COPROCESSOR I2C MAX9275 MAX9279 49.9kΩ 1.8V IN+ IN- LMN0 DCLK+/- DOUT0– DOUT3+/- RX/SDA TX/SCL GPI I2CSEL CX/TP CDS 45.3kΩ 4.99kΩ 49.9kΩ MAX9288 MAX9290 FSYNC I2C 0.22µF 0.22µF 0.22µF Typical Application Circuit

Ordering Information

Package Information

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Chip Information PROCESS: CMOS

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output © 2019 Maxim Integrated Products, Inc. │ 103 REVISION NUMBER REVISION DATE DESCRIPTION PAGES CHANGED 0 3/14 Initial release — 1 9/14 Added simplified diagram, removed Table 1 and renumbered the subsequent tables, clarified functions, removed future product designations, and corrected typos 1, 28, 33, 48, 49, 51–56, 59, 66, 67, 69–72, 74–77, 79–82, 84, 85, 86, 88–102 2 11/15 Clarified timing requirements 8, 27, 30, 50 3 3/17 Various updates, beginning with AC Electrical Characteristics 12, 18, 21, 26, 58, 61, 62, 67, 71, 80, 84, 86, 90, 99 4 3/18 Deleted QFND package and added side-wettable TQFN (SWTQFN) to General Description, Absolute Maximum Ratings, Package Thermal Characteristics, Pin Configuration, Ordering Information, and Package Information 1, 8, 18, 102 5 8/19 Updated High-Immunity Reverse Control-Channel Mode, Selection of AC-Coupling Capacitors, and Typical Application Circuit sections 71, 85, 102

Revision History

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

Product Information

48SWTQFN-EP specifications and overview.

Summary

3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output 2019

Description

3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output 2019

Source title 48SWTQFN-EP Datasheet(PDF) - Maxim Integrated Products

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