480227

480227 TI | Alldatasheet

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Technical content

2007 SLL

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Series Supply V oltage V CC (V) Operating Free-air Temperature Ta (ˆ) SN74AUP1G 0.8 ʙ3.6 –40 ʙ85 SN74AUC1G/2G/3G 0.8 ʙ2.7 –40 ʙ85 SN74LVC1G/2G/3G 1.65 ʙ5.5 –40 ʙ85 SN74AHC1G 2.0 ʙ5.5 –40 ʙ85 SN74AHCT1G 4.5 ʙ5.5 –40 ʙ85 UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See [www.ti.com/sc/logic] for the most current data sheets. Little Logic Series Supply V oltage V CC (V) Operating Free-air Temperature Ta (°C) SN74ABT 4.5 ʙ5.5 –40 ʙ85 SN64BCT 4.5 ʙ5.5 –40 ʙ85 SN74BCT SN74F SN74ALS 4.5ʙ5.5 0 ʙ70 SN74AS SN74LS SN74S 4.75 ʙ5.25 0 ʙ70 SN74xx(TTL) SN74AC SN74AC11xxx 2.0 ʙ5.5 –40 ʙ85 SN74AHC SN74HC 2.0 ʙ6.0 –40 ʙ85 SN74LV 2.0 ʙ5.5 –40 ʙ85 SN74LVC 2.0 ʙ3.6 –40 ʙ85 SN74LVT 2.7 ʙ3.6 –40 ʙ85 SN74ALVC 1.65 ʙ3.6 –40 ʙ85 SN74ALVT 2.3 ʙ3.6 –40 ʙ85 SN74A VC 1.4 ʙ3.6 –40 ʙ85 SN74AUC 0.8 ʙ2.7 –40 ʙ85 GATE/OCTAL/Widebus™/Widebus+

1T45 SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS 23 1T57 SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR WITH NINE CONFIGURABLE GATE LOGIC FUNCTIONS 27 1T58 SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR WITH NINE CONFIGURABLE GATE LOGIC FUNCTIONS 28 1T97 SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR WITH NINE CONFIGURABLE GATE LOGIC FUNCTION 29 1T98 SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR WITH NINE CONFIGURABLE GATE LOGIC FUNCTIONS 30 2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS 31 4T245 4-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS 35 8T245 8-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS 37 16T245 16-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS 41 20T245 20-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS 45 24T245 24-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS 47 32T245 32-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS WITH 3-STATE DESELECTED OUTPUT 50

406 MMC, SD CARD, MEMORY STICK, SMARTMEDIA, AND

XD-PICTURE CARD ±15-KV ESD-PROTECTED VOLTAGE-TRANSLATION TRANCEIVER 53 406L MMC, SD CARD, MEMORY STICK, SMARTMEDIA, AND XD-PICTURE CARD ±15-KV ESD-PROTECTED VOLTAGE-TRANSLATION TRANCEIVER 58

3245 OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT

VOLTAGE AND 3-STATE OUTPUTS 61 4245 OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER WITH 3-STATE OUTPUTS (SN74LVC4245A) 62

4320 LOW-POWER, DUAL-SUPPLY, LEVEL-TRANSLATING

CompactFlashTM INTERFACE WITH 16-BIT DATA, 11-BIT ADDRESS, AND 13-BIT CONTROL LINES 63 164245 16-BIT TRANSCEIVER AND 3.3-V TO 5-V SHIFTER WITH 3-STATE OUTPUTS 67 324245 32-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS 69 1G00 SINGLE 2-INPUT POSITIVE-NAND GATE 91 1G02 SINGLE 2-INPUT POSITIVE-NOR GATE 91 1G04 SINGLE INVERTER GATE 92 1GU04 SINGLE INVERTER 92 1GX04 CRYSTAL OSCILLATOR DRIVER 93 1G06 SINGLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT 94 1G07 SINGLE BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT 94 1G08 SINGLE 2-INPUT POSITIVE-AND GATE 95 1G10 SINGLE 3-INPUT POSITIVE-NAND GATE 95 1G11 SINGLE 3-INPUT POSITIVE-AND GATE 96 1G14 SINGLE SCHMITT-TRIGGER INVERTER GATE 96 TTL CMOS SN74 BiCMOS Page Device Function 1G17 SINGLE SCHMITT-TRIGGER BUFFER 97 1G18 1-OF-2 NONINVERTING DEMULTIPLEXER WITH 3-STATE DESELECTED OUTPUT 97 1G19 1-OF-2 DECODER/DEMULTIPLEXER 98 1G27 3-INPUT POSITIVE-NOR GATE 98 1G29 2-OF-3 DECODER/DEMULTIPLEXER 99 1G32 SINGLE 2-INPUT POSITIVE-OR GATE 100 1G34 SINGLE BUFFER GATE 100 1G38 SINGLE 2-INPUT NAND GATE WITH OPEN-DRAIN OUTPUT 101 1G57 CONFIGURABLE MULTIPLE-FUNCTION GATE 101 1G58 CONFIGURABLE MULTIPLE-FUNCTION GATE 102 1G66 SINGLE BILATERAL ANALOG SWITCH 102 1G74 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET 103 1G79 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP 104 1G80 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP 105 1G86 SINGLE 2-INPUT EXCLUSIVE-OR GATE 106 1G97 CONFIGURABLE MULTIPLE-FUNCTION GATE 106 1G98 CONFIGURABLE MULTIPLE-FUNCTION GATE 107 1G99 SINGLE RETRIGGERABLE MONOSTABLE MULTIVIBRATOR WITH SCHMITT-TRIGGER INPUTS 108 1G123 SINGLE RETRIGGERABLE MONOSTABLE MULTIVIBRATOR WITH SCHMITT-TRIGGER INPUTS 109 1G125 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT 110 1G126 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT 110 1G132 SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS 111 1G139 2-TO-4 LINE DECODER 112 1G175 SINGLE D-TYPE FLIP-FLOP WITH ASYNCHRONOUS CLEAR 113 1G240 SINGLE BUFFER/DRIVER WITH 3-STATE OUTPUT 114 1G332 SINGLE 3-INPUT POSITIVE-OR GATE 114 1G373 SINGLE D-TYPE LATCH WITH 3-STATE OUTPUT 115 1G374 SINGLE D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT 116 1G386 SINGLE 3-INPUT EXCLUSIVE-XOR GATE 117 1G0832 SINGLE 3-INPUT POSITIVE AND-OR GATE 117 1G3157 SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH 118 1G3208 SINGLE 3-INPUT POSITIVE OR-AND GATE 119 2G00 DUAL 2-INPUT POSITIVE-NAND GATE 120 2G02 DUAL 2-INPUT POSITIVE-NOR GATE 120 2G04 DUAL INVERTER GATE 121 2GU04 DUAL INVERTER GATE 121 2G06 DUAL INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS 122 2G07 DUAL BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS 122 2G08 DUAL 2-INPUT POSITIVE-AND GATE 123 2G14 DUAL INVERTER GATE 123 2G17 DUAL SCHMITT-TRIGGER BUFFER 124 2G32 DUAL 2-INPUT POSITIVE-OR GATE 124 2G34 DUAL INVERTER GATE 125 2G38 SINGLE 2-INPUT NAND GATE WITH OPEN-DRAIN OUTPUT 125 2G53 SINGLE-POLE DOUBLE-THROW (SPDT) ANALOG SWITCH OR 2:1 ANALOG MULTIPLEXER/DEMULTIPLEXER 126 2G66 DUAL BILATERAL ANALOG SWITCH 126 2G74 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET 127

2G79 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP 128 2G80 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP 129 2G86 DUAL 2-INPUT EXCLUSIVE-OR GATE 130 2G125 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS 130 2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS 131 2G132 SINGLE 2-INPUT NAND GATE WITH OPEN-DRAIN OUTPUT 131 2G157 SINGLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER 132 2G240 DUAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 133 2G241 DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS 133 3G04 TRIPLE INVERTER GATE 134 3GU04 TRIPLE INVERTER GATE 134 3G06 TRIPLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS 135 3G07 TRIPLE BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS 135 3G14 TRIPLE SCHMITT-TRIGGER INVERTER 136 3G17 TRIPLE SCHMITT-TRIGGER BUFFER 136 3G34 TRIPLE BUFFER GATE 137

00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES 231

01 QUADRUPLE 2-INPUT POSITIVE-NAND GATES WITH

OPEN-COLLECTOR OUTPUTS 232

02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES 233

03 QUADRUPLE 2-INPUT POSITIVE-NAND GATES WITH

OPEN-COLLECTOR OUTPUTS 234

04 HEX INVERTERS 235

05 HEX INVERTERS WITH OPEN-DRAIN OUTPUTS 236

06 HEX INVERTER BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS 237

07 HEX BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS 237

08 QUADRUPLE 2-INPUT POSITIVE-AND GATES 238

09 QUADRUPLE 2-INPUT POSITIVE-AND GATES WITH

OPEN-COLLECTOR OUTPUTS 239

10 TRIPLE 3-INPUT POSITIVE-NAND GATES 240

11 TRIPLE 3-INPUT POSITIVE-AND GATES 241

14 HEX SCHMITT-TRIGGER INVERTERS 242

16 HEX INVERTER BUFFERS/DRIVERS WITH OPEN-COLLECTOR

17 HEX SCHMITT-TRIGGER BUFFER 243

19 HEX SCHMITT-TRIGGER INVERTERS 244

20 DUAL 4-INPUT POSITIVE-NAND GATES 245

21 DUAL 4-INPUT POSITIVE-AND GATES 246

25 DUAL 4-INPUT POSITIVE-NOR GATES WITH STROBE 246

26 QUADRUPLE 2-INPUT HIGH-VOLTAGE INTERFACE

27 TRIPLE 3-INPUT POSITIVE-NOR GATES 247

30 8-INPUT POSITIVE-NAND GATES 248

31 DELAY ELEMENTS 248

32 QUADRUPLE 2-INPUT POSITIVE-OR GATES 249

33 QUADRUPLE 2-INPUT POSITIVE-NOR BUFFERS WITH

OPEN-COLLECTOR OUTPUTS 250

34 HEX BUFFER GATE 250

35 HEX NONINVERTERS WITH OPEN-COLLECTOR OUTPUTS 251

37 QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS 252

38 QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS WITH

OPEN-COLLECTOR OUTPUTS 253 TTL CMOS SN74 BiCMOS Page Device Function 42 4-LINE-TO-10-LINE DECODERS (1 of 10) 254

45 BCD-TO-DECIMAL DECODERS/DRIVERS 256

47 BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS 258

51 AND-OR-INVERT GATES 260

64 4-2-3-2 INPUT AND-OR INVERT GATES 261

73 DUAL J-K FLIP-FLOPS WITH CLEAR 262

74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH

75 4-BIT BISTABLE LATCHES 266 85 4-BIT MAGNITUDE COMPARATORS 267

86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES 268

90 DECADE COUNTER 269

92 DIVIDE-BY-TWELVE DECODE COUNTERS 270

93 4-BIT BINARY COUNTERS 271

97 SYNCHRONOUS 6-BIT BINARY RATE MULTIPLIERS 272

107 DUAL J-K FLIP-FLOPS WITH CLEAR 274

109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH

112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH

121 MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS 280

122 RETRIGGERABLE MONOSTABLE MULTIVIBRATORS 281

123 DUAL RETRIGGERABLE MONOSTABLE MULTIVIBARATORS

WITH SCHMITT-TRIGGER INPUTS 282

124 DUAL VOLTAGE-CONTROLLED OSCILLATORS 283

125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS 284

126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS 285

128 50- Ω LINE DRIVER 286

132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT TRIGGER

133 13-INPUT POSITIVE-NAND GATES 287

136 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES WITH OPEN

137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES 288 138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXRS 290

139 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS 292

140 DUAL 4-INPUT POSITIVE-NAND 50- Ω LINE DRIVERS 294

145 BCD-TO-DECIMAL DECODERS/DRIVERS 295

147 10-LINE TO 4-LINE BCD PRIORITY ENCODER 296 148 8-LINE TO 3-LINE PRIORITY ENCODERS 298 150 16-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER 300 151 8-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS 302

153 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS 304

154 4-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS 306

155 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS 308

156 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS WITH

OPEN-COLLECTOR OUTPUTS 310

157 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS 312

158 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS 314

159 4-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH OPEN-COLLECTOR OUTPUTS 316 161 4-BIT SYNCHRONOUS BINARY COUNTERS 318

163 4-BIT SYNCHRONOUS BINARY COUNTERS 320 164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS 322

165 PARALLEL-LOAD 8-BIT SHIFT REGISTERS 324

166 8-BIT PARALLEL-LOAD SHIFT REGISTERS 326

169 SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS 328

170 4-BY-4-REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS 330 173 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS 332

174 HEX D-TYPE FLIP-FLOPS WITH CLEAR 334

175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR 335

181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS 336

182 LOOK-AHEAD CARRY GENERATOR 338

190 SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY

191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS 342

192 PRESETTABLE SYNCHRONOUS 4-BIT UP/DOWN COUNTERS 344

193 4-BIT SYNCHRONOUS UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR) 346 194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS 348 195 4-BIT PARALLEL-ACCESS SHIFT REGISTERS 350

221 DUAL MONOSTABLE MULTIVIBRATORS WITH

SCHMITT-TRIGGER INPUTS 352 237 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES 354 238 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS 356

240 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 358

241 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 360

243 QUADRUPLE BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 362

244 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 364

245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 366

247 BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS 368

250 1-OF-16 DATA GENERATORS/MULTIPLEXERS WITH 3-STATE OUTPUTS 370

251 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS 372

253 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS

257 QUADRUPLE 2-LINE TO 1-LINE DATA

SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS 376

258 QUADRUPLE 4-LINE TO 1-LINE DATA

SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS 378 259 8-BIT ADDRESSABLE LATCHES 380

260 DUAL 5-INPUT POSITIVE-NOR GATES 382

265 QUADRUPLE COMPLEMENTARY-OUTPUT ELEMENTS 382

266 QUADRUPLE 2-INPUT EXCLUSIVE-NOR GATES WITH

273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR 384

276 QUADRUPLE J-K FLIP-FLORS 386

279 QUADRUPLE S-R LATCHES 387

280 9-BIT PARITY GENERATORS/CHECKERS 388 283 4-BIT BINARY FULL ADDERS WITH FAST CARRY 390 286 9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS WITH BUS DRIVER PARITY I/O PORT 392

292 PROGRAMMABLE FREQUENCY DIVIDERS/DIGITAL TIMERS 394

293 4-BIT BINARY COUNTERS 396 TTL CMOS SN74 BiCMOS Page Device Function

294 PROGRAMMABLE FREQUENCY DIVIDERS/DIGITAL TIMERS 398

297 DIGITAL PHASE-LOCKED-LOOP FILTERS 400

298 QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE 402

299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS 404

321 CRYSTAL-CONTROLLED OSCILLATORS 406

323 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS 408 348 8-LINE TO 3-LINE PRIORITY ENCODERS WITH 3-STATE OUTPUTS 410 354 8-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS/ TRANSPARENT/REGISTERS WITH 3-STATE OUTPUTS 412 356 8-INPUT MULTIPLEXER/REGISTERS 3-STATE 414

365 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS 416

366 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS 417

367 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS 418

368 HEX INVERTING BUFFERS AND LINE DRIVERS WITH 3-STATE

373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS 420

374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE

375 4-BIT BISTABLE LATCHES 424

377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE 425

378 HEX D-TYPE FLIP-FLOPS WITH CLOCK ENABLE 426

390 DUAL 4-BIT DECADE COUNTERS 427

393 DUAL 4-BIT BINARY COUNTERS 428

395 CASCADABLE SHIFT REGISTERS 429

399 QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE 430

423 RETRIGGERABLE MONOSTABLE MULTIVIBRATORS 431

442 QUADRUPLE TRIDIRECTIONAL BUS TRANSCEIVERS 432

465 OCTAL BUFFERS WITH 3-STATE OUTPUTS 433

518 OCTAL BINARY/BCD IDENTITY COMPARATORS WITH ENABLE 433

520 OCTAL BINARY/BCD IDENTITY COMPARATORS WITH ENABLE 434

521 8-BIT IDENTITY COMPARATORS WITH OPEN-COLLECTOR OUTPUTS 435

533 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS 436

534 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE

540 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 438

541 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 439

543 OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS 440

561 SYNCHRONOUS 4-BIT COUNTERS WITH 3-STATE OUTPUTS 442

563 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS 444

564 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE

569 SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS WITH

573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS 448

574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE

575 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE

576 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE

577 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE

580 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE

590 8-BIT BINARY COUNTERS WITH 3-STATE OUTPUT REGISTERS 456 592 8-BIT BINARY COUNTERS WITH INPUT REGISTERS 458 593 8-BIT BINARY COUNTERS WITH INPUT REGISTERS 460 594 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS 462 595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS 464 596 8-BIT SHIFT REGISTERS WITH OUTPUT LATCHES 466

597 SERIAL-OUT SHIFT REGISTERS WITH INPUT LATCHES 468

598 8-BIT SHIFT REGISTERS WITH INPUT LATCHES 470

620 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 472

621 OCTAL BUS TRANSCEIVERS 473

623 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 474

624 VOLTAGE-CONTROLLED OSCILLATORS 475

628 VOLTAGE-CONTROLLED OSCILLATORS 476

629 DUAL VOLTAGE-CONTROLLED OSCILLATORS 477

638 OCTAL BUS TRANSCEIVERS 478

639 OCTAL BUS TRANSCEIVERS 479

640 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 480

641 OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS 481

642 OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS 482

645 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 483

646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE

647 OCTAL BUS TRANSCEIVERS AND REGISTERS 486

648 OCTAL BUS TRANSCEIVERS AND REGISTERS 488

651 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE

652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE

653 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE

654 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE

657 OCTAL BUS TRANSCEIVERS WITH PARITY

GENERATORS/CHECKERS AND 3-STATE OUTPUTS 498 666 8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES WITH 3-STATE OUTPUTS 500 667 8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES WITH 3-STATE OUTPUTS 501

669 SYNCHRONOUS 4-BIT UP/DOWN COUNTERS 502

670 4-BY-4 REGISTER FILES WITH 3-STATE OUTPUTS 504 673 16-BIT SHIFT REGISTERS 506 674 16-BIT SHFIT REGISTERS 508 679 12-BIT ADDRESS COMPARATOR 510 682 8-BIT MAGNITUDE COMPARATORS 512 684 8-BIT MAGNITUDE COMPARATORS 514 686 8-BIT MAGNITUDE/IDENTITY COMPARATORS 516 688 8-BIT IDENTITY COMPARATORS 518

697 SYNCHRONOUS UP/DOWN COUNTERS WITH OUTPUT

REGISTERS AND MULTIPLEXED 3-STATE OUTPUTS 520 TTL CMOS SN74 BiCMOS Page Device Function

699 SYNCHRONOUS UP/DOWN COUNTERS WITH OUTPUT

REGISTERS AND MULTIPLEXED 3-STATE OUTPUTS 522

756 OCTAL BUFFER/DRIVER WITH OPEN-COLLECTOR OUTPUTS 524

757 OCTAL BUFFER/DRIVER WITH OPEN-COLLECTOR OUTPUTS 525

760 OCTAL BUFFERS/DRIVERS WITH OPEN-COLLECTOR OUTPUTS 526

804 HEX 2-INPUT NAND DRIVERS 527

805 HEX 2-INPUT NOR DRIVERS 528

808 HEX 2-INPUT AND DRIVERS 528

821 10-BIT BUS-INTERFACE FLIP FLOPS WITH 3-STATE OUTPUTS 529 823 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS 530 825 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS 531 827 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 532 828 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 532

832 HEX 2-INPUT OR DRIVERS 533

833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS 534 841 10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS 536 843 9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS 537 853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS 538

857 HEX 2-TO-1 UNIVERSAL MULTIPLEXERS WITH 3-STATE OUTPUTS 540

861 10-BIT TRANSCEIVERS WITH 3-STATE OUTPUTS 542 863 9-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 543

867 SYNCHRONOUS 8-BIT UP/DOWN COUNTERS 544

869 SYNCHRONOUS 8-BIT UP/DOWN COUNTERS 546

870 DUAL 16-BY 4-BIT REGISTER FILES 548

873 DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS 550

DUAL 4-BIT D-TYPE EDGE-TRIGGERD FLIP-FLOPS WITH 3-STATE OUTPUTS 551

876 DUAL 4-BIT D-TYPE EDGE-TRIGGERD FLIP-FLOPS WITH 3-STATE

885 8-BIT MAGNITUDE COMPARATORS 554 990 8-BIT D-TYPE TRANSPARENT READ-BACK LATCH 556 992 9-BIT D-TYPE TRANSPARENT READ-BACK LATCH WITH 3-STATE OUTPUTS 557 994 10-BIT D-TYPE TRANSPARENT READ-BACK LATCH 558 996 8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES 559

1000 QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS/DRIVERS 560

1004 HEX INVERTING DRIVERS 560

1005 HEX INVERTING BUFFERS WITH OPEN-COLLECTOR OUTPUTS 561

1008 QUADRUPLE 2-INPUT POSITIVE-AND BUFFER/DRIVER 561

1032 QUADRUPLE 2-INPUT POSITIVE-OR BUFFERS/DRIVERS 562

1034 HEX DRIVERS 562

1035 HEX NONINVERTING BUFFERS WITH OPEN-COLLECTOR

1240 OCTAL BUFFER AND LINE DRIVER WITH 3-STATE OUTPUTS 563

1244 OCTAL BUFFERS AND DRIVERS WITH 3-STATE OUTPUTS 564

1245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 564

1404 OSCILLATOR DRIVER FOR CRYSTAL OSCILLATOR OR CERAMIC

1640 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 566

1645 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 567

2240 OCTAL BUFFERS AND LINE/MOS DRIVERS WITH 3-STATE

2241 OCTAL BUFFERS AND LINE/MOS DRIVERS WITH 3-STATE

2244 OCTAL BUFFERS AND LINE/MOS DRIVERS WITH 3-STATE

2245 OCTAL TRANSCEIVER AND LINE/MOS DRIVERS WITH 3-STATE

2373 25-W OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS 572

2414 MEMORY DECODER WITH ON-CHIP SUPPLY VOLTAGE MONITOR 573

2541 OCTAL LINE DRIVER/MOS DRIVER WITH 3-STATE OUTPUTS 574

2827 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 574 2828 10-BIT BUS/MOS MEMORY DRIVERS WITH 3-STATE INVERTING 575

2952 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE

2953 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE

4002 DUAL 4-INPUT POSITIVE-NOR GATES 579

4015 DUAL 4-STAGE STATIC SHIFT REGISTER 580

4016 QUAD BILATERAL SWITCH 581

4017 DECADE COUNTERS/DIVIDER 582

4020 14-STAGE BINARY COUNTERS 583 4024 7-STAGE BINARY COUNTERS 584 4040 12-STAGE BINARY COUNTERS 585

4046 PHASE-LOCKED-LOOP WITH VCO 586

4049 HEX INVERTING BUFFERS 588

4050 HEX NON-INVERTING BUFFERS 588

4051 8-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS 589

4052 DUAL 4-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS 590

4053 TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS 591

4059 CMOS PROGRAMMABLE DIVIDE-BY-N COUNTER 592

4060 ASYNCHRONOUS 14-STAGE BINARY COUNTERS AND

4066 QUADRUPLE BILATERAL SWITCHES 594

4067 16-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER 595

4075 TRIPLE 3-INPUT OR GATES 596

4094 8-STAGE SHIFT AND STORE BUS REGISTER, THREE-STATE 597

4316 QUAD ANALOG SWITCH WITH LEVEL TRANSLATION 598

4351 ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LATCH 599

4352 ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LATCH 600

4374 OCTAL EDGE-TRIGGERED D-TYPE DUAL-RANK FLIP-FLOP WITH

4511 BCD-TO-7 SEGMENT LATCH/DECODER/DRIVERS 602

4514 4-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES 604 4515 4-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES 605

4518 DUAL SYNCHRONOUS COUNTERS 606

4520 DUAL SYNCHRONOUS COUNTERS 607

4538 DUAL RETRIGGERABLE PRECISION MONO STABLE

4543 BCD-TO-7 SEGMENT LATCH/DECODER/DRIVERS 610

4851 8-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER WITH INJECTION-CURRENT EFFECT CONTROL 612 TTL CMOS SN74 BiCMOS Page Device Function

4852 DUAL 4-TO-1 CHANNEL ANALOG MULTIPLEXER/

DEMULTIPLEXER WITH INJECTION-CURRENT EFFECT CONTROL 612 5400 11-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS 614 5401 11-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS 614 5402 12-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS 615 5403 12-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS 615

7001 QUADRUPLE POSITIVE-AND GATES WITH SCHMITT-TRIGGER

7002 QUADRUPLE POSITIVE-NOR GATES WITH SCHMITT-TRIGGER

7032 QUADRUPLE POSITIVE-OR GATES WITH SCHMITT-TRIGGER

7046 PHASE-LOCKED LOOP WITH VCO AND LOCK DETECTOR 618

7266 QUAD 2-INPUT EXCLUSIVE-NOR GATES 619

8003 DUAL 2-INPUT POSITIVE-NAND GATES 619

16240 16-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 620 16241 16-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 622 16244 16-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 624 16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS 626 16260 12-BIT TO 24-BIT MULTIPLEXES D-TYPE LATCH WITH 3-STATE OUTPUTS 628 16269 12-BIT TO 24-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS 630 16270 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS 632 16271 12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS 634 16282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS 636 16334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS 638 16344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS 640 16373 16-BIT TRANSPARENT LATCHES WITH 3-STATE OUTPUTS 642 16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS 644 16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS 646 16460 4-TO-1 MULTIPLEXED/DEMULTIPLEXED TRANSCEIVERS WITH 3-STATE OUTPUTS 648 16470 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS 650 16500 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS 652 16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS 654 16524 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS 656 16525 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS 658 16540 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 660 16541 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 661 16543 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS 662 16600 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 664 16601 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 666 16620 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 668 16623 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 670 16640 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS 671 16646 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS 672

16651 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS 674 16652 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS 676 16657 16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS 678 16721 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS 680 16722 22-BIT FLIP-FLOP WITH 3-STATE OUTPUTS 681 16820 10-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH DUAL OUTPUTS 682 16821 20-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS 683 16823 18-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH DUAL OUTPUTS 684 16825 18-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 685 16827 20-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 686 16831 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS 688 16832 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS 689

16833 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS 690

16834 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS 692 16835 3.3-V ABT 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS 693 16841 20-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS 694 16843 18-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS 695

16853 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS 696

16861 20-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 698 16863 18-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 699 16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS 700 16903 3.3-V 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS 702 16952 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS 704 16973 8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH WITH FOUR INDEPENDENT BUFFERS 706 25244 25-W OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS 708 25245 25-W OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 709 25642 25-W OCTAL BUS TRANSCEIVER 710 29821 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS 711 29825 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS 712 29827 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 713 29828 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 714 29841 10-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS 715 29843 9-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS 716 29854 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER 718 29863 9-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 720 29864 9-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS 721 32240 32-BIT BUFFER/DRIVER 722 32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS 724 32245 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS 726 32316 16-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS 728 32318 18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS 730 32373 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS 732 TTL CMOS SN74 BiCMOS Page Device Function 32374 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS 734 32501 36-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATEOUTPUTS 736 32543 36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 738 32973 16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH WITH EIGHT INDEPENDENT BUFFERS 740 40103 8-STAGE SYNCHRONOUS DOWN COUNTERS 742 162240 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 744 162241 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 745 162244 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 746 162245 16-BIT TRANSCEIVER WITH 3-STATE OUTPUTS 747 162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS 748 162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS 750 162280 16-BIT TO 32-BIT REGISTERED BUS EXCHANGER WITH BYTE MASKS AND 3-STATE OUTPUTS 752 162282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS 754 162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS 756 162344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS 758 162373 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS 760 162374 3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS 761 162460 4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS 762 162500 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS 764 162501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS 766 162525 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS 768 162541 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 770 162601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS 772 162721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS 774 162820 3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS 775 162823 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS 776 162825 18-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 777 162827 20-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 778 162830 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS 779 162831 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS 780 162832 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS 781 162834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS 782 162835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS 783 162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS 784 162841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS 785 322244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS 786 322374 3.3-V ABT 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS 787

Single-Supply Voltage-Translator Low-Power LV LVC ALVC AVC AUP Dual-Supply Bus Transceiver Low-Power CMOS LV LVC ALVC AVC AUP 1T45 ˔ ˔/H˔ 2T45 ˔ ˔/H˔ 4T245 ˔/H˔ 8T245 ˔ ˔/H˔ 3245 C˔ 4245 ˔/C˔ 16T245 ˔/H˔ ˔ /H˔ 164245 ˔ A˔/AH˔ B˔/BH˔ 20T245 ˔/H˔ 24T245 ˔/H˔ 32T245 ˔/H˔ 324245 B˔ Statusɹɹ˔ɿProduct available in technology indicatedɹɹ*ɿNew product planned in technology indicated APPLICATION SPECIFIC (CompactFlashTM, SD CARD, MultiMediaCards, I2C) Low-Power CMOS LV LVC ALVC AVC AUP 406 A˔ 406L A˔ 4320 ˔A Statusɹɹ˔ɿProduct available in technology indicatedɹɹ*ɿNew product planned in technology indicated MMC, SD CARD, Memory Stick, SmartMedia, AND xD-Picture Card ±15-kV ESD VOLTAGE-TRANSLATION TRANSCEIVER MMC, SD CARD, Memory StickTM VOLTAGE-TRANSLATION TRANSCEIVER LOW-POWER, DUAL-SUPPY, LEVEL-TRANSLATING CompactFlashTM INTERFACE WITH DATA, 11-BIT ADRESS, AND 13BIT CONTROL LINES Description Device Function DeviceDescription 2-input AND gate Device 2-input OR gate with one inverted input 2-input NAND gate with one inverted input 2-input NOR gate with one inverted input Inverter Noninverted buffer Single BusTransceiver Dual BusTransceivers 16-Bit BusTransceivers 32-Bit BusTransceivers Voltage-Translation

Description

˔1G57 1G58 2-input AND gate with both inputs inverted 2-input NOR gate 2-input NOR gate with both inputs inverted 2-input NAND gate with inverted input 2-input OR gate with inverted input 2-input XNOR Inverter Noninverted buffer Inverter Noninverted buffer 2-to-1 data selector 2-input NAND gate 2-input NAND gate with both inputs inverted 2-input OR gate 2-input OR gate with both inputs inverted 2-input AND gate with inverted input 2-input NOR gate with inverted input 2-input XNOR 2-input AND gate 2-input AND gate with one inverted input 2-input OR gate 2-input OR gate with one inverted input 2-input OR gate 2-input NAND gate with one inverted input 2-input NOR gate with one inverted input Inverter Noninverted buffer 1G97 1G98 Configurable Gate 2-to-1 data selector 2-input AND gate 2-input AND gate with one inverted input

A C VCCA VCCB 12 4 VCCAA 1 GNDA2 VCCB B1 DIR B GND VCC Y A C 1 1234567 8 16 15 14 13 12 11 10 9 VCCA 1DIR 2DIR 1A1 1A2 2A1 2A2 GND VCCB 1OE 2OE 1B1 1B2 2B1 2B2 GND 9 10 11 125 6 7 81 2 3 4 24 23 22 21 20 19 18 17 16 15 14 13 VCCA DIR A1 A2 A3 A4 A5 A6 A7 A8 GND GND VCCB VCCB OE B1 B2 B3 B4 B5 B6 B7 B8 GND B GND VCC Y A C VCCA VCCA GND DIR B A VCCB VCCB 1 2 BG N D VCC Y A C Pin Assignments See page 23 See page 27 See page 28 See page 29 See page 30 See page 31 See page 35 1T45 SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIG- URABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS 1T98 SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR WITH NINE CONFIG- URABLE GATE LOGIC FUNCTIONS 1T57 SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR WITH NINE CONFIG- URABLE GATE LOGIC FUNCTIONS 2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS 1T58 SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR WITH NINE CONFIG- URABLE GATE LOGIC FUNCTIONS 4T245 4-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS 1T97 SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR WITH NINE CONFIG- URABLE GATE LOGIC FUNCTION 8T245 8-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS See page 37

C 1B4 1B3 V CCB VCCA 1A3 1A4 D 1B6 1B5 GND GND 1A5 1A6 E 1B8 1B7 1A7 1A8 F 2B1 2B2 2A2 2A1 G 2B3 2B4 GND GND 2A4 2A3 H 2B5 2B6 V CCB VCCA 2A6 2A5 J 2B7 2B8 GND GND 2A8 2A7 K 2DIR NC NC NC NC 2OEJ H G F E D C B A K GQL OR ZQL PACKAGE (TOP VIEW) 2OE 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 48 47 46 45 44 43 42 41 1DIR 1B1 1B2 GND 1B3 1B4 V CCB 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 V CCB 2B5 2B6 GND 2B7 2B8 2DIR 1OE 1A1 1A2 GND 1A3 1A4 V CCA 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 V CCA 2A5 2A6 GND 2A7 2A8 (1) NC - No internal connection 13 2 456213 46 5 terminal assignments A B C D E F G H J K J H G F E D C B A K GQL OR ZQL PACKAGE (TOP VIEW) 1B1 1B2 1DIR 1OE 1A2 1A1 1B3 1B4 GND GND 1A4 1A3 1B5 1B6 V CCB VCCA 1A6 1A5 1B7 1B8 GND GND 1A8 1A7 1B9 1B10 1A10 1A9 2B1 2B2 2A2 2A1 2B3 2B4 GND GND 2A4 2A3 2B5 2B6 V CCB VCCA 2A6 2A5 2B7 2B8 GND GND 2A8 2A7 2B9 2B10 2DIR 2OE 2A10 2A9 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 9 10 11 12 56 55 54 53 52 51 50 49 5 6 7 81 2 3 4 1DIR 1B1 1B2 GND 1B3 1B4 V CCB 1B5 1B6 1B7 GND 1B8 1B9 1B10 2B1 2B2 2B3 GND 2B4 2B5 2B6 V CCB 2B7 2B8 GND 2B9 2B10 2DIR 1OE 1A1 1A2 GND 1A3 1A4 V CCA 1A5 1A6 1A7 GND 1A8 1A9 1A10 2A1 2A2 2A3 GND 2A4 2A5 2A6 V CCA 2A7 2A8 GND 2A9 2A10 2OE Pin Assignments See page 41 See page 45 16T245 16-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS 20T245 20-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

B 1B1 1B2 V CCB VCCA 1A2 1A1 C 1B3 1B4 GND GND 1A4 1A3 D 2B1 2B2 V CCB VCCA 2A2 2A1 E 2B3 2B4 GND GND 2A4 2A3 F 3B1 3B2 GND GND 3A2 3A1 G 3B3 3B4 GND 3A4 3A3 H 4B1 4B2 V CCB VCCA 4A2 4A1 J 4B3 4B4 GND GND 4A4 4A3 K 5B1 5B2 GND GND 5A2 5A1 L 5B3 5B4 V CCB VCCA 5A4 5A3 M 6B1 6B2 GND GND 6A2 6A1 N 6B3 6B4 V CCB VCCA 6A4 6A3 P 6DIR 5DIR 4DIR 3DIR 2DIR 1DIR GRG OR ZRG PACKAGE (TOP VIEW) J H G F E D C B A 213 4 65 P N M L K See page 47 24T245 24-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS terminal assignments 13 2 456 A B C D E F G H J K L M N P R T GRG OR ZRG PACKAGE (TOP VIEW) J H G F E D C B A 213 4 65 P N R T M L K 1B2 1B1 1DIR 1OE 1A1 1A2 1B4 1B3 GND GND 1A3 1A4 1B6 1B5 V CCB VCCA 1A5 1A6 1B8 1B7 GND GND 1A7 1A8 2B2 2B1 GND GND 2A1 2A2 2B4 2B3 V CCB VCCA 2A3 2A4 2B6 2B5 GND GND 2A5 2A6 2B7 2B8 2DIR 2OE 2A8 2A7 3B2 3B1 3DIR 3OE 3A1 3A2 3B4 3B3 GND GND 3A3 3A4 3B6 3B5 V CCB VCCA 3A5 3A6 3B8 3B7 GND GND 3A7 3A8 4B2 4B1 GND GND 4A1 4A2 4B4 4B3 V CCB VCCA 4A3 4A4 4B6 4B5 GND GND 4A5 4A6 4B7 4B8 4DIR 4OE 4A8 4A7 Pin Assignments See page 50 32T245 32-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS WITH 3-STATE DESELECTED OUTPUT

(TOP VIEW) BAC D GQS OR ZQS PACKAGE (TOP VIEW) E D C B A 213 4 5 TERMINAL ASSIGNMENTS (20-Ball GXY/ZXY Package) AB C D

5 VCCA CMD-dir DAT0-dir V CCB

4 DAT3A DAT2A DAT2B DAT3B

3 CLKA GND GND CLKB

2 DAT1A DAT0A CMDB DAT0B

1 CLK-f CMDA DAT123-dir DAT1B

(24-Ball GQS/ZQS Package) 12 3 4 5 A DAT2A CMD-dir DAT0-dir RSV DAT2B B DAT3A V CCA VCCB DAT3B C CLKA RSV GND GND CLKB D DAT0A CMDA RSV CMDB DAT0B E DAT1A CLK-f DAT123-dir RSV DAT1B 406L MMC, SD CARD, Memory Stick, SmartMedia, AND xD-Picture Card ±15-kV ESD-PROTECTED VOLTAGE-TRANSLATION TRANCEIVER See page 58 GQC/ZQC PACKAGE (TOP VIEW) G F E D C B A 213 46 5 7 TERMINAL ASSIGNMENTS (1) 1 234567 A VCCA 2A 4DIR 2DIR MODE1 10B1 V CCB0 B 10A1 3A 1A 1DIR MODE0 9B1 1B C 9A 10A2 3DIR GND 2B 3B D 9DIR 4A 56DIR GND 4B 11B 12B E 78DIR 6A GND CS0 GND 10B2 9B2 F 7A 8A 12A 13A 7B 5B 14B G VCCA 5A 11A CS1 8B 6B V CCB1 (1) V CCA powers all A-port I/Os and control inputs. VCCB0 powers 1B, 2B, 3B, 4B, 9B1, and 10B1. VCCB1 powers 5B, 6B, 7B, 8B, 9B2, 10B2, 11B, 12B, and 14B. See page 53 406 MMC, SD CARD, Memory Stick, SmartMedia, AND xD-Picture Card ±15-kV ESD-PROTECTED VOLTAGE-TRANSLATION TRANCEIVER

A D12 D04 D03 SD14 SD12 SD11 B D13 D05 D11 SD13 SD10 SD09 C D14 D06 SD15 SINPACK SD08 SD07 D D15 D07 VCC_CF VCC_S SD06 SD05 E CE2 CE1 GND GND SD04 SD03 F OE A10 VCC_CF VCC_S SD02 SD01 G A09 IORD GND GND SD00 SCE1 H A08 IOWR VCC_CF VCC_S EN_L EN_H J A07 WE GND GND MASTER_EN BUF_EN K A06 READY A05 SCE2 SOE SIORD L A04 RESET GND GND SWE SIOWR M A03 WAIT VCC_CF VCC_S SREADY SRESET N A02 INPACK GND GND SWAIT SREG P A01 REG VCC_CF GND SBVD2 SBVD1 R A00 BVD2 VCC_CF VCC_S SA10 SWP T D00 BVD1 VCC_SD DIR (S/CF) SA08 SA09 U D01 D08 CD1 DIR_OUT SA06 SA07 V D02 D09 CD2 SA00 SA04 SA05 W WP D10 SCD SA01 SA02 SA03 GKF PACKAGE (TOP VIEW) J H G F E D C B A 213 46 5 P N M L K T R U W V Pin Assignments See page 63 4320 LOW-POWER, DUAL-SUPPLY, LEVEL-TRANSLATING CompactFlashTM INTERFACE WITH 16-BIT DATA, 11-BIT ADDRESS, AND 13-BIT CONTROL LINES 123 24 22 VCCA DIR A1 VCCB NC OE A4 A5 A6 A7 A8 GND GND GND 123 24 22 (5V) VCCA DIR A1 (3.3V) VCCB (3.3V) VCCB OE A4 A5 A6 A7 A8 GND GND GND See page 61 See page 62 3245 OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS 4245 OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER WITH 3-STATE OUTPUTS (SN74LVC4245A) OCTAL DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS (SN74LVCC4245A)

A 1B2 1B1 1DIR 1OE 1A1 1A2 B 1B4 1B3 GND GND 1A3 1A4 C 1B6 1B5 V CCB VCCA 1A5 1A6 D 1B8 1B7 GND GND 1A7 1A8 E 2B2 2B1 GND GND 2A1 2A2 F 2B4 2B3 V CCB VCCA 2A3 2A4 G 2B6 2B5 GND GND 2A5 2A6 H 2B7 2B8 2DIR 2OE 2A8 2A7 J 3B2 3B1 3DIR 3OE 3A1 3A2 K 3B4 3B3 GND GND 3A3 3A4 L 3B6 3B5 V CCB VCCA 3A5 3A6 M 3B8 3B7 GND GND 3A7 3A8 N 4B2 4B1 GND GND 4A1 4A2 P 4B4 4B3 V CCB VCCA 4A3 4A4 R 4B6 4B5 GND GND 4A5 4A6 T 4B7 4B8 4DIR 4OE 4A8 4A7 GKE PACKAGE (TOP VIEW) J H G F E D C B A 2314 6 5 P N M L K T R Pin Assignments See page 69 324245 32-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS 1A5 2A2 2A11A71A4 1A8(3.3V)VCCA 1A6 GND (3.3V)VCCA 2OE2A8GND2A3 2A7GND 2A4 2A5 2A61A3GND1A1 1A21OE 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 2B11B4 (5V)VCCB 1B6 GND 1B7 2B2 1B81B3 1B5 2B82B3 2B4 (5V)VCCB 2B5 2B6 GND 2DIR 2B7GND 1 2 3 4 48 47 46 45 44 43 42 41 1B1 1B21DIR GND GQL OR ZQL PACKAGE (TOP VIEW) J H G F E D C B A 213 46 5 K TERMINAL ASSIGNMENTS (1) 12 3 4 5 6 A 1DIR NC NC NC NC 1OE B 1B2 1B1 GND GND 1A1 1A2 C 1B4 1B3 V CCB VCCA 1A3 1A4 D 1B6 1B5 GND GND 1A5 1A6 E 1B8 1B7 1A7 1A8 F 2B1 2B2 2A2 2A1 G 2B3 2B4 GND GND 2A4 2A3 H 2B5 2B6 V CCB VCCA 2A6 2A5 J 2B7 2B8 GND GND 2A8 2A7 K 2DIR NC NC NC NC 2OE (1) NC - No internal connection See page 67 164245 16-BIT TRANSCEIVER AND 3.3-V TO 5-V SHIFTER WITH 3-STATE OUTPUTS

• SN74ALVC164245: A port has VCCA, which is set to operate at 2.5 V and 3.3 V B port has VCCB, which is set to operate at 3.3 V and 5 V
• SN74AVCB164245, SN74AVCBH164245: The A-port is designed to track VCCA, VCCA accepts any supply voltage from 1.4 V to 3.6 V The B-port is designed to track VCCB, VCCB accepts any supply voltage from 1.4 V to 3.6 V

23PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. B DIR 5 A 3 VCCA VCCB Logic Diagram INPUT OPERATION DIR LB data to A bus HA data to B bus FUNCTION TABLE (1) (1) Input circuits of the data I/Os always are active. 1T45 SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLA- TION AND 3-STATE OUTPUTS

• VCC Isolation Feature - If Either VCC Input Is at GND, Both Ports Are in the High-Impedance State
• DIR Input Circuit Referenced to VCCA
• This Single-Bit Noninverting Bus Transceiver Uses Two Separate Configurable Power-Supply Rails
• Designed for asynchronous Communication Between Two Data Buses

24 : PREVIEW RECOMMENDED OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTECS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V UNIT IOH MAX -32 -24 -8 -4 -12 -9 -8 -6 -12 -9 -8 -6 mA IOL MAX 32 24 8 4 12 9 8 6 12 9 8 6 mA *ICCA + ICCB SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V UNIT : ns *The enable time is a calculated value, derived using the formula shown in the enable times section. PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V DIR B MAX MAXDIR A BA MAX MAXDIR A VCCA = 1.5V AB MAX AB MAX VCCA = 1.8V DIR B MAX DIR B MAX BA MAX DIR A MAX DIR B MAX DIR A MAX PARAMETER INPUT OUTPUT MAX or MIN AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V tPLH 3.4 3.9 5 5.3 tPHL 3.4 3.9 5 5.3 tPLH 4.4 4.6 5 5.2 tPHL 4.4 4.6 5 5.2 tPHZ 65 . 9 5 . 95 . 9 tPLZ 65 . 9 5 . 95 . 9 tPHZ 5.3 4.4 6.8 7.7 tPLZ 5.3 4.4 6.8 7.7 tPZH* 8.7 9 11.8 12.9 tPZL* 8.7 9 11.8 12.9 tPZH* 9.4 9.8 10.9 11.2 tPZL* 9.4 9.8 10.9 11.2 UNIT : ns *The enable time is a calculated value, derived using the formula shown in the enable times section. AB MAX VCCA = 1.8V DIR B MAX BA MAX DIR A MAX DIR B MAX DIR A MAX

25PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AB MAX BA MAX DIR A MAX DIR B MAX AB MAX DIR A MAX DIR B MAX A MAX BA MAX DIR A MAX VCCA = 2.5V VCCA = 3.3V DIR B MAX DIR B MAX DIR PARAMETER INPUT OUTPUT MAX or MIN AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V tPLH 33 . 4 4 . 64 . 9 tPHL 33 . 4 4 . 64 . 9 tPLH 3.3 3.4 3.8 4.2 tPHL 3.3 3.4 3.8 4.2 tPHZ 3.8 3.8 3.8 3.8 tPLZ 3.8 3.8 3.8 3.8 tPHZ 44 . 1 6 . 57 . 6 tPLZ 44 . 1 6 . 57 . 6 tPZH* 7.3 7.5 10.3 11.8 tPZL* 7.3 7.5 10.3 11.8 tPZH* 6.6 7 8.1 8.6 tPZL* 6.6 7 8.1 8.6 UNIT : ns *The enable time is a calculated value, derived using the formula shown in the enable times section. AB MAX BA MAX DIR A MAX DIR B MAX DIR A MAX DIR B MAX VCCA = 2.5V PARAMETER INPUT OUTPUT MAX or MIN AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V tPLH 2.8 3.3 4.4 4.7 tPHL 2.8 3.3 4.4 4.7 tPLH 2.8 3 3.4 3.8 tPHL 2,8 3 3.4 3.8 tPHZ 4.3 4.3 4.3 4.3 tPLZ 4.3 4.3 4.3 4.3 tPHZ 4.9 4 6.5 7.4 tPLZ 4.9 4 6.5 7.4 tPZH* 6.7 7 9.9 11.2 tPZL* 6.7 7 9.9 11.2 tPZH* 6.8 7.2 8.5 8.9 tPZL* 6.8 7.2 8.5 8.9 UNIT : ns *The enable time is a calculated value, derived using the formula shown in the enable times section. AB MAX A MAX BA MAX DIR A MAX VCCA = 3.3V DIR B MAX DIR B MAX DIR

26 : PREVIEW PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 3.9 5.4 7.5 15.1 tPHL 3.5 4.5 6.2 12.2 tPLH 3.9 4.4 5.1 7.2 tPHL 3.5 44 . 6 7 tPHZ 5.4 5.5 5.4 5.4 tPLZ 3.7 3.7 3.8 3.8 tPHZ 6.5 8.5 9.8 20.2 tPLZ 4.5 77 . 4 14.8 tPZH* 8.4 11.4 12.5 22 tPZL* 10 12.5 14.4 27.2 tPZH* 7.6 9.1 11.3 18.9 tPZL* 8.6 10 11.6 17.6 UNIT : ns *The enable time is a calculated value, derived using the formula shown in the enable times section. DIR B MAX DIR A MAX DIR B MAX DIR A MAX AB MAX BA MAX V CCA = 5.0V

27PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. B A 4 Y Logic Diagram FUNCTION SELECTION TABLE LOGIC FUNCTION 2-input AND gate 2-input NOR gate with both inputs inverted 2-input NAND gate with inverted input 2-input OR gate with inverted input 2-input AND gate with both inputs inverted 2-input NOR gate 2-input XNOR gate Inverter Noninverted buffer FUNCTION TABLE INPUTS OUTPUT YCBA LLL H LLH L LHL H LHH L HLL L HLH L HHL H HHH H 1T57 SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR WITH NINE CONFIGURABLE GATE LOGIC FUNCTIONS

• Single-Supply Voltage Translator
• Nine Configurable Gate Logic Functions
• Scmitt-Trigger Inputs Reject Input Noise and Provide Better Output Signal Integrity RECOMMENDED OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTECS PARAMETER MAX or MIN AUP 3.3V AUP 2.5V UNIT ICC MAX 0.0009 0.0009 mA IOH MAX -4 -3.1 mA IOL MAX 4 3.1 mA SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN AUP 3.3V AUP 2.5V tPLH 8.5 7.9 tPHL 8.5 7.9 tPLH 6.1 7.1 tPHL 6.1 7.1 PARAMETER VI = 1.8V VI = 2.5V A, B, or C Y MAX A, B, or C Y MAX UNIT : ns

28 : PREVIEW B A 4 Y Logic Diagram FUNCTION SELECTION TABLE LOGIC FUNCTION 2-input NAND gate 2-input OR gate with both inputs inverted 2-input AND gate with inverted input 2-input NOR gate with inverted input 2-input NAND gate with both inputs inverted 2-input OR gate 2-input XOR gate Inverter Noninverted buffer FUNCTION TABLE INPUTS OUTPUT YCBA LLL L LLH H LHL L LHH H HLL H HLH H HHL L HHH L 1T58 SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR WITH NINE CONFIGURABLE GATE LOGIC FUNCTIONS

• Single-Supply Voltage Translator
• Nine Configurable Gate Logic Functions
• Scmitt-Trigger Inputs Reject Input Noise and Provide Better Output Signal Integrity RECOMMENDED OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTECS PARAMETER MAX or MIN AUP 3.3V AUP 2.5V UNIT ICC MAX 0.0009 0.0009 mA IOH MAX -4 -3.1 mA IOL MAX 4 3.1 mA SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN AUP 3.3V AUP 2.5V tPLH 8.5 7.9 tPHL 8.5 7.9 tPLH 6.1 7.1 tPHL 6.1 7.1 PARAMETER VI = 1.8V VI = 2.5V A, B, or C Y MAX A, B, or C Y MAX UNIT : ns

29PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. B A 4 Y Logic Diagram FUNCTION SELECTION TABLE LOGIC FUNCTION 2-to-1 data selector 2-input AND gate 2-input OR gate with one inverted input 2-input NAND gate with one inverted input 2-input AND gate with one inverted input 2-input NOR gate with one inverted input 2-input OR gate Inverter Noninverted buffer FUNCTION TABLE INPUTS OUTPUT YCBA LLL L LLH L LHL H LHH H HLL L HLH H HHL L HHH H 1T97 SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR WITH NINE CONFIGURABLE GATE LOGIC FUNCTION

• Single-Supply Voltage Translator
• Nine Configurable Gate Logic Functions
• Scmitt-Trigger Inputs Reject Input Noise and Provide Better Output Signal Integrity RECOMMENDED OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTECS PARAMETER MAX or MIN AUP 3.3V AUP 2.5V UNIT ICC MAX 0.0009 0.0009 mA IOH MAX -4 -3.1 mA IOL MAX 4 3.1 mA SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN AUP 3.3V AUP 2.5V tPLH 8.5 7.9 tPHL 8.5 7.9 tPLH 6.1 7.1 tPHL 6.1 7.1 PARAMETER VI = 1.8V VI = 2.5V A, B, or C Y MAX A, B, or C Y MAX tPLH 5.7 6.5 t UNIT : ns PHL 5.7 6.5VI = 3.3V A, B, or C Y MAX

30 : PREVIEW B A 4 Y Logic Diagram FUNCTION SELECTION TABLE LOGIC FUNCTION 2-to-1 data selector 2-input AND gate 2-input OR gate with one inverted input 2-input NAND gate with one inverted input 2-input AND gate with one inverted input 2-input NOR gate with one inverted input 2-input OR gate Inverter Noninverted buffer FUNCTION TABLE INPUTS OUTPUT YCBA LLL H LLH H LHL L LHH L HLL H HLH L HHL H HHH L 1T98 SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR WITH NINE CONFIGURABLE GATE LOGIC FUNCTIONS

• Single-Supply Voltage Translator
• Nine Configurable Gate Logic Functions
• Scmitt-Trigger Inputs Reject Input Noise and Provide Better Output Signal Integrity RECOMMENDED OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTECS PARAMETER MAX or MIN AUP 3.3V AUP 2.5V UNIT ICC MAX 0.0009 0.0009 mA IOH MAX -4 -3.1 mA IOL MAX 4 3.1 mA SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN AUP 3.3V AUP 2.5V tPLH 8.5 7.9 tPHL 8.5 7.9 tPLH 6.1 7.1 tPHL 6.1 7.1 PARAMETER VI = 1.8V VI = 2.5V A, B, or C Y MAX A, B, or C Y MAX tPLH 5.7 6.5 t UNIT : ns PHL 5.7 6.5VI = 3.3V A, B, or C Y MAX

31PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. DIR 5 A1 2 VCCA VCCB B26 A2 3 Logic Diagram INPUT OPERATION DIR LB data to A bus HA data to B bus FUNCTION TABLE (1) (each transceiver) (1) Input circuits of the data I/Os always are active. 2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

• Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
• This Dual-Bit Noninverting Bus Transceiver Uses Two Separate Configurable Power-Supply Rails
• Designed for asynchronous Communication Between Two Data Buses

32 : PREVIEW RECOMMENDED OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTECS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V UNIT IOH MAX -32 -24 -8 -4 -12 -9 -8 -6 -12 -9 -8 -6 mA IOL MAX 32 24 8 4 12 9 8 6 12 9 8 6 mA *ICCA + ICCB SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V UNIT : ns *The enable time is a calculated value, derived using the formula shown in the enable times section. PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V A MAX DIR B MAX DIR A MAX DIR B MAX DIR B MAX BA MAX DIR AB MAX VCCA = 1.8V VCCA = 1.5V AB MAX BA MAX MAXDIR A DIR B MAX MAXDIR A PARAMETER INPUT OUTPUT MAX or MIN AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V tPLH 3.1 3.4 4.3 5.2 tPHL 3.1 3.4 4.3 5.2 tPLH 3.8 4 4.4 4.7 tPHL 3.8 4 4.4 4.7 tPHZ 4.5 5.3 6.9 8.1 tPLZ 4.5 5.3 6.9 8.1 tPHZ 5.9 5.7 5.9 5.8 tPLZ 5.9 5.7 5.9 5.8 tPZH* 9.7 9.7 10.3 10.4 tPZL* 9.7 9.7 10.3 10.4 tPZH* 7.4 8.6 11.2 13.3 tPZL* 7.4 8.6 11.2 13.3 UNIT : ns *The enable time is a calculated value, derived using the formula shown in the enable times section. A MAX DIR B MAX DIR A MAX DIR B MAX BA MAX DIR AB MAX VCCA = 1.8V

33PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V PARAMETER INPUT OUTPUT MAX or MIN AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V tPLH 2.4 2.8 3.8 4.7 tPHL 2.4 2,8 3.8 4.7 tPLH 2.4 2.6 3.1 3.6 tPHL 2.4 2.6 3.1 3.6 tPHZ 44 . 7 6 . 58 tPLZ 44 . 7 6 . 58 tPHZ 3.5 4.6 5.6 6.6 tPLZ 3.5 4.6 5.6 6.6 tPZH* 5.9 6.2 6.6 6.9 tPZL* 5.9 6.2 6.6 6.9 tPZH* 6.3 7.4 10.3 12.7 tPZL* 6.3 7.4 10.3 12.7 UNIT : ns *The enable time is a calculated value, derived using the formula shown in the enable times section. VCCA = 2.5V VCCA = 3.3V DIR B MAX DIR B MAX DIR A MAX BA MAX DIR A MAX AB MAX DIR A MAX DIR B MAX DIR A MAX DIR B MAX AB MAX BA MAX PARAMETER INPUT OUTPUT MAX or MIN AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V tPLH 2.6 3 4 4.9 tPHL 2.6 3 4 4.9 tPLH 2.8 3 3.4 3.8 tPHL 2.8 3 3.4 3.8 tPHZ 4.3 5 6.4 7.9 tPLZ 4.3 5 6.4 7.9 tPHZ 4.1 4.2 4.3 4.3 tPLZ 4.1 4.2 4.3 4.3 tPZH* 6.9 7.2 7.7 7.9 tPZL* 6.9 7.2 7.7 7.9 tPZH* 6.8 7.9 10.4 12.8 tPZL* 6.8 7.9 10.4 12.8 UNIT : ns *The enable time is a calculated value, derived using the formula shown in the enable times section. VCCA = 2.5V DIR A MAX DIR B MAX DIR A MAX DIR B MAX AB MAX BA MAX PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V tPHL 457 12.6 2.4 2,8 3.8 4.7 VCCA = 3.3V DIR B MAX DIR B MAX DIR A MAX BA MAX DIR A MAX AB MAX

34 : PREVIEW PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 3.9 5.4 7.5 15.1 tPHL 3.5 4.5 6.2 12.2 tPLH 3.9 4.4 5.1 7.2 tPHL 3.5 44 . 6 7 tPHZ 5.4 5.5 5.4 5.4 tPLZ 3.7 3.7 3.8 3.8 tPHZ 6.5 8.5 9.8 20.2 tPLZ 4.5 77 . 4 14.8 tPZH* 8.4 11.4 12.5 22 tPZL* 10 12.5 14.4 27.2 tPZH* 7.6 9.1 11.3 18.9 tPZL* 8.6 10 11.6 17.6 UNIT : ns *The enable time is a calculated value, derived using the formula shown in the enable times section. DIR B MAX DIR A MAX DIR B MAX DIR A MAX AB MAX BA MAX V CCA = 5.0V

35PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 1DIR 1OE 1A1 1B1 1A2 1B2 2DIR 2OE 2A1 2B1 2A2 2B2 Logic Diagram INPUTS OPERATION OE DIR LL B data to A bus LH A data to B bus HX All output Hi-Z FUNCTION TABLE (each 4-bit section) 4T245 4-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

• Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
• This 4-Bit Noninverting Bus Transceiver Uses Two Separate Configurable Power-Supply Rails
• Designed for asynchronous Communication Between Data Buses RECOMMENDED OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTECS PARAMETER MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V UNIT IOH MAX -12 -9 -8 -6 -12 -9 -8 -6 mA IOL MAX 12 9 8 6 12 9 8 6 mA *ICCA + ICCB SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V UNIT : ns A OE B MAX MAXOE VCCA = 1.5V AB MAX BA MAX MAXOE A OE B MAX

36 : PREVIEW PARAMETER INPUT OUTPUT MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V UNIT : ns VCCA = 3.3V OE B MAX OE B MAX OE A MAX BA MAX OE A MAX AB MAX PARAMETER INPUT OUTPUT MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V UNIT : ns PARAMETER INPUT OUTPUT MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V tPZH 44 . 878 . 844 . 878 . 8 tPZL 44 . 878 . 844 . 878 . 8 UNIT : ns VCCA = 1.8V VCCA = 2.5V OE A MAX OE B MAX OE A MAX OE B MAX AB MAX BA MAX OE B MAX OE A MAX OE B MAX BA MAX OE A MAX AB MAX

37PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. DIR OE To Seven Other Channels OUTPUTS CIRCUITS OPERATION A PORT B PORT Enabled Hi-Z B data to A bus Hi-Z Enabled A data to B bus Hi-Z Hi-Z CONTROL INPUTS OE DIR LL LH HX Isolation FUNCTION TABLE(1) (each 8-bit section) (1) Input circuits of the data I/Os are always active. 8T245 8-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

• Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
• VCC Isolation Feature - If Either VCC Input Is at GND, All I/O Ports Are in the High-Impedance State
• This 8-Bit Noninverting Bus Transceiver Uses Two Separate Configurable Power-Supply Rails
• Designed for asynchronous Communication Between Data Buses Logic Diagram

38 : PREVIEW PARAMETER MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V UNIT IOH MAX -12 -9 -8 -6 -12 -9 -8 -6 mA IOL MAX 12 9 8 6 12 9 8 6 mA *ICCA + ICCB SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V UNIT : ns PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V LVCH LVCH 3.3V LVCH 2.5V LVCH 1.8V tPZH 10.8 12.6 16 32 10.8 12.6 16 32 tPZL 10.8 12.6 16 32 10.8 12.6 16 32 OE B MAX MAXOE A MAX BA MAX MAXOE A VCCA = 1.5V AB MAX A OE B MAX VCCA = 1.8V AB MAX OE B MAX BA MAX OE OE B MAX OE A MAX UNIT mA mA mA RECOMMENDED OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTECS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V LVCH LVCH 3.3V LVCH 2.5V LVCH 1.8V IOH MAX -32 -24 -8 -4 -32 -24 -8 -4 IOL MAX 32 24 8 4 32 24 8 4 PARAMETER INPUT OUTPUT MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V UNIT : ns A MAX VCCA = 1.8V AB MAX OE B MAX BA MAX OE OE B MAX OE A MAX

39PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V LVCH LVCH 3.3V LVCH 2.5V LVCH 1.8V tPHZ 99999999 tPLZ 99999999 PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V LVCH LVCH 3.3V LVCH 2.5V LVCH 1.8V VCCA = 2.5V VCCA = 3.3V AB MAX BA MAX OE A MAX OE B MAX AB MAX OE A MAX OE B MAX BA MAX OE A MAX OE B MAX OE B MAX OE A MAX PARAMETER INPUT OUTPUT MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V UNIT : ns VCCA = 2.5V AB MAX BA MAX OE A MAX OE B MAX OE A MAX OE B MAX PARAMETER INPUT OUTPUT MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V tPZH 44444444 tPZL 44444444 tPHZ 44444444 tPLZ 44444444 UNIT : ns VCCA = 3.3V AB MAX BA MAX OE A MAX OE B MAX OE B MAX OE A MAX

40 : PREVIEW PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V LVCH LVCH 3.3V LVCH 2.5V LVCH 1.8V UNIT : ns VCCA = 5.0V OE B MAX OE A MAX OE B MAX OE A MAX AB MAX BA MAX

41PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. To Seven Other Channels 1DIR 1A1 1B1 1OE To Seven Other Channels 2DIR 2A1 2B1 2OE Logic Diagram INPUTS OPERATION OE DIR LL B data to A bus LH A data to B bus HX Isolation FUNCTION TABLE (each 8-bit section) 16T245 16-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

• Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
• VCC Isolation Feature - If Either VCC Input Is at GND, Both Ports Are in the High-Impedance State
• Overvoltage-Tolerant Inputs / Outputs Allow Mixed-Voltage-Mode Data Communications
• This 16-Bit Noninverting Bus Transceiver Uses Two Separate Configurable Power-Supply Rails
• Designed for asynchronous Communication Between Data Buses

42 : PREVIEW PARAMETER MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.8V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.8V UNIT IOH MAX -12 -9 -8 -6 -12 -9 -8 -6 mA IOL MAX 12 9 8 6 12 9 8 6 mA *ICCA + ICCB SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V UNIT : ns PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V LVCH LVCH 3.3V LVCH 2.5V LVCH 1.8V tPZH 10.8 12.6 16 32 10.8 12.6 18 32 tPZL 10.8 12.6 16 32 10.8 12.6 18 32 OE A MAX OE B MAX BA MAX OE VCCA = 1.8V AB MAX A OE B MAX VCCA = 1.5V AB MAX BA MAX MAXOE A OE B MAX MAXOE A MAX RECOMMENDED OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTECS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V LVCH LVCH 3.3V LVCH 2.5V LVCH 1.8V UNIT IOH MAX -32 -24 -8 -4 -32 -24 -8 -4 mA IOL MAX 32 24 8 4 32 24 8 4 mA PARAMETER INPUT OUTPUT MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V UNIT : ns OE B MAX OE A MAX OE B MAX BA MAX OE VCCA = 1.8V AB MAX A MAX

43PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V LVCH LVCH 3.3V LVCH 2.5V LVCH 1.8V tPHZ 99999999 tPLZ 99999999 PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V LVCH LVCH 3.3V LVCH 2.5V LVCH 1.8V OE B MAX OE A MAX BA MAX OE A MAX AB MAX OE A MAX OE B MAX OE A MAX OE B MAX AB MAX BA MAX VCCA = 2.5V VCCA = 3.3V PARAMETER INPUT OUTPUT MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V UNIT : ns OE A MAX OE B MAX OE A MAX OE B MAX AB MAX BA MAX VCCA = 2.5V PARAMETER INPUT OUTPUT MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V tPHZ 55555555 tPLZ 55555555 UNIT : ns OE B MAX OE B MAX OE A MAX BA MAX OE A MAX AB MAX VCCA = 3.3V

44 : PREVIEW PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V LVCH LVCH 3.3V LVCH 2.5V LVCH 1.8V UNIT : ns A MAX AB MAX BA MAX OE B MAX OE A MAX OE B MAX OE VCCA = 5.0V

45PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. To Nine Other Channels 1DIR 1A1 1B1 1OE To Nine Other Channels 2DIR 2A1 2B1 2OE INPUTS OPERATION OE DIR LL B data to A bus LH A data to B bus HX Isolation FUNCTION TABLE (each 10-bit section) 20T245 20-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

• Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
• VCC Isolation Feature - If Either VCC Input Is at GND, Both Ports Are in the High-Impedance State
• Overvoltage-Tolerant Inputs / Outputs Allow Mixed-Voltage-Mode Data Communications
• This 20-Bit Noninverting Bus Transceiver Uses Two Separate Configurable Power-Supply Rails
• Designed for asynchronous Communication Between Data Buses Logic Diagram RECOMMENDED OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTECS PARAMETER MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.8V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.8V UNIT IOH MAX -12 -9 -8 -6 -12 -9 -8 -6 mA IOL MAX 12 9 8 6 12 9 8 6 mA *ICCA + ICCB SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V tPHZ 99999999 tPLZ 99999999 UNIT : ns OE B MAX MAXOE A BA MAX MAXOE A VCCA = 1.5V AB MAX OE B MAX

46 : PREVIEW PARAMETER INPUT OUTPUT MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V UNIT : ns PARAMETER INPUT OUTPUT MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V UNIT : ns PARAMETER INPUT OUTPUT MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V tPHZ 55555555 tPLZ 55555555 UNIT : ns VCCA = 2.5V VCCA = 3.3V A MAX AB MAX VCCA = 1.8V OE B MAX BA MAX OE OE B MAX OE A MAX AB MAX BA MAX OE A MAX OE B MAX AB MAX OE A MAX OE B MAX BA MAX OE A MAX OE B MAX OE B MAX OE A MAX

47PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. To Three Other Channels 1DIR 1A1 1B1 1OE To Three Other Channels 2DIR 2A1 2B1 2OE To Three Other Channels 3DIR 3A1 3B1 3OE To Three Other Channels 4DIR 4A1 4B1 4OE To Three Other Channels 5DIR 5A1 5B1 5OE To Three Other Channels 6DIR 6A1 6B1 6OE 24T245 24-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

• Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
• VCC Isolation Feature - If Either VCC Input Is at GND, All Outputs Are in the High-Impedance State
• Overvoltage-Tolerant Inputs / Outputs Allow Mixed-Voltage-Mode Data Communications
• This 24-Bit Noninverting Bus Transceiver Uses Two Separate Configurable Power-Supply Rails
• Designed for asynchronous Communication Between Data Buses Logic Diagram

48 : PREVIEW RECOMMENDED OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTECS PARAMETER MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.8V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.8V UNIT IOH MAX -12 -9 -8 -6 -12 -9 -8 -6 mA IOL MAX 12 9 8 6 12 9 8 6 mA *ICCA + ICCB SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V UNIT : ns PARAMETER INPUT OUTPUT MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V UNIT : ns OE B MAX MAXOE A MAX A BA MAX MAXOE A VCCA = 1.5V AB MAX OE B MAX AB MAX VCCA = 1.8V OE B MAX BA MAX OE OE B MAX OE A MAX INPUTS OPERATION OE DIR LL B data to A bus LH A data to B bus HX Isolation FUNCTION TABLE (each 4-bit section)

49PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER INPUT OUTPUT MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V tPHZ 55555555 tPLZ 55555555 UNIT : ns VCCA = 3.3V AB MAX BA MAX OE A MAX OE B MAX OE B MAX OE A MAX PARAMETER INPUT OUTPUT MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V UNIT : ns VCCA = 2.5V AB MAX BA MAX OE A MAX OE B MAX OE A MAX OE B MAX

50 : PREVIEW To Seven Other Channels 1DIR 1A1 1B1 1OE To Seven Other Channels 2DIR 2A1 2B1 2OE To Seven Other Channels 3DIR 3A1 3B1 3OE To Seven Other Channels 4DIR 4A1 4B1 4OE INPUTS OPERATION OE DIR LL B data to A bus LH A data to B bus HX Isolation FUNCTION TABLE (each 8-bit section) 32T245 32-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

• Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
• VCC Isolation Feature - If Either VCC Input Is at GND, Both Ports Are in the High-Impedance State
• Overvoltage-Tolerant Inputs / Outputs Allow Mixed-Voltage-Mode Data Communications
• This 24-Bit Noninverting Bus Transceiver Uses Two Separate Configurable Power-Supply Rails
• Designed for asynchronous Communication Between Data Buses Logic Diagram

51PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. RECOMMENDED OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTECS PARAMETER MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.8V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.8V UNIT IOH MAX -12 -9 -8 -6 -12 -9 -8 -6 mA IOL MAX 12 9 8 6 12 9 8 6 mA *ICCA + ICCB SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V UNIT : ns PARAMETER INPUT OUTPUT MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V UNIT : ns PARAMETER INPUT OUTPUT MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V UNIT : ns OE A MAX OE B MAX OE A MAX OE B MAX AB MAX BA MAX OE B MAX OE A MAX OE B MAX BA MAX OE OE B MAX AB MAX VCCA = 1.8V VCCA = 1.5V AB MAX BA MAX MAXOE A VCCA = 2.5V OE B MAX MAXOE A MAX A

52 : PREVIEW PARAMETER INPUT OUTPUT MAX or MIN AVC 3.3V AVC 2.5V AVC 1.8V AVC 1.5V AVCH 3.3V AVCH 2.5V AVCH 1.8V AVCH 1.5V tPHZ 55555555 tPLZ 55555555 UNIT : ns OE B MAX OE B MAX OE A MAX BA MAX OE A MAX AB MAX VCCA = 3.3V

53PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 10A1 10B1 TP(2) 10B2 13A 10A2 CLK Path CTRL(1) CTRL(1) CTRL(1) (1) CTRL represents a decoded MODE0, MODE1, CS0, and CS1 state. (2) Translation point TP(2) TP(2) TP(2) CTRL(1) CTRL(1) 406 MMC, SD CARD, Memory Stick, SmartMedia, AND xD-Picture Card ±15-kV ESD-PROTECTED VOLTAGE-TRANSLATION TRANCEIVER

• Transceiver for Memory Card Interface [MultiMediaCard (MMC), Secure Digital (SD), Memory StickTM Complliant Products, SmartMedia Card, and xD-Picture CardTM]
• For Low-Power Operation, A ports Are Placed in High-Impedance State When Card-Side Supply Voltage Is Switched Off Logic Diagram B (5, 6, 7, 8) Data Path CTRL(1) CTRL(1) (1) CTRL represents a decoded MODE0, MODE1, CS0, and CS1 state. (2) Translation point CTRL(1) CTRL(1) CTRL(1) CTRL(1) B (1, 2, 3, 4) DIR (1, 2, 3, 4) DIR (5, 6, 7, 8) A (1, 2, 3, 4) A (5, 6, 7, 8) CTRL(1) TP(2) TP(2) TP(2) TP(2) TP(2) TP(2) TP(2)

54 : PREVIEW 9B2 CMD Path CTRL(1) CTRL(1) CTRL(1) CTRL(1) 9B1 9DIR CS1 CTRL(1) (1) CTRL represents a decoded MODE0, MODE1, CS0, and CS1 state. (2) Translation point TP(2) TP(2) TP(2) TP(2) TP(2) TP(2) WP and R/B Paths (1) CTRL represents a decoded MODE0, MODE1, CS0, and CS1 state. (2) Translation point (3) 12A is open drain in NAND (XD) mode and pushúpull in other modes. 11B11A CTRL(1) 12A 12B (3) TP(2) TP(2) 14B IRQ and CEout Paths CTRL(1) (1) CTRL represents a decoded MODE0, MODE1, CS0, and CS1 state. (2) Pushúpull in NAND flash (XD) mode and open drain in other modes CTRL(1) CS0 (2)

55PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.

ELECTRICAL CHARACTERISTICS

RECOMMENDED OPERATING CONDITIONS AVCA 3.3V AVCA 2.5V AVCA 1.8V AVCA 1.5V UNIT IOH -8 -4 -2 -1 mA IOL 8421 m A IOH -16 -8 -4 -2 mA IOL 16 8 4 2 mA *IO_SD = 0 SWITCHING CHARACTERISTICS PARAMETER INPUT (FROM OUTPUT (TO) MAX or MIN AVCA VCCA 3.3V AVCA VCCA 2.5V AVCA VCCA 1.8V tpd AB MAX 4.4 4.9 7.7 tpd BA MAX 5 5 6.3 tpd CLK, or SCLK.h CLK, or SCLK.0 MAX 4.9 5 7.7 tpd CLK, or SCLK.h CLK, or SCLK.-f.h MAX 9.7 12 19 tpd CMD.h CMD.1 MAX 4.2 4.6 7 tpd CS0 B MAX 3.9 4.2 6 tpd R/B R/B.h MAX 4.8 4.8 5.7 tpd WE WE.h MAX 4.2 4.3 7.4 tpd WP WP .h MAX 4.3 4.5 6.6 ten DAT1.0 or DATA1.0 IRQ MAX 3.3 3.3 4.8 ten DAT1.0 or DATA1.1 IRQ MAX 3.3 3.4 4.9 ten DIR B MAX 4.6 4.5 6.7 ten DIR A MAX 9.5 9.6 10.3 ten R/B R/B.h open drain MAX 5.4 5.4 5.9 tdis DAT1.0 or DATA1.0 IRQ MAX 5.5 4.9 6.7 tdis DAT1.0 or DATA1.1 IRQ MAX 5.4 4.7 6.5 tdis DIR B MAX 6.3 6.4 6.9 tdis DIR A MAX 5.2 5.3 5.3 tdis R/B R/B.h open drain MAX 4.1 17.4 16.9 UNIT : ns PARAMETER A port B port ICCB PARAMETER VCCA = 1.5V AVCA VCCA = 3.3V VCCB = 0V AVCA VCCA = 3.3V VCCB = 3.3V AVCA VCCA = 2.5V VCCB = 2.5V 0.01 0.001 0.0075 MAX or MIN MAX MAX AVCA VCCA = 1.8V VCCB = 0V AVCA VCCA = 1.8V VCCB = 1.8V AVCA VCCA = 1.5V VCCB = 1.5V 0.007 0.0045 0.0065 MAX MAX 0.0005 MAX or MIN

56 : PREVIEW PARAMETER INPUT (FROM OUTPUT (TO) MAX or MIN AVCA VCCA 3.3V AVCA VCCA 2.5V AVCA VCCA 1.8V tpd AB MAX 3.7 4.6 7.5 tpd BA MAX 4 4.2 4.6 tpd CLK, or SCLK.h CLK, or SCLK.0 MAX 4,2 4.8 8 tpd CLK, or SCLK.h CLK, or tpd CMD.0 CMD.h MAX 3.8 4 4.5 tpd CS0 B MAX 3.8 4 6.6 tpd R/B R/B.h MAX 3.8 4 4.4 tpd WE WE.h MAX 3.7 3.9 7.3 tpd WP WP .h MAX 3.8 4 5.6 ten DAT1.0 or DATA1.0 IRQ MAX 3.3 3.3 5 ten DAT1.0 or DATA1.1 IRQ MAX 3.1 3.1 4.6 ten DIR B MAX 3.6 3.8 6.4 ten DIR A MAX 6.9 6.9 7.7 ten R/B R/B.h open drain MAX 4.1 4.1 4.4 tdis DAT1.0 or DATA1.0 IRQ MAX 5.5 4.8 6.5 tdis DAT1.0 or DATA1.1 IRQ MAX 5.3 4.8 6.6 tdis DIR B MAX 5.7 5.4 6.3 tdis DIR A MAX 5.2 5.3 5.2 tdis R/B R/B.h open drain MAX 3.8 19.5 15.9 UNIT : ns PARAMETER INPUT (FROM OUTPUT (TO) MAX or MIN AVCA VCCA 3.3V AVCA VCCA 2.5V PARAMETER INPUT (FROM OUTPUT (TO) MAX or MIN AVCA VCCA 3.3V tpd AB MAX 3,1 4 tpd AB MAX 2.9 tpd BA MAX 3,6 3.7 tpd BA MAX 3.8 tpd CLK, or SCLK.h CLK, or SCLK.0 MAX 3,5 3.9 tpd CLK, or SCLK.h CLK, or SCLK.0 MAX 3.3 tpd CLK, or SCLK.h CLK, or SCLK.-f.h MAX 7 8.3 tpd CLK, or SCLK.h CLK, or SCLK.-f.h MAX 6.1 tpd CS0 B MAX 3.3 4.2 tpd CS0 B MAX 3.7 tpd WE WE.h MAX 3 3.6 tpd WE WE.h MAX 3 ten DAT1.0 or DATA1.0 IRQ MAX 3.2 3.3 ten DAT1.0 or DATA1.0 IRQ MAX 3.2 ten DAT1.0 or DATA1.1 IRQ MAX 3.2 3.6 ten DAT1.0 or DATA1.1 IRQ MAX 3.2 ten DIR B MAX 3.6 4.7 ten DIR B MAX 3.7 ten DIR A MAX 5.1 5.3 ten DIR A MAX 4.7 ten R/B R/B.h open drain MAX 3 3.2 ten R/B R/B.h open drain MAX 4.9 tdis DAT1.0 or DATA1.0 IRQ MAX 5.4 7.2 tdis DAT1.0 or DATA1.0 IRQ MAX 5.3 tdis DAT1.0 or DATA1.1 IRQ MAX 5.4 7 tdis DAT1.0 or DATA1.1 IRQ MAX 5.2 tdis DIR B MAX 5.1 4.5 tdis DIR B MAX 5 tdis DIR A MAX 3.7 3.7 tdis DIR A MAX 4.7 tdis R/B R/B.h open drain MAX 3.9 3.2 tdis R/B R/B.h open drain MAX 6 UNIT : ns UNIT : ns VCCA = 2.5V VCCA = 1.8V VCCA = 3.3V

57PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. MAXIMUM FREQUENCY AND OUTPUT SKEW INPUT (FROM OUTPU T (TO) MAX or MIN AVCA VCCA 3.3V AVCA VCCA 2.5V AVCA VCCA 1.8V AVCA VCCA 1.5V UNIT AB 5 2 52 52 52 MHz BA 5 2 52 52 52 MHz AB 2 6 26 26 26 MHz BA 2 6 26 26 26 MHz AB MAX 0.7 0.7 0.8 1.5 ns UNIT : ns MIN MIN PARAMETER Clock Data fmax tsk(o) VCCB = 3.3V

58 : PREVIEW Logic Diagram CMD-dir DAT0-dir CMDA DAT0A DAT123-dir DAT0B DAT1B CMDB DAT2B DAT3B CLKB VCCBVCCA DAT1A DAT2A DAT3A CLKA CLK-f FUNCTION TABLES OUTPUT CIRCUITSCONTROL INPUT OPERATIONCMD-dir CMDA CMDB High Hi-Z Enabled CMDA to CMDB Low Enabled Hi-Z CMDB to CMDA OUTPUT CIRCUITSCONTROL INPUT FUNCTIONDAT0-dir DAT0A DAT0B High Hi-Z Enabled DAT0A to DAT0B Low Enabled Hi-Z DAT0B to DAT0A 406L MMC, SD CARD, Memory Stick, SmartMedia, AND xD-Picture Card ±15-kV ESD-PROTECTED VOLTAGE-TRANSLATION TRANCEIVER

• Transceiver for Memory Card Interface [MultiMediaCard (MMC), Secure Digital (SD), Memory StickTM Complliant Products]
• For Low-Power Operation, A and B ports Are Placed in High-Impedance State When Either Supply Voltage Is Switched Off

59PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. RECOMMENDED OPERATING CONDITIONS AVCA 3.3V AVCA 2.5V AVCA 1.8V AVCA 1.5V UNIT I OH -8 -4 -2 -1 mA IOL 8421 m A IOH -16 -8 -4 -2 mA IOL 16 8 4 2 mA *IO_SD = 0 SWITCHING CHARACTERISTICS PARAMETER INPUT (FROM OUTPUT (TO) MAX or MIN AVCA VCCA 3.3V AVCA VCCA 2.5V AVCA VCCA 1.8V AVCA VCCA 1.5V tpd AB MAX 3.8 3.9 4.8 5.6 tpd BA MAX 5.2 5.2 5.6 6 tpd CLKB MAX 3.8 3.9 4.8 5.6 tpd CLK-f MAX 9 9.1 10.4 116 tpd CMDA CMDB MAX 3.8 3.9 4.8 5.6 tpd CMDB CMDA MAX 5.2 5.2 5.6 6 ten B MAX 5.9 6.1 6.9 7.7 ten A MAX 7.7 8.2 7.4 7 tdis B MAX 11.4 8.7 10.4 8.9 tdis A MAX 6.6 6.5 6.8 7 UNIT : ns PARAMETER INPUT (FROM OUTPUT (TO) MAX or MIN AVCA VCCA 3.3V AVCA VCCA 2.5V AVCA VCCA 1.8V AVCA VCCA 1.5V tpd AB MAX 3.1 3.5 4.4 5.2 tpd BA MAX 4.3 4.3 4.8 5.2 tpd CLKB MAX 3.1 3.5 4.4 5.2 tpd CLK-f MAX 7.4 7.8 9.1 10.4 tpd CMDA CMDB MAX 3.1 3.5 4.4 5.2 tpd CMDB CMDA MAX 4.3 4.3 4.8 5.2 ten B MAX 4.8 5.1 6 6.8 ten A MAX 5.3 5.1 5.2 4.7 tdis B MAX 8.2 8.2 9.5 8.4 tdis A MAX 7.6 7.5 7.9 7.7 UNIT : ns PARAMETER INPUT (FROM OUTPUT (TO) MAX or MIN AVCA VCCA 3.3V AVCA VCCA 2.5V AVCA VCCA 1.8V AVCA VCCA 1.5V tpd AB MAX 2.5 2.9 3.8 4.7 tpd BA MAX 3.2 3.3 3.9 4.4 tpd CLKB MAX 2.5 2.9 3.8 4.7 tpd CLK-f MAX 5.7 6.2 7.7 9.1 tpd CMDA CMDB MAX 2.5 2.9 3.8 4.7 tpd CMDB CMDA MAX 3.2 3.3 3.9 4.4 ten B MAX 3.6 3.9 4.8 5.7 ten A MAX 4.7 4.4 4.3 3.5 tdis B MAX 7.5 7.2 8.4 7.6 tdis A MAX 5.8 5.5 5.4 5.6 UNIT : ns VCCA = 1.5V CLKA MAX - - DIR CLKA DIR PARAMETER A port B port ICCB PARAMETER ICCA + ICCB AVCA VCCA = 3.3V VCCB = 0V AVCA VCCA = 0V VCCB = 3.3V -0.001 0.01 MAX or MIN MAX MAX 0.01 -0.001 AVCA VCCA = 1.2 to 3.3V VCCB = 1.2 to 3.3V DIR MAX or MIN DIR VCCA = 2.5V CLKA DIR DIR MAX MAX VCCA = 1.8V

60 : PREVIEW MAXIMUM FREQUENCY PARAMETER INPUT (FROM OUTPUT (TO) MAX or MIN AVCA VCCA 3.3V AVCA VCCA 2.5V AVCA VCCA 1.8V AVCA VCCA 1.5V INPUT (FROM OUTPUT (TO) MAX or MIN AVCA VCCA 3.3V AVCA VCCA 2.5V AVCA VCCA 1.8V AVCA VCCA 1.5V UNIT tpd AB MAX 2.3 2.7 3.6 4.5 CLKB 95 95 95 95 MHz tpd BA MAX 2.7 3 3.7 4.3 CLK-f 95 95 95 95 MHz tpd CLKB MAX 2.3 2.7 3.6 4.5 AB 9 5 95 95 95 MHz tpd CLK-f MAX 5 5.7 7.3 8.8 BA 9 5 95 95 95 MHz tpd CMDA CMDB MAX 2.3 2.7 3.6 4.5 tpd CMDB CMDA MAX 2.7 3 3.7 4.3 ten B MAX 3 3.4 4.3 5.1 ten A MAX 5.4 5.4 5.4 3.1 tdis B MAX 7.3 7 8.3 7.4 tdis A MAX 8 7.9 7.9 8.1 UNIT : ns OUTPUT SKEW VCCA INPUT (FROM OUTPUT (TO) MAX or MIN AVCA VCCA 3.3V AVCA VCCA 2.5V AVCA VCCA 1.8V AVCA VCCA 1.5V UNIT MIN MIN DIR tsk(o) PARAMETER VCCA = 3.3V CLKA DIR PARAMETER fmax Clock Data CLKA

61PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram DIR OE To Seven Other Channels MAX or MIN V CCA(V) V CCB(V) LVCC UNIT 3.6 0.05 mA 5.5 0.05 mA 3.6 0.05 mA 5.5 0.08 mA 2.3 -8 2.7 -12 3.3 -24 2.3 -8 2.7 -12 3.3 3.0 -24 2.3 8 2.7 12 3.3 24 2.3 8 2.7 12 3.3 3.0 24 PARAMETER A to BICCB 3.6MAX IOHA MAX 3.0IOLA MAX MAX 3.0 3.3IOHB MAX mA mA mA mA I CCA B to A MAX 3.6 3.3IOLB LVCC LVCC LVCC LVCC LVCC tPZL 13 8.1 8 .1 9.2 9.2 UNIT: ns MAX MAX MAX MAX MAX MAX OE A BOE OE OE A B A B B A OUTPUT MAX or MINPARAMETER INPUT ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS L DIR H OPERATION B data to A bus IsolationX OE L L H A data to B bus 3245 OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS

62 : PREVIEW Logic Diagram DIR OE To Seven Other Channels MAX or MIN LVC LVCC UNIT VCCA=5.5V VCCB=5.5V VCCA=5.5V VCCB=3.6V VCCA=5.5V VCCB=5.5V VCCA=5.5V VCCB=3.6V IOH -24 -24 IOL 24 24 IOH -12 -24 IOL 12 24 IOH -24 -24 IOL 24 24 mA mA mA mA mA PARAMETER VCCB=3.3V VCCB=2.7V VCCA=4.5V ICCA MAX MAX 0.08 0.08 MAX 0.05 0.08 MAX MAX 0.08 0.05 0.08 ICCB MAX mA mA MAX 0.05 UNIT: ns t PHL tPLH PARAMETER OE OE OE A INPUT OUTPUT OE B tPZH tPZL A AtPHL BtPLH tPZL tPHZ tPZH tPLZ tPHZ tPLZ B MAX or MIN MAX MAX MAX MAX MAX MAX B A LVCCLVC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS L DIR H OPERATION B data to A bus IsolationX OE L L H A data to B bus 4245 OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER WITH 3-STATE OUTPUTS (SN74LVC4245A) OCTAL DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS (SN74LVCC4245A)

63PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram SD07 SD00D07–D00 SD15 SD08 8 8 A10–A00 SA10 SA00 SRESETRESET 11 11 7 7 6 6 DIR_OUT D15–D08 8 8 SCD CE1, CE2, IORD, IOWR, OE, REG, WE BVD1, BVD2, INPACK , READY, WAIT, WP CD1 CD2 DIR(S/CF) ENL MASTER_EN ENH BUF_EN SCE1, SCE2, SIORD, SIOWR, SOE, SREG, SWE SBVD1, SBVD2, SINPACK, SREADY, SWAIT, SWP NOTE: R INT ≥ 100 kΩ To 7 Other Channels SIORD IN T SOE IN T SIORD–INT SOE I–INT R INT To 7 Other Channels To 7 Other Channels To 7 Other Channels T R A N S L A T I O N VCC_SD VCC_SD R INT VCC_SD R INT VCC_SVCC_CF VCC_S VCC_S R INT R INT VCC_S R INT VCC_CF 4320 LOW-POWER, DUAL-SUPPLY, LEVEL-TRANSLATING CompactFlashTM INTERFACE WITH 16-BIT DATA, 11-BIT ADDRESS, AND 13-BIT CONTROL LINES

• Designed to Optimize Power Savings in Portable Applications
• Matched Pinout with CompactFlashTM (CF) Connector Pin Configurations to Optimize PCB Layout
• Input-Disable Feature Allows Floating Input Conditions

64 : PREVIEW FUNCTION TABLES Lower 8-Bit Data Bus Transceivers (D07-D00, SD07-SD00) INPUTS MASTER_EN ENL DIR (S/CF) OPERATION LL H SD data to D bus LL LD data to SD bus LH X Isolation. D07-D00 and SD07-SD00 inputs can float. HX X Isolation, low power mode X = H or L MASTER_EN ENH DIR (S/CF) Upper 8-Bit Data Bus Transceivers (D15-D08, SD15-SD08) INPUTS OPERATION LL H SD data to D bus LL LD data to SD bus LH X Isolation. D15-D08 and SD15-SD08 inputs can float. HX X Isolation, low power mode X = H or L Address Bus Buffers INPUTS OUTPUT MASTER_EN BUF_EN SA A LL H H LL L L LH X Z. SA inputs can float. HX X Z, low power mode X = H or L Command Line Buffers (BVD1, BVD2, INPACK, OE, IORD, IOWR, READY, REG, CE1, CE2, WAIT, WE, WP, ) INPUTS OUTPUTMASTER_EN BUF_EN INPUT LL H H LL L L LH X Z. Command line buffer inputs can float. HX X Z, low power mode X = H or L Reset INPUTS OUTPUT MASTER_EN SRESET RESET LH H LL L HX Z, low power mode X = H or L DIR_OUT INPUTS OUTPUT BUF_EN MASTER_EN SOE SIORD DIR_OUT LL L L L LL LH H H L LL L L LL H H HL X XL XH XX Z, low power mode X = H or L

65PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. LV LV 3.3V LV 2.5V LV 1.8V UNIT 0.001 - - - mA 0.01 - - - mA - 0.003 0.003 0.003 mA - 0.003 0.003 0.003 mA - 0.036 0.036 0.036 mA - 0.003 0.003 0.003 mA - 0.003 0.003 0.003 mA - 0.06 0.06 0.06 mA IOH -12 -8 -4 -2 mA IOL 12 8 4 2 mA IOH -1 26 2 m A IOL -1 26 2 m A IOH 16 12 - - mA IOL 16 12 - - mA *IO_SD = 0 PARAMETER INPUT MAX or MIN VCC_SD LV LV 3.3V LV 2.5V LV 1.8V PARAMETER INPUT MAX or MIN VCC_CF LV VCC_S 3.3V LV VCC_S 2.5V LV VCC_S 1.8V tPLH 8.8 10 12.9 tPHL 8.8 10 12.9 tPLH 7 8.6 13.9 tPHL 7 8.6 13.9 tPZH 18.3 22.6 35.5 tPZL 18.3 22.6 35.5 tPZH 18.2 22.6 35.6 tPZL 18.2 22.6 35.6 tPHZ 13.2 14.5 25.1 tPLZ 13.2 14.5 25.1 tPHZ 18.2 14.5 23.3 tPLZ 18.2 14.5 23.3 tPZH 18.3 22.6 35.5 tPZL 18.3 22.6 35.5 tPZH 18.2 22.6 35.6 tPZL 18.2 22.6 35.6 tPHZ 12.3 14.5 24.2 tPLZ 12.3 14.5 24.2 tPHZ 12.4 14.2 22.8 tPLZ 12.4 14.2 22.8 tPLH 8.8 10 13.7 tPHL 8.8 10 13.7 tPLH 71 2.4 13.9 tPHL 71 2.4 13.9 tPLH 7.6 8.2 11.1 tPHL 7.6 8.2 11.1 tPLH 67 9.6 tPHL 67 9.6 UNIT : ns CD1 or CD2 CF input 3.3V MASTER_EN BUF_EN BUF_EN BUF_EN CF input MASTER_EN MASTER_EN MASTER_EN S output S output MAX MAX I CC_SD CD1 and CD2 = VCC_SD ICC_S* GND, Other = VCC_S GND, Other = VCC_CF MAX Inputs SD12-SD00, SA10-SA00, SCE1, SCE2, SIORD SIOWR, SOE, SREG, SWE CD1 or CD2 = GND, CD1 or CD2 = VCC_SD MAX MAX MAXControl inputs ( ENL, ENH, BUF_EN ) VCC_S SCD MAX MAX or MIN MAX MAX PARAMETER ICC_CF Input ( D15- D00 ) Input ( BVD1, BVD2, INPACK, READY, WAIT, WP ) VCC_CF 3.3V MAX MAX MAX Card detect System port CF port S output MAX OUTPUT S output S output MAX MAX OUTPUT 3.3V S output 5V MAX S output S output S output 3.3V 3.3V MAX MAX MAX MAX 5V DS D MAX 3.3V BUF_EN S output 5VDS D MAX SD D SD D MAX MAX 3.3V ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

66 : PREVIEW tPZH 21.4 23 27.9 tPZL 21.4 23 27.9 tPZH 20.3 21.8 31 tPZL 20.3 21.8 31 tPZH 18.3 22.6 36.3 tPZL 18.3 22.6 36.3 tPZH 18.2 22.6 36.2 tPZL 18.2 22.6 36.2 tPHZ 15 16.4 20.2 tPLZ 15 16.4 20.2 tPHZ 12.5 13.8 17.8 tPLZ 12.5 13.8 17.8 tPHZ 12 14.5 24.2 tPLZ 12 14.5 24.2 tPHZ 18.2 14.2 22.8 tPLZ 18.2 14.2 22.8 tPZH 21.4 22.8 27.2 tPZL 21.4 22.8 27.2 tPZH 20.3 21.6 27.8 tPZL 20.3 21.6 27.8 tPZH 18.3 22.6 35.5 tPZL 18.3 22.6 35.5 tPZH 18.2 22.6 35.6 tPZL 18.2 22.6 35.6 tPHZ 15 16.4 20.2 tPLZ 15 16.4 20.2 tPHZ 12 13.1 16.6 tPLZ 12 13.1 16.6 tPHZ 12 14.5 24.2 tPLZ 12 14.5 24.2 tPHZ 18.2 14.2 22.8 tPLZ 18.2 14.2 22.8 UNIT : ns MASTER_EN D MASTER_EN D MAX MAX 3.3V MASTER_EN SD MASTER_EN SD MAX MAX 3.3V MASTER_EN D MAX 3.3V MASTER_EN D MAX 5V MASTER_EN SD MAX 3.3V MASTER_EN SD MAX 5V D SD SD ENL or ENH ENL or ENH ENL or ENH ENL or ENH D MAX MAX MAX MAX 3.3V 3.3V ENL or ENH D MAX 3.3V ENL or ENH D MAX 5V ENL or ENH SD MAX 3.3V ENL or ENH SD MAX 5V PARAMETER INPUT MAX or MIN VCC_CF LV VCC_S 3.3V LV VCC_S 2.5V LV VCC_S 1.8V OUTPUT

67PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. MAX or MIN ALVC AVCA AVCAH AVCB AVCBH UNIT VCCA=3.6V VCCB=5.5V VCCA=2.3V VCCB=3.3V VCCA=3.6V VCCB=3.6V VCCA=3.6V VCCB=0V VCCA=0V VCCB=3.6V VCCA=2.7V VCCB=2.7V VCCA=1.6V VCCB=1.6V IOH -24 -12 -12 -12 -12 IOL 24 12 12 12 12 IOH -24 -12 -12 -12 -12 IOL 24 12 12 12 12 IOL 18 8888 IOH -- 2 - 2- 2- 2 IOL - 2222 mA mA mA mA mA mA mA mA mA MAXV CCB=3.3V PARAMETER mA VCCA=3.0V VCCA=2.3V MAX MAX MAXV CCA=1.4V 0.04 0.02 MAX MAX MAX MAX MAX MAX 0.04 -0.04 0.04 0.03 --- --- 0.04 0.04 0.04 -0.04 -0.04 -0.04 0.04 0.03 0.03 0.03 MAX I CC mA0.02- 0.02 0.02 0.02 0.04 0.04 ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS Logic Diagram To Seven Other Channels 1DIR 1A1 1B1 1OE To Seven Other Channels 2DIR 2A1 2B1 2OE 13FUNCTION TABLE (each 8-bit section) INPUTS L DIR OPERATION L OE H Isolation LH X B data to A bus A data to B bus 164245 16-BIT TRANSCEIVER AND 3.3-V TO 5-V SHIFTER WITH 3-STATE OUTPUTS

• SN74ALVC164245: A port has VCCA, which is set to operate at 2.5 V and 3.3 V B port has V CCB, which is set to operate at 3.3 V and 5 V
• SN74AVCB164245, SN74AVCBH164245: The A-port is designed to track VCCA, VCCA accepts any supply voltage from 1.4 V to 3.6 V The B-port is designed to track V CCB, VCCB accepts any supply voltage from 1.4 V to 3.6 V

68 : PREVIEW VCCB=3.3V V CCB=5.5V V CCB=5.5V VCCA=2.3V V CCA=2.7V V CCA=3.3V 7.6 5.9 5.9 6.7 6.7 9.3 9.3 10.2 10.2 9.2 9.2 9.0 9.0 5.8 7.6 5.8 7.6 5.8 7.6 5.8 11.5 8.9 11.5 8.9 12.3 9.1 12.3 9.1 10.5 9.5 10.5 9.5 9.3 8.6 9.3 8.6 V V UNIT: ns B A OUTPUT t PHL tPLH PARAMETER OE OE B ALVC OE OE tPZH tPZL A INPUT tPHL BtPLH tPZL tPHZ tPZH tPLZ tPHZ tPLZ A MAX or MIN MAX MAX MAX MAX MAX MAX A B AVCA/AVCAH AVCB/AVCBH PARAMETER INPUT OUTPUT MAX or MIN t PLH AB MAXtPHL tPLH BA MAXtPHL tPZL OE B MAXtPZH tPZL OE A MAXtPZH tPLZ OE B MAXtPHZ tPLZ OE A MAXtPHZ PARAMETER INPUT OUTPUT MAX or MIN tPLH AB MAXtPHL tPLH BA MAXtPHL tPZL OE B MAXtPZH tPZL OE A MAXtPZH tPLZ OE B MAXtPHZ tPLZ OE A MAXtPHZ SWITCHING CHARACTERISTICS

69PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. To Seven Other Channels 1DIR 1A1 1B1 1OE To Seven Other Channels 2DIR 2A1 2B1 2OE To Seven Other Channels 3DIR 3A1 3B1 3OE To Seven Other Channels 4DIR 4A1 4B1 4OE FUNCTION TABLE (each 8-bit section) INPUTS OPERAOE DIR OPERATION LL B data to A bus LH A data to B bus HX Isolation Logic Diagram 324245 32-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

70 : PREVIEW MAX or MIN AVCB UNIT VCCA=3.6V VCCB=3.6V VCCA=3.6V VCCB=0V VCCA=0V VCCB=3.6V VCCA=2.7V VCCB=2.7V VCCA=1.6V VCCB=1.6V IOH -12 IOL 12 IOH -12 IOL 12 IOH -8 IOL 8 IOH -2 IOL 2 0.04 MAX MAX MAXV CCA=1.4V PARAMETER MAXVCCB=3.3V VCCA=3.0V VCCA=2.3V mA mA mA mA mA mA mA mA mA I CC MAX 0.04 MAX MAX MAX MAX 0.08 -0.08 0.08 UNIT: ns A MAX or MIN MAX MAX MAX MAX MAX MAXt PHZ tPZH tPLZ tPHZ tPLZ B tPHL BtPLH tPZL tPZH tPZL A OE OUTPUT OE B A OE OE A INPUT B tPHL tPLH PARAMETER AVCB ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

LITTLE LOGIC GATE (AND/NAND/OR/NOR/EX-OR) Advanced CMOS Low-Voltage CMOS Low-Power CMOS AHC AHCT LVC AUC AUP

22 G 0 8 ●●

31 1 G 11 ● * OD 1G38 ● SCH 1G132 ● 2G00 ●● OD 2G38 ● SCH 2G132 31 1 G 10 ● *

22 G 3 2 ●●

31 1 G 332 ●

22 G 0 2 ●●

31 1 G 27 ●

11 G 8 6 ●●●●

22 G 8 6 ●●

31 1 G 386 ● POSITIVE AND-OR 31 1G0832 ● POSITIVE OR-AND 31 1G3208 ● Explanatory notes [Input] SCH: Schmitt-Trigger Inputs [Output] BUF: Buffered Output OC: Open-Collector Output 3S: 3-State Output LITTLE LOGIC GATE (INVERTER / NON-INVERTER) Advanced CMOS Low-Voltage CMOS Low-Power CMOS AHC AHCT LVC AUC AUP UBF 1GU04 ●● ● UBF/BUF 1GX04 ● OC 1G06 ●●● BUF 2G04 ●● UBF 2GU04 ●● OC 2G06 ●● SCH 2G14 ● * BUF 3G04 ● UBF 3GU04 ● OC 3G06 ● SCH 3G14 ● OC 1G07 ●●● SCH 1G17 ●●● BUF 1G34 ●● OC 2G07 ●● SCH 2G17 ● BUF 2G34 ●● OC 3G07 ● SCH 3G17 ● BUF 3G34 ● NON-INVERTING 1 Curcuit Curcuit No. of Input POSITIVE AND INVERTING Description No. of Input EXCLUSIVE OR Technology Technology Input Output Device Input POSITIVE OR Output DeviceDescription POSITIVE NOR POSITIVE NAND Status ●: Product available in technology indicated *: New product planned in technology indicated Explanatory notes [Input] SCH: Schmitt-Trigger Inputs [Output] BUF: Buffered Output OC: Open-Collector Output 3S: 3-State Output Status ●: Product available in technology indicated *: New product planned in technology indicated

LITTLE LOGIC BUFFER/DRIVER Advanced CMOS Low-Voltage CMOS Low-Power CMOS AHC AHCT LVC AUC AUP 2G125 ●● 2G126 ●● 2G241 ●● 1G240 ●●● 2G240 ●● LITTLE LOGIC LATCH Advanced CMOS Low-Voltage CMOS Low-Power CMOS AHC AHCT LVC AUC AUP 3S Q 373 ● Explanatory notes [Type] S-R: S-R Latch AD: Addressable Latch BIS: Bistable Latch R-B: Read-Back Latch D: D-Type Transparent Latch LITTLE LOGIC D-TYPE FLIP-FLOP Advanced CMOS Low-Voltage CMOS Low-Power CMOS AHC AHCT LVC AUC AUP SB 2 SB1 G 7 4 ●● S2 S Q 1G79 ●●● S2 S Q 1G80 ●●● C2 S Q 1G175 ● 3S Q 1G374 ● SB 2 SB2 G 7 4 ● D2 S Q 2G79 ●● D2 S Q 2G80 ●● Explanatory notes [Trigger] POS: POSITIVE EDGE, NEG: NEGATIVE EDGE [PRE • CLR] B: Preset and Clear, C: Clear only [Edge] S: Single Edge Triggered, D: Dual Edge Triggered [Output] 2S: Totem pole Output 3S: 3-State Output [Q • Q] B: Q • Q-Output Q: Q-Output Q: Q-Output Explanatory notes [CLR] C: With Clear [Retrigger] R: With Retrigger Status ●: Product available in technology indicated *: New product planned in technology indicated Status ●: Product available in technology indicated *: New product planned in technology indicated Status ●: Product available in technology indicated *: New product planned in technology indicated LITTLE LOGIC DATA SELECTOR/MULTIPLEXER Advanced CMOS Low-Voltage CMOS Low-Power CMOS AHC AHCT LVC AUC AUP 1G18 ● 2G157 ● Explanatory notes [Output] 2S: Totem Pole Output 3S: 3-State Output OC: Open-Collector Output Explanatory notes [Output] 3S: 3-State Output R3S: Series Resistor and 3-State output OC: Open-Collector Output LITTLE LOGIC MONOSTABLE MULTIVIBRATOR Advanced CMOS Low-Voltage CMOS Low-Power CMOS AHC AHCT LVC AUC AUP 1G123 ● Output Trigger Curcuit PRE • CLR Q • Q Type Curcuit DeviceCurcuit 2S 1 3S 1 INVERTING Output No. of Input/Output Device Device Output Output Technology Technology Technology 1C 1 Curcuit CLR Retrigger Device Device Technology Technology D POS 1 Edge PRE · CLR Q · Q

LITTLE LOGIC DECODER/DEMULTIPLEXER Advanced CMOS Low-Voltage CMOS Low-Power CMOS AHC AHCT LVC AUC AUP 1G19 ● ● 1G29 ● 1G139 ● Explanatory notes [Output] 2S: Totem Pole Output 3S: 3-State Output OC: Open-Collector Output LITTLE LOGIC ANALOG SWITCH Advanced CMOS Low-Voltage CMOS Low-Power CMOS AHC AHCT LVC AUC AUP 1G3157 ● 2G53 ●● 1G66 ●● 2G66 ●● LITTLE LOGIC MULTIFUNCTION GATE Advanced CMOS Low-Voltage CMOS Low-Power CMOS AHC AHCT LVC AUC AUP 2/4 2S 1 DUAL ANALOG MULTIPLEXER/DEMULTIPLEXER TypeDescription SINGLE BILATERAL ANALOG SWITCH DUAL ANALOG MULTIPLEXER/DEMULTIPLEXER Type DUAL BILATERAL ANALOG SWITCH CONFIGURABLE MULTI-FUNCTION GATE Input 3 1G57 AND gate with one inverted input CONFIGURABLE MULTI-FUNCTION GATE 3 1G98 NAND gate with one inverted input OR gate with one inverted input AND gate/ AND with both inputs inverted NAND with inverted input OR with inverted input AND with inverted input NOR gate / NOR with both inputs inverted XNOR 1G58 2-to-1 data selector CONFIGURABLE MULTI-FUNCTION GATE 3 1G97 OR gate / OR with both inputs inverted NOR with inverted input XOR gate AND gate OR gate with one inverted input CONFIGURABLE MULTI-FUNCTION GATE NAND gate with one inverted input AND gate with one inverted input NAND gate, NAND with both inputs inverted NOR gate with one inverted input OR gate Inverter NOR gate with one inverted input Noninverted buffer 2-to-1 data selector with inverted output NAND gate 3-state 2-input XOR 3-state 2-input XNOR COMPLEMENTARY FUNCTION NOR gate Noninverted buffer Inverter 3-state 2-input AND, both inputs inverted 3-state 2-input NAND ULTRA-CONFIGURABLE MULTI-FUNCTION GATE 3-state buffer 3-state inverter PRIMARY FUNCTION 3-state 2-input NAND, both inputs inverted

• 3-state 2-input NAND, one input inverted 3-state 2-in-1 data selector MUX 3-state 2-in-1 data selector MUX, inverted out 3-state 2-input AND 3-state 2-input AND, one input inverted Technology Technology 1G994 3-state 2-input XOR, one input inverted 3-state 2-input NOR 3-state 2-input NOR, one input inverted 3-state 2-input NOR, both inputs inverted 3-state 2-input OR 3-state 2-input OR, one input inverted 3-state 2-input OR, both inputs inverted 2S 1 Technology 1/1 2S 1 No. of Input/Output Output Curcuit Type Status ●: Product available in technology indicated *: New product planned in technology indicated Status ●: Product available in technology indicated *: New product planned in technology indicated Status ●: Product available in technology indicated *: New product planned in technology indicated

Y GND VCC X2 123 AB GND VCC Y 123 NC A GND VCC Y 123 NC A GND VCC Y 123 AB G N D VCC Y 123 NC A GND VCC Y 123 AB GND VCC Y 123 NC A GND VCC Y Pin Assignments See page 91 See page 91 See page 92 See page 92 See page 94 See page 94 See page 95 1G00 SINGLE 2-INPUT POSITIVE-NAND GATE Y = AB 1G06 SINGLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT 1G02 SINGLE 2-INPUT POSITIVE-NOR GATE Y = A + B 1G07 SINGLE BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT 1G04 SINGLE INVERTER GATE Y = A 1G08 SINGLE 2-INPUT POSITIVE-AND GATE Y = A • B 1GU04 SINGLE INVERTER Y = A NC-No internal connection NC-No internal connectionNC-No internal connection NC-No internal connection 1GX04 CRYSTAL OSCILLATOR DRIVER See page 93 NC-No internal connection

C VCC Y 123 A GND VCC Y1 E 123 NC A GND VCC Y 123 AB GND C VCC Y 123 NC A GND VCC Y 123 S GND A VCC Y1 Pin Assignments See page 96 See page 96 See page 97 See page 97 See page 98 See page 98 1G11 SINGLE 3-INPUT POSITIVE-AND GATE Y = A • B • C 1G19 1-OF-2 DECODER/DEMULTIPLEXER 1G14 SINGLE SCHMITT-TRIGGER INVERTER GATE Y = A 1G27 3-INPUT POSITIVE-NOR GATE Y = A + B + C 1G17 SINGLE SCHMITT-TRIGGER BUFFER Y = A 1G18 1-OF-2 NONINVERTING DEMULTIPLEXER WITH 3-STATE DESELECTED OUTPUT NC-No internal connection NC-No internal connection 123 AB GND A VCC Y 1G10 SINGLE 3-INPUT POSITIVE-NAND GATE Y = A • B • C See page 95 G VCC GND 1G29 2-OF-3 DECODER/DEMULTIPLEXER See page 99

C 123 D D CLK CK GND VCC Q Q In1 GND VCC Y In0 In2 Pin Assignments See page 102 See page 102 See page 104 1G58 CONFIGURABLE MULTIPLE-FUNCTION GATE 1G66 SINGLE BILATERAL ANALOG SWITCH 1G79 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP 123 AB GND VCC Y In1 GND VCC Y In0 In2 See page 100 See page 101 1G32 SINGLE 2-INPUT POSITIVE-OR GATE Y = A + B 1G57 CONFIGURABLE MULTIPLE-FUNCTION GATE 123 NC A GND VCC Y 1G34 SINGLE BUFFER GATE Y = A 123 A GNDB VCC Y 1G38 SINGLE 2-INPUT NAND GATE WITH OPEN-DRAIN OUTPUT Y = A•B or Y = A + B See page 101 CLR PRED CK Q Q CLK VCC GND Q Q CLR D PRE 1G74 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET See page 103 See page 100 NC-No internal connection

Y = A 123 IN1 GND I N0 IN2 VCC Y 123 IN1 GND I N0 IN2 VCC Y 123 D CLK GND VCC Q Q D CK 123 AB GND VCC Y 123 OE A GND VCC Y See page 105 See page 106 See page 106 See page 107 See page 110 1G86 SINGLE 2-INPUT EXCLUSIVE-OR GATE Y = A ≈ B 1G97 CONFIGURABLE MULTIPLE-FUNCTION GATE 1G98 CONFIGURABLE MULTIPLE-FUNCTION GATE 1G80 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP 1G125 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT Y = A OE VCC GND C B D A Y 1G99 SINGLE RETRIGGERABLE MONOSTABLE MULTIVIBRATOR WITH SCHMITT-TRIGGER INPUTS See page 108 OE VCC GND C B D A Y 1G123 SINGLE RETRIGGERABLE MONOSTABLE MULTIVIBRATOR WITH SCHMITT-TRIGGER INPUTS See page 109

A VCC Y 123 AB GND C VCC Y See page 114 See page 114 See page 117 1G240 SINGLE BUFFER/DRIVER WITH 3-STATE OUTPUT 1G332 SINGLE 3-INPUT POSITIVE-OR GATE Y = A + B + C 1G386 SINGLE 3-INPUT EXCLUSIVE-XOR GATE Y = A ≈ B ≈ C 123 AB GND VCC Y See page 111 1G132 SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS Y = A•B or Y = A + B A VCC GND B See page 112 1G139 2-TO-4 LINE DECODER CLK CLR GND VCC Q D D R See page 113 1G175 SINGLE D-TYPE FLIP-FLOP WITH ASYNCHRONOUS CLEAR Q C D 123 64 5 LE GND D OE V CC Q See page 115 1G373 SINGLE D-TYPE LATCH WITH 3-STATE OUTPUT QC1 D 123 64 5 CLK GND D OE V CC Q See page 116 1G374 SINGLE D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT

DUAL INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS 2GU04 DUAL INVERTER GATE Y = A 123 1A GND 2A VCC 2Y B2 GND VCC A S 12 4 1A 1B GND VCC 1Y 2A 12 4 1A 1B GND VCC 1Y 2A See page 118 See page 120 See page 120 1G3157 SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH 2G00 DUAL 2-INPUT POSITIVE-NAND GATE Y = A • B 2G02 DUAL 2-INPUT POSITIVE-NOR GATE Y = A + B See page 121 2G04 DUAL INVERTER GATE Y = A 123 GND C A VCC Y B See page 117 1G0832 SINGLE 3-INPUT POSITIVE AND-OR GATE Y = (A•B) + C 123 GND C A VCC Y B See page 119 1G3208 SINGLE 3-INPUT POSITIVE OR-AND GATE Y = (A + B) • C

SINGLE-POLE DOUBLE-THROW (SPDT) ANALOG SWITCH OR 2:1 ANALOG MULTIPLEXER/DEMULTIPLEXER See page 126 123 1A GND 2A VCC 2Y 12 4 1A 1B GND VCC 1Y 2A See page 122 See page 123 2G07 DUAL BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS 2G08 DUAL 2-INPUT POSITIVE-AND GATE Y = A • B 123 1A GND 2A VCC 2Y 123 1A GND 2A VCC 2Y 123 1A GND 2A VCC 2Y 12 4 1A 1B GND VCC 1Y 2A See page 124 See page 124 See page 125 2G14 DUAL INVERTER GATE Y = A 2G32 DUAL 2-INPUT POSITIVE-OR GATE Y = A + B 2G17 DUAL SCHMITT-TRIGGER BUFFER Y = A 2G34 DUAL INVERTER GATE Y = A See page 123 12 4 1A 1B GND VCC 1Y 2A See page 125 2G38 SINGLE 2-INPUT NAND GATE WITH OPEN-DRAIN OUTPUT Y = A•B or Y = A + B

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP See page 129 12 4 1A 1B GND VCC 1C 2A 12 4 1A 1B GND VCC 1Y 2A 12 4 1OE 1A GND VCC 2A 2OE 12 4 1OE 1A GND VCC 2A 2OE 12 4 CLK CK D D GND VCC Q Q Q CLR Q PRE PRE CLR VCC 1Q 2CLK 12 4 1CLK 1D GND 2Q TG TG TG TG TG TG TG TG See page 130 2G125 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS 2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS See page 126 See page 127 See page 130 2G74 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET 2G79 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP 2G66 DUAL BILATERAL ANALOG SWITCH 2G86 DUAL 2-INPUT EXCLUSIVE-OR GATE Y = A ≈ B See page 131See page 128 2G132 SINGLE 2-INPUT NAND GATE WITH OPEN-DRAIN OUTPUT Y = A•B or Y = A + B See page 131

DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS See page 133 12 4 1A 3Y GND VCC 1Y 2Y See page 134 3G04 TRIPLE INVERTER GATE Y = A Pin Assignments 12 4 AB GND VCC Y Y A/B G See page 132 2G157 SINGLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER 2G240 DUAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 12 4 1A 3Y GND VCC 1Y 2Y 12 4 1A 3Y GND VCC 1Y 2Y 12 4 1A 3Y GND VCC 1Y 2Y See page 135 See page 135 See page 136 3G14 TRIPLE SCHMITT-TRIGGER INVERTER Y = A 3G06 TRIPLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS 3G07 TRIPLE BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS 12 4 1A 3Y GND VCC 1Y 2Y 3GU04 TRIPLE INVERTER GATE Y = A See page 134

Y = A See page 137 12 4 1A 3Y GND VCC 1Y 2Y See page 136 3G17 TRIPLE SCHMITT-TRIGGER BUFFER Y = A

91PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 1G00 SINGLE 2-INPUT POSITIVE-NAND GATE

• Y = A•B 1G02 SINGLE 2-INPUT POSITIVE-NOR GATE
• Y = A + B B Y Logic Diagram INPUTS L BA L OUTPUT Y L H X X HH H FUNCTION TABLE A B Y Logic Diagram (positive logic) INPUTS BA L OUTPUT Y H L X XH H L L FUNCTION TABLE ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN AHC AHCT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V IOH MAX -8 -8 -32 -24 -8 -4 -9 -8 IOL MAX 8 8 32 24 8 4 98 SWITCHING CHARACTERISTICS PARAMETER INPUT AHC AHCT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V tPLH 8.5 9 4 4.7 5.5 9 2 2.2 tPHL 8.5 9 4 4.7 5.5 9 2 2.2 UNIT:ns A or B OUTPUT Y MAX or MIN MAX AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V UNIT 0.0009 0.0009 0.0009 0.0009 mA 43 . 1 1 . 91 . 1m A AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V 5.2 6.8 9.8 18.8 5.2 6.8 9.8 18.8 ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN AHC AHCT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V IOH MAX -8 -8 -32 -24 -8 -4 -9 -8 IOL MAX 88 3 2 2 4 8498 SWITCHING CHARACTERISTICS PARAMETER INPUT AHC AHCT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT:ns A or B OUTPUT Y MAX or MIN MAX AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V UNIT 0.0009 0.0009 0.0009 0.0009 mA 43 . 1 1 . 91 . 1m A AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V 56 . 5 9 . 5 17.9 56 . 5 9 . 5 17.9

92 : PREVIEW AY 24 A Y13 5pin Package 4pin Package Logic Diagram OUTPUT Y INPUT A H LH L FUNCTION TABLE 1G04 SINGLE INVERTER GATE

• Y = A AY 24 A Y13 5pin Package 4pin Package Logic Diagram OUTPUT Y INPUT A LH LH FUNCTION TABLE 1GU04 SINGLE INVERTER GATE
• Y = A
• Unbuffered Output
• Supply Voltage Renge : 2V to 5.5V ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN AHC AHCT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V IOH MAX -8 -8 -32 -24 -8 -4 -9 -8 IOL MAX 8 8 32 24 8 4 98 SWITCHING CHARACTERISTICS PARAMETER INPUT AHC AHCT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT:ns A OUTPUT Y MAX or MIN MAX AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V UNIT 0.0009 0.0009 0.0009 0.0009 mA 43 . 1 1 . 91 . 1m A AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V 4.5 5.6 7.9 15 4.5 5.6 7.9 15 ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN AHC LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT IOH MAX -8 -32 -24 -8 -4 -9 -8 mA IOL MAX 83 22 4 8498 m A SWITCHING CHARACTERISTICS PARAMETER INPUT AHC LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V tPLH 83 3 . 7 45 2.1 2.4 tPHL 83 3 . 7 45 2.1 2.4 UNIT:ns A OUTPUT Y MAX or MIN MAX

93PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 1GX04 CRYSTAL OSCILLATOR DRIVER

• One Unbuffered Inverter (1GU04)
• One Buffered Inverter (1G04)
• Suitable for Commonly Used Clock Frequencies
• Optimized for Use in Crystal Oscillator Applications X1 X2 3 4 Y Logic Diagram ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT ICC MAX 0.01 0.01 0.01 0.01 mA IOH MAX -32 -24 -8 -4 mA IOL MAX 32 24 8 4 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 3 3.7 4 7 tPHL 3 3.7 4 7 tPLH 5 7.8 7.4 18 tPHL 5 7.8 7.4 18 UNIT : ns *X2 : no external load X1 X2 MAX X1 Y* MAX INPUTS H YX2 OUTPUT H L HL L FUNCTION TABLE

94 : PREVIEW AY 24 A Y13 5pin Package 4pin Package Logic Diagram OUTPUT Y INPUT A H LH L FUNCTION TABLE 1G06 SINGLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT AY 24 A Y13 5pin Package 4pin Package Logic Diagram OUTPUT Y INPUT A H L H L FUNCTION TABLE 1G07 SINGLE BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V IOL MAX 32 24 8 498 SWITCHING CHARACTERISTICS PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V tPLH 344 6.5 1.8 2.5 tPHL 344 6.5 1.8 2.5 UNIT:ns A OUTPUT MAX or MIN Y MAX AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V UNIT 0.0009 0.0009 0.0009 0.0009 mA 3.6 3.6 3.6 3.6 V 43 . 1 1 . 91 . 1m A AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V 4.9 4.5 6.7 14.1 4.9 4.5 6.7 14.1 ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V IOL MAX 32 24 8498 SWITCHING CHARACTERISTICS PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT:ns AY MAX OUTPUT MAX or MIN AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V UNIT 0.0009 0.0009 0.0009 0.0009 mA 3.6 3.6 3.6 3.6 V 43 . 1 1 . 91 . 1m A AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V 4.5 4.8 7.1 16.2 4.5 4.8 7.1 16.2

95PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. B Y 3 4A B Y Logic Diagram INPUTS L BA L OUTPUT Y H L X X HH L FUNCTION TABLE 1G08 SINGLE 2-INPUT POSITIVE-AND GATE

• Y = A•B ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN AHC AHCT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V IOH MAX -8 -8 -32 -24 -8 -4 -9 -8 IOL MAX 8 8 32 24 8 4 98 SWITCHING CHARACTERISTICS PARAMETER INPUT AHC AHCT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V tPLH 994 4 . 5 5.5 8 22 . 4 tPHL 994 4 . 5 5.5 8 2 2.4 UNIT:ns A or B OUTPUT Y MAX or MIN MAX AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V UNIT 0.0009 0.0009 0.0009 0.0009 mA 43 . 1 1 . 91 . 1 m A AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V 4.7 6.1 9 17.2 4.7 6.1 9 17.2 Logic Diagram1G10 SINGLE 3-INPUT POSITIVE-NAND GATE
• Y = A•B•C ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT IOH MAX -32 -24 -8 -4 -9 -8 mA IOL MAX 32 24 8 4 98 m A SWITCHING CHARACTERISTICS PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V tPLH 3.6 5.0 6.5 18.0 TBD TBD tPHL 3.6 5.0 6.5 18.0 TBD TBD UNIT:ns A, B or C OUTPUT MAX or MIN Y MAX FUNCTION TABLE INPUTS OUTPUT ABC Y HHH L LX H XL H XX H X X L

96 : PREVIEW 3 4A B Y AY 24 A Y13 5pin Package 4pin Package Logic Diagram OUTPUT Y INPUT A LH L H FUNCTION TABLE 1G14 SINGLE SCHMITT-TRIGGER INVERTER GATE

• Y = A ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN AHC AHCT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V IOH MAX -8 -8 -32 -24 -8 -4 -9 -8 IOL MAX 8 8 32 24 8 4 98 SWITCHING CHARACTERISTICS PARAMETER INPUT AHC AHCT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V tPLH 12 9 5 5.5 6.5 11 2.5 2.5 tPHL 12 9 5 5.5 6.5 11 2.5 2.5 UNIT:ns MAX or MIN Y MAXA OUTPUT AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V UNIT 0.0009 0.0009 0.0009 0.0009 mA 43 . 1 1 . 91 . 1m A AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V 5.6 6.8 9.5 16.7 5.6 6.8 9.5 16.7 Logic Diagram1G11 SINGLE 3-INPUT POSITIVE-AND GATE
• Y = A•B•C ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT IOH MAX -32 -24 -8 -4 -9 -8 mA IOL MAX 32 24 8 4 98 m A SWITCHING CHARACTERISTICS PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V tPLH 3.5 4.9 6.2 17.2 TBD TBD tPHL 3.5 4.9 6.2 17.2 TBD TBD UNIT:ns A, B or C MAX OUTPUT MAX or MIN Y FUNCTION TABLE INPUTS OUTPUT ABC Y HHH H LX L XL L XX L X X L

97PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. AY 24 A Y13 5pin Package 4pin Package Logic Diagram OUTPUT Y INPUT A H L H L FUNCTION TABLE 1G17 SINGLE SCHMITT-TRIGGER BUFFER

• Y = A AY 13 S 1 Y06 Logic Diagram FUNCTION TABLE INPUTS S ZH L L H A H L LL H Z H H L Z Z OUTPUTS Y1Y0 1G18 1-OF-2 NONINVERTING DEMULTIPLEXER WITH 3-STATE DESELECTED OUTPUT ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V IOH MAX -32 -24 -8 -4 -9 -8 IOL MAX 32 24 8 4 98 SWITCHING CHARACTERISTICS PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V tPLH 55 . 5 6.5 11 2.5 2.4 tPHL 55 . 5 6.5 11 2.5 2.4 UNIT:ns MAX OUTPUT MAX or MIN YA AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V UNIT 0.0009 0.0009 0.0009 0.0009 mA 43 . 1 1 . 91 . 1 m A AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V 5.7 6.8 9 15.6 5.7 6.8 9 15.6 ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT ICC MAX 0.01 0.01 0.01 0.01 mA IOH MAX -32 -24 -8 -4 mA IOL MAX 32 24 8 4 mA SWITCHING CHARACTERISTICS PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 3.2 4.2 5 9.3 tPHL 3.2 4.2 5 9.3 tPZL 3.4 4.6 5.6 10.2 tPZH 3.4 4.6 5.6 10.2 tPLZ 3.3 4.9 5.3 12.7 tPHZ 3.3 4.9 5.3 12.7 UNIT:ns A S S OUTPUT Y Y Y MAX or MIN MAX MAX MAX

98 : PREVIEW E Y13 Y06A 1 Logic Diagram FUNCTION TABLE INPUTS OUTPUTS E AY 0 Y 1 LL LH LH H L HX H H FUNCTION TABLE INPUTS OUTPUT ABC Y HXX L XH L XX L LL H X H L 1G19 1-OF-2 DECODER/DEMULTIPLEXER ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT ICC MAX 0.01 0.01 0.01 0.01 mA IOH MAX -32 -24 -8 -4 mA IOL MAX 32 24 8 4 AUC 2.5V 0.01 AUC 1.8V 0.01 8mA SWITCHING CHARACTERISTICS PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 3.9 5.2 6.5 16.1 tPHL 3.9 5.2 6.5 16.1 AUC 2.5V 2.0 2.0 AUC 1.8V 2.8 2.8 UNIT:ns OUTPUT MAX or MIN A or E Y MAX Y4A 1 B 3 C 6 Logic Diagram1G27 SINGLE 3-INPUT POSITIVE-NOR GATE

• Y = A + B + C ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT ICC MAX 0.01 0.01 0.01 0.01 mA IOH MAX -32 -24 -8 -4 mA IOL MAX 32 24 8 4 mA SWITCHING CHARACTERISTICS PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 3.6 5.4 7.1 20.5 tPHL 3.6 5.4 7.1 20.5 UNIT:ns OUTPUT MAX or MIN A, B or C Y MAX

99PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 1G29 2-OF-3 DECODER/DEMULTIPLEXER FUNCTION TABLE INPUTS OUTPUTS GA 1 A 0 LL X LH LH HX L H X Y0 Y1 Y2 LH H HL HH HH H L H G A1 6 Y12 Y25 Logic Diagram ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT ICC MAX 0.01 0.01 0.01 0.01 mA IOH MAX -32 -24 -8 -4 mA IOL MAX 32 24 8 4 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 5.1 6.1 7.5 15.8 tPHL 5.1 6.1 7.5 15.8 UNIT : ns Y MAXA or G

100 : PREVIEW B Y Logic Diagram INPUTS BA L OUTPUT Y L H X XH H L H FUNCTION TABLE 1G32 SINGLE 2-INPUT POSITIVE-OR GATE

• Y = A + B ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN AHC AHCT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V IOH MAX -8 -8 -32 -24 -8 -4 -9 -8 IOL MAX 8 8 32 24 8498 SWITCHING CHARACTERISTICS PARAMETER INPUT AHC AHCT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT:ns A or B OUTPUT Y MAX or MIN MAX AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V UNIT 0.0009 0.0009 0.0009 0.0009 mA 43 . 1 1 . 91 . 1 m A AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V 56 . 6 9 . 6 18.4 56 . 6 9 . 6 18.4 AY 24 A Y13 5pin Package 4pin Package Logic Diagram OUTPUT Y INPUT A H L H L FUNCTION TABLE 1G34 SINGLE BUFFER GATE
• Y = A ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT ICC MAX 0.001 0.001 0.001 0.001 mA IOH MAX -32 -24 -8 -4 mA IOL MAX 32 24 8 4 AUP 3.3V 0.009 AUP 2.5V 0.009 -3.1 3.1 AUP 1.8V 0.009 -1.9 1.9 AUP 1.1V 0.009 -1.1 1.1 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 3.2 4.1 4.4 8.6 tPHL 3.2 4.1 4.4 8.6 AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V 4.8 5.8 8.3 15.4 4.8 5.8 8.3 15.4 UNIT : ns AY MAX

101PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 6In2 In1 In0 4 Y Logic Diagram FUNCTION SELECTION TABLE FUNCTION TABLE INPUTS OUTPUT In2 In1 In0 Y LLL H LL L LH H LH L HL L HL L HH H L H L H LH HHH H 1G57 CONFIGURABLE MULTIPLE-FUNCTION GATE ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V ICC MAX 0.01 0.01 0.01 0.01 IOH MAX -32 -24 -8 -4 IOL MAX 32 24 8 4 SWITCHING CHARACTERISTICS PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 5.1 6.3 8.3 14.4 tPHL 5.1 6.3 8.3 14.4 UNIT:ns Any In OUTPUT MAX or MIN Y MAX AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V UNIT 0.0009 0.0009 0.0009 0.0009 mA 43 . 1 1 . 91 . 1 m A AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V 6.1 7.3 10 18.1 6.1 7.3 10 18.1 2-input AND 2-input AND with both inputs inverted 2-input NAND with inverted input 2-input OR with inverted input 2-input NOR 2-input NOR with both inputs inverted 2-input XNOR 1G38 SINGLE 2-INPUT NAND GATE WITH OPEN-DRAIN OUTPUT

• Y = A•B or Y = A + B INPUTS BA L OUTPUT Y H H L LH L H HLH H FUNCTION TABLE A B Y Logic Diagram ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT ICC MAX 0.01 0.01 0.01 0.01 mA VO MAX 5.5 5.5 5.5 5.5 mA IOL MAX 32 24 8 4 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 3.9 4.5 6 10 tPHL 3.9 4.5 6 10 UNIT : ns A or B Y MAX

102 : PREVIEW B C A Logic Diagram SWITCHI CONTROL INPUT (C) ON OFFL H FUNCTION TABLE 1G66 SINGLE BILATERAL ANALOG SWITCH

• High On-Off Outputs Voltage Ratio
• High Degree of Linearity 6In2 In1 In0 4 Y Logic Diagram FUNCTION TABLE INPUTS OUTPUT In2 In1 In0 Y LLL L LL H LH L LH H HL H HL H HH H L H L H LL HHH L 1G58 CONFIGURABLE MULTIPLE-FUNCTION GATE ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V ICC MAX 0.01 0.01 0.01 0.01 IOH MAX -32 -24 -8 -4 IOL MAX 32 24 8 4 SWITCHING CHARACTERISTICS PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 5.1 6.3 8.3 14.4 tPHL 5.1 6.3 8.3 14.4 UNIT:ns MAXYAny In OUTPUT MAX or MIN AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V UNIT 0.0009 0.0009 0.0009 0.0009 mA 43 . 1 1 . 91 . 1 m A AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V 6.3 7.6 10.2 19 6.3 7.6 10.2 19 ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT RON MAX 10 15 20 30 15 20 Ω RON(P) MAX 15 20 30 120 20 80 Ω SWITCHING CHARACTERISTICS PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V tPZH 4.2 5 6.5 12 1.4 2.3 tPZL 4.2 5 6.5 12 1.4 2.3 tPHZ 56 . 5 6.9 10 1.5 2.9 tPLZ 56 . 5 6.9 10 1.5 2.9 UNIT : ns CB o r A MAX MAX MAX A or B OUTPUT C MAX or MIN B or A B or A FUNCTION SELECTION TABLE 2-input AND with inverted input 2-input NAND 2-input NAND with both inputs inverted 2-input OR 2-input OR with both inputs inverted 2-input NOR with inverted input 2-input XOR

103PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 1G74 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET Logic Diagram PRE QCLR INPUTS L DQCLK H X OUTPUTS LX H X X X L HH LH H LH X Q0H L H H H L H L FUNCTION TABLE ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS MAX or MIN AUC 2.5V AUC 1.8V AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V AUC 2.5V AUC 1.8V AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V UNIT MAX 9 8 4 3.1 1.9 1.1 mA TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS MAX or MIN MIN 275 250 160 130 60 50 MIN 11 2222 low MIN 11 2222 low MIN 0.4 0.5 111 1 . 2 t h MIN 0.3 0.3 0000 UNIT fmax : MHz other : ns Hold time, data after CLK ↑ fmax ICC IOH IOL tsu Setup time, before CLK ↑ CLK PRE or CLR PRE or CLR PARAMETER PARAMETER INPUT tw Pulse duration OUTPUT Data MAX MAX CLK PRE or CLR Q Q or Q CLK Q MAX TG C C TG C C TG C C C TG C C CLR CLK D PRE Q Q C

104 : PREVIEW C C CLK 2 Logic Diagram INPUTS OUTPUT D Q L X L H H CLK L FUNCTION TABLE 1G79 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V IOH MAX -32 -24 -8 -4 -9 -8 IOL MAX 32 24 8498 TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS PARAMETER I NPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V fmax 160 160 160 160 275 250 t PLH 4.5 5 7 9.9 1.8 2.4 tPHL 4.5 5 7 9.9 1.8 2.4 UNIT fmax : MHz other : ns CLK high or low MIN MIN OUTPUT MAX or MIN tsu CLK MAX Q Before CLK ↑ , Data high Before CLK ↑ , Data low Data after CLK ↑ MIN MIN AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V UNIT 0.0009 0.0009 0.0009 0.0009 mA 43 . 1 1 . 91 . 1 m A AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V 260 250 240 160 1.9 1.7 1.6 2.2 0.6 0.7 0.9 1.4 11 1 . 1 1 . 8 0000 4.5 5.7 8 14.4 4.5 5.7 8 14.4 C C TG C C TG C C C D Q C TG TG1

105PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. C C CLK 2 Logic Diagram INPUTS OUTPUT D Q L X LH H CLK L FUNCTION TABLE 1G80 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V IOH MAX -32 -24 -8 -4 -9 -8 IOL MAX 32 24 8498 TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS PARAMETER I NPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V fmax 160 160 160 160 275 250 t UNIT fmax : MHz other : ns tsu Before CLK ↑ , Data high Before CLK ↑ , Data low Data after CLK ↑ QCLK MIN OUTPUT MAX or MIN CLK high or low MIN MIN MAX MIN AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V UNIT 0.0009 0.0009 0.0009 0.0009 mA 43 . 1 1 . 91 . 1 m A AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V 260 250 240 170 1.9 1.7 1.6 2.5 0.4 0.6 0.8 1.2 0.7 0.8 1.1 2 0000 4.9 6.3 7.3 17.7 4.9 6.3 7.3 17.7 C C TG C C TG C C C D Q C TG TG1

106 : PREVIEW Logic Diagram INPUTS L BA H H OUTPUT Y L HL L H L H L LH FUNCTION TABLE 1G86 SINGLE 2-INPUT EXCLUSIVE-OR GATE

• Y = A ⊕ B ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN AHC AHCT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT IOH MAX -8 -8 -32 -24 -8 -4 -9 -8 mA IOL MAX 8 8 32 24 8 4 98 m A SWITCHING CHARACTERISTICS PARAMETER INPUT AHC AHCT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V tPLH 10 9 4 5 5.5 9.9 2 2.6 tPHL 10 9 4 5 5.5 9.9 2 2.6 UNIT:ns A or B OUTPUT Y MAX or MIN MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V ICC MAX 0.01 0.01 0.01 0.01 IOH MAX -32 -24 -8 -4 IOL MAX 32 24 8 4 SWITCHING CHARACTERISTICS PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 5.1 6.3 8.3 14.4 tPHL 5.1 6.3 8.3 14.4 UNIT:ns OUTPUT MAX or MIN Any In Y MAX AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V UNIT 0.0009 0.0009 0.0009 0.0009 mA 43 . 1 1 . 91 . 1m A AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V 6.4 7.8 10.5 19.2 6.4 7.8 10.5 19.2 An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols. EXCLUSIVE OR 1G97 CONFIGURABLE MULTIPLE-FUNCTION GATE 3 6In2 In1 In0 4 Y Logic Diagram FUNCTION TABLE INPUTS OUTPUT In2 In1 In0 Y LLL L LL L LH H LH H HL L HL H HH H L H L H LL HHH H FUNCTION SELECTION TABLE 2-to-1 data selector 2-input AND gate 2-input OR gate with one inverted input 2-input NAND gate with one inverted input 2-input AND gate with one inverted input 2-input NOR gate with one inverted input 2-input OR gate Inverter Noninverted buffer

107PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 1G98 CONFIGURABLE MULTIPLE-FUNCTION GATE ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V ICC MAX 0.01 0.01 0.01 0.01 IOH MAX -32 -24 -8 -4 IOL MAX 32 24 8 4 SWITCHING CHARACTERISTICS PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 5.1 6.3 8.3 14.4 tPHL 5.1 6.3 8.3 14.4 UNIT:ns Any In OUTPUT Y MAX or MIN MAX AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V UNIT 0.0009 0.0009 0.0009 0.0009 mA 43 . 1 1 . 91 . 1m A AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V 67 . 3 10.2 19 67 . 3 10.2 19 6In2 In1 In0 4 Y Logic Diagram FUNCTION TABLE INPUTS OUTPUT In2 In1 In0 Y LLL H LL H LH L LH L HL H HL L HH H L H L H LH HHH L FUNCTION SELECTION TABLE 2-to-1 data selector with inverted output 2-input NAND gate 2-input NOR gate with one inverted input 2-input AND gate with one inverted input 2-input NAND gate with one inverted input 2-input OR gate with one inverted input 2-input NOR gate Noninverted buffer Inverter

108 : PREVIEW 1G99 SINGLE RETRIGGERABLE MONOSTABLE MULTIVIBRATOR WITH SCHMITT-TRIGGER INPUTS

• Offers Nine Different Logic Functions in a Single Package FUNCTION TABLE INPUTS OUTPUT Y L H L H L L H OE D C LLL LL LL LL LL LL LL L L L H H H LL H B L L H H L L H H A L H L H L H L HH H L H LH LH LH L L L LHL L L H H L H L HL H H L LH LH LH H H H LH H L L H H L H L HH HH or L H or L H or L H or L Z A 2 B 3 C 7 D 6 Y OE 1 Logic Diagram ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V UNIT IOL MAX 32 24 8 4 4 3.1 1.9 1.1 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V UNIT : ns AY MAX BY MAX CY MAX DY MAX OE Y MAX OE Y MAX 3-state buffer 3-state inverter 3-state 2-in-1 data selector MUX 3-state 2-in-1 data selector MUX, inverted out 3-state 2-input AND 3-state 2-input AND, one input inverted 3-state 2-input AND, both inputs inverted 3-state 2-input NAND 3-state 2-input NAND, one input inverted 3-state 2-input NAND, both inputs inverted 3-state 2-input XOR 3-state 2-input XNOR PRIMARY FUNCTION 3-state 2-input NOR, both inputs inverted 3-state 2-input NOR, one input inverted 3-state 2-input NOR 3-state 2-input OR, both inputs inverted 3-state 2-input OR, one input inverted 3-state 2-input OR 3-state 2-input XOR, one input inverted COMPLEMENTARY FUNCTION

109PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 1G123 SINGLE RETRIGGERABLE MONOSTABLE MULTIVIBRATOR WITH SCHMITT-TRIGGER INPUTS

• Schmitt-Triggered Circuitry on A and B Inputs for Slow Input Transition Rates
• Edge Triggered From Active-High or Active-Low Gated Logic Inputs
• Retriggerable for Very Long Outputs Pulses, up to 100% Duty Cycle
• Overriding Clear Terminates Output Pulse
• Glitch-Free Power-Up Reset on Outputs CLR Cext Rext/Cext R B A Q Logic Diagram FUNCTION TABLE INPUTS OUTPUT CLR A B Q LX X L XH L (1) XX L (1) HL H ↓ ↑ L X L H H (1) These outputs are based on the assumption that the indicated steady-state conditions at the A and B inputs have been set up long enough to complete any pulse started before the setup.ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS MAX or MIN LVC 3.3V LVC 2.5V LVC 1.8V UNIT ICC Quiescent MAX 0.01 - - - mA ICC Active State MAX 0.975 0.65 0.28 0.22 mA MAX -32 -24 -8 -4 mA MAX 32 24 8 4 mA TIMING REQUIREMENTS MAX or MIM LVC LVC LVC 3.3V LVC 2.5V LVC 1.8V MAX 2.5 3 4 8 MAX 2.5 3 4 8 UNIT : ns SWITCHING CHARACTERISTICS PARAMETER INPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V t PLH 8.2 12.5 18.5 57 tPHL 8.2 12.5 18.5 57 tPLH 6 8.6 12.5 36.5 tPHL 6 8.6 12.5 36.5 tPLH 7.5 11.5 17 59 tPHL 7.5 11.5 17 59 UNIT : ns Q MAX twIN Q MAX Q MAX PARAMETER IOH IOL OUTPUT PARAMETER CLR A or B trigger A or B CLR CLR trigger VCC R C Cext Rext/Cext REQUIRED TIMING CIRCUIT

110 : PREVIEW A OE Y Logic Diagram INPUTS H AOE L OUTPUT Y H ZX H H L L FUNCTION TABLE INPUTS L AOE L OUTPUT Y H ZX L H H L FUNCTION TABLE 1G126 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

• Y = A ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN AHC AHCT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V IOH MAX -8 -8 -32 -24 -8 -4 -9 -8 IOL MAX 8 8 32 24 8 4 98 SWITCHING CHARACTERISTICS PARAMETER INPUT AHC AHCT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT:ns A OE OE OUTPUT Y Y Y MAX or MIN MAX MAX MAX AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V UNIT 0.0009 0.0009 0.0009 0.0009 mA 43 . 1 1 . 91 . 1 m A AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V 5.2 6.4 9.1 16.6 5.2 6.4 9.1 16.6 6.4 7.8 11 20.2 6.4 7.8 11 20.2 5.6 5.4 7.5 14 5.6 5.4 7.5 14 A OE 1 24 Y Logic Diagram1G125 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
• Y = A ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN AHC AHCT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V IOH MAX -8 -8 -32 -24 -8 -4 -9 -8 IOL MAX 88 3 2 2 4 8498 SWITCHING CHARACTERISTICS PARAMETER INPUT AHC AHCT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V tPHZ 10 10 4.2 5 5 9.2 1.7 3.1 tPLZ 10 10 4.2 5 5 9.2 1.7 3.1 UNIT:ns MAX MAX MAX MAX or MIN A OE OE OUTPUT Y Y Y AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V UNIT 0.0009 0.0009 0.0009 0.0009 mA 43 . 1 1 . 91 . 1 m A AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V 5.2 6.4 9.1 16.6 5.2 6.4 9.1 16.6 6.4 7.8 11 20.2 6.4 7.8 11 20.2 5.6 5.4 7.5 14 5.6 5.4 7.5 14

111PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 1G132 SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS

• Y = A•B or Y = A + B INPUTS L BA H H OUTPUT Y H HL L H L H L LH FUNCTION TABLE A B Y Logic Diagram ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT ICC MAX 0.01 0.01 0.01 0.01 mA IOH MAX -32 -24 -8 -4 mA IOL MAX 32 24 8 4 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 5 67 . 5 1 6 tPHL 5 67 . 5 1 6 UNIT : ns A or B Y MAX

112 : PREVIEW 1G139 2-TO-4 LINE DECODER Select Inputs Data Outputs A 1 B 2 Y33 Y25 Y16 Y07 Logic Diagram FUNCTION TABLE INPUTS B HH L L H A H L LL H H H H H H L OUTPUTS Y1Y0 H H H L L H H H Y3Y2 ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT MAX 0.01 0.01 0.01 0.01 mA MAX -32 -24 -8 -4 mA MAX 32 24 8 4 mA SWITCHING CHARACTERISTICS MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V t PLH 4.2 5.9 8.2 16.7 tPHL 4.2 5.9 8.2 16.7 UNIT : ns MAXA or B Y PARAMETER PARAMETER INPUT OUTPUT ICC IOH IOL

113PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 1G175 SINGLE D-TYPE FLIP-FLOP WITH ASYNCHRONOUS CLEAR

• Complementary Outputs (Q, Q)
• Buffered Clock and Direct Clear Inputs
• Asynchronous Clear Function Q D CLR CLK D R Logic Diagram ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT MAX 0.01 0.01 0.01 0.01 mA MAX -32 -24 -8 -4 mA MAX 32 24 8 4 mA TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V MIN 175 150 125 100 CLR Low MIN 2.5 2.8 3 5.6 CLK High or low MIN 2.5 2.8 3 3.5 Data MIN 1.5 2 2.5 3 CLR inactive MIN 0.5 0.5 0 0 th MIN 0.5 0.5 0 0 tPLH 4 5.7 7.1 13.4 tPHL 4 5.7 7.1 13.4 tPLH 4.1 5.8 7 12.9 tPHL 4.1 5.8 7 12.9 UNIT fmax : MHz other : ns Hold time, data after CLK ↑ fmax ICC IOH IOL tsu Setup time, before CLK ↑ PARAMETER PARAMETER INPUT tw Pulse duration OUTPUT MAX MAX CLK CLR Q Q FUNCTION TABLE INPUTS OUTPUT CLR CLK D Q H ↑ LL H ↑ H HH o r L Q O LX L H X X

114 : PREVIEW A OE 1 2 4 Y Logic Diagram INPUTS L AOE L OUTPUT Y H ZX L H H L FUNCTION TABLE 1G240 SINGLE BUFFER/DRIVER WITH 3-STATE OUTPUT ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V IOH MAX -32 -24 -8 -4 -9 -8 IOL MAX 32 24 8498 SWITCHING CHARACTERISTICS PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT:ns A MAX OE OE MAX or MIN Y MAX Y MAX OUTPUT Y AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V UNIT 0.0009 0.0009 0.0009 0.0009 mA 43 . 1 1 . 91 . 1 mA AUP 3.3V AUP 2.5V AUP 1.8V AUP 1.1V 5.2 6.3 9.1 17.3 5.2 6.3 9.1 17.3 6.3 7.7 10.9 20.9 6.3 7.7 10.9 20.9 9.1 7.3 10.1 12.9 9.1 7.3 10.1 12.9 Y4A 1 B 3 C 6 Logic Diagram1G332 SINGLE 3-INPUT POSITIVE-OR GATE

• Y = A + B + C ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT ICC MAX 0.01 0.01 0.01 0.01 mA IOH MAX -32 -24 -8 -4 mA IOL MAX 32 24 8 4 mA SWITCHING CHARACTERISTICS PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 3.5 4.8 6.2 17.2 tPHL 3.5 4.8 6.2 17.2 UNIT:ns MAX or MIN MAX OUTPUT YA, B or C FUNCTION TABLE INPUTS OUTPUT ABC Y HXX H XH H XX H LL L X H L

115PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 1G373 SINGLE D-TYPE LATCH WITH 3-STATE OUTPUT

• 3-State Outputs
• Buffered Control Inputs OE 6 LE D C D Q Logic Diagram ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT MAX 0.01 0.01 0.01 0.01 mA MAX -32 -24 -8 -4 mA MAX 32 24 8 4 mA TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V t w MIN 3333 tsu MIN 1.5 1.5 2 2.4 th MIN 1.5 1.5 1.5 2.5 tPLH 4 5.4 7.3 16 tPHL 4 5.4 7.3 16 tPLH 4 5.5 7.4 16.3 tPHL 4 5.5 7.4 16.3 3.7 5.1 6.3 13 3.7 5.1 6.3 13 4.6 6.5 5.9 17.4 4.6 6.5 5.9 17.4 UNIT : ns IOL Setup time, data before LE ↓ MAX MAX PARAMETER PARAMETER INPUT Pulse duration, LE high OUTPUT Hold time, data after LE ↓ ICC IOH MAX MAX D LE Q Q Q Q t PZH tPZL tPHZ tPLZ OE OE FUNCTION TABLE INPUTS OUTPUT OE LE D Q LHL L LH H LL Q O HX Z H X X

116 : PREVIEW 1G374 SINGLE D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT

• 3-State Outputs
• Buffered Control Inputs OE 6 CLK D D Q Logic Diagram FUNCTION TABLE INPUTS OUTPUT OE CLK D Q LL L L ↑ H LH or L Q ZHX H X X ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS LVC 3.3V LVC 2.5V LVC 1.8V UNIT 0.01 0.01 0.01 mA -24 -8 -4 mA MAX or MIN MAX MAX MAX LVC 0.01 -32 32 24 8 4 mA TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V f max MIN 175 150 125 100 tw MIN 2.5 2.8 3 3.3 tsu MIN 1.5 2 2.5 3.5 th MIN 1.5 1.5 1.6 3.4 tPLH 4 68 . 2 18.3 tPHL 4 68 . 2 18.3 3.5 56 . 3 1 3 3.5 56 . 3 1 3 3.1 4.5 5.3 14 3.1 4.5 5.3 14 UNIT fmax : MHz other : ns tPZH tPZL tPHZ tPLZ OE OE MAXCLK Q MAX MAX Q Q PARAMETER PARAMETER INPUT Pulse duration, CLK high or low OUTPUT Hold time, data after CLK ↑ ICC IOH IOL Setup time, data before CLK ↑

117PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Y A B C Logic Diagram FUNCTION TABLE INPUTS OUTPUT ABC Y LLL L LL H LH H LH L HL H HL L HH H L H L H LL HHH H 1G386 SINGLE 3-INPUT EXCLUSIVE-XOR GATE

• Y = A ⊕ B ⊕ C ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT ICC MAX 0.01 0.01 0.01 0.01 mA IOH MAX -32 -24 -8 -4 mA IOL MAX 32 24 8 4 mA SWITCHING CHARACTERISTICS PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 45 5 . 5 1 2 tPHL 45 5 . 5 1 2 UNIT:ns MAX MAX or MIN Y OUTPUT A, B or C 1G0832 SINGLE 3-INPUT POSITIVE AND-OR GATE
• Y = (A•B) + C
• Can Be Used in Three Combinations AND-OR Gate AND Gate OR Gate A B Y6C Logic Diagram FUNCTION TABLE INPUTS OUTPUT ABC Y XH H HH H XL L LLX X L L X X = Valid H or L ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT ICC MAX 0.01 0.01 0.01 0.01 mA IOH MAX -32 -24 -8 -4 mA IOL MAX 32 24 8 4 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 4 5.9 7.6 17.5 tPHL 4 5.9 7.6 17.5 UNIT : ns A, B, or C Y MAX FUNCTION SELECTION TABLE 2-Input AND Gate 2-Input OR Gate Y = (A • B) + C

118 : PREVIEW A S Logic Diagram FUNCTION TABLE CONTROL INPUT S ON CHANNEL LB 1 HB 2 1G3157 SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH

• Useful for Both Analog and Digital Apprications
• Specified Break-Before-Make Switching
• Rail-to-Rail Signal Handling
• High Degree of Linearity RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT ICC MAX 0. 01 0.01 0.01 0.01 mA

30 -30 24 -24 8 -8 4 -4 mA RON IO MAX 71 592 0 1 2 3 02 05 0W UNIT:ns UNITLVC 2.5V LVC 1.8VLVC 5V LVC 3.3VPARAMETER MAX or MIN SWITCHING CHARACTERISTICS PARAMETER I NPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 0.3 0.8 1.2 2 tPHL 0.3 0.8 1.2 2 tPZH 5.7 7.6 14 24 tPZL 5.7 7.6 14 24 tPHZ 3.8 5.3 7.5 13 tPLZ 3.8 5.3 7.5 13 UNIT:ns SB n MAX SB n MAX OUTPUT MAX or MIN A or Bn Bn or A MAX

119PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 1G3208 SINGLE 3-INPUT POSITIVE OR-AND GATE

• Y = (A + B)•C
• Can Be Used in Three Combinations OR-AND Gate OR Gate AND Gate A B Y6C Logic Diagram FUNCTION TABLE INPUTS OUTPUT ABC Y HH H XH H XX L LLL H L H X X = Valid H or L ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT ICC MAX 0.01 0.01 0.01 0.01 mA IOH MAX -32 -24 -8 -4 mA IOL MAX 32 24 8 4 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 4 5.9 7.6 17.5 tPHL 4 5.9 7.6 17.5 UNIT : ns A, B, or C Y MAX FUNCTION SELECTION TABLE 2-Input AND Gate 2-Input OR Gate Y = (A + B) • C

120 : PREVIEW 71A 32A Logic Diagram INPUTS L BA L OUTPUT Y L H X X HH H FUNCTION TABLE (each gate) 2G00 DUAL 2-INPUT POSITIVE-NAND GATE

• Y = A•B PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT IOH MAX -32 -24 -8 -4 -9 -8 mA IOL MAX 32 24 8498 m A PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT:ns A or B OUTPUT Y MAX or MIN MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS Logic Diagram INPUTS BA L OUTPUT Y H L X XH H L L FUNCTION TABLE (each gate) 2G02 DUAL 2-INPUT POSITIVE-NOR GATE
• Y = A + B PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT IOH MAX -32 -24 -8 -4 -9 -8 mA IOL MAX 32 24 8498 m A PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT:ns A or B OUTPUT MAX or MIN Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

121PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram Logic Diagram 1A 1Y 2A 2Y OUTPUT Y INPUT A H LH L FUNCTION TABLE (each inverter) 2G04 DUAL INVERTER GATE

• Y = A PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT IOH MAX -32 -24 -8 -4 -9 -8 mA IOL MAX 32 24 8 498 m A PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V tPLH 3.2 4.1 4.4 8 1.5 2 tPHL 3.2 4.1 4.4 8 1.5 2 UNIT:ns AY MAX OUTPUT MAX or MIN ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS OUTPUT Y INPUT A LH LH FUNCTION TABLE (each inverter) ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT IOH MAX -32 -24 -8 -4 -9 -8 mA IOL MAX 32 24 8498 m A SWITCHING CHARACTERISTICS PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V tPLH 33 . 74 5.5 2 2.7 tPHL 33 . 74 5.5 2 2.7 UNIT:ns A OUTPUT MAX or MIN Y MAX 1A 1Y 2A 2Y 2GU04 DUAL INVERTER GATE
• Y = A

122 : PREVIEW 1A 1Y1 2A 2Y3 Logic Diagram OUTPUT Y INPUT A H LH L FUNCTION TABLE (each inverter) 2G06 DUAL INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT IOL MAX 32 24 8498 m A PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT:ns A OUTPUT MAX or MIN Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS 1A 1Y1 2A 2Y3 Logic Diagram OUTPUT Y INPUT A H L H L FUNCTION TABLE (each buffer/deiver) 2G07 DUAL BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT IOL MAX 32 24 8498 m A PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT:ns AY MAX OUTPUT MAX or MIN ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

123PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 71A 32A Logic Diagram INPUTS L BA L OUTPUT Y H L X X HH L FUNCTION TABLE (each gate) 2G08 DUAL 2-INPUT POSITIVE-AND GATE

• Y = A•B PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT IOH MAX -32 -24 -8 -4 -9 -8 mA IOL MAX 32 24 8 498 m A PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT:ns A or B OUTPUT MAX or MIN Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS OUTPUT Y INPUT A LH L H FUNCTION TABLE (each inverter) PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT IOH MAX -32 -24 -8 -4 -9 -8 mA IOL MAX 32 24 8498 m A PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V tPLH 4.3 5.4 5.7 9.5 TBD TBD tPHL 4.3 5.4 5.7 9.5 TBD TBD UNIT:ns A OUTPUT MAX or MIN Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS 1A 1Y 2A 2Y Logic Diagram2G14 DUAL SCHMITT-TRIGGER INVERTER
• Y = A

124 : PREVIEW 1A 1Y 2A 2Y Logic Diagram OUTPUT Y INPUT A H L H L FUNCTION TABLE (each inverter) 2G17 DUAL SCHMITT-TRIGGER BUFFER

• Y = A PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT ICC MAX 0.01 0.01 0.01 0.01 mA IOH MAX -32 -24 -8 -4 mA IOL MAX 32 24 8 4 mA PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 4.3 5.4 5.7 9.3 tPHL 4.3 5.4 5.7 9.3 UNIT:ns AY MAX OUTPUT MAX or MIN ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS 71A 32A Logic Diagram INPUTS BA L OUTPUT Y L H X XH H L H FUNCTION TABLE (each gate) 2G32 DUAL 2-INPUT POSITIVE-OR GATE
• Y = A + B PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT IOH MAX -32 -24 -8 -4 -9 -8 mA IOL MAX 32 24 8498 m A PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT:ns A or B OUTPUT Y MAX or MIN MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

125PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 2G34 DUAL BUFFER GATE

• Y = A 1A 1Y1 2A 2Y3 OUTPUT Y INPUT A L H L H FUNCTION TABLE (each gate) PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT IOH MAX -32 -24 -8 -4 -9 -8 mA IOL MAX 32 24 8 498 m A PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V tPLH 3.2 4.1 4.4 8.6 tPHL 3.2 4.1 4.4 8.6 1.8 1.8 2.4 2.4 UNIT:ns A MAX or MIN Y MAX OUTPUT ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS Logic Diagram 2G38 SINGLE 2-INPUT NAND GATE WITH OPEN-DRAIN OUTPUT
• Y = A•B or Y = A + B INPUTS L BA H OUTPUT Y H L H H LHH LL H FUNCTION TABLE (each gate) 71A 32A Logic Diagram PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT ICC MAX 0.01 0.01 0.01 0.01 mA VO MAX 5.5 5.5 5.5 5.5 mA IOL MAX 32 24 8 4 mA PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 3.9 4.5 6 10 tPHL 3.9 4.5 6 10 UNIT : ns A or B Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

126 : PREVIEW CONTROL INPUTS L L AINH L ON CHANNEL NoneX H H FUNCTION TABLE 2G53 SINGLE-POLE DOUBLE-THROW (SPDT) ANALOG SWITCH 2:1 ANALOG MULTIPLEXER/DEMULTIPLEXER

• High On-Off Outputs Voltage Ratio
• High Degree of Linearity PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT RON MAX 13 17 20 30 15 20 mA RON(P) MAX 15 20 30 120 20 80 mA PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT:ns A COM or Y INH OUTPUT MAX or MIN MAX MAX Y or COM COM or Y COM or Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS A INH COM SW SW Logic Diagram 1A 1 One of Two Switches Logic Diagram, each switch SWITCHI CONTROL INPUT (C) ON OFFL H FUNCTION TABLE (each section) 2G66 DUAL BILATERAL ANALOG SWITCH
• High On-Off Outputs Voltage Ratio
• High Degree of Linearity
• Rail-to-Rail Input/Output PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT RON MAX 10 15 20 30 15 20 mA RON(P) MAX 15 20 30 120 20 80 mA PARAMETER LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V tPLH 0.6 0.8 1.2 2 tPHL 0.6 0.8 0.7 0.7 0.7 0.71.2 2 tPZH 3.9 4.4 5.6 10 tPZL 3.9 4.4 5.6 2.3 2.3 2.7 2.710 tPHZ 6.3 7.2 6.9 10.5 tPLZ 6.3 7.2 6.9 3.4 3.410.5 UNIT:ns C C MAX OUTPUT B or A A or B A or B MAX or MIN MAX MAX INPUT A or B ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

127PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 2G74 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT ICC 0.01 0.01 0.01 0.01 mA IOH -32 -16 -8 -4 mA IOL 32 16 8 4 mAMAX MAX or MIN MAX MAX TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS PARAMETER LVC LVC 3.3V LVC 2.5V LVC 1.8V fmax 200 175 175 80 22 . 7 2.7 6.2 22 . 7 2.7 6.2 1.1 1.3 1.7 2.9 11 . 2 1.4 1.9 th 0.5 1.2 0.3 0 tPLH 4.1 5.9 7.1 13.4 tPHL 4.1 5.9 7.1 13.4 tPLH 4.4 6.2 7.7 14.4 tPHL 4.4 6.2 7.7 14.4 tPLH 4.1 5.9 7 12.9 tPHL 4.1 5.9 7 12.9 UNIT:ns MAX MIN MIN MIN MIN PRE or CLR low OUTPUT PRE or CLR inactive INPUT CLK MAX or MIN Q or Q MAX MAX tsu Data tw CLK CLK PRE or CLR Q Q † This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. PRE QCLR INPUTS X H DQCLK H X OUTPUTS H H†X L H X L X X L H H H LH H LH X Q0H L L L L L H H FUNCTION TABLE TG C C TG C C TG C C C TG C C PRE CLK D CLR Q Q C Logic Diagram

128 : PREVIEW Logic Diagram INPUTS DCLK L OUTPUT Q L Q0X ↑ H L H FUNCTION TABLE 2G79 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V ICC MAX 0.005 0.005 0.005 0.005 IOH MAX -32 -24 -8 -4 IOL MAX 32 24 8 AUC 2.5V 0.01 AUC 1.8V 0.01 UNIT mA mA mA TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V fmax 160 160 160 160 tw 2.5 2.5 2.5 2.5 0.9 1.1 1.4 2.2 0.9 1.1 1.4 2.2 th 0.5 0.7 0.8 1.4 t PLH 4.5 5.2 7.0 9.9 tPHL 4.5 5.2 7.0 9.9 AUC 2.5V AUC 1.8V 275 250 0.5 0.6 0.5 0.6 0.1 0.1 1.8 2.4 1.8 2.4 UNIT fmax : MHz other : ns CLK high or low MIN MIN OUTPUT MAX or MIN tsu CLK MAX Q Before CLK ↑ , Data high Before CLK ↑ , Data low Data after CLK ↑ MIN MIN C C TG C C TG C C C C C CLK D Q C TG TG

129PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 2G80 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP C C TG C C TG C C C C C CLK D Q C TG TG Logic Diagram INPUTS DCLK L OUTPUT Q L Q0X ↑ H L H FUNCTION TABLE (each flip-flop) ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V ICC MAX 0.005 0.005 0.005 0.005 IOH MAX -32 -24 -8 -4 IOL MAX 32 24 8 AUC 2.5V 0.01 AUC 1.8V 0.01 UNIT mA mA mA TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V fmax 160 160 160 160 tw 2.5 2.5 2.5 2.5 0.9 1.1 1.4 2.2 0.9 1.1 1.4 2.2 th 0.6 0.8 1.0 1.6 t PLH 4.5 5.2 7.0 3.9 tPHL 4.5 5.2 7.0 AUC 2.5V 275 0.5 0.5 0.5 1.8 1.8 AUC 1.8V 250 0.6 0.6 0.1 2.4 2.43 1. 9 UNIT fmax : MHz other : ns MIN QCLK MIN MAX OUTPUT MAX or MIN CLK high or low MIN MIN tsu Before CLK ↑ , Data high Before CLK ↑ , Data low Data after CLK ↑

130 : PREVIEW 2G86 DUAL 2-INPUT EXCLUSIVE-OR GATE

• Y = A ⊕ B ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT IOH -32 -24 -8 -4 -9 -8 mA IOL 32 24 8498 m AMAX MAX or MIN MAX MAX SWITCHING CHARACTERISTICS PARAMETER LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT:ns MAX or MIN MAX INPUT A or B OUTPUT Y INPUTS L BA H H OUTPUT Y L HL L H L H L LH FUNCTION TABLE (each gate) Logic Diagram An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols. EXCLUSIVE OR 1A 1Y 1OE 2A 2Y 2OE Logic Diagram INPUTS L AOE L OUTPUT Y H ZX L H H L FUNCTION TABLE (each buffer) 2G125 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT IOH MAX -32 -24 -8 -4 -9 -8 mA IOL MAX 32 24 8498 m A SWITCHING CHARACTERISTICS PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V tPLH 3.7 4.3 4.8 9.1 tPHL 3.7 4.3 4.8 9.1 tPZH 3.8 4.7 5.6 9.9 tPZL 3.8 4.7 5.6 9.9 tPHZ 3.4 4.6 5.8 11.6 tPLZ 3.4 4.6 5.8 1.8 2.6 1.8 2.6 2.2 2.9 2.2 2.9 2 3.6 2 3.611.6 UNIT:ns OE A OUTPUT Y Y Y MAX or MIN MAX MAX MAX OE

131PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 1A 1Y 1OE 2OE Logic Diagram INPUTS H AOE L OUTPUT Y H ZX H H L L FUNCTION TABLE (each buffer) 2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT IOH MAX -32 -24 -8 -4 -9 -8 mA IOL MAX 32 24 8498 m A SWITCHING CHARACTERISTICS PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V tPLH 3.2 4 4.9 9.8 tPHL 3.2 4 4.9 9.8 tPZH 3.1 4.1 5 10 tPZL 3.1 4.1 5 10 tPHZ 3.3 4.4 5.7 12.6 tPLZ 3.3 1.8 1.8 2.2 2.2 1.8 1.8 2.3 2.3 2.4 2.4 3.3 3.34.4 5.7 12.6 UNIT:ns OE Y MAX Y MAX OUTPUT MAX or MIN Y MAX OE A 2G132 DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUT

• Y = A•B or Y = A + B INPUTS L BA H OUTPUT Y H L H H LHH LL H FUNCTION TABLE (each gate) Logic Diagram PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT ICC MAX 0.01 0.01 0.01 0.01 mA IOH MAX -32 -24 -8 -4 mA IOL MAX 32 24 8 4 mA PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 5 67 . 5 1 6 tPHL 5 67 . 5 1 6 UNIT : ns A or B Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

132 : PREVIEW 2G157 SINGLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER G A/B B A Y Y GY A/B INPUTS XH BYA L X OUTPUTS L H H X L X L L L X X H L X H H L H L LL L L L H H FUNCTION TABLE Logic Diagram ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT ICC MAX 0.01 0.01 0.01 0.01 mA IOH MAX -32 -24 -8 -4 mA IOL MAX 32 24 8 4 mA SWITCHING CHARACTERISTICS PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 468 1 4 tPHL 468 1 4 tPLH 469 1 6 tPHL 469 1 6 tPLH 468 1 4 tPHL 468 1 4 UNIT:ns A or B A/B G OUTPUT Y or Y Y or Y Y or Y MAX or MIN MAX MAX MAX

133PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 5 3 1A 1Y 2A 2Y 1OE 2OE Logic Diagram2G240 DUAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT IOH MAX -32 -24 -8 -4 -9 -8 mA IOL MAX 32 24 8 498 m A SWITCHING CHARACTERISTICS PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V tPLH 4 4.6 5.5 11.3 tPHL 4 4.6 5.5 11.3 tPZH 5 5.4 6.6 11.7 tPZL 5 5.4 6.6 11.7 tPLZ 4.2 5.5 5.7 12.8 tPHZ 4.2 5.5 5.7 1.7 2.5 1.7 2.5 2.1 3.1 2.1 3.1 1.9 3.7 1.9 3.712.8 UNIT:ns OE A OE OUTPUT Y Y Y MAX or MIN MAX MAX MAX INPUTS L AOE L OUTPUT Y H ZX L H H L FUNCTION TABLE (each buffer) 2 6 1OE 5 3 2Y 2OE Logic Diagram INPUTS L 1A1OE L OUTPUT H ZX LH H L INPUTS L 2A2OE L OUTPUT H ZX H H H L FUNCTION TABLE 2G241 DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V UNIT IOH MAX -32 -24 -8 -4 -9 -8 mA IOL MAX 32 24 8498 m A SWITCHING CHARACTERISTICS PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V AUC 2.5V AUC 1.8V tPLH 3.7 4.3 4.8 8.8 tPHL 3.7 4.3 4.8 8.8 tPZL 3.8 4.7 5.6 9.9 tPZH 3.8 4.7 5.6 9.9 tPLZ 3.4 4.4 5.8 11.6 tPHZ 3.4 4.4 5.8 11.6 tPZL 3.3 4.1 4.7 8.8 tPZH 3.3 4.1 4.7 8.8 tPLZ 3.3 4.2 5.2 12.5 tPHZ 3.3 4.2 5.2 1.8 2.5 1.8 2.5 22 . 8 22 . 8 2.1 3.6 2.1 3.6 22 . 8 22 . 8 2.1 8.6 2.1 8.612.5 UNIT:ns A OE Y YOE OE OE Y Y MAX or MIN MAX OUTPUT Y MAX MAX MAX MAX

134 : PREVIEW 1A 1Y 2A 2Y 3A 3Y Logic Diagram OUTPUT Y INPUT A H LH L FUNCTION TABLE (each inverter) PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT ICC MAX 0.01 0.01 0.01 0.01 mA IOH MAX -32 -24 -8 -4 mA IOL MAX 32 24 8 4 mA PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 3.2 4.1 4.4 7.9 tPHL 3.2 4.1 4.4 7.9 UNIT:ns OUTPUT Y MAX or MIN MAXA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS 3G04 TRIPLE INVERTER GATE

• Y = A 1A 1Y 2A 2Y 3A 3Y Logic Diagram OUTPUT Y INPUT A L H H L FUNCTION TABLE (each inverter) PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT ICC MAX 0.01 0.01 0.01 0.01 mA IOH MAX -32 -24 -8 -4 mA IOL MAX 32 24 8 4 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 3.2 3.9 4 9.2 tPHL 3.2 3.9 4 9.2 UNIT : ns AY MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS 3GU04 TRIPLE INVERTER GATE
• Y = A

135PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 1A 1Y1 2A 2Y3 3A 3Y6 Logic Diagram OUTPUT Y INPUT A H L H L FUNCTION TABLE (each buffer/driver) 3G07 TRIPLE BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT ICC MAX 0.01 0.01 0.01 0.01 mA VO MAX 5.5 5.5 5.5 5.5 mA IOL MAX 32 24 8 4 mA PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 2.9 3.7 4.3 7.8 tPHL 2.9 3.7 4.3 7.8 UNIT:ns MAX OUTPUT MAX or MIN AY ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS 1A 1Y1 2A 2Y3 3A 3Y6 Logic Diagram OUTPUT Y INPUT A H LH L FUNCTION TABLE (each inverter) 3G06 TRIPLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT ICC MAX 0.01 0.01 0.01 0.01 mA VO MAX 5.5 5.5 5.5 5.5 mA IOL MAX 32 24 8 4 mA PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 2.9 3.4 3.9 7.2 tPHL 2.9 3.4 3.9 7.2 UNIT:ns MAX or MIN Y MAXA OUTPUT ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

136 : PREVIEW 1A 1Y1 2A 2Y3 3A 3Y6 Logic Diagram OUTPUT Y INPUT A H L H L FUNCTION TABLE 3G17 TRIPLE SCHMITT-TRIGGER BUFFER

• Y = A PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT ICC MAX 0.01 0.01 0.01 0.01 mA IOH MAX -32 -24 -8 -4 mA IOL MAX 32 24 8 4 mA PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 4.1 5.4 6.2 9.2 tPHL 4.1 5.4 6.2 9.2 UNIT:ns MAX or MIN MAXA OUTPUT Y ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS 1A 1Y 2A 2Y 3A 3Y Logic Diagram OUTPUT Y INPUT A LH L H FUNCTION TABLE (each inverter) PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT ICC MAX 0.01 0.01 0.01 0.01 mA IOH MAX -32 -24 -8 -4 mA IOL MAX 32 24 8 4 mA PARAME TER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 4.3 5.4 5.7 9.2 tPHL 4.3 5.4 5.7 9.2 UNIT:ns OUTPUT Y MAX or MIN MAXA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS 3G14 TRIPLE SCHMITT-TRIGGER INVERTER
• Y = A

137PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 1A 1Y1 2A 2Y3 3A 3Y6 Logic Diagram OUTPUT Y INPUT A L H L H FUNCTION TABLE (each gate) 3G34 TRIPLE BUFFER GATE

• Y = A PARAMETER MAX or MIN LVC LVC 3.3V LVC 2.5V LVC 1.8V UNIT ICC MAX 0.01 0.01 0.01 0.01 mA IOH MAX -32 -24 -8 -4 mA IOL MAX 32 24 8 4 mA PARAMETER INPUT LVC LVC 3.3V LVC 2.5V LVC 1.8V tPLH 3.2 4.1 4.4 7.9 tPHL 3.2 4.1 4.4 7.9 UNIT:ns MAX OUTPUT MAX or MIN AY ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

GATE (AND / NAND / OR / NOR) Technology Bipolar CMOS BiCMOS Advanced CMOS Low-Voltage CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LVC ALVC AVC AUC OC 09 ʷ ˔ ˔ ˔ ʷ ʷ/- OC 15 ʷ ʷ ʷ BUF 1008 ʷA ˔A SCH 7001 ˔/- 6B U F 808 ʷ ˔B ʷ/- BUF 1808 ʷ ʷ BUF 1011 ʷ 2 8003 ʷ ˔ OC 01 ʷ ʷ ʷ ʷ/- SCH 24 ʷ OC 26 ʷ ˔ BUF 37 ʷ ˔ ˔ ˔A ʷ BUF 1000 ʷA ˔A OC 1003 ʷA SCH OC 7003 ʷ/- OC 39 ʷ BUF 804 ˔A ˔B ʷ/- BUF 1804 ʷA ʷ OC 12 ʷ ʷ ʷ BUF 1010 ʷ SCH 13 ʷ ʷ ʷ/-/- -/ ʷ/- SCH 18 ʷ OC 22 ʷ ʷ ʷ ʷ BUF 40 ʷ ʷ ʷ ʷ ʷ BUF 140 ˔ BUF 1020 ʷ

3 SCH 618 ʷ

12 1 3S 134 ʷ 13 1 133 ʷ ˔ ʷ/- BUF 1032 ʷ ˔A SCH 7032 ˔/- BUF 832 ˔A ˔B ʷ/- BUF 1832 ʷA ʷ 33 4075 ʷ/˔ -/ ˔ BUF 28 ʷ ʷ ʷ OC 33 ʷ ˔ ˔A 36 ʷ ʷ/- BUF 128 ˔ BUF 1002 ʷA SCH 7002 ˔/- BUF 1036 ʷA BUF 805 ˔A ˔B ʷ/- BUF 1805 ʷ ʷ 23 ʷ 25 ˔ 4002 ʷ/˔ 52 260 ˔ ˔ Explanatory notes [Input] SCH: Schmitt-Trigger Inputs Explanatory notes [Output] BUF: Buffered Output OC: Open-Collector Output ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx AC: 74AC11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACxx / CD74ACxx ACT: 74ACT11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACTxx / CD74ACTxx POS- NOR POS-NAND POS- OR 2 DeviceCurcuit Input OutputDescription No. of Input POS-AND

GATE (EX-OR / EX-NOR / INVERTER / NONINVERTER / etc.) Technology Bipolar CMOS BiCMOS Advanced CMOS Low-Voltage CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LVC ALVC AVC AUC OC 136 ʷ ˔ ʷ ʷ 386 ʷ ʷ/- OC 266 ˔ ˔/- OC 811 ʷ ʷ 7266 ʷ/˔ EX-OR/NOR 24 135 ʷ OC 16 ˔ ʷ SCH 19 ˔ BUF 1004 ʷ ˔ ˔A OC 1005 ʷ ˔ 4049 ʔ/˔

8 SCH 619 ʷ

425 ʷ 426 ʷ OC 17 ˔ ˔ OC 35 ˔A BUF 1034 ˔ ˔A OC 1035 ˔ 4050 ʔ/˔ 16 6 3 ʷ 26 3 1 ˔ 50 ʷ 60 ʷ 53 ʷ 55 ʷ 4078 ʷ/- 10 1 54 ʷ ʷ 64 ʷ ʷ ʷ/-/- ʷ/-/- OC 65 ʷ BUF 800 ʷ/-/- ʷ/-/- BUF 802 ʷ/-/- ʷ/-/- 7006 ʷ/- 7008 ʷ/- 7074 ʷ/- 7075 ʷ/- 7076 ʷ/- Explanatory notes [Input] SCH: Schmitt-Trigger Inputs Explanatory notes [Output] BUF: Buffered Output OC: Open-Collector Output Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx AC: 74AC11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACxx / CD74ACxx ACT: 74ACT11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACTxx / CD74ACTxx OTHER NON- INVERTING 1 INVERTING EX-OR 2 EX-NOR 2 DeviceCurcuit Input OutputDescription No. of Input

BUFFER / DRIVER (NON-INVERTING) Technology Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LV-AT LVC ALVC AVC AUC Z˔A 3S 455 ʷ/- 3S 465 ˔ʷ 3S 467 ʷʷ 3S 541 ˔ ˔ 3S 656 ʷ/-/- ʷ/-/- 3S 747 ʷ OC 757 ˔ ˔/˔ OC 760 ˔˔ ˔/- 3S 1241 3S 1244 ˔A R3S 2241 ˔/- ˔ R3S 2244 ʷ ˔/- ˔A ˔A R3S 2541 ˔ 3S 25241 ʷ/- 3S 25244 ˔/˔ OC 25757 ʷ/- OC 25760 ʷ/- R3S 2827 ˔C/- ʷ 3S 29827 ˔ ˔B/-

11 R3S 5400 ˔A

3S 5402 ˔A R3S 16903 H˔ 3S 16241 ˔AH ˔ ʷ HʷA Z˔A R3S 162241 H˔ ˔A ˔A H˔ H˔A R3S 162541 H˔ ʷ 3S 16825 ˔˔ H˔ R3S 162825 ˔ 3S 16835 H˔ ˔ H˔ ˔ 3S 162827 ˔AH ˔ H˔ H˔A Z˔A R3S 322244 H˔A Explanatory notes [Output] 3S: 3-State Output R3S: Series Resistor and 3-State Output OC: Open-Collector Output Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx AC: 74AC11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACxx / CD74ACxx ACT: 74ACT11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACTxx / CD74ACTxx H˔3S 32244 Description No. of Output Output Device 162835R3S 16244 R3S 162244 NON- INVERTING 244 ˔B H˔A ˔C1 H˔˔ H˔A

BUFFER / DRIVER (INVERTING, INVERTING AND NON-INVERTING, ADDRESS DRIVERS) Technology Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LV-AT LVC ALVC AVC AUC 3S 366 ʷ ʷ ʷ/˔ 3S 436 ʷ 3S 437 ʷ 3S 231 ʷ ʷ 3S 240 ˔ ˔ ˔A Z˔A 3S 456 ʷ/- 3S 466 ʷ ʷ 3S 468 ʷ ʷ 3S 540 ˔ ˔ 3S 655 ʷ/-/- ʷ/-/- 3S 746 ʷ OC 756 ʷ ˔ ˔/- OC 763 ʷ 3S 1240 ʷ R3S 2240 ʷ ˔/- ˔A R3S 2540 ʷ 3S 25240 ʷ/- OC 25756 ʷ/- R3S 2828 ʷ/- 3S 29828 ʷ ʷB/-

11 R3S 5401 ˔

12 R3S 5403 ˔

3S 16240 ˔A ˔ Z˔A H˔ ˔ 3S 16540 ˔A ʷ ˔ ˔ H˔A ʷ R3S 162240 ˔ R3S 162540 ʷ 20 3S 16828 ʷ ʷ 32 3S 32240 ˔ Z˔A 3S 230 ʷ ʷ OC 762 ʷ 3S 16830 H* R3S 162830 H˔ HS˔ 3S 16344 H˔ 3S 16831 H˔ 3S 16832 H˔ R3S 162344 H˔ R3S 162831 ˔ R3S 162832 H˔ Explanatory notes [Output] 3S: 3-State Output R3S: Series Resistor and 3-State Output OC: Open-Collector Output Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx AC: 74AC11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACxx / CD74ACxx ACT: 74ACT11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACTxx / CD74ACTxx Output ADDRESS DRIVERS 1-2 1-4 INVERTING AND NON- INVERTING Description No. of Output INVERTING Device

BUS TRANSCEIVER (NON-INVERTING) Technology Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LV-AT LVC ALVC AVC AUC 3S 226 ʷ 3S 440 ʷ OC 441 ʷ 3S 442 ˔ 3S 443 ʷ 3S 444 ʷ OC 448 ʷ 3S 449 ʷ 3S 1243 3S 245 ˔ ˔A H˔A Z˔A 3S 470 ʷ/-/- ʷ/-/- 3S 472 ʷ/-/- ʷ/-/- 3S 474 ʷ/-/- ʷ/-/- 3S 543 ˔ ˔/- ˔A ˔ H˔ ʷ/-/- ˔/-/- ˔A OC 615 ʷ OC 621 ʷ ˔A ˔A1 ʷ ʷ 3SOC 639 ʷ ˔A ʷ OC 641 ˔ ˔A1 ˔ 3S 645 ˔ ˔A1 ˔ ˔/- ˔/- 3S 646 ˔ ˔A OC 647 ʷ ʷ 3S 652 ˔ ˔A 3SOC 654 ʷ ˔ 3S 659 ʷ/- ʷ/- 3S 665 ʷ/- ʷ/- 3S 899 ʷ/- 3S 1245 ˔A 3S 1645 ˔A 3S 2245 ˔/- ˔ R˔ H˔ R˔A 3S 2623 ʷ 3S 2645 ʷ 3S 2952 ʷ/- ˔AH ˔ ˔ A 3S 25245 ˔/˔ ˔H 3S 25543 ʷ/- 3S 25621 ʷ/- 3S 25623 ʷ/- 3S 25641 ʷ/- 3S 25646 ʷ/- 3S 25647 ʷ/- 3S 25652 ʷ/- 3S 25654 ʷ/- 3SOC 29833 ʷ ʷ/- 3SOC 29853 ʷ ʷ/- 3S 29863 ˔ ˔B/- 3S 16409 H˔ HR˔ 3S 29861 ʷ ʷB/- Explanatory notes [No. of Output] +P: With Parity Bit [Output] 3S: 3-State Output R3S: Series Resistor and 3-State Output [Output] OC: Open-Collector Output 3SOC: 3-State Output / Open-Collector Output Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx AC: 74AC11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACxx / CD74ACxx ACT: 74ACT11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACTxx / CD74ACTxx NON- INVERTING 8+1P 9 x 4 DeviceOutputDescription No. of Output

BUS TRANSCEIVER (NON-INVERTING) Technology Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LV-AT LVC ALVC AVC AUC 3S 16268 ʷ 3S 16269 H˔ HR˔A ˔ 3S 16270 H˔ 3S 16271 H˔ 3S 16272 ʷ 3S 162268 H˔ 3S 162269 3S 162280 HG˔ H˔A HR˔A R˔A Z˔A 3S 16334 ˔ H˔ ˔ 3S 16470 ˔ ʷ 3S 16543 ˔ ˔ 3S 16623 ˔ ʷ˔ 3S 16646 ˔ ˔ H˔ ʷ˔ ˔A H˔A H˔ ˔ * 3S 16952 ˔ ˔ H˔ ˔ H˔AH ˔ R3S 162245 ˔ H˔ H˔ Rʷ R3S 162334 ˔ 3S 32316 H˔ 3S 32318 H˔ 3S 16657 ˔˔ 3S 16833 ˔ʷ 3S 16853 ˔ʷ 3S 16472 ʷ 3S 16474 ʷ 3S 16500 ˔BH ˔ H˔ 3S 16501 ˔ H˔ H˔ * 3S 16525 H˔ 3S 16600 ˔ - H˔ 3S 16601 ˔ H˔ - H˔ HR˔ 3S 16834 ʷ ˔ ˔ 3S 16863 ˔˔ H˔ 3S 16901 H˔ H˔ R3S 162500 ˔ R3S 162501 ˔ R3S 162525 H˔ R3S 162600 R3S 162601 ˔ H˔ R3S 162834 ˔ 3S 16282 H˔ R3S 162282 HG˔ 3S 16836 H* * 3S 16861 ˔ R3S 162836 ˔ 3S 32543 H˔ 3S 32952 ʷ H˔A R˔A HR˔A Z˔A 3S 32500 ʷ 3S 32501 H˔ H˔ Explanatory notes [No. of Output] +P: With Parity Bit [Output] 3S: 3-State Output R3S: Series Resistor and 3-State Output [Output] OC: Open-Collector Output 3SOC: 3-State Output / Open-Collector Output Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx NON- INVERTING Device 16245 3S H˔ H˔ ˔ H˔ HR˔ Output 16X3 16+2P 18X3 32245 Description No. of Output H˔A ˔H˔ HR˔ ˔˔ * HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx AC: 74AC11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACxx / CD74ACxx ACT: 74ACT11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACTxx / CD74ACTxx

BUS TRANSCEIVER (INVERTING, NON-INVERTING / INVERTING) Technology Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LV-AT LVC ALVC AVC AUC 3S 242 ʷʷ ʷ ʷ ʷ/- ʷ/- 3S 446 ʷ 3S 1242 ʷ R3S 2242 ʷ 3S 471 ʷ/-/- ʷ/-/- 3S 473 ʷ/-/- ʷ/-/- 3S 475 ʷ/-/- ʷ/-/- OC 614 ʷ OC 622 ʷʷ ʷ ʷ 3SOC 638 ʷ ˔A ˔A1 ˔A 3S 640 ˔ OC 642 ˔ ʷA ˔A1 ʷ ʷ/- OC 649 ʷʷ 3SOC 653 ʷ˔ 3S 658 ʷ/- ʷ/- 3S 664 ʷ/- ʷ/- 3S 1640 ʷ 3S 2620 ʷ 3S 2640 ʷ ʷ/- 3S 2953 ʷ/- 3S 25620 ʷ/- 3S 25622 ʷ/- 3S 25640 ʷ/- 3S 25642 ˔/- 3S 25648 ʷ/- 3S 25649 ʷ/- 3S 25651 ʷ/- 3S 25653 ʷ/- 3SOC 834 ʷ/-/- ʷ/-/- 3SOC 854 ʷ/-/- ʷ/-/- 3SOC 29834 ʷ ʷ/- 3SOC 29854 ˔ ˔/- 3S 864 ʷ/-/- ʷ/-/- 3S 29864 ʷ ˔B/- 3S 862 ʷ/-/- ʷ/-/- 3S 29862 ʷ ʷB/- 3S 16471 3S 16544 ʷ 3S 16620 ʷʷ 3S 16640 ˔ʷ ʷ 3S 16648 ʷ 3S 16651 ˔ 3S 16862 3S 16953 ʷ 3S 16475 ʷ 3S 16524 H˔ 3S 16864 ʷ 3S 643 ʷʷ ʷ ʷ/- ʷ/- ʷ/-/- ʷ/-/- OC 644 ʷʷ ʷ OC 758 ʷʷ OC 759 ʷ 3S 7340 ʷ/- Explanatory notes [No. of Output] +P: With Parity Bit [Output] 3S: 3-State Output R3S: Series Resistor and 3-State Output [Output] OC: Open-Collector Output 3SOC: 3-State Output / Open-Collector Output Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx AC: 74AC11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACxx / CD74ACxx ACT: 74ACT11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACTxx / CD74ACTxx Description Output Device NON- INVERTING /INVERTING INVERTING 8+1P No. of Output

Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LV-AT LV-AT LVC ALVC AVC AUC 1B 2 S B 7 2 ʷ B2 SB 7 0 ʷ B2 SB 7 3 ʷ ˔A ʷ/˔ -/ ˔ B2 SB 110 ʷ B2 SB 111 ʷ 4B 2 S Q 376 ʷ B2 SB 7 6 ʷ ʷ ʷ/-/- B2 SB 7 8 ʷ ʷ/-/- B2 SB 113 ʷ ʷ ʷ ʷ ʷ/-/- B2 SB 114 ʷ ʷ ʷ ʷ ʷ/-/- 4B 2 S Q 276 ʷ D-TYPE FLIP-FLOP Technology Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LVC ALVC AVC AUC C2 SB 171 ʷ 2S B 379 ʷʷ ʷ/- ʷ/-/- ʷ/-/- 3S Q 534 ˔A ʷʷ ʷ/˔ʷ /˔ʷ /- ˔A ʷ/˔/˔ʷ /˔/- 3S Q 575 ˔A ʷ 3S Q 576 ˔B ˔ 3S Q 577 ˔A ʷ P3 S Q 876 ˔A ˔ C3 SQ 878 ʷʷ C3 S Q 879 ʷA ʷ 3S Q 4374 ˔B 3S Q 29825 ʷʷ ˔/- 3S Q 29826 ʷʷ ʷ/- C3 S Q 824 ʷA ʷ/-/- ʷ/-/- C3 SQ 29823 ʷʷ ʷ/- C3 S Q 29824 ʷʷ ʷ/- 3S Q 1821 ʷ 3S Q 29821 ˔ʷ ˔/- 3S Q 29822 ʷʷ ʷ/- 3S Q 16820 H˔ 3S Q 162820 H˔ H˔A H˔˔ ˔ 3S Q 16534 ʷ 3S Q 162374 H˔ H˔ C3 SQ 16823 ˔ H˔ ʷ˔ H˔ C3 SQ 162823 ˔A 3S Q 16721 * H˔ 3S Q 16821 ˔ H˔ ʷ H˔ 3S Q 162721 H˔ 3S Q 162821 ʷ 22 3S Q 16722 ˔ H˔A 3S Q 322374 H˔ Explanatory notes [Trigger] POS: Positive edge NEG: Negative Edge [PRE ŋ CLR] B: Preset and Clear C: Clear Only [Output] 2S: Totem pole Output 3S: 3-State Output [QŋQ] B: Qŋ-Output Q: Q-Output Q: Q-Output Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx AC: 74AC11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACxx / CD74ACxx ACT: 74ACT11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACTxx / CD74ACTxx H˔3237432 3S Q H˔H˔ Trigger Curcuit PRE CLR Output Q Q Device Trigger Curcuit PRE CLR Output Q Q Device 10X2 POS 2 NEG 2 POS

Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LV-AT LVC ALVC AVC AUC S-R 4 2S Q 279 ʷ ˔A

82 S Q 4724 ʷ/-

42 S Q 77 ʷ/-

42 S Q 375 ˔ ʷ/-

82 S Q 100 ʷ

83 S Q 990 ˔

83 S Q 991 ʷ

83 S B Q 666 ˔

83 S C Q 996 ˔

83 S B Q 667 ˔

93 S C Q 992 ˔

93 S C Q 993 ʷ

10 3S Q 994 ˔ 10 3S Q 995 ʷ

82 S C Q 116 ʷ

83 S Q 2373 ˔

83 S Q 580 ˔B ʷ

83 S C Q 873 ˔B ʷA ʷ/-/- ʷ/-/-

83 S P Q 880 ʷA ʷ

83 S B Q 845 ʷ ʷ ʷ/-/- ʷ/-/-

83 S B Q 29845 ʷ ʷ ʷ/-

83 S B Q 846 ʷ ʷ ʷ/-/- ʷ/-/-

83 S B Q 29846 ʷ ʷ ʷ/-

93 S B Q 1843

93 S B Q 29843 ʷ ʷ ˔/-

93 S B Q 844 ʷ ʷ ʷ/-/- ʷ/-/-

93 S B Q 29844 ʷ ʷ ʷ/-

10 3S Q 29841 ʷ ʷ ʷ/- 10 3S Q 29842 ʷ ʷ/- 12/24 3S Q 16260 H˔ H˔ 12/24 3S Q 162260 H˔ H˔ H˔A H˔ ˔ ˔ 16 3S Q 16533 ʷ 16 3S Q 162373 H˔ H˔ 18 3S B Q 16843 ˔ ʷ ʷ 20 3S Q 16841 ˔ ˔ H˔ 20 3S Q 162841 ˔ H˔ 32 3S Q 32373 H˔ H˔ ˔ H˔A ** Explanatory notes [Type] S-R: S-R Latch AD: Addressable Latch BIS: Bistable Latch [Type] R-B: Read-Back Latch D: D-Type Transparent Latch [PRE ŋ CLR] B: Preset and Clear C: Clear Only [Output] 2S: Totem pole Output 3S: 3-State Output [QŋQ] B: Qŋ-Output Q: Q-Output Q: Q-Output Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx PRE CLR Q Q Device D R/B Output AD BIS Type Curcuit

Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LVC ALVC AVC AUC R2 S 178 ʷ CR 2 S 179 ʷ R2 S 195 ʷ ʷ ʷ ʷ ʷ/˔ B2 S 9 5 ʷ ʷ ʷ B2 S 295 ʷC CR 3 S 395 ʷA 5C R2 S 9 6 ʷ ʷ CR 3 S 322 ʷ ʷ/- CB 2 S 198 ʷ CB 3 S 323 ʷ ˔ ʷ ʷ ʷ/- ʷ/-/ ˔ ʷ/-/- CB 2 S 199 ʷ SS 8 R 2S 91 ʷ ʷ 4C R2 S 9 4 ʷ

16 R 3S 674 ˔

Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LVC ALVC AVC AUC 4C B3 S 671 ʷ 4C B3 S 672 ʷ 8C R2 S 598 ˔ 8C R O C 599 ʷ 8C R O C 596 ˔

16 C B 3S 673 ˔

Explanatory notes [Input/Output Type] S: Serial P: Parallel S/P: Alternative Serial/Parallel [CLR] C: With Clear [Shift] R: Right-Shift B: Alternative Shift Right/Left [Output] 2S: Totem-Pole Output 3S: 3-State Output Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx AC: 74AC11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACxx / CD74ACxx ACT: 74ACT11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACTxx / CD74ACTxx Device SS / P Input Type Output Type No. of Bit S/P S 8 S/P S/P CLR Shift DeviceOutput PS Output S/P S/P CLR ShiftInput Type Output Type No. of Bit

REGISTER (ETC) Technology Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LVC ALVC AVC AUC 172 ʷ 170 ʷ ʷ 670 ˔ -/ ˔ -/ ˔ 858 ʷ/-/- ʷ/-/- 871 ʷ ʷ 859 ʷ/-/- ʷ/-/- 298 ʷ ˔ ˔A ʷ/- 398 ʷ 173 ʷ ˔A ʷ/˔ -/ ˔ 396 ʷ 818 ʷ/-/- ʷ/-/- 819 ʷ/-/- ʷ/-/- 29818 ʷ ʷ/- Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx AC: 74AC11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACxx / CD74ACxx ACT: 74ACT11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACTxx / CD74ACTxx MONOSTABLE MULTIVIBRATOR Technology Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LVC ALVC AVC AUC 121 ˔ 122 ʷ ˔ 422 ʷ 423 ˔ -/ ˔ -/ ˔ 4538 -/ ˔ -/ ˔ Explanatory notes [CLR] C: With Clear [Retrigger] R: With Retrigger Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx AC: 74AC11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACxx / CD74ACxx ACT: 74ACT11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACTxx / CD74ACTxx Device DeviceCurcuit CLR Retrigger REGISTER FILES 8W x 2B REGISTER FILES 4W x 4B Descriotion REGISTER FILES 4W x 4B REGISTER FILES 16W x 5B REGISTER FILES 16W x 5B REGISTER FILES 16W x 6B REGISTER FILES 32W x 4B MUX WITH STRAGE MUX WITH STRAGE 4BIT BUS-BUFFER REGISTER 8BIT STORAGE REGISTER 8BIT DIAGNOTICCS/PIPELINE REGISTER 1C R CR CR CR C CR

Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LVC ALVC AVC AUC A6 8 ʷ 99 0 ʷ ˔ 290 ʷ ʷ AA 176 ʷ AA 196 ʷ ʷ ʷ A9D 490 ʷ ʷ ʷ/- 560 ʷ SS 162 ʷ ʷA ʷ ʷB ʷ ʷ ʷ/- ʷ/-/- ʷ/-/- AS 160 ʷ ʷA ʷB ʷ ʷ ʷ/- ʷ/-/- ʷ/-/- AS 690 ʷ SS 692 ʷ S 168 ʷ ʷ ʷ ʷ ʷ/-/- ʷ/-/- S 668 ʷ A 190 ʷ ʷ ʷ ʷA ʷ/˔ ʷ /-/- ʷ/-/- AS 696 ʷ SS 698 ʷ AA 192 ʷ ʷ ʷ ʷ/˔ ʷ /-/- ʷ/-/- 8A J 4017 ʷ/˔ A6 9 ʷ 93 ʷ ˔ -/ ˔ -/ ˔ 293 ʷ ˔ AA 177 ʷ AA 197 ʷ ʷ ʷ 7A 4024 ʷ/˔ -/ ˔ A 4020 ˔/˔ -/ ˔ A 4060 ˔/˔ -/ ˔ A 4061 ʷ/- 561 ˔A SS 693 ʷ AS 691 ʷ D 4518 -/ ˔ S 669 ˔ SS 699 ʷ AS 697 ˔ AA 569 ˔A ʷ ʷ/-/- ʷ/-/- AS 461 ʷ/-/- ʷ/-/- SS 463 ʷ/-/- ʷ/-/- AAR 591 ʷ AJ 4022 ʷ/- 4520 -/ ˔ -/ ˔ AJ 7022 ʷ/- 40103 -/ ˔ -/ ˔ S 469 ʷ/-/- ʷ/-/- 579 ʷ/-/- ʷ/-/- OTH A 1 12 92 ʷ ˔ Explanatory notes [DECŋBIN] DEC: Decoder BIN: Binary Counter OHE: Other [ASYNŋSYN] ASYN: Asynchronous SYN: Synchronous [Up/Down] Y: Up/Down [CLR] A: With Asynchronous Clear S: With Synchronous Clear [LOAD] A: With Asynchronous Clear S: With Synchronous Clear 9: Preset 9 [ETC] D: 2-Curcuit R: With Series Register J: Johnson Counter 12: Devide By-Twelve Counter Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx AC: 74AC11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACxx / CD74ACxx ACT: 74ACT11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACTxx / CD74ACTxx LOAD A DEC BIN ASYN SYN No. of Bit UP/DOWN Mode DEC S Y Device ETCCLR Y Y BIN S A

RATE MULTIPLIER/FREQUENCY DIVIDERS Technology Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LVC ALVC AVC AUC 56 ʷ 57 ʷ 97 ˔ 167 ʷ 292 ˔ 294 ˔ Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx AC: 74AC11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACxx / CD74ACxx ACT: 74ACT11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACTxx / CD74ACTxx DATA SELECTOR/MULTIPLEXER Technology Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LVC ALVC AVC AUC 3S 850 ʷ 3S 851 ʷ 2S 4067 ʷ/˔ -/ ˔ 2S 152 ʷ/- 3S 354 ʷ ʷ/˔ -/ ˔ 3S 356 ʷ ʷ/- -/ ˔ 3S 4351 -/ ˔ -/ ˔ 3S 4851 ˔/- OC 355 ʷ OC 357 ʷ 2S 352 ʷ ʷ ʷ ʷ ʷ/- ʷ/-/- ʷ/-/- 3S 353 ʷ ʷ ʷ ʷ ʷ/- ʷ/-/- ʷ/-/- 3S 4352 -/ ˔ 3S 16460 H˔ ʷ 3S 162460 H˔ 2S S 399 ˔ 3S U 857 ˔ ʷ 3S S 604 ʷ ʷ/- OC S 605 ʷ 3S S 606 ʷ OC S 607 ʷ 3S AD 16254 ʷ Explanatory notes [Output] 2S: Totem pole Output 3S: 3-State Output OC: Open-Collector Output [ETC] S: Storage Register Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx 8/1 1 DECADE RATE MULTILIER Device DeviceOutput Curcuit ETC PROGRAMABLE FREQUENCY DIVIDER/DIGITAL TIMERS FREQUENCY DIVIDERS FREQUENCY DIVIDERS 6BIT BINARY RATE MULTIPLIER Descriotion No. of Input/output

Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LV-AT LV-AT LVC ALVC AVC AUC 2S 1 AD 4514 ʷ/˔ ʷ/˔ 2S 1 AD 4515 ʷ/˔ -/ ˔ OC 1 159 ˔ 2S 1 BD 43 ʷ 2S 1 BD 44 ʷ 2S 1 AD 237 ʷ/˔ -/ ˔ 2S 1 AD 137 ʷ ˔A ʷ ʷ/˔ -/ ˔ * 2S 1 AD 131 ʷ ʷ 2S 2 155 ʷ ˔A OC 2 156 ʷ ˔ ˔ Explanatory notes [Output] 2S: Totem pole Output 3S: 3-State Output OC: Open-Collector Output [ETC] AD: Adress Latch BD: BCD TO DECIMAL Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx AC: 74AC11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACxx / CD74ACxx ACT: 74ACT11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACTxx / CD74ACTxx CODE CONVERTER / PRIORITY ENCODER / REGISTER Technology Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LVC ALVC AVC AUC 184 ʷ 185 ʷ 147 ʷ ʷ -/˔ -/˔ 148 ʷ ˔ ʷ ˔/- 348 ˔ ʷ 278 ʷ Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx AC: 74AC11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACxx / CD74ACxx ACT: 74ACT11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACTxx / CD74ACTxx Output ETC Descriotion Device 8-3 PRIORITY ENCODER 4BIT CASCADABLE PRIORITY REGISTER CODE CONVERTER CODE CONVERTER 10-4 PRIORITY ENCODER 8-3 PRIORITY ENCODER CurcuitNo. of Input/output Device

Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LVC ALVC AVC AUC 45 ˔ 141 ʷ 145 ˔ ˔ 445 ʷ 46 ʷ 47 ˔A ˔ 48 ʷ ʷ 49 ʷ 246 ʷ 247 ʷ ˔ 347 447 248 ʷ 249 ʷ 142 ʷ 143 ʷ 144 ʷ Explanatory notes [Function] D: BCD TO DECIMAL, 7: BCD TO 7-SEGMENT, B: COUNTER/LATCH/DECODER/DRIVER [VOH] Off-Stage Output Voltage (V) Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx AC: 74AC11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACxx / CD74ACxx ACT: 74ACT11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACTxx / CD74ACTxx COMPARATOR Technology Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LVC ALVC AVC AUC 4S Y N Y Y 2S 85 ʷ ˔ ˔ ʷ ʷA/˔ -/˔ 6S NY NN 2S 29806 ʷ 82 0 Y N N NO C 518 ˔ ʷ 82 0 N Y N NO C 522 ʷ 82 0 N Y Y N2 S 682 ˔ ˔/- 82 0 N Y Y NO C 683 ʷ 8S Y N N N OC 519 ʷ ʷ 8S N Y Y N 2S 684 ˔ ˔/- 8S N Y Y N OC 685 ʷ 8S N Y Y N 2S 686 ʷ 8S N Y Y N OC 687 ʷ 8S N Y N N OC 689 ʷ ʷ 8S Y N Y Y 2S 860 ʷ/-/- ʷ/-/- 8S NNYY 2 S 8 6 5 ʷ/-/- ʷ/-/- 8L P NNYY 2 S 8 8 5 ˔ ʷ/-/- ʷ/-/- 8L P Q YN YY O C 866 ʷA 9- NY NN 2S 29809 ʷ Explanatory notes [Input] S: Standard 20: 20-kW Pullup Resistors LP: P-Port Latch LPQ: L,P-port Latch [P=Q, P=Q, P>Q, P<Q] Y: Yes N: No [Output] 2S: Totem Pole Output, OC: Open-Collector Output Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx B B B 5.5 Function D D D 5.57 5.5 DeviceNo. of Bit Input P=Q P=Q P>Q P<Q Output DeviceV OH (V) D 5.57

ADRESS COMPARATOR / FUSE-PROGRAMMABLE IDENTITY COMPARATOR Technology Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LVC ALVC AVC AUC 679 ˔ ʷ/- 680 ʷ ʷ/- 526 ʷ 528 ʷ 527 ʷ Explanatory notes [Function] A: Adress Comparator F: Fuse-Programmable Identity Comparators [ETC] OE: Output-With Enable L: Output-With Latch Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx AC: 74AC11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACxx / CD74ACxx ACT: 74ACT11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACTxx / CD74ACTxx PARITY GENERATOR / CHECKER Technology Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LVC ALVC AVC AUC 180 ʷ ʷ/- Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx AC: 74AC11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACxx / CD74ACxx ACT: 74ACT11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACTxx / CD74ACTxx VOLTAGE CONTROLLED OSCILLATOR (VCO) Technology Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LVC ALVC AVC AUC

20 Y Y Y 624 ˔

20 Y Y Y Y 628 ˔

20 627 ʷ

20 Y Y 629 ˔

20 Y 625 ʷ

20 Y Y 626 ʷ

60 Y Y 124 ˔

Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx AC: 74AC11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACxx / CD74ACxx ACT: 74ACT11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACTxx / CD74ACTxx PLLRextRANGE INPUTENABLECOMP'L Z OUT F Device Curcuit Fmax (MHz) A 12-4 L F1 6 16-4 A 12-4 OE OE Device DeviceNo. of Bit Descriotion ETC No. of Bit A 16-4 L A

ACCUMULATORS / ARITHMETIC LOGIC UNIT (ALU) / LOOK-AHEAD CARRY GENERATOR Technology Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LVC ALVC AVC AUC 281 ʷ 681 ʷ 381 ʷ ʷ ʷ 881 ʷA ʷ/-/- ʷ/-/- 382 ʷ ʷ 264 ʷ 182 ʷ ʷ ʷ 282 ʷ 882 ʷA ʷ/-/- ʷ/-/- 385 ʷ Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx AC: 74AC11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACxx / CD74ACxx ACT: 74ACT11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACTxx / CD74ACTxx ADDER Technology Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LVC ALVC AVC AUC 83 ʷ ʷ 183 ʷ 80 ʷ 82 ʷ Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx AC: 74AC11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACxx / CD74ACxx ACT: 74ACT11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACTxx / CD74ACTxx MULTIPLIER Technology Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LVC ALVC AVC AUC 261 ʷ 284 ʷ 285 ʷ 384 ʷ Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx AC: 74AC11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACxx / CD74ACxx ACT: 74ACT11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACTxx / CD74ACTxx Descriotion 4BIT PARALLEL BINARY ACCUMULATORS 4BIT PARALLEL BINARY ACCUMULATORS 4BIT ALU/FUNCTION GENERATORS Device Device Device 4BIT BINARY FULL ADDER DUAL CARRY SAVE FULL ADDER GATED FULL ADDER 2BIT BINARY FULL ADDER 4-4 PARALLEL BINARY MULTIPLIERS LOOK AHEAD CARRY GENERATORS QUAD SERIAL ADDER/SUBTRACTOR Descriotion 4BIT BINARY FULL ADDER 4-4 PARALLEL BINARY MULTIPLIERS 2'S COMPLEMENT MULTIPLIERS Descriotion 4BIT ALU/FUNCTION GENERATORS 4BIT ALU/FUNCTION GENERATORS 4BIT ALU WITH RIPPLE CARRY LOOK AHEAD CARRY GENERATORS 2-4 PARALLEL BINARY MULTIPLIERS LOOK AHEAD CARRY GENERATORS LOOK AHEAD CARRY GENERATORS

Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LVC ALVC AVC AUC 600 ʷ 601 ʷ 603 ʷ 608 ʷ 612 ʷ 613 ʷ 610 ʷ 611 ʷ 412 ʷ 2414 ˔/- Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx AC: 74AC11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACxx / CD74ACxx ACT: 74ACT11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACTxx / CD74ACTxx CLOCK GENERATOR CIRCUIT Technology Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LVC ALVC AVC AUC 265 ʷ 120 ʷ 320 ʷ 321 ʷ Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx AC: 74AC11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACxx / CD74ACxx ACT: 74ACT11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACTxx / CD74ACTxx SWITCH, SHIFTER, ERROR DETECTION CORRECTION CIRCUIT, HARD DISK DRIVER Bipolar CMOS BiCMOS Advanced CMOS TTL LS S ALS AS F HC HCT BCT ABT LVT ALVT AC ACT AHC AHCT LV LVC ALVC AVC AUC 4016 -/˔ 4316 -/˔ -/˔ 350 ʷ ʷ 636 ʷ 637 ʷ 616 ʷ 617 630 ʷ 631 ʷ 632 ʷ ʷ 633 ʷ 634 ʷ ʷ 635 ʷ 1250 ʷ Status ˔: Product available in technology indicated *: New product planned in technology indicated ʷ: Discontinued ˙: Not recommended for new designs HC: SN74HCxx / CD74HCxx HCT: SN74HCxx / CD74HCTxx BCT: SN74BCTxx / SN64BCTxx AC: 74AC11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACxx / CD74ACxx ACT: 74ACT11xxx (Product available in reduced-noise advanced CMOS: 11000 Series) / SN74ACTxx / CD74ACTxx MEMORY REFRESH CONTROLLERS MEMORY CYCLE CONTROLLER MEMORY REFRESH CONTROLLERS MEMORY REFRESH CONTROLLERS Device MEMMORY MAPPERS MEMMORY MAPPERS Descriotion Device 32BIT PARALLEL ERROR DETECTION CORRECTION CIRCUIT 4BIT SHIFTERS MEMMORY MAPPERS WITH LATCH MEMMORY MAPPERS WITH LATCH MULTI-MODE LATCH ANALOG SWITCHES WITH LEVEL TRANSLATION QUAD BILATERAL SWITCHES 3-8 MEMORY DECIDER HARD DISK DRIVER DUAL PULSE SYNCHRONIZERS/DRIVERS CRYSTAL-CONTOROLLED OSCILLATORS CRYSTAL-CONTOROLLED OSCILLATORS 8BIT PARALLEL ERROR DETECTION CORRECTION CIRCUIT DIGITAL PHASE-LOCK LOOP Descriotion DeviceDescriotion QUAD COMPLEMENTARY-OUTPUT LOGIC 16BIT PARALLEL ERROR DETECTION CORRECTION CIRCUIT Technology

QUADRUPLE 2-INPUT POSITIVE-NAND GATES WITH OPEN-COLLECTOR OUTPUTS positive logic: Y = A•B HEX INVERTER BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS positive logic: Y = A See page 231 See page 232 See page 233 See page 234 See page 235 See page 236 See page 236 See page 237 QUADRUPLE 2-INPUT POSITIVE-NAND GATES positive logic: Y = A•B HEX INVERTERS positive logic: Y = A QUADRUPLE 2-INPUT POSITIVE-NAND GATES WITH OPEN-COLLECTOR OUTPUTS positive logic: Y = A•B U04 HEX INVERTERS positive logic: Y = A QUADRUPLE 2-INPUT POSITIVE-NOR GATES positive logic: Y = A + B HEX INVERTERS WITH OPEN-DRAIN OUTPUTS positive logic: Y = A

HEX BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS positive logic: Y = A TRIPLE 3-INPUT POSITIVE-AND GATES positive logic: Y = A•B•C QUADRUPLE 2-INPUT POSITIVE-AND GATES positive logic: Y = A•B HEX SCHMITT-TRIGGER INVERTERS positive logic: Y = A QUADRUPLE 2-INPUT POSITIVE-AND GATES WITH OPEN-COLLECTOR OUTPUTS positive logic: Y = A•B HEX INVERTER BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS positive logic: Y = A TRIPLE 3-INPUT POSITIVE-NAND GATES positive logic: Y = A•B•C HEX SCHMITT-TRIGGER BUFFER positive logic: Y = A

DUAL 4-INPUT POSITIVE-NOR GATES WITH STROBE positive logic: Y = G (A + B + C + D) DELAY ELEMENTS See page 244 See page 245 See page 246 See page 246 See page 247 See page 247 See page 248 See page 248 HEX SCHMITT-TRIGGER INVERTERS positive logic: Y = A QUADRUPLE 2-INPUT HIGH-VOLTAGE INTERFACE POSITIVE-NAND GATES positive logic: Y = AB DUAL 4-INPUT POSITIVE-NAND GATES positive logic: Y = A•B•C•D TRIPLE 3-INPUT POSITIVE-NOR GATES positive logic: Y = A + B + C DUAL 4-INPUT POSITIVE-AND GATES positive logic: Y = A•B•C•D 8-INPUT POSITIVE-NAND GATES positive logic: NC-No internal connection NC-No internal connection NC-No internal connection

positive logic: Y = A + B QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS WITH OPEN-COLLECTOR OUTPUTS positive logic: Y = A•B QUADRUPLE 2-INPUT POSITIVE-NOR BUFFERS WITH OPEN-COLLECTOR OUTPUTS positive logic: Y = A + B 4-LINE-TO-10-LINE DECODERS (1 of 10) HEX NONINVERTERS WITH OPEN-COLLECTOR OUTPUTS positive logic: Y = A BCD-TO-DECIMAL DECODERS/DRIVERS QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS positive logic: Y = A•B HEX BUFFER GATE

3–4 VCC 3D 4D 4Q 1Q 2Q 2Q ENABLE 1–2 GND 3Q 3Q 1516 Q Q D G D G Q Q Q G D Q D G Q Q 1234567 14 13 12 11 10 9 8 AEFG HI GND VCC D CBKJY VCC 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 A<B IN A=B IN A>B IN A>B OUT A=B OUT A<B OUT A3 B2 A1 B1 A0 DATA INPUT A<B A=B A>B A>B A=B A<B GND A3 A1 B1 A0 A2 B0B2 DATA INPUTS CASCADE INPUTS OUTPUTS 1234567 14 13 12 11 10 9 8 1CK 1CLR 1K V CC 2CK 2CLR 2J 1J 1Q 1Q GND 2K 2Q 2Q QQ K CK J Q J CLR Q K CLR CK 1234567 14 13 12 11 10 9 8 1A 2A 2B 2C 2D 2Y GND VCC 1B 1D 1C 1Y MAKE NO EXTERNAL CONNECTION 1234567 14 13 12 11 10 9 8 1CLR 1D 1CK 1PR 1Q 1Q GND VCC 2CLR 2D 2CK 2PR 2Q 2Q CLR PRDQ Q CK Q QD CK CLR PR 165 Pin Assignments DUAL J-K FLIP-FLOPS WITH CLEAR See page 260 See page 261 See page 262 See page 264 See page 266 See page 267 AND-OR-INVERT GATES \51, \S51 DUAL 2-WIDE 2-INPUT positive logic: Y = AB + CD DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET AND-OR-INVERT GATES \`LS51 2-WIDE 3-INPUT, 2-WIDE 2-INPUT positive logic: 1Y = (1A 1B 1C) + (1D 1E 1F) 4-BIT BISTABLE LATCHES 4-2-3-2 INPUT AND-OR INVERT GATES positive logic: Y = ABCD + EF + GHI + JK 4-BIT MAGNITUDE COMPARATORS 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC f ga bcde GNDADRB IN- PUT RB OUT- PUT LAMP TEST CB f gab CL T BI/ RBO RBI D AB OUTPUTS cde INPUTS INPUTS See page 258 BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS

A 14 13 12 11 10 9 8 1 2 3 4 5 6 7 QA QD QB BD INPUT R0 (1) R0 (2) NC V CC Q9 (1) Q9 (2) NC Q A QD GND Q B QC INPUT BD A QC Q9 (2) 14 13 12 11 10 9 8 1 2 3 4 5 6 7 1J 1Q 1K VCC GND 1CK 2K 2CK 2J 1CLR 2CLR 1Q 2Q J CKKCK Q CLR CLR QQQ K J A 14 13 12 11 10 9 8 1 2 3 4 5 6 7 R0 (1) QA QD QC INPUT B NC NC NC V CC R0 (1) R0 (2) NC Q A QB GND Q C QD INPUT B A QD R0 (2) 2QVCC 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 1CLR 1J 1CK 1PR GND 2CLR 2CK 2PR2J 2Q CK KQK CLR J Q CLR PRJ CK Q Q 1K 1Q PR A 14 13 12 11 10 9 8 1 2 3 4 5 6 7 R0 (1) R0 (2) QA QD QB INPUT B R0 (1) R0 (2) NC V CC NC NC NC Q A QD GND Q B QC INPUT B A QC 2Q1Q VCC 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 1CK 1K 1J 1PR 1Q GND 2K 2J2CK 2Q2CLR 2PR1CLR CLRK CK JQ Q PR PR Q Q J CK K CLR VCC 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 BEFAZY ENABLE OUTPUT GND D CASCADE INPUT STROBE B CLEAR CLOCKC CK RATE INPUT ENA- BLEUNITY/ RATE INPUTS OUTPUTS D C CLEAR UNITY/ CASCADE ENA- BLE INPUT STROBE EFAZY ENABLE OUTPUT Pin Assignments 166 See page 269 See page 270 See page 271 See page 272 See page 274 See page 276 See page 278 DECADE COUNTER 107 DUAL J-K FLIP-FLOPS WITH CLEAR DIVIDE-BY-TWELVE DECODE COUNTERS 109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET 4-BIT BINARY COUNTERS 112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SYNCHRONOUS 6-BIT BINARY RATE MULTIPLIERS 14 13 12 11 10 9 8 1 2 3 4 5 6 7 1B 1Y 2A 2B 2Y GND 4A 4Y 3B 3A 3YVCC QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES positive logic: Y = A ≈ B or Y = AB + AB See page 268 NC-No internal connection NC-No internal connection NC-No internal connection

Q Q Q Q CLR 14 13 12 11 10 9 8 1 2 3 4 5 6 7 1A 1B 2Y 2A 2B GND 4B 4A 3Y 3B 3AVCC OUTPUT GNDVCC 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 211 RANGE ENABLE RANGE OUTPUT VCC GND FREQUENCY CONTROL 1Cext RNG FREQ CONT FREQ CONT RNG EN Cext Cext EN Y Y 2Cext ENABLE 14 13 12 11 10 9 8 1 2 3 4 5 6 7 1B 1Y 2A 2B 2Y GND 4A 4Y 3B 3A 3YVCC 14 13 12 11 10 9 8 1 2 3 4 5 6 7 1C 1A 1Y 2C VCC GND 4C 4A 4Y 3C 3A 2A 2Y Q 14 13 12 11 10 9 8 1 2 3 4 5 6 7 A1 A2 B1 B2 VCC GND Rext/ Cext NC Cext NC Rint CLR Q Q Q CLR 14 13 12 11 10 9 8 1 2 3 4 5 6 7 1C 1A 1Y 2C VCC GND 4C 4A 4Y 3C 3A 2A 2Y 167 Pin Assignments 125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS positive logic: Y = A See page 281 See page 282 See page 283 See page 284 See page 285 See page 286 See page 286 122 RETRIGGERABLE MONOSTABLE MULTIVIBRATORS 126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS positive logic: Y = A 123 DUAL RETRIGGERABLE MONOSTABLE MULTIVIBARATORS WITH SCHMITT-TRIGGER INPUTS 128 SN54128...75-Ω LINE DRIVER SN74128...50-Ω LINE DRIVER positive logic: Y = A + B 124 DUAL VOLTAGE-CONTROLLED OSCILLATORS 132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT TRIGGER INPUTS positive logic: Y = A•B NC 14 13 12 11 10 9 8 1 2 3 4 5 6 7 NC A1 A2 VCC GND NC Rext/ Cext Cext Rint BQ Q Q NC Q See page 280 121 MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS NC-No internal connection NC-No internal connection

G G GL G2 VCC 16 15 14 13 12 11 10 9 12 3 45 6 7 8 ABC G 1 Y 7 G N D Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y0 Y1 Y2 Y3 Y4 Y5 Y6A BC GL G2 G1 Y7 DATA OUTPUTS SELECT ENABLE OUTPUT 14 13 12 11 10 9 8 1 2 3 4 5 6 7 1B NC 1C 1D 1Y GND 2C NC 2B 2A 2YVCC VCC 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 ABC G 1 Y7 GND Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y0 Y1 Y2 Y3 Y4 Y5 Y6A BC G 1 Y7 DATA OUTPUTS SELECT ENABLE OUTPUT G2A G2B G2A G2B B AVCC 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 12 56 G N D CD 987 OUTPUTS OUTPUTS AB CD 0 12 34 56 78 9 BCD-TO-DECIMAL PARALLEL INPUTS Pin Assignments See page 287 See page 288 See page 290 See page 292 See page 294 See page 295 168 136 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES WITH OPEN COLLECTOR OUTPUTS positive logic: Y = A•B = AB + AB 139 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS 137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES 140 DUAL 4-INPUT POSITIVE-NAND 50-Ω LINE DRIVERS positive logic: Y = ABCD 138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXRS 145 BCD-TO-DECIMAL DECODERS/DRIVERS VCC 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 ABCDEF G GND MLK J I HY 133 13-INPUT POSITIVE-NAND GATES positive logic: See page 287 NC-No internal connection

A I4 I5 I6 I7 I8 Y2 Y1 GND NC Y3 I3 I2 I1 I9 Y0 INPUTS INPUTS OUTPUTS VCC 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 D2 D1 D0 Y W S D4 D5 D6 D7 A B C 32 10 YW STROBE GND 4567ABC DATA INPUTS DATA INPUTS DATA SELECT OUTPUTS VCC 16 15 14 13 12 11 10 9 1 23 4 5 6 7 8

567 E I A 2 A 1

4567 E I A 2 A 1 G N D

B SELECT 1C3 1C2 1C1 1C0 OUTPUT GND STROBE A SELECT 2C3 2C2 2C1 2C0 OUTPUT DATA INPUTS DATA INPUTS 2C3 2C2 2C1 2C0 2Y AABB AABB 1Y1C01C11C21C3 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 E5 E4 E3 E2 E1 E0 S E9 E10 E11 E12 E13 E14 E15

543210 STROBE W

C W A B B D D DATA SELECT DATA INPUTS DATA SELECTDATA INPUTS A 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 2345678 BCD 1 5 1 4 23456789 BCD 1 5 1 4VCC 13 0 11 GND A OUTPUTS OUTPUTSINPUTS G2 G1 G2 G1 Pin Assignments See page 296 See page 298 See page 300 See page 302 See page 304 See page 306 169 147 10-LINE TO 4-LINE BCD PRIORITY ENCODER 151 8-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS 148 8-LINE TO 3-LINE PRIORITY ENCODERS 153 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS 150 16-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER 154 4-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS NC-No internal connection

T GNDENABLE P DCBACLOCKCLEAR CK OUTPUTS DATA INPUTS ENABLE PDCBA QA QB QC QD ENABLE T LOAD RIPPLE CARRY OUTPUT CLEAR LOAD 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC STROBE 4A 4B 4Y 3A 3B 3Y GND2Y2B2A1Y1B1ASELECT INPUTS INPUTS INPUTS INPUTS OUTPUTS OUTPUTS OUTPUTS OUTPUTS G 4A 4B 4Y 3A 3B 2Y2B2A1Y1B1A S 14 13 12 11 10 9 8 1 2 3 4 5 6 7 VCC QF QE CLEAR CLOCK GNDQDQCQBQABA QGQH SERIAL INPUTS OUTPUTS OUTPUTS QDQCQBQAB QF QE CLEARQGQH A CK 20 19 18 17 16 15 14 13 5 6 7 8 9 10 11 12 DG 2 G1 15 14 13 12 11 GND10987654 24 23 22 21 1 2 3 4 VCC A BC 2103 10987654213 0 11 DG 2 G1 15 14 13 12A BC INPUTS OUTPUTS OUTPUTS 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC CLOCK INHIBIT DCBA SERIAL INPUT OUTPUT QH GNDOUTPUT QH HGFECLOCKSHIFT/ LOAD CK HGFEQ H SHIFT/ LOAD CLOCK INHIBIT DCBA SERIAL IN QH PARALLEL INPUTS PARALLEL INPUTS Pin Assignments See page 308, 310 See page 312, 314 See page 316 See page 318, 320 See page 322 See page 324 170 155 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS 156 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS WITH OPEN-COLLECTOR OUTPUTS 161 163 4-BIT SYNCHRONOUS BINARY COUNTERS 157 158 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS 164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS 159 4-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH OPEN-COLLECTOR OUTPUTS 165 PARALLEL-LOAD 8-BIT SHIFT REGISTERS

H OUTPUT QH GE C LEAR GNDCLOCKCLOCK INHIBIT DCBASERIAL INPUT SHIFT/ LOAD HQ H GFE BCD CLOCK INHIBIT CKA SERIAL INPUT CLEAR F PARALLEL INPUTS PARALLEL INPUTS 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC CLEAR 1D 2D 3D 4D G2 G1 GNDCLOCK4Q3Q2Q1QNM CLEAR 1D 2D 3D 4D DATA ENABLE OUTPUT CONTROL DATA ENABLE INPUTSDATA INPUTS OUTPUT CONTROL OUTPUTS CK4Q3Q2Q1Q 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC RIPPLE CARRY OUTPUT QA QB QC QD ENABLE T LOAD GNDDCBACKU/D RIPPLE CARRY OUTPUT QA QB QC QD ABC DCK ENABLE P ENABLE T ENABLE P UP/DOWN LOAD OUTPUTS DATA INPUTS 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC 6Q 6D 5D 5Q 4D 4Q CLOCK GND3Q3D2Q2D1D1QCLEAR QD CK CLEAR DQ CLEAR DQ CLEAR CK CK CK CKCK QD DQ DQ CLEAR CLEAR CLEAR 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC DATA D1 WA WB WRITE READ Q1 Q2 GNDQ3Q4RARBD4D3D2 D1 WA WB GW GR Q1 D4 R A Q4 Q3D3 OUTPUTSWRITE SELECT ENABLE Q2D2 RB DATA READ SELECT OUTPUTS 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC 4Q 4Q 4D 3D 3Q 3Q CLOCK GND2Q2Q2D1D1Q1QCLEAR CK D CLR Q Q Q DCK CLR QQ D CK CLR Q CK CLR Q Q D Pin Assignments See page 326 See page 328 See page 330 See page 332 See page 334 See page 335 171 166 8-BIT PARALLEL-LOAD SHIFT REGISTERS 173 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS 169 SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS 174 HEX D-TYPE FLIP-FLOPS WITH CLEAR 170 4-BY-4-REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS 175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

B2 A3 B3 G C n+4 PA = B F3 GNDF2F1F0MCnS0S1 INPUTS OUTPUTS INPUTS 24 23 22 21 1 2 3 4 VCC A1 B1 A2 S3A0B0 S2 OUTPUTS F2F1F0MCnS0S1S3A0 S2 B2 A3 B3 G C n+4 PA = BA1 B1 A2 F3B0 P1 Q1 Q0 CPD CPU Q2 Q3 VCC P0 MR TCD TCU PL P2 1 2 3 4 5 6 7 16 15 14 13 12 11 10 GND 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC P2 G2 C n Cn+x Cn+y G GNDP OUTPUT P3G3P0G0P1G1 INPUTS OUTPUTS INPUTS Cn+z P2 G2 C n Cn+x Cn+y G Cn+z P3G3P0G0P1 P 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC DATA A CLEAR BO- RROW CARRY LOAD DATA C GNDQDQCCOUNT UP COUNT DOWN QAQBDATA B INPUT DATA D INPUTS OUTPUTS INPUTS INPUTSOUTPUTS OUTPUTS QDQCQAQB A BO- RROW CARRY LOAD CCLEAR COUNT UP COUNT DOWN BD 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC DATA A CLOCK RIPPLE CLOCK MAX/ MIN LOAD DATA C GNDQDQCDOWN/ UP ENA- BLE QAQBDATA B INPUT DATA D INPUTS OUTPUTS INPUTS INPUTSOUTPUTS OUTPUTS QDQCDN/UPCTENQAQB A RIPPLE CLOCK MAX/ MIN LOAD C 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC QA QB QC QD CLOCK S1 GNDSHIFT LEFT SERIAL INPUT DCBASHIFT RIGHT SERIAL INPUT CLEAR PARALLEL INPUTS QA QB QC QD CLOCK S1 DCBALR CLEAR Pin Assignments See page 336 See page 338 See page 340, 342 See page 344 See page 346 See page 348 172 181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS 192 PRESETTABLE SYNCHRONOUS 4-BIT UP/DOWN COUNTERS 182 LOOK-AHEAD CARRY GENERATOR 193 4-BIT SYNCHRONOUS UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR) 190 SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS 191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS 194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS

1 Rext/

Q Q CLR Q Q CLR 2CLR 2G 18 17 16 15 14 13 56789 1 0 GND2Y11A42Y21A32Y31A22Y4 1234 1G 1A1 12 1120 19 2A11Y42A21Y32A31Y22A41Y1VCC A0 A1 A3 LE OE1 OE0 Y7 VCC Y0 Y1 Y2 Y3 Y4 Y5 1 2 3 4 5 6 7 16 15 14 13 12 11 10 GND Y6 2G 18 17 16 15 14 13 56789 1 0 GND2Y11A42Y21A32Y31A22Y4 1234 1G 1A1 12 1120 19 2A11Y42A21Y32A31Y22A41Y1VCC Pin Assignments See page 350 See page 352 See page 354 See page 356 See page 358 See page 360 173 195 4-BIT PARALLEL-ACCESS SHIFT REGISTERS 238 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS 221 DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS 240 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 237 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES 241 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

W OUT- PUT STROBE0123 24 23 22 21 1 2 3 4 VCC 8 91 0 5674 E11 E12 E13 E14 E15 A BE8 E9 E10 DWGE0E1E2E3E5E6 E4 CE7 DATA INPUTS DATA INPUTS 18 17 16 15 14 13 56789 1 0 GND2Y11A42Y21A32Y31A22Y4 1234 1G 1A1 12 1120 19 2A11Y42A21Y32A31Y22A41Y1VCC 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC 4 56 7 ABC GNDSTROBEWY0123 DATA SELECTDATA INPUTS DATA INPUTS OUTPUTS D4 D5 D6 D7 A B SWYD0D1D2 D3 C A1 A2 A3 A4 A5 A6 A7 A8 GND B1 B2 B3 B4 B5 B6 B7VCC B8G DIR ENABLE 18 17 16 15 14 13 56789 1 01234 12 1120 19 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC OUTPUT CONTROL A SELECT 2C3 2C2 2C1 2CO OUTPUT GNDOUTPUT 1C01C11C21C3B SELECT OUTPUT CONTROL DATA INPUTS DATA INPUTS 2C3 2C2 2C1 2CO BBAA 1Y1C01C11C21C3 1G BBAA 16 15 14 13 12 11 10 9 12345678 VCC f gabcd GNDADRB IN- PUT RB OUT- PUT LAMP TEST C OUTPUTS INPUTS e INPUTS B f g abcde B CL T BI/ RBO RBI D A 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC OUTPUT CONTROL G 4A AB OUTPUT 4Y 3A 3B OUTPUT GND2Y OUTPUT 2B2A1Y OUTPUT 1B1ASELECT INPUTS INPUTS INPUTS INPUTS 2Y2B2A1Y1B1A S G 4A AB 4Y 3A 3B Pin Assignments 174 See page 362 See page 364 See page 366 See page 368 See page 370 See page 372 See page 374 See page 376 243 QUADRUPLE BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 250 1-OF-16 DATA GENERATORS/MULTIPLEXERS WITH 3-STATE OUTPUTS 244 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 251 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS 245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 253 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS 247 BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS 257 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS NC-No internal connection

A Q4Q3 Q5 Q6 Q7 CLEAR G DA B C Q2Q1Q0 Q3 QD CK CLEAR DQ CK CLEAR CLEAR CLEAR QD DQ CK CK 18 17 16 15 14 13 56789 1 0 GND4Q4D3D3Q2Q2D1D 1234 CLEAR 1Q 12 1120 19 CLOCK5Q5D6D6Q7Q7D8DVCC QD CK CLEAR DQ CK CLEAR CLEAR CLEAR QD DQ CK CK 14 13 12 11 10 9 8 1 2 3 4 5 6 7 VCC 2E 2D 2C 2B GND2Y1Y2A1C1B1A 1D1E 18 17 16 15 14 13 56789 1 0 GND2J2CK2K2Q1Q1K1CK 1234 CLEAR 1J 12 1120 19 PRESET3J3CK3K3Q4Q4K4CKVCC CLR K CK J PR Q CLR K CK J PR Q CLR CLR CK CK J Q J Q PR PR K K 16 15 14 13 12 11 10 9 12345678 VCC 4A 4W 4Y 3B 3A 3W GND2Y2W2B2A1Y1W 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC OUTPUT CONTROL G 4A AB OUTPUT 4Y 3A 3B OUTPUT GND2Y OUTPUT 2B2A1Y OUTPUT 1B1ASELECT INPUTS INPUTS INPUTS INPUTS 2Y2B2A1Y1B1A S G 4A AB 4Y 3A 3B 1234567 14 13 12 11 10 9 8 1A 1B 1Y 2Y 2A 2B GND VCC 4B 4A 4Y 3Y 3B 3A 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC 4S 4R 4Q 3S1 3R GND2Q2S2R1Q1S21S11R 3Q3S1 175 Pin Assignments 265 QUADRUPLE COMPLEMENTARY-OUTPUT ELEMENTS positive logic: Y = A, W = A Y = AB, W = AB 279 QUADRUPLE S-R LATCHES See page 378 See page 380 See page 382 See page 382 See page 383 See page 384 See page 386 See page 387 258 QUADRUPLE 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS 266 QUADRUPLE 2-INPUT EXCLUSIVE-NOR GATES WITH OPEN-DRAIN OUTPUTS positive logic: Y = A ≈ B 259 8-BIT ADDRESSABLE LATCHES 273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR 260 DUAL 5-INPUT POSITIVE-NOR GATES positive logic: Y = A + B + C + D + E 276 QUADRUPLE J-K FLIP-FLORS

GNDΣ ODDΣ EVENI INPUT NCHG FEDCB H A EF G INPUTS INPUTS OUTPUTS Σ EVEN Σ ODDI 14 13 12 11 10 9 8 1 2 3 4 5 6 7 VCC INPUT B INPUT AQ A QD GNDNCQBQCNCNCNC RO(1)RO(2) OUTPUTS OUTPUTS BA QARO(1)RO(2) QBQC QD 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC B3 A3 Σ 3A 4 B 4 Σ 4 GNDC0B1A1Σ 1A2B2Σ 2 B3 A3 Σ 3A 4 B 4 Σ 4 C0B1A1Σ 1A2B2 C4Σ 2 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC C DN C N C C LEAR NC GNDQOUTNCCLK2CLK1TPAB NC C DC L R A QCLK2CLK1TPA B 14 13 12 11 10 9 8 1 2 3 4 5 6 7 VCC D CBA GNDPARITY I/O PARITY ERROR I INPUT XMITHG EF INPUTS INPUTS OUTPUTS DCBEF AG PARITY I/O PARITY ERRORIXMITH 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC C DN C N C C LEAR NC GNDQOUTNCCLK2CLK1TPAB NC C DC L R A QCLK2CLK1TPA B 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC C DT P 3 NC CLEAR A GNDQOUTTP2CLK2CLK1TP1EB NC C DT P 3 CLR A QTP2CLK2CLK1TP1E B 16 15 14 13 12 11 10 9 12345678 VCC QA QB QC QD CLOCK WORD SELECT GNDD1D2C2B1A1A2 DATA INPUT DATA INPUTS OUTPUTS QA QB QC QD CK WS D1D2C2B1A1A2 B2 C1 Pin Assignments 176 See page 388 See page 390 See page 392 See page 394 See page 396 See page 398 See page 400 See page 402 280 9-BIT PARITY GENERATORS/CHECKERS 293 4-BIT BINARY COUNTERS 283 4-BIT BINARY FULL ADDERS WITH FAST CARRY 294 PROGRAMMABLE FREQUENCY DIVIDERS/DIGITAL TIMERS 286 9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS WITH BUS DRIVER PARITY I/O PORT 297 DIGITAL PHASE-LOCKED-LOOP FILTERS 292 PROGRAMMABLE FREQUENCY DIVIDERS/DIGITAL TIMERS 298 QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE NC-No internal connection NC-No internal connection NC-No internal connection NC-No internal connection NC-No internal connection

SL Q H´ H/QH GNDCLEARQA´A/QAC/QCE/QEG/QG 1234 VCC S1 12 1120 19 F/QF D/QD B/QB CKSL Q H´ H/QHS1 CLEARQA´A/QAC/QCE/QEG/QGG S0 SR OUTPUT CONTROLS 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC EO GS 3 210 OUTPUT GNDA1A2EI7654 INPUTSOUTPUTS INPUTS OUTPUTS EO GS 3 210 A1A2EI765 A04 16 15 14 13 12 11 10 9 12345678 VCC XTAL XTAL

1 F/2 F V CC´F ´

F/2 F´ F S0 S1 S2 SELECT CONTROL 18 17 16 15 14 13 56789 1 0 WG 3 GNDDATA CONTROL /CLOCK D0D1D2D3D4D5 1234 VCC Y D7 D6 12 1120 19 G1G2 S0 S1 S2WG 3YG 1 G2 DATA C/CD0D1D2D3D4D5D6 D7 SC G2G1 F/QF D/QD B/QB CLOCK SHIFT RIGHT SR 18 17 16 15 14 13 56789 1 0 SHIFT LEFT SL Q H´ H/QH GNDCLEARQA´A/QAC/QCE/QEG/QG 1234 VCC S1 12 1120 19 F/QF D/QD B/QB CKSL Q H´ H/QHS1 CLEARQA´A/QAC/QCE/QEG/QGG S0 SR OUTPUT CONTROLS 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC G2 6A 6Y 5A 5Y 4A 4Y GND3Y3A2Y2A1Y1AG1 Pin Assignments See page 404 See page 406 See page 408 See page 410 See page 412, 414 See page 416 177 299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS 348 8-LINE TO 3-LINE PRIORITY ENCODERS WITH 3-STATE OUTPUTS 321 CRYSTAL-CONTROLLED OSCILLATORS 354 8-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS/TRANSPARENT/ REGISTERS WITH 3-STATE OUTPUTS 356 8-INPUT MULTIPLEXER/REGISTERS 3-STATE 323 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS 365 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

G DQ G QD DQ 18 17 16 15 14 13 56789 1 0 GND4Q4D3D3Q2Q2D1D 1234 ENABLE G 12 1120 19 CLOCK5Q5D6D6Q7Q7D8DVCC QD G DQ G QD DQ GGGG CK CK CK CK CK CK CK CK QD OE DQ OE QD DQ 18 17 16 15 14 13 56789 1 0 GND4Q4D3D3Q2Q2D1D 1234 OUTPUT CONTROL 12 1120 19 ENABLE G5Q5D6D6Q7Q7D8DVCC QD OE DQ OE QD DQ OE OE OE OE G G G G G G G G 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC 6Q 6D 5D 5Q 4D 4Q CLOCK GND3Q3D2Q2D1D1QENABLE G QD CK G DQ G QD G CK CK CK CKCK QD DQ QD GGG Pin Assignments 178 See page 417 See page 418 See page 419 See page 420 See page 422 See page 424 See page 425 See page 426 366 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS 374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS 367 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS 375 4-BIT BISTABLE LATCHES 368 HEX INVERTING BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS 377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE 373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS 378 HEX D-TYPE FLIP-FLOPS WITH CLOCK ENABLE

CLEAR 2 Q A 2 QB 2 QC 2 QD GND1 QD1 QC1 QA1 CLEAR OUTPUTS OUTPUTS QA CLEAR A QB QC CLEAR A QB QC 1 QB QA QD QD 18 17 16 15 14 13 56789 1 0 CS GC A1 A2 S1 GNDB4B3 1234 B1 B2 12 1120 19 S0GB GA A3 A4VCC C4C3C1 16 15 14 13 12 11 10 9 12345678 VCC QA QB QC QD CASCADE OUTPUT QD´ CLOCK GND LOAD SHIFTDCBA SERIAL INPUT OUTPUT CONTROL PARALLEL INPUTS CLEAR OUTPUTS QA QB QC QD QD´ CK SERIAL INPUT OUTPUT CONTROLCLEAR LOAD SHIFT DCBA A1 Y1 A2 Y2 A3 Y3 A4 Y4 GND A8 Y8 A7 Y7 A6 Y6 A5VCC Y5 1 2 3 4 5 6 7 8 9 10 16 15 14 13 12 1120 19 18 17 A1 Y1 A2 Y2 A3 Y3 A4 Y4 A8 Y8 A7 Y7 A6 Y6 A5G2 C2 C1 Q C CLOCKD1 D2 GNDQBB1B2A2A1 VCC QD WORD SELECT QA 16 15 14 13 12 11 10 9 12345678 C2 C1 Q CD1 D2QD QBB1B2A2A1QA WS CK 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC 2A CLEAR OUTPUT

2 QA 2B 2 Q B 2 QC 2 QD

GND1 QD1 QC1 QB1B1 QAOUTPUT CLEAR OUTPUTS OUTPUTS QA CLEAR A B QB QC QD QA CLEAR A B QB QC QD

1 Rext/Cext

1 Cext 1Q 2Q 2CLR 2B 2A

P=Q P0 Q0 P1 Q1 P2 Q2 P3 Q3 GND Q7 P7 Q6 P6 Q5 P5 Q4VCC P4 G 1 2 3 4 5 6 7 8 9 10 16 15 14 13 12 1120 19 18 17 P4G P0 Q0 P1 Q1 P2 Q2 P3 Q3 Q7 P7 Q6 P6 Q5 P5 Q4P=Q 179 Pin Assignments 399 QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE 518 OCTAL BINARY/BCD IDENTITY COMPARATORS WITH ENABLE See page 427 See page 428 See page 429 See page 430 See page 431 See page 432 See page 433 See page 433 390 DUAL 4-BIT DECADE COUNTERS 423 RETRIGGERABLE MONOSTABLE MULTIVIBRATORS positive logic: Y = A 393 DUAL 4-BIT BINARY COUNTERS 442 QUADRUPLE TRIDIRECTIONAL BUS TRANSCEIVERS 395 CASCADABLE SHIFT REGISTERS 465 OCTAL BUFFERS WITH 3-STATE OUTPUTS

P=Q P0 Q0 P1 Q1 P2 Q2 P3 Q3 GND Q7 P7 Q6 P6 Q5 P5 Q4VCC P4 G 1 2 3 4 5 6 7 8 9 10 16 15 14 13 12 1120 19 18 17 P0 Q0 P1 Q1 P2 Q2 P3 Q3 Q7 P7 Q6 P6 Q5 P5 Q4 P=Q G 1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 1524 23 22 21 14 13 OEABLEBA VCC OEABLEAB CEAB CEBA OEBA A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 LEBA GND CEABOEBA A1 A2 A3 A4 A5 A6 A7 A8 LEABCEBA B1 B2 B3 B4 B5 B6 B7 B8 1Q 2Q 3Q 4Q1D 2D 3D 4D GND 8D 7D 6D 5DVCC C8Q 7Q 6Q 5Q 1 2 3 4 5 6 7 8 9 10 16 15 14 13 12 1120 19 18 17 OC D C7 Q D Q D QD C6Q D Q OCD OC D OC QQ D Q OC OCOC OC OC RCO CLK D A DB DC DD ENP GND CCO Q A QB QC QD ENTVCC G SLOAD ALOAD ACLR SCLR 1 2 3 4 5 6 7 8 9 10 16 15 14 13 12 1120 19 18 17 RCO CCO Q A QB QC QD ENTG DA DB DC DD ENP ACLR SCLR ALOAD SLOAD CLK D CK OC D OC CK 7Q8Q D CK D CK 5Q6Q OC OC D OCDOC D OC 2Q1Q D OC CK CKCK CK 8D 7D 6D 5DVCC CLK8Q 7Q 6Q 5Q 1Q 2Q 3Q 4Q1D 2D 3D 4D GND 1 2 3 4 5 6 7 8 9 10 16 15 14 13 12 1120 19 18 17 OC 1D 2D 3D 4D 5D 6D GND VCC ENABLE C OC 7D 8D 2Q 3Q 4Q 5Q 6Q 7Q 8Q 1 2 3 4 5 6 7 8 9 10 16 15 14 13 12 1120 19 18 17 OC C 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 1D 2D 3D 4D 5D 6D 7D 8D A1 A2 A3 A4 A5 A6 A7 A8 GND Y1 Y2 Y3 Y4 Y5 Y6 Y7VCC Y8 1 2 3 4 5 6 7 8 9 10 16 15 14 13 12 1120 19 18 17 1 2 3 4 5 6 7 8 9 10 16 15 14 13 12 1120 19 18 17 1D 2D 3D 4D 5D 6D GND VCC OC CLK CLK OC 7D 8D 2Q 3Q 4Q 5Q 6Q 7Q 8Q 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 1D 2D 3D 4D 5D 6D 7D 8D Pin Assignments 180 See page 434, 435 See page 436 See page 437 See page 438, 439 See page 440 See page 442 See page 444 See page 445 520 OCTAL BINARY/BCD IDENTITY COMPARATORS WITH ENABLE 521 8-BIT IDENTITY COMPARATORS WITH OPEN-COLLECTOR OUTPUTS 543 OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS 533 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS 561 SYNCHRONOUS 4-BIT COUNTERS WITH 3-STATE OUTPUTS 534 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS 563 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS 540 541 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 564 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

C OC 7D 8D 2Q 3Q 4Q 5Q 6Q 7Q 8Q G Q OE D G Q OE D G Q OE D G Q OE D G Q OE D G Q OE D G Q OE D G Q OE D 1 2 3 4 5 6 7 8 9 10 16 15 14 13 12 1120 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 1524 23 22 21 14 13 OC NC D0 D1 D2 D3 D4 D5 D6 D7SCLR NC CLK GND NC CLK VCC SCLR OC D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 1QVCC CLK2Q 3Q 4Q 5Q 6Q 7Q 8Q 1 2 3 4 5 6 7 8 9 10 16 15 14 13 12 1120 19 18 17 1D 2D 3D 4D 5D 6D GNDOC 7D 8D CK Q OE D CK Q OE D CK Q OE D CK Q OE D CK Q OE D CK Q OE D CK Q OE D CK Q OE D 1QVCC ENABLE C2Q 3Q 4Q 5Q 6Q 7Q 8Q 1D 2D 3D 4D 5D 6D GNDOC 7D 8D 1 2 3 4 5 6 7 8 9 10 16 15 14 13 12 1120 19 18 17 OE D Q G OE D Q G OE D Q G OE D Q G OE D Q G OE D Q G OE D Q G OE D Q G 1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 1524 23 22 21 14 13 OC NC D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 SCLR NC CLK GND NC CLK VCC SCLR OC D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 OCRCO CLK D A DB DC DD GND VCC U/D CCO Q A QB QC QD ENT SLOAD ENP ACLR SCLR 1 2 3 4 5 6 7 8 9 10 16 15 14 13 12 1120 19 18 17 DC DD ENP ACLR SCLR U/D SLOAD DA DB OCRCO CCO Q A QB QC QD ENT CLK 1QVCC CLK2Q 3Q 4Q 5Q 6Q 7Q 8Q 1D 2D 3D 4D 5D 6D GNDOC 7D 8D 1 2 3 4 5 6 7 8 9 10 16 15 14 13 12 1120 19 18 17 CK OE D Q CK OE D Q CK OE D Q CK OE D Q CK OE D Q CK OE D Q CK OE D Q CK OE D Q 1 2 3 4 5 6 7 8 12 11 10 916 15 14 13 RCOCCKENRCK CCKG CCLRQA QC QD QE QF QG GND VCC QB QH RCK CCKCCKENG CCLRQA QC QD QE QF QG QH QB RCO 181 Pin Assignments 575 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS 590 8-BIT BINARY COUNTERS WITH 3-STATE OUTPUT REGISTERS See page 446 See page 448 See page 450 See page 452 See page 453 See page 454 See page 455 See page 456 569 SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS WITH 3-STATE OUTPUTS 576 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS 573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS 577 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS 574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS 580 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS NC-No internal connection NC-No internal connection

RCOCCKENRCK CCKCLOAD CCLRQA QC QD QE QF QG GND QB RCO QB QH QC QD QE QF QG QH CCKEN CCLRQA CLOAD RCK CCK 1 2 3 4 5 6 7 8 12 11 1016 15 14 13 9 QH'RCK SCKSER SCLRGQA QC QD QE QF QG GND VCC QB QH' QB QH QC QD QE QF QG QH RCKQA SCKSER SCLRG 1 2 3 4 5 6 7 8 9 10 16 15 14 13 12 1120 19 18 17 RCOCCKEN CCK CCLRGVCC CLOAD G B/QB C/QC D/QD E/QE F/QF G/QG GND RCK CCKEN A/QA H/QH A/QA CCLRCCKENG RCK CCKEN CCKRCKENG RCO CLOADB/QB C/QC D/QD E/QE F/QF G/QG H/QH RCKEN 1 2 3 4 5 6 7 8 12 11 1016 15 14 13 9 SLOAD QH'RCK SCKSER SCLRA CDEF G GND VCC B QH' BH RCK SCK CDEFGH AS E R SCLRSLOAD RCLR QH'RCK SCKSER SCLRQA QC QD QE QF QG GND VCC QB QH' QB QH QC QD QE QF QG QH RCKQA RCLR SCKSER SCLR 1 2 3 4 5 6 7 8 12 11 10 916 15 14 13 SLOAD SCLRSCKENDS B/QB C/QC D/QD E/QE F/QF G/QG GND RCK SCKSER1 A/QA H/QH SER0 RCK 1 2 3 4 5 6 7 8 9 10 16 15 14 13 12 1120 19 18 17 VCC QH' SLOADB/QB C/QC D/QD E/QE F/QF G/QG H/QH QH'G SCLRSCKENDS SCK SER1SER0 G A/QA Pin Assignments See page 458 See page 460 See page 462 See page 464, 466 See page 468 See page 470 182 592 8-BIT BINARY COUNTERS WITH INPUT REGISTERS 595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS 596 8-BIT SHIFT REGISTERS WITH OUTPUT LATCHES 593 8-BIT BINARY COUNTERS WITH INPUT REGISTERS 597 SERIAL-OUT SHIFT REGISTERS WITH INPUT LATCHES 594 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS 598 8-BIT SHIFT REGISTERS WITH INPUT LATCHES

Y Cext FREQ CONT RNG Y CextRNG FREQ CONT FREQ CONTROL RANGE GND OUT- PUT 2Cext 1Cext EN EN FREQ CONT- ROL 14 13 12 11 10 9 8 1 2 3 4 5 6 7 RANGE CX1 CX2 ENABLE Y OUTPUT GND Z OUTPUTNC NC NC V CC EN GND VCC RANGE FREQ CONTROL Cext Z Y ENABLE G A1 A2 A3 A4 A5 A6 A7 A8 GND B1 B2 B3 B4 B5 B6 B7VCC B8 DIR 1 2 3 4 5 6 7 8 9 10 16 15 14 13 12 1120 19 18 17 FREQ CONT- ROL 14 13 12 11 10 9 8 1 2 3 4 5 6 7 RANGE CX1 CX2 ENABLE Y OUTPUT GND Z OUTPUTNC V CC EN GND VCC RANGE FREQ CONTROL Cext Z Y Rext ENABLE G A1 A2 A3 A4 A5 A6 A7 A8 GND B1 B2 B3 B4 B5 B6 B7VCC B8 DIR 1 2 3 4 5 6 7 8 9 10 16 15 14 13 12 1120 19 18 17 Pin Assignments See page 472, 473, 474 See page 475 See page 476 See page 477 See page 478 See page 479 183 620 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 621 OCTAL BUS TRANSCEIVERS 623 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 629 DUAL VOLTAGE-CONTROLLED OSCILLATORS 624 VOLTAGE-CONTROLLED OSCILLATORS 638 OCTAL BUS TRANSCEIVERS 628 VOLTAGE-CONTROLLED OSCILLATORS 639 OCTAL BUS TRANSCEIVERS NC-No internal connection NC-No internal connection

1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 1524 23 22 21 14 13 SELECT AB A1 A2 A3 A4 A5 A6 A7CLOCK AB A8 GND SELECT AB A1 A2 A3 A4 A5 A6 A7 A8 CLOCK AB CLOCK BA B7 SELECT BA ENABLE GBA B1 B2 B3 B4 B5 B6 B8 VCC CLOCK BA B7SELECT BA B1 B2 B3 B4 B5 B6 ENABLE GAB ENABLE GBA A1 A2 A3 A4 A5 A6 A7 A8 GND B1 B2 B3 B4 B5 B6 B7VCC B8 DIR 1 2 3 4 5 6 7 8 9 10 16 15 14 13 12 1120 19 18 17 ENABLE G A1 A2 A3 A4 A5 A6 A7 A8 GND B1 B2 B3 B4 B5 B6 B7VCC B8 DIR 1 2 3 4 5 6 7 8 9 10 16 15 14 13 12 1120 19 18 17 ENABLE G 1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 1524 23 22 21 14 13 VCC B8B4 GND GND B5 B6 B7 PARITY OE B3B2B1 A1 A2 A3 A4 A5 A6 A7 A8 ERROR ODD /EVEN T/R A1 A2 A3 A4 A5 A6 A7 A8 ODD /EVEN T/R OE B8B4 B5 B6 B7 PARITY B3B2B1 ERROR 1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 1524 23 22 21 14 13 SELECT AB DIREC- TION A1 A2 A3 A4 A5 A6 A7CLOCK AB A8 GND SELECT AB DIREC- TION A1 A2 A3 A4 A5 A6 A7 A8 CLOCK AB CLOCK BA B7 SELECT BA CONT- ROL G B1 B2 B3 B4 B5 B6 B8 VCC CLOCK BA B7SELECT BA B1 B2 B3 B4 B5 B6CONT- ROL G OE1 CLR 1 2 3 4 5 6 7 8 9 10 11 12 1D 2D 3D 4D 5D 6D 7D 8D GND 24 23 22 2QVCC 14 13 COE2 PRE OERB OE1 CLR1D 2D 3D 4D 5D 6D 7D 8D 3Q 4Q 5Q 6Q 7Q 8Q1Q 2QOE2 PRE OERB C Pin Assignments See page 480, 482 See page 481, 483 See page 484, 486, 488 See page 490, 492, 494, 496 See page 498 See page 500, 501 184 640 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 642 OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS 651 652 653 654 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS 641 OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS 645 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 657 OCTAL BUS TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS 646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS 647 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH OPEN-COLLECTOR OUTPUTS 648 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS 666 667 8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES WITH 3-STATE OUTPUTS

P 1 2 3 4 5 6 7 8 ABCD QC 15 14 QA QBVCC 12 11 QD RIPPLE CARRY OUTPUT LOAD U/D 10 9 DATA INPUTS RIPPLE CARRY OUTPUT ENABLE T QCQA QB QD ENABLE T CK ENABLE PABCD UP/DOWN LOAD OUTPUTS GNDCLOCK 1 2 3 4 5 6 12 READ/ WRITE NC MODE CONTROL DATA I/O P12 23 22 P14 P13VCC 20 19 P11 CHIP SELECT PARALLEL INPUTS P15 PARALLEL INPUTS P10 P8P15 P6 P5 CK DATA I/O CS P12P14 P13 P11 P10 P9 P8 P7 P6 MODE P0 P1 P2 P3 P4R/W GNDD3 Q3 1 2 3 4 5 6 7 8 D4 R B RA Q4 WRITE 15 14 WA WBVCC 12 11 READ DATA 10 9 DATA D1 GWWA WB GR Q1 D4 R B RA Q4 D2 Q2 Q1 Q2 READ SELECT OUTPUTS D3 Q3 ENABLEWRITE SELECT OUTPUT GNDA2 1 2 3 4 5 6 A3 A4 A5 A6 P2YP 3VCC 20 19 A12 A11 A10 G A2 A3 A4 A5 A6A1 A7 A8 A9 P2YP 3 P 1 P 0 A 12 A11 A10G 1112 GNDSHIFT CLOCK 1 2 3 4 5 6 12 READ/ WRITE STORE CLR STORE CK DATA I/O Y12 23 22 Y14 Y13VCC 20 19 Y11 CHIP SELECT STRAGE REGISTER OUTPUTS Y15 STORE CK STORAGE REGISTER OUTPUT Y10 Y8Y15 Y6 Y5 Y12Y14 Y13 Y11 Y10 Y9 Y8 Y7 Y6 SH CK R/W STORE CLR DATA I/O Y0 Y1 Y2 Y3 Y4 CS P=Q Q7 P7 Q6 P6 Q5 P5 Q4VCC P4 P0 Q0 P1 Q1 P2 Q2 P3 Q3 GNDP>Q 1 2 3 4 5 6 20 19 13 15 14 1112 Q0 P1 Q1 P2 Q2 P3 Q3P0 P=Q Q7 P7 Q6 P6 Q5 P5 Q4 P4P>Q Pin Assignments See page 502 See page 504 See page 506 See page 508 See page 510 See page 512, 514 185 669 SYNCHRONOUS 4-BIT UP/DOWN COUNTERS 674 16-BIT SHIFT REGISTERS 670 4-BY-4 REGISTER FILES WITH 3-STATE OUTPUTS 679 12-BIT ADDRESS COMPARATOR 673 16-BIT SHIFT REGISTERS 682 684 8-BIT MAGNITUDE COMPARATORS NC-No internal connection

NCG2 P=Q Q7 P7 Q6 P6 Q5 P5 Q4 P4 P0 Q0 P1 Q1 P2 Q2 P3 Q3P>Q G1 P0 Q0 P1 Q1 P2 Q2 P3 Q3G1 G2 P=Q Q7 P7 Q6 P6 Q5 P5 Q4 P4P>Q 1 2 3 4 5 6 10 20 19 18 17 VCC 16 15 11 1A1 1Y1 2Y4 2A4 1A2 1Y2 2Y3 2A3 1A3 1Y3 2Y2 2A2 1A4 1Y4 2Y1 2A1 GND P=Q Q7 P7 Q6 P6 Q5 P5 Q4VCC P4 P0 Q0 P1 Q1 P2 Q2 P3 Q3 GND 1 2 3 4 5 6 20 19 13 15 14 1112 Q0 P1 Q1 P2 Q2 P3 Q3P0 P=Q Q7 P7 Q6 P6 Q5 P5 Q4 G G 1 2 3 4 5 6 10 20 19 18 17 VCC 16 15 11 1A1 1Y1 2Y4 2A4 1A2 1Y2 2Y3 2A3 1A3 1Y3 2Y2 2A2 1A4 1Y4 2Y1 2A1 GND GND COUNTER CLOCK 1 2 3 4 5 6 10 ABCD QC 19 18 QA QBVCC 16 15 QD R/C SELECT QCQA QB QD ABCD U/D R/C COUNT- ER CLEAR LOAD ESIST- ER CLOCK RIPPLE CAPPY OUTPUT OUTPUT CONTROL UP/ DOWN CCK CCLR RCK RCO LOAD G 3-STATE OUTPUT DATA INPUTS ENABLE T ENA P ENABLE P ENABLE T 1 2 3 4 5 6 10 20 19 18 17 VCC 16 15 11 1A1 1Y1 2Y4 2A4 1A2 1Y2 2Y3 2A3 1A3 1Y3 2Y2 2A2 1A4 1Y4 2Y1 2A1 GND Pin Assignments See page 516 See page 518 See page 520, 522 See page 524 See page 525 See page 526 186 686 8-BIT MAGNITUDE/IDENTITY COMPARATORS 756 OCTAL BUFFER/DRIVER WITH OPEN-COLLECTOR OUTPUTS 688 8-BIT IDENTITY COMPARATORS 757 OCTAL BUFFER/DRIVER WITH OPEN-COLLECTOR OUTPUTS 697 699 SYNCHRONOUS UP/DOWN COUNTERS WITH OUTPUT REGISTERS AND MULTIPLEXED 3-STATE OUTPUTS 760 OCTAL BUFFERS/DRIVERS WITH OPEN-COLLECTOR OUTPUTS NC-No internal connection

A3 A4 A5 A6 A7 A8 A9 A10 GND Y4 Y5 Y6 Y7 Y8 Y9 Y10Y2 OE2 4 5 6 7 8 9 10 11 12 18 17 16 15 14 1321 20 VCC OE1 1 2 24 23 19 GND 1 2 3 4 5 6 12 24 23 22 21 VCC 20 19 13 OC CLKOC 10Q 10D CLK 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q 1 2 3 4 5 6 10 20 19 18 17 VCC 16 15 11 GND GND 1 2 3 4 5 6 12 24 23 22 21 VCC 20 19 13 OC CLKOC CLK 1D 2D 3D 4D 5D 6D 7D 8D 9D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q CLR CLKEN CLR CLKEN A3 A4 A5 A6 A7 A8 A9 A10 GND Y4 Y5 Y6 Y7 Y8 Y9 Y10Y2 OE2 4 5 6 7 8 9 10 11 12 18 17 16 15 14 1321 20 VCC OE1 1 2 24 23 19 187 Pin Assignments 821 10-BIT BUS-INTERFACE FLIP FLOPS WITH 3-STATE OUTPUTS 828 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS See page 527 See page 528 See page 528 See page 529 See page 530 See page 531 See page 532 See page 532 804 HEX 2-INPUT NAND DRIVERS positive logic: Y = A•B 823 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS 805 HEX 2-INPUT NOR DRIVERS positive logic: Y = A + B 825 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS 808 HEX 2-INPUT AND DRIVERS positive logic: Y = A + B 827 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

B1 B2 B3 B4 B5 B6 B7 B8 PARITY OEB LE OEA A1 A8 ERR CLR GND 1 2 3 4 5 6 12 24 23 22 21 VCC 20 19 13 A2 A3 A4 A5 A6 A7 B1 B2 B3 B4 B5 B6 B7 B8 PARITY OEB CLK OEA A1 A8 ERR CLR GND 1 2 3 4 5 6 12 24 23 22 21 VCC 20 19 13 3Y OPER ZERO OPER=0 T/C T/C S1 6B 6Y 5A 5B 5Y 4A 4B 4Y6A 1A 1B 1Y 2A 2B 2Y 3A 3B 3Y GND 1 2 3 4 5 6 12 24 23 22 21 VCC 20 19 13 OC COC 10Q 10D C 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q GND 1 2 3 4 5 6 12 24 23 22 21 VCC 20 19 13 A2 A3 A4 A5 A6 A7 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 OEAB OEBA A1 A8 A9 A10 GND 1 2 3 4 5 6 12 24 23 22 21 VCC 20 19 13 OC COC C 1D 2D 3D 4D 5D 6D 7D 8D 9D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q CLR PRE CLR PRE GND 1 2 3 4 5 6 12 24 23 22 21 VCC 20 19 13 A2 A3 A4 A5 A6 A7 B1 B2 B3 B4 B5 B6 B7 B8 B9 OEAB2 OEAB1 OEBA1 A1 A8 A9 OEBA2 Pin Assignments 188 See page 533 See page 534 See page 536 See page 537 See page 538 See page 540 See page 542 See page 543 832 HEX 2-INPUT OR DRIVERS positive logic: Y = A + B 853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS 833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS 857 HEX 2-TO-1 UNIVERSAL MULTIPLEXERS WITH 3-STATE OUTPUTS 841 10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS 861 10-BIT TRANSCEIVERS WITH 3-STATE OUTPUTS 843 9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS 863 9-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 1D 2D 3D 4D 5D 6D 7D 8D 2Q 3Q 4Q 5Q 6Q 7Q 8Q C 1D 2D 3D 4D 5D 6D 7D 8D GND 2Q 3Q 4Q 5Q 6Q 7Q 8QVCC C OERB OERBGND 1 2 3 4 5 6 12 24 23 22 21 VCC 20 19 13 CLR 1Q1 1Q2 1Q3 1Q4 2Q1 2Q2 2Q3 2Q4 1OC ENABEL 1D1 ENABEL 2C 2CLR 1CLR 2OC1D2 1D3 1D4 2D1 2D2 2D3 2D4 CLR D1 D2 D3 D4 D1 D2 D3 D4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OC OC C C 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 2D 3D 4D 5D 6D 7D 8D 2Q 3Q 4Q 5Q 6Q 7Q 8Q 2D 3D 4D 5D 6D 7D 8D 9D 2Q 3Q 4Q 5Q 6Q 7Q 8QVCC 9Q OERB C OERB GND C OEQ OEQ CLR CLR GND 1 2 3 4 5 6 12 24 23 22 21 VCC 20 19 13 PRE 1OC 1CLK 1D1 2CLK 2PRE 1PRE 2OC1D2 1D3 1D4 2D1 2D2 2D3 2D4 PRE D1 D2 D3 D4 D1 D2 D3 D4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OC OC CLK CLK 1Q1 1Q2 1Q3 1Q4 2Q1 2Q2 2Q3 2Q4 GND 1 2 3 4 5 6 12 24 23 22 21 VCC 20 19 13 CLR 1Q1 1Q2 1Q3 1Q4 2Q1 2Q2 2Q3 2Q4 1OC 1CLK 1D1 2CLK 2CLR 1CLR 2OC1D2 1D3 1D4 2D1 2D2 2D3 2D4 CLR D1 D2 D3 D4 D1 D2 D3 D4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OC OC CLK CLK GND 1 2 3 4 5 6 12 24 23 22 21 VCC 20 19 13 QA A QB B QC C QD D QE E QF F QG G QH H CLK ENABEL P RCO ENABEL T RCO S1 ABCDEFGH EN T QA QB QC QD QE QF QG QH CLKEN P GND 1 2 3 4 5 6 12 24 23 22 21 VCC 20 19 13 P<Q IN P>Q IN PLE P>QOUT P>QOUT L/A P<QOUT L/A P7 P6 P5 P4 P3 P2 P1 P0PLE P<QOUT P<QIN P>QIN Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 189 Pin Assignments 874 DUAL 4-BIT D-TYPE EDGE-TRIGGERD FLIP-FLOPS WITH 3-STATE OUTPUTS 992 9-BIT D-TYPE TRANSPARENT READ-BACK LATCH WITH 3-STATE OUTPUTS See page 544, 546 See page 548 See page 550 See page 551 See page 552 See page 554 See page 556 See page 557 867 869 SYNCHRONOUS 8-BIT UP/DOWN COUNTERS 876 DUAL 4-BIT D-TYPE EDGE-TRIGGERD FLIP-FLOPS WITH 3-STATE OUTPUTS 870 DUAL 16-BY 4-BIT REGISTER FILES 885 8-BIT MAGNITUDE COMPARATORS 873 DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS 990 8-BIT D-TYPE TRANSPARENT READ-BACK LATCH

24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 2D 3D 4D 5D 6D 7D 8D 2Q 3Q 4Q 5Q 6Q 7Q 8Q 2D 3D 4D 5D 6D 7D 8D 9D 2Q 3Q 4Q 5Q 6Q 7Q 8QVCC 9Q OERB C OERB GND C 10Q 10Q 10D 10D 123 20 18 1D 2D VCC 5D 6D 7D 8D RD 8Q OE CLK T/C GND CLR EN 14 13 12 11 10 9 8 1 2 3 4 5 6 7 1B 1Y 2A 2B 2Y GND 4A 4Y 3B 3A 3YVCC 14 13 12 11 10 9 8 1 2 3 4 5 6 7 1B 1Y 2A 2B 2Y GND 4A 4Y 3B 3A 3YVCC 14 13 12 11 10 9 8 1 2 3 4 5 6 7 1B 1Y 2A 2B 2Y GND 4A 4Y 3B 3A 3YVCC 14 13 12 11 10 9 8 1 2 3 4 5 6 7 1Y 2A 2Y 3A 3Y GND 6Y 5A 5Y 4A 4YVCC 14 13 12 11 10 9 8 1 2 3 4 5 6 7 1Y 2A 2Y 3A 3Y GND 6Y 5A 5Y 4A 4YVCC 14 13 12 11 10 9 8 1 2 3 4 5 6 7 1Y 2A 2Y 3A 3Y GND 6Y 5A 5Y 4A 4YVCC Pin Assignments 190 See page 558 See page 559 See page 560 See page 560 See page 561 See page 561 See page 562 See page 562 994 10-BIT D-TYPE TRANSPARENT READ-BACK LATCH 1005 HEX INVERTING BUFFERS WITH OPEN-COLLECTOR OUTPUTS 996 8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES 1008 QUADRUPLE 2-INPUT POSITIVE-AND BUFFER/DRIVER 1000 QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS/DRIVERS 1032 QUADRUPLE 2-INPUT POSITIVE-OR BUFFERS/DRIVERS positive logic: Y = A + B 1004 HEX INVERTING DRIVERS 1034 HEX DRIVERS

20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4VCC 2A12G 1A1 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4VCC 2A12G 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 A2 A3 A4 A5 A6 A7 A8 GND B1 B2 B3 B4 B5 B6 B7VCC B8G DIR ENABLE 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 A2 A3 A4 A5 A6 A7 A8 GND B1 B2 B3 B4 B5 B6 B7VCC B8G DIR ENABLE 1A1 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4VCC 2A12G 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 A2 A3 A4 A5 A6 A7 A8 GND B1 B2 B3 B4 B5 B6 B7VCC B8G DIR ENABLE 191 Pin Assignments 1404 OSCILLATOR DRIVER FOR CRYSTAL OSCILLATOR OR CERAMIC RESONATOR See page 563 See page 564 See page 564 See page 565 See page 566 See page 567 See page 568 1035 HEX NONINVERTING BUFFERS WITH OPEN-COLLECTOR OUTPUTS 1640 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 1244 OCTAL BUFFERS AND DRIVERS WITH 3-STATE OUTPUTS 1645 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 1245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 2240 OCTAL BUFFERS AND LINE/MOS DRIVERS WITH 3-STATE OUTPUTS 1240 OCTAL BUFFER AND LINE DRIVER WITH 3-STATE OUTPUTS See page 563

1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4VCC 2A1 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 A2 A3 A4 A5 A6 A7 A8 GND B1 B2 B3 B4 B5 B6 B7VCC B8G DIR ENABLE 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 A2 A3 A4 A5 A6 A7 A8 Y2 Y3 Y4 Y5 Y7 Y8 Y9 A2 A3 A4 A5 A6 A7 A8 A9 Y2 Y3 Y4 Y5 Y6 Y7 Y8VCC Y9 OE1 GND Y10 Y10 A10 A10 OE2 OE1 OE2 OUTPUTS 18 17 16 15 14 13 56789 1 0 OE 8Q 7Q 6Q 5Q GND4Q3Q 1234 1Q 2Q 12 1120 19 LE8D 7D 6D 5DVCC 4D3D1D A1 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 A2 A3 A4 A5 A6 A7 A8 Y2 Y3 Y4 Y5 Y7 Y8 Y9 A2 A3 A4 A5 A6 A7 A8 A9 Y2 Y3 Y4 Y5 Y6 Y7 Y8VCC Y9 OE1 GND Y10 Y10 A10 A10 OE2 OE1 OE2 OUTPUTS Vbat 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 1A 2A 1B 2B 2G 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 1A 2A 1B 2B 2G GND 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2VCC 2Y3 Vbat VS VS SD 1G G SD 1G G A1 A2 A3 A4 A5 A6 A7 A8 GND Y1 Y2 Y3 Y4 Y5 Y6 Y7VCC Y8 1 2 3 4 5 6 7 8 9 10 16 15 14 13 12 1120 19 18 17 Pin Assignments 192 See page 570 See page 571 See page 572 See page 573 See page 574 See page 574 See page 575 2244 OCTAL BUFFERS AND LINE/MOS DRIVERS WITH 3-STATE OUTPUTS 2541 OCTAL LINE DRIVER/MOS DRIVER WITH 3-STATE OUTPUTS 2245 OCTAL TRANSCEIVER AND LINE/MOS DRIVERS WITH 3-STATE OUTPUTS 2827 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 2373 25-Ω OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS 2828 10-BIT BUS/MOS MEMORY DRIVERS WITH 3-STATE INVERTING 2414 MEMORY DECODER WITH ON-CHIP SUPPLY VOLTAGE MONITOR 1A1 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4VCC 2A12G 2241 OCTAL BUFFERS AND LINE/MOS DRIVERS WITH 3-STATE OUTPUTS See page 569

24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 B6 B5 B4 B3 B2 B1 A7 A6 A5 A4 A2 A1 B6 B5 B4 B3 B2 B1 CLKAB A7 A6 A5 A4 A3 A2 A1VCC GND CLKAB CLKBA CLKBA CEBA CEAB OUTPUTS OEBA OEBA OEAB CEBA OEAB CEAB 14 13 12 11 10 9 8 1 2 3 4 5 6 7 1A 1B 1C 1D NC GND 2D 2C 2B 2A NCVCC VCC 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 QM QN QF QE QG QD QK QJ QH QI CLR CLK QA QL QM QN QF QE QG QD GND QK QJ QH QI CLR CLK Q A QL OUTPUTS OUTPUTS OUTPUT 1Q1 16 15 14 13 5678 910 2CP 2D 2Q 1 2Q2 1MR GND 1234 2Q3 1Q0 12 11 2MR 2Q 0 1Q3 1CPVCC 1D1Q2 14 13 567 8910 1E 4Z 2E GND 1234 1Z 2Y 12 11 4E 4Y 3Z 3YVCC 3E2Z 16 15 14 13 12 11 10 9 12345678 VCC CLR CLK CLKEN CO Y9 Y4 GNDY3Y7Y6Y2Y0Y1 OUTPUTS OUTPUTS CLR CLK CO Y9 Y4 Y6Y2Y0Y1 Y3 Y8Y5 193 Pin Assignments 4015 DUAL 4-STAGE STATIC SHIFT REGISTER See page 578 See page 579 See page 580 See page 581 See page 582 See page 583 2953 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS 4016 QUAD BILATERAL SWITCH 4017 DECADE COUNTERS/DIVIDER 4002 DUAL 4-INPUT POSITIVE-NOR GATES positive logic: Y = A + B + C + D 4020 14-STAGE BINARY COUNTERS 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 B6 B5 B4 B3 B2 B1 A7 A6 A5 A4 A2 A1 B6 B5 B4 B3 B2 B1 CLKAB A7 A6 A5 A4 A3 A2 A1VCC GND CLKAB CLKBA CLKBA CEBA CEAB OUTPUTS OEBA OEBA OEAB CEBA OEAB CEAB See page 576 2952 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS NC-No internal connection VCC 14 13 12 11 10 9 8 1 2 3 4 5 6 7 CLR Q G QF QE QD QA QB QC CLK CLR Q G QF QE QD GND NC Q A QB NC Q C NC CLK OUTPUTS OUTPUTS OUTPUT 4024 7-STAGE BINARY COUNTERS See page 584 NC-No internal connection

PCPOUT PC1OUT COMPIN VCOOUT INH C1 A C1B GND PC3OUT SIGIN PC2OUT R2 R1 DEMOUT VCOIN 123 16 14 2Y0 2Y2 2-COM VCC 1Y2 1Y1 2Y3 1-COM 2Y1 1Y0 INH 1Y3 GND A GND B VCC 1Y 1A 2Y 2A 3Y 3A NC 6Y 6A NC 5Y 5A 4Y 1 2 3 4 5 6 7 16 15 14 13 12 11 10 GND 123 16 14 2Y1 2Y0 3Y1 VCC 2-COM 1-COM 3-COM 1Y1 3Y0 1Y0 INH A GND B GND C VCC 1Y 1A 2Y 2A 3Y 3A NC 6Y 6A NC 5Y 5A 4Y 1 2 3 4 5 6 7 16 15 14 13 12 11 10 GND CP LE J1 J2 J3 J4 J16 VCC QJ 5 J 6J 7J 8J 9 1 2 3 4 5 6 7 24 23 22 21 20 19 18 J15 J10 J14 J13 Kc J11 J12 Ka 9 10 11 16 15 14 GND Kb 123 16 14 Y4 Y6 COM VCC Y2 Y1 INH A GND B GND C Pin Assignments 194 See page 585 See page 586 See page 588 See page 588 See page 589 See page 590 See page 591 See page 592 4040 12-STAGE BINARY COUNTERS 4051 8-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS 4046 PHASE-LOCKED-LOOP WITH VCO 4052 DUAL 4-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS 4049 HEX INVERTING BUFFERS 4053 TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS 4050 HEX NON-INVERTING BUFFERS 4059 CMOS PROGRAMMABLE DIVIDE-BY-N COUNTER NC-No internal connection NC-No internal connection

positive logic: Y = A + B + C See page 593 See page 594 See page 595 See page 596 See page 597 See page 598 4060 ASYNCHRONOUS 14-STAGE BINARY COUNTERS AND OSCILLATORS 4094 8-STAGE SHIFT AND STORE BUS REGISTER, THREE-STATE 4066 QUADRUPLE BILATERAL SWITCHES 4067 16-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER 4316 QUAD ANALOG SWITCH WITH LEVEL TRANSLATION B COMMON 18 17 16 15 14 13 56789 1 0 A2 A3 NC A COMMON GNDVEEB1 1234 B2 B3 12 1120 19 LEA1 A0 S0 S1VCC E2E1NC See page 600 4352 ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LATCH A COMMON 18 17 16 15 14 13 56789 1 0 A2 A3 S0 S2 GNDVEEA5 1234 A6 A7 12 1120 19 LEA1 A0 NC S1VCC E2E1NC 4351 ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LATCH See page 599 NC-No internal connection NC-No internal connection

D CVCC 20 19 Y11 LE DATA INPUTS DATA INPUTS Y14G Y15 Y12 Y13 INPUTS INPUTS AB Y 7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Y10DC Y 1 1 Y 8 Y 9 Y 1 4GY 1 5 Y 1 2 Y13LE GNDA 1 2 3 4 5 6 12 BY 7 Y 6Y 5 Y10 23 22 D CVCC 20 19 Y11 LE DATA INPUTS DATA INPUTS Y14G Y15 Y12 Y13 INPUTS INPUTS AB Y 7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Y10DC Y 1 1 Y 8 Y 9 Y 1 4GY 1 5 Y 1 2 Y13LE 18 17 16 15 14 13 56789 1 0 OE8Q7Q6Q5QGND4Q3Q 1234 1Q 2Q 12 1120 19 CLK8D7D6D5DVCC4D3D1D VCC 1E1CP 1Q 0 1Q1 1Q2 1Q3 2Q3 2Q2 2Q1 2Q0 1MR 2MR 2E 1 2 3 4 5 6 7 16 15 14 13 12 11 10 GND 2CP b c 10 9 D3D1 Bt LE fga d eVCC GND LT 7-SEGMENT OUTPUTS BCD INPUTS BCD INPUTS VCC 1E1CP 1Q 0 1Q1 1Q2 1Q3 2Q3 2Q2 2Q1 2Q0 1MR 2MR 2E 1 2 3 4 5 6 7 16 15 14 13 12 11 10 GND 2CP Pin Assignments 196 See page 601 See page 602 See page 604 See page 605 See page 606 See page 607 4514 4-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES 4515 4-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES 4374 OCTAL EDGE-TRIGGERED D-TYPE DUAL-RANK FLIP-FLOP WITH 3-STAE OUTPUTS 4518 DUAL SYNCHRONOUS COUNTERS 4511 BCD-TO-7 SEGMENT LATCH/DECODER/DRIVERS 4520 DUAL SYNCHRONOUS COUNTERS d c 10 9 PHDL fge b aVCC GND 7-SEGMENT OUTPUTS BCD INPUTS See page 610 4543 BCD-TO-7 SEGMENT LATCH/DECODER/DRIVERS VCC 1CX 2CX 1RXCX 2RXCX 1R 1A 1B 1Q 1Q 1 2 3 4 5 6 7 16 15 14 13 12 11 10 GND 1R 1A 1B 1Q 1Q See page 608 4538 DUAL RETRIGGERABLE PRECISION MONO STABLE MULTIVIBRATOR

A 10 9 INHY4 Y2 Y1 Y0 B CVCC GND COM 16 15 10 9 61 42 5 1214 13 83 7 2Y0 2Y2 2-COM 2Y3 2Y1 INH NC GND VCC 1Y2 1Y1 1-COM 1Y0 1Y3 A B D1 OE2D10 Y10 Y3 Y4 Y5 Y6 GND Y7 Y8 Y9 D3 D4 D5 D6 D7 V CC D8 D9 Y1 OE1Y11 Y12 D11 D12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 20 19 18 17 16 1528 27 26 25 24 23 22 21 D1 OE2D9 Y3 Y4 Y5 Y6 GND GND Y7 Y8 D3 D4 D5 D6 V CC VCC D7 D8 Y1 OE1Y10 Y11 D10 D11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 20 19 18 17 16 1528 27 26 25 24 23 22 21 D1 OE2D9 Y3 Y4 Y5 Y6 GND GND Y7 Y8 D3 D4 D5 D6 V CC VCC D7 D8 Y1 OE1Y10 Y11 D10 D11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 20 19 18 17 16 1528 27 26 25 24 23 22 21 D1 OE2D10 Y10 Y3 Y4 Y5 Y6 GND Y7 Y8 Y9 D3 D4 D5 D6 D7 V CC D8 D9 Y1 OE1Y11 Y12 D11 D12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 20 19 18 17 16 1528 27 26 25 24 23 22 21 197 Pin Assignments 5400 11-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS See page 612 See page 614 See page 614 See page 615 See page 615 5401 11-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS 5402 12-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS 4851 8-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER WITH INJEC- TION-CURRENT EFFECT CONTROL 5403 12-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS 4852 DUAL 4-TO-1 CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER WITH INJECTION-CURRENT EFFECT CONTROL See page 612 14 13 12 11 10 9 8 1 2 3 4 5 6 7 1B 1Y 2A 2B 2Y GND 4A 4Y 3B 3A 3YVCC 7002 QUADRUPLE POSITIVE-NOR GATES WITH SCHMITT-TRIGGER INPUTS positive logic: Y = A + B See page 616 14 13 12 11 10 9 8 1 2 3 4 5 6 7 1B 1Y 2A 2B 2Y GND 4A 4Y 3B 3A 3YVCC 7001 QUADRUPLE POSITIVE-AND GATES WITH SCHMITT-TRIGGER INPUTS positive logic: Y = A•B See page 616 NC-No internal connection

PHASE-LOCKED LOOP WITH VCO AND LOCK DETECTOR 7266 QUAD 2-INPUT EXCLUSIVE-NOR GATES positive logic: Y = A ≈ B 7032 QUADRUPLE POSITIVE-OR GATES WITH SCHMITT-TRIGGER INPUTS positive logic: Y = A + B See page 619 8003 DUAL 2-INPUT POSITIVE-NAND GATES

2A1 3A2 3A12A31A4 2A4VCC 2A2 GND VCC 3OE4A4GND3A3 4A3GND 3A4 4A1 4A21A3GND1A1 1A22OE 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 3Y11Y4 VCC 2Y2 GND 2Y3 3Y2 2Y41Y3 2Y1 4Y43Y3 3Y4 VCC 4Y1 4Y2 GND 4OE 4Y3GND 1 2 3 4 48 47 46 45 44 43 42 41 1Y1 1Y21OE GND 2A1 3A2 3A12A31A4 2A4VCC 2A2 GND VCC 3OE4A4GND3A3 4A3GND 3A4 4A1 4A21A3GND1A1 1A22OE 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 3Y11Y4 VCC 2Y2 GND 2Y3 3Y2 2Y41Y3 2Y1 4Y43Y3 3Y4 VCC 4Y1 4Y2 GND 4OE 4Y3GND 1 2 3 4 48 47 46 45 44 43 42 41 1Y1 1Y21OE GND 1A5 2A2 2A11A71A4 1A8VCC 1A6 GND VCC 2OE2A8GND2A3 2A7GND 2A4 2A5 2A61A3GND1A1 1A21OE 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 2B11B4 VCC 1B6 GND 1B7 2B2 1B81B3 1B5 2B82B3 2B4 VCC 2B5 2B6 GND 2DIR 2B7GND 1 2 3 4 48 47 46 45 44 43 42 41 1B1 1B21DIR GND 2A1 3A2 3A12A31A4 2A4VCC 2A2 GND VCC 3OE4A4GND3A3 4A3GND 3A4 4A1 4A21A3GND1A1 1A22OE 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 3Y11Y4 VCC 2Y2 GND 2Y3 3Y2 2Y41Y3 2Y1 4Y43Y3 3Y4 VCC 4Y1 4Y2 GND 4OE 4Y3GND 1 2 3 4 48 47 46 45 44 43 42 41 1Y1 1Y21OE GND 199 Pin Assignments 16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS See page 620 See page 622 See page 624 See page 626 16240 16-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 16241 16-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 16244 16-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

2B7 2B12 2B11GND2B6 2B10VCC 2B8 2B9 GND 1B51B61B71B11 V CC1B12 1B10 1B9 1B82B5GNDLEA2B 2B4OE2B 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 OE1BLEA1BGND 1B4 32 31 30 29 A12A6 A7 A9 GND A10 VCCA11A5 A8 1B2 GND 1B3 LE2B SEL1B1 9 10 11 12 56 55 54 53 52 51 50 49 A3 GNDA2 A4 5 6 7 8 2B1 VCC2B2 A1 1 2 3 4 LE1B 2B3OEA GND 2B7 2B12 2B11GND2B6 2B10VCC 2B8 2B9 GND 1B51B61B71B11 V CC1B12 1B10 1B9 1B82B5GNDCLKENA2 2B4OEB2 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 CLKCLKENA1GND 1B4 32 31 30 29 A12A6 A7 A9 GND A10 VCCA11A5 A8 1B2 GND 1B3 NC SEL1B1 9 10 11 12 56 55 54 53 52 51 50 49 A3 GNDA2 A4 5 6 7 8 2B1 VCC2B2 A1 1 2 3 4 OEB1 2B3OEA GND 2B7 2B12 2B11GND2B6 2B10VCC 2B8 2B9 GND 1B51B61B71B11 V CC1B12 1B10 1B9 1B82B5GNDCLKENA2 2B4OEB 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 CLKCLKENA1GND 1B4 32 31 30 29 A12A6 A7 A9 GND A10 VCCA11A5 A8 1B2 GND 1B3 CLKEN2B SEL1B1 9 10 11 12 56 55 54 53 52 51 50 49 A3 GNDA2 A4 5 6 7 8 2B1 VCC2B2 A1 1 2 3 4 CLKEN1B 2B3OEA GND OEA 1234567 LE1B GND2B3 2B2 V CC CLKENA2 GND2B4 2B5 V CC 2B1 2B6 2B7 2B8 2B9 GND GND GND 2B10 2B11 2B12 1B12 1B11 1B10 1B9 A9 A10 A11 A12 1B8 1B7 GND GND 1B1 1B6 1B2 1B5 VCC VCC 1B3 1B4 CLKENA1 33 32 GND 31 30 SEL CLKOEB LE2B 49545556 29 Pin Assignments 200 See page 628 See page 630 See page 632 See page 634 16260 12-BIT TO 24-BIT MULTIPLEXES D-TYPE LATCH WITH 3-STATE OUTPUTS 16269 12-BIT TO 24-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS 16270 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS 16271 12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS NC-No internal connection

1A 2B4 2B3 3B2 3B1 3B4 3B32A 4A 3A 4B2 4B1 4B4 4B3 1B2 47 42 41 3845 44 43 40 3946 37 32 3135 34 33 30 2936 161512 1918171413 20 21 22 23 24 25 26 27 2811 VCC GND GND VCC OE2 7B2 GND7B18B4OE4 GND8B1 8B3 8A 7B4 7B3 6B2 6B1 6B4 6B37A 5A 6A 5B2 5B1 5B4 5B38B2 V CC GND GND VCC OE3 1D5 2D2 2D11D71D4 1D8VCC 1D6 GND VCC 2LE2D8GND2D3 2D7GND 2D4 2D5 2D61D3GND1D1 1D21LE 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 2Q11Q4 VCC 1Q6 GND 1Q7 2Q2 1Q81Q3 1Q5 2Q82Q3 2Q4 VCC 2Q5 2Q6 GND 2OE 2Q7GND 1 2 3 4 48 47 46 45 44 43 42 41 1Q1 1Q21OE GND 1234567 GND GND 1B92B9 VCC VCCVCCVCC GNDVCC 2B8 A17 A16 A15 A14 A13 GND GND GND 2B101B10 1B11 2B11 2B12 1B12 1B13 2B13 1B14 2B14 A91B8 2B7 1B7 GND GND GND 2B6 1B17 1B6 2B5 1B5 2B4 1B4 2B3 1B3 2B2 1B2 2B1 1B1 2B17 1B18 VCC VCC 1B15 2B15 1B16 2B16 V CC 2B18 57 56 GND V CC A18 V CCGND A11 A10 A12 GND 55 5477 73787980 53 OE SELCLK DIR 201 Pin Assignments 16373 16-BIT TRANSPARENT LATCHES WITH 3-STATE OUTPUTS See page 636 See page 638 See page 640 See page 642 16282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS 16334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS 16344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS NC-No internal connection

1D5 2D2 2D11D71D4 1D8VCC 1D6 GND VCC 2CLK2D8GND2D3 2D7GND 2D4 2D5 2D61D3GND1D1 1D21CLK 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 2Q11Q4 VCC 1Q6 GND 1Q7 2Q2 1Q81Q3 1Q5 2Q82Q3 2Q4 VCC 2Q5 2Q6 GND 2OE 2Q7GND 1 2 3 4 48 47 46 45 44 43 42 41 1Q1 1Q21OE GND 1B4 1B9 1B8GND1B3 1B7VCC 1B5 1B6 GND 2B82B72B62B2 V CC2B1 2B3 2B4 2B51B2GNDSELEN 1B1CLK 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SEL3SEL4GND 2B9 32 31 30 29 2A61A9 2A1 2A3 GND 2A4 VCC2A51A8 2A2 2A8 GND 2A9 SEL1 SEL22A7 9 10 11 12 56 55 54 53 52 51 50 49 1A6 GND1A5 1A7 5 6 7 8 1A3 VCC1A2 1A4 1 2 3 4 SEL0 1A1PRE GND 1B3 2B4 2B3GND1B2 2B2VCC 1B4 2B1 GND 4B44B34B23B2 V CC3B1 3B3 3B4 4B11B1GNDOEB2 SEL0OEB1 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 OEB4OEB3GND SEL1 32 31 30 29 CLKENBACE_SEL0 CE_SEL1 4A GND CLKENAB VCCCLKENB2A 3A LEB4 GND OEA LEAB3 LEAB3LEB3 9 10 11 12 56 55 54 53 52 51 50 49 CLKAB GNDOEB 1A 5 6 7 8 LEB2 VCCLEB1 CLKBA 1 2 3 4 LEAB2 LEBALEAB1 GND 1B3 1B8 1B7GND1B2 1B6VCC 1B4 1B5 GND 2B82B72B62B2 V CC2B1 2B3 2B4 2B51B1GND1CLKBA 1CLKENBA1OEBA 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2OEBA2CLKBAGND 2CLKENBA 32 31 30 29 2A61A8 2A1 2A3 GND 2A4 VCC2A51A7 2A2 2A8 GND 2CLKENAB 2CLKAB 2OEAB2A7 9 10 11 12 56 55 54 53 52 51 50 49 1A5 GND1A4 1A6 5 6 7 8 1A2 VCC1A1 1A3 1 2 3 4 1CLKAB 1CLKENAB1OEAB GND Pin Assignments 202 See page 644 See page 646 See page 648 See page 650 16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS 16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS 16460 4-TO-1 MULTIPLEXED/DEMULTIPLEXED TRANSCEIVERS WITH 3-STATE OUTPUTS 16470 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

B4 B9 B8GNDB3 B7 VCC B5 B6 GND B17B16B15B11 V CCB10 B12 B13 B14B2GNDCLKAB B1GND 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 GNDCLKBAGND B18 32 31 30 29 A15A9 A10 A12 GND A13 VCCA14A8 A11 A17 GND A18 OEBA LEBAA16 9 10 11 12 56 55 54 53 52 51 50 49 A6 GNDA5 A7 5 6 7 8 A3 VCCA2 A4 1 2 3 4 LEAB A1OEAB GND B4 B9 B8GNDB3 B7 VCC B5 B6 GND B17B16B15B11 V CCB10 B12 B13 B14B2GNDSEL B1GND 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 GNDCLKGND B18 32 31 30 29 A15A9 A10 A12 GND A13 VCCA14A8 A11 A17 GND A18 OEBA CLKENBAA16 9 10 11 12 56 55 54 53 52 51 50 49 A6 GNDA5 A7 5 6 7 8 A3 VCCA2 A4 1 2 3 4 OEAB A1GND GND 1234567 GNDA1 V CC CLKAB GNDB1 B2 V CC B5 B6 GND GND GND B10 B11 B12 B13 A9 A10 A11 A12 A13 A14 A15 B14 B15 GND GND A16 B16 A17 B17 VCC VCC A18 B18 CLK1BA 33 32 GND 31 30 SEL CLK2BA CLKENAB OEAB CLKENABOEBA 49545556 29 B4 B9 B8GNDB3 B7 VCC B5 B6 GND B17B16B15B11 V CCB10 B12 B13 B14B2GNDCLKAB B1GND 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 GNDCLKBAGND B18 32 31 30 29 A15A9 A10 A12 GND A13 VCCA14A8 A11 A17 GND A18 OEBA LEBAA16 9 10 11 12 56 55 54 53 52 51 50 49 A6 GNDA5 A7 5 6 7 8 A3 VCCA2 A4 1 2 3 4 LEAB A1OEAB GND 203 Pin Assignments 16525 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS See page 652 See page 654 See page 656 See page 658 16500 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS 16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS 16524 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS

1A5 2A2 2A11A71A4 1A8VCC 1A6 GND VCC 2OE22A8GND2A3 2A7GND 2A4 2A5 2A61A3GND1A1 1A21OE2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 2Y11Y4 VCC 1Y6 GND 1Y7 2Y2 1Y81Y3 1Y5 2Y82Y3 2Y4 VCC 2Y5 2Y6 GND 2OE1 2Y7GND 1 2 3 4 48 47 46 45 44 43 42 41 1Y1 1Y21OE1 GND 1A5 2A2 2A11A71A4 1A8VCC 1A6 GND VCC 2OE22A8GND2A3 2A7GND 2A4 2A5 2A61A3GND1A1 1A21OE2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 2Y11Y4 VCC 1Y6 GND 1Y7 2Y2 1Y81Y3 1Y5 2Y82Y3 2Y4 VCC 2Y5 2Y6 GND 2OE1 2Y7GND 1 2 3 4 48 47 46 45 44 43 42 41 1Y1 1Y21OE1 GND 1B3 1B8 1B7GND1B2 1B6VCC 1B4 1B5 GND 2B82B72B62B2 V CC2B1 2B3 2B4 2B51B1GND1LEBA 1CEBA1OEBA 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2OEBA2LEBAGND 2CEBA 32 31 30 29 2A61A8 2A1 2A3 GND 2A4 VCC2A51A7 2A2 2A8 GND 2CEAB 2LEAB 2OEAB2A7 9 10 11 12 56 55 54 53 52 51 50 49 1A5 GND1A4 1A6 5 6 7 8 1A2 VCC1A1 1A3 1 2 3 4 1LEAB 1CEAB1OEAB GND B4 B9 B8GNDB3 B7 VCC B5 B6 GND B17B16B15B11 V CCB10 B12 B13 B14B2GNDCLKAB B1CLKENAB 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 CLKENBACLKBAGND B18 32 31 30 29 A15A9 A10 A12 GND A13 VCCA14A8 A11 A17 GND A18 OEBA LEBAA16 9 10 11 12 56 55 54 53 52 51 50 49 A6 GNDA5 A7 5 6 7 8 A3 VCCA2 A4 1 2 3 4 LEAB A1OEAB GND Pin Assignments 204 See page 660 See page 661 See page 662 See page 664 16540 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 16541 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 16543 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS 16600 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

1A5 2A2 2A11A71A4 1A8VCC 1A6 GND VCC 2OEBA2A8GND2A3 2A7GND 2A4 2A5 2A61A3GND1A1 1A21OEBA 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 2B11B4 VCC 1B6 GND 1B7 2B2 1B81B3 1B5 2B82B3 2B4 VCC 2B5 2B6 GND 2OEAB 2B7GND 1 2 3 4 48 47 46 45 44 43 42 41 1B1 1B21OEAB GND 1A5 2A2 2A11A71A4 1A8VCC 1A6 GND VCC 2OEBA2A8GND2A3 2A7GND 2A4 2A5 2A61A3GND1A1 1A21OEBA 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 2B11B4 VCC 1B6 GND 1B7 2B2 1B81B3 1B5 2B82B3 2B4 VCC 2B5 2B6 GND 2OEAB 2B7GND 1 2 3 4 48 47 46 45 44 43 42 41 1B1 1B21OEAB GND 1A5 2A2 2A11A71A4 1A8VCC 1A6 GND VCC 2OE2A8GND2A3 2A7GND 2A4 2A5 2A61A3GND1A1 1A21OE 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 2B11B4 VCC 1B6 GND 1B7 2B2 1B81B3 1B5 2B82B3 2B4 VCC 2B5 2B6 GND 2DIR 2B7GND 1 2 3 4 48 47 46 45 44 43 42 41 1B1 1B21DIR GND B4 B9 B8GNDB3 B7 VCC B5 B6 GND B17B16B15B11 V CCB10 B12 B13 B14B2GNDCLKAB B1CLKENAB 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 CLKENBACLKBAGND B18 32 31 30 29 A15A9 A10 A12 GND A13 VCCA14A8 A11 A17 GND A18 OEBA LEBAA16 9 10 11 12 56 55 54 53 52 51 50 49 A6 GNDA5 A7 5 6 7 8 A3 VCCA2 A4 1 2 3 4 LEAB A1OEAB GND 205 Pin Assignments 16640 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS See page 666 See page 668 See page 670 See page 671 16601 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 16620 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 16623 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

1B3 1B8 1B7GND1B2 1B6VCC 1B4 1B5 GND 2B82B72B62B2 V CC2B1 2B3 2B4 2B51B1GND1CLKBA 1SBA1OE 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2OE2CLKBAGND 2SBA 32 31 30 29 2A61A8 2A1 2A3 GND 2A4 VCC2A51A7 2A2 2A8 GND 2SAB 2CLKAB 2DIR2A7 9 10 11 12 56 55 54 53 52 51 50 49 1A5 GND1A4 1A6 5 6 7 8 1A2 VCC1A1 1A3 1 2 3 4 1CLKAB 1SAB1DIR GND 1B3 1B8 1B7GND1B2 1B6VCC 1B4 1B5 GND 2B82B72B62B2 V CC2B1 2B3 2B4 2B51B1GND1CLKBA 1SBA1OEBA 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2OEBA2CLKBAGND 2SBA 32 31 30 29 2A61A8 2A1 2A3 GND 2A4 VCC2A51A7 2A2 2A8 GND 2SAB 2CLKAB 2OEAB2A7 9 10 11 12 56 55 54 53 52 51 50 49 1A5 GND1A4 1A6 5 6 7 8 1A2 VCC1A1 1A3 1 2 3 4 1CLKAB 1SAB1OEAB GND 1B3 1B8 1B7GND1B2 1B6VCC 1B4 1B5 GND 2B82B72B62B2 V CC2B1 2B3 2B4 2B51B1GND1CLKBA 1SBA1OEBA 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2OEBA2CLKBAGND 2SBA 32 31 30 29 2A61A8 2A1 2A3 GND 2A4 VCC2A51A7 2A2 2A8 GND 2SAB 2CLKAB 2OEBA2A7 9 10 11 12 56 55 54 53 52 51 50 49 1A5 GND1A4 1A6 5 6 7 8 1A2 VCC1A1 1A3 1 2 3 4 1CLKAB 1SAB1OEAB GND 1B3 1B8 1B7GND1B2 1B6VCC 1B4 1B5 GND 2B82B72B62B2 V CC2B1 2B3 2B4 2B51B1GND1ODD/EVEN 1PARITY1T/R 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2T/R2ODD/EVENGND 2PARITY 32 31 30 29 2A61A8 2A1 2A3 GND 2A4 VCC2A51A7 2A2 2A8 GND 2ERR NC 2OE2A7 9 10 11 12 56 55 54 53 52 51 50 49 1A5 GND1A4 1A6 5 6 7 8 1A2 VCC1A1 1A3 1 2 3 4 NC 1ERR1OE GND Pin Assignments 206 See page 672 See page 674 See page 676 See page 678 16646 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS 16651 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS 16652 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS 16657 16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS NC-No internal connection

49 3348 3447 3546 3645 3744 3843 3942 404164 Q10 D10 D14 GND D19 D22 5863 5962 Q13Q12OE CLKENGND 6061 D3 NC D5GNDNC NC VCC NC D4 GND NCD9NCNC V CCD6 D7 NC D8D2GNDD1 NCCLK 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NCNCGND D10 32 31 30 29 8Q25Q2 6Q1 7Q1 GND 7Q2 VCC8Q15Q1 6Q2 9Q2 GND 10Q1 10Q2 2OE9Q1 9 10 11 12 56 55 54 53 52 51 50 49 4Q1 GND3Q2 4Q2 5 6 7 8 2Q2 VCC2Q1 3Q1 1 2 3 4 1Q1 1Q21OE GND 1D5 1D10 1D9GND1D4 1D8VCC 1D6 1D7 GND 2D82D72D62D2 V CC2D1 2D3 2D4 2D51D3GND1D1 1D21CLK 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2CLK2D10GND 2D9 32 31 30 29 2Q61Q10 2Q1 2Q3 GND 2Q4 VCC2Q51Q9 2Q2 2Q8 GND 2Q9 2Q10 2OE2Q7 9 10 11 12 56 55 54 53 52 51 50 49 1Q7 GND1Q6 1Q8 5 6 7 8 1Q4 VCC1Q3 1Q5 1 2 3 4 1Q1 1Q21OE GND D5 D10 D9GNDD4 D8 VCC D6 D7 GND D18D17D16D12 V CCD11 D13 D14 D15D3GNDD1 D2CLK 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 CLKEND20GND D19 32 31 30 29 Q16Q10 Q11 Q13 GND Q14 VCCQ15Q9 Q12 Q18 GND Q19 Q20 NCQ17 9 10 11 12 56 55 54 53 52 51 50 49 Q7 GNDQ6 Q8 5 6 7 8 Q4 VCCQ3 Q5 1 2 3 4 Q1 Q2OE GND 207 Pin Assignments 16821 20-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS See page 680 See page 682 See page 683 16721 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS 16820 10-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH DUAL OUTPUTS 16722 22-BIT FLIP-FLOP WITH 3-STATE OUTPUTS See page 681 NC-No internal connection NC-No internal connection NC-No internal connection

1A5 GND 1A9GND1A4 1A8VCC 1A6 1A7 GND 2A72A62A52A1 V CCGND 2A2 2A3 2A41A3GND1A1 1A21OE2 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2OE22A9GNA 2A8 32 31 30 29 2Y5GND GND 2Y2 GNA 2Y3 VCC2Y41Y9 2Y1 2Y7 GNA 2Y8 2Y9 2OE12Y6 9 10 11 12 56 55 54 53 52 51 50 49 1Y7 GNA1Y6 1Y8 5 6 7 8 1Y4 VCC1Y3 1Y5 1 2 3 4 1Y1 1Y21OE1 GNA 1A5 1A10 1A9GND1A4 1A8VCC 1A6 1A7 GND 2A82A72A62A2 V CC2A1 2A3 2A4 2A51A3GND1A1 1A21OE2 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2OE22A10GNA 2A9 32 31 30 29 2Y61Y10 2Y1 2Y3 GNA 2Y4 VCC2Y51Y9 2Y2 2Y8 GNA 2Y9 2Y10 2OE12Y7 9 10 11 12 56 55 54 53 52 51 50 49 1Y7 GNA1Y6 1Y8 5 6 7 8 1Y4 VCC1Y3 1Y5 1 2 3 4 1Y1 1Y21OE1 GNA 1234567 1Y1GND3Y1 NC A3VCC GND 1Y2 GND2Y2 3Y2 V CC 4Y2 NC 1Y3 2Y3 GND GND NC 3Y3 4Y3 2Y1 2Y4 4Y1 1Y4 NC 2Y5 3Y4 4Y4 GND GND GND CLK 2Y6 A7 NC GND A8 NC GND A9 NC 2Y9 4Y9 1Y93Y9 1Y5 SEL 3Y5 VCC VCC VCC VCC VCC VCC 4Y5 65 57 4164 GND GND GND GND GND GND 5863 5962 OE2OE1 1Y6 4Y6 3Y6 2Y7 1Y7 4Y7 3Y7 2Y8 1Y8 4Y8 3Y8 6061 Pin Assignments 208 See page 685 See page 686 See page 688 16825 18-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 16827 20-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 16831 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS 1D4 1D9 1D8GND1D3 1D7VCC 1D5 1D6 GND 2D82D72D62D2 V CC2D1 2D3 2D4 2D51D2GND1CLKEN 1D11CLK 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2CLK2CLKENGND 2D9 32 31 30 29 2Q61Q9 2Q1 2Q3 GND 2Q4 VCC2Q51Q8 2Q2 2Q8 GND 2Q9 2OE 2CLR2Q7 9 10 11 12 56 55 54 53 52 51 50 49 1Q6 GND1Q5 1Q7 5 6 7 8 1Q3 VCC1Q2 1Q4 1 2 3 4 1OE 1Q11CLR GND See page 684 16823 18-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH DUAL OUTPUTS NC-No internal connection

1B3 1B8 1B7GND1B2 1B6VCC 1B4 1B5 GND 2B82B72B62B2 V CC2B1 2B3 2B4 2B51B1GND1CLR 1PARITY1OEA 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2OEA2CLRGND 2PARITY 32 31 30 29 2A61A8 2A1 2A3 GND 2A4 VCC2A51A7 2A2 2A8 GND 2ERR 2CLK 2OEB2A7 9 10 11 12 56 55 54 53 52 51 50 49 1A5 GND1A4 1A6 5 6 7 8 1A2 VCC1A1 1A3 1 2 3 4 1CLK 1ERR1OEB GND 1234567 Y18Y1 GND Y2 Y3 V CC NCGND A1 GND A2 A3 V CC GND GND Y10 A10 Y11 A11 Y12 A12 GND GND Y13 A13 Y14 A14 Y15 A15 VCC VCC Y16 A16 A17 3353 32 GND GND A18 CLK GND 54 3155 30 OEY17 LE NC NC 4956 29 A4 A9 A8GNDA3 A7 VCC A5 A6 GND A17A16A15A11 V CCA10 A12 A13 A14A2GNDNC A1GND 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 GNDCLKGND A18 32 31 30 29 Y15Y9 Y10 Y12 GND Y13 VCCY14Y8 Y11 Y17 GND Y18 OE LEY16 9 10 11 12 56 55 54 53 52 51 50 49 Y6 GNDY5 Y7 5 6 7 8 Y3 VCCY2 Y4 1 2 3 4 NC Y1NC GND 1234567 1Y1GND3Y1 A3 VCC GND 1Y2 GND2Y2 3Y2 V CC 4Y2 1Y3 2Y3 GND GND 3Y3 4Y3 2Y1 2Y4 4Y1 1Y4 NC 2Y5 3Y4 4Y4 GND GND GND CLK 2Y6 A7GND GND 2Y7 4Y7 1Y73Y7 1Y5 SEL 3Y5 VCC VCC VCC VCC VCCVCC 4Y5 49 3348 3447 3546 3645 3744 3843 3942 404164 GND GND GND GND GND GND 5863 5962 OE2OE1 1Y6 4Y6 3Y6 6061 209 Pin Assignments 16835 3.3-V ABT 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS See page 689 See page 690 See page 692 See page 693 16832 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS 16833 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS 16834 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS NC-No internal connection NC-No internal connection NC-No internal connection

1B3 1B8 1B7GND1B2 1B6VCC 1B4 1B5 GND 2B82B72B62B2 V CC2B1 2B3 2B4 2B51B1GND1CLR 1PARITY1OEA 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2OEA2CLRGND 2PARITY 32 31 30 29 2A61A8 2A1 2A3 GND 2A4 VCC2A51A7 2A2 2A8 GND 2ERR 2LE 2OEB2A7 9 10 11 12 56 55 54 53 52 51 50 49 1A5 GND1A4 1A6 5 6 7 8 1A2 VCC1A1 1A3 1 2 3 4 1LE 1ERR1OEB GND 1A5 1A10 1A9GND1A4 1A8VCC 1A6 1A7 GND 2A82A72A62A2 V CC2A1 2A3 2A4 2A51A3GND1A1 1A21OEBA 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2OEBA2A10GNA 2A9 32 31 30 29 2B61B10 2B1 2B3 GNA 2B4 VCC2B51B9 2B2 2B8 GNA 2B9 2B10 2OEAB2B7 9 10 11 12 56 55 54 53 52 51 50 49 1B7 GNA1B6 1B8 5 6 7 8 1B4 VCC1B3 1B5 1 2 3 4 1B1 1B21OEAB GNA Pin Assignments 210 See page 696 See page 698 16853 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS 16861 20-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 1D5 1D10 1D9GND1D4 1D8VCC 1D6 1D7 GND 2D82D72D62D2 V CC2D1 2D3 2D4 2D51D3GND1D1 1D21LE 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2LE2D10GND 2D9 32 31 30 29 2Q61Q10 2Q1 2Q3 GND 2Q4 VCC2Q51Q9 2Q2 2Q8 GND 2Q9 2Q10 2OE2Q7 9 10 11 12 56 55 54 53 52 51 50 49 1Q7 GND1Q6 1Q8 5 6 7 8 1Q4 VCC1Q3 1Q5 1 2 3 4 1Q1 1Q21OE GND 1D4 1D9 1D8GND1D3 1D7VCC 1D5 1D6 GND 2D82D72D62D2 V CC2D1 2D3 2D4 2D51D2GND1PRE 1D11LE 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2LE2PREGND 2D9 32 31 30 29 2Q61Q9 2Q1 2Q3 GND 2Q4 VCC2Q51Q8 2Q2 2Q8 GND 2Q9 2OE 2CLR2Q7 9 10 11 12 56 55 54 53 52 51 50 49 1Q6 GND1Q5 1Q7 5 6 7 8 1Q3 VCC1Q2 1Q4 1 2 3 4 1OE 1Q11CLR GND See page 694 16841 20-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS 16843 18-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS See page 695

1B2 GND 1B61B4GND 1B51B1 1B3 V CC 2B2 2B6VCC2B41B8 2B51B7 2B1 GND 2B31BPAR1ERRBLEBA CLKBA1CLKENBA 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 2BPARGND2B7 2B8 40 39 38 37 2A4GND 1A7 2A1 2A2 GND 2A52A31A6 1A8 2B6 2A7 2B8 GND 2APARVCC 9 10 11 12 64 63 62 61 60 59 58 57 VCC 1A41A3 1A5 5 6 7 8 GND 1A11APAR 1A2 1 2 3 4 LEAB CLKAB1CLKENAB 1ERRA 29 30 31 32 2CLKENBAODD/EVEN2ERRB OEBA 36 35 34 33 OEAB SEL 2CLKENAB CLKEN PAROE 1234567 9Y21Y1 GND1Y2 2Y1 V CC CLK 1A GND11A/YERREN 11Y1 V CC 2Y2 11Y2 3Y1 3Y2 GND GND 4Y1 4Y2 12A 5Y1 12Y1 5Y2 12Y2 6Y1 6Y2 GND GND 7Y1 7Y2 APAR 8Y1 VCC VCC 8Y2 YERR 9A MODE 3353 32 GND GND 10A PARI/O 54 3155 30 OE 9Y1 10Y2 10Y1 4956 29 1B3 1B8 1B7GND1B2 1B6VCC 1B4 1B5 GND 2B82B72B62B2 V CC2B1 2B3 2B4 2B51B1GND1CLKBA 1CLKENBA1OEBA 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2OEBA2CLKBAGND 2CLKENBA 32 31 30 29 2A61A8 2A1 2A3 GND 2A4 VCC2A51A7 2A2 2A8 GND 2CLKENAB 2CLKAB 2OEAB2A7 9 10 11 12 56 55 54 53 52 51 50 49 1A5 GND1A4 1A6 5 6 7 8 1A2 VCC1A1 1A3 1 2 3 4 1CLKAB 1CLKENAB1OEAB GND 1A5 GND 1A9GND1A4 1A8VCC 1A6 1A7 GND 2A72A62A52A1 V CCGND 2A2 2A3 2A41A3GND1A1 1A21OEBA 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2OEBA2A9GNA 2A8 32 31 30 29 2B5GND GND 2B2 GNA 2B3 VCC2B41B9 2B1 2B7 GNA 2B8 2B9 2OEAB2B6 9 10 11 12 56 55 54 53 52 51 50 49 1B7 GNA1B6 1B8 5 6 7 8 1B4 VCC1B3 1B5 1 2 3 4 1B1 1B21OEAB GNA 211 Pin Assignments 16952 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS See page 699 See page 700 See page 702 See page 704 16863 18-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS 16903 3.3-V 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS

24 23 22 21 20 19 18 17 16 15 14 13 2A2 2A41A4 2OE2A1 V CC 2A31A3VCC1A1 1A21OE 9 10 11 12 CLR8D GND 5 6 7 8 5D 6D4D 7D 1 2 3 4 1D 2DOE1 OE2 3D 24 23 22 21 20 19 18 17 16 15 14 13 6Q CLKEN4Q CLK 5Q 7Q 8Q3Q2QOE3 1QVCC 9 10 11 12 A7 GNDA6 A8 5 6 7 8 A4 A5GND GND 1 2 3 4 GND A2A1 A3 24 23 22 21 20 19 18 17 16 15 14 13 B6 B8B4 OE B5 V CC B7B3VCCB1 B2DIR 9 10 11 12 A9 A10A8 GND 5 6 7 8 A5 A6A4 A7 1 2 3 4 A1 A2OE1 A3 24 23 22 21 20 19 18 17 16 15 14 13 Y7 Y10Y5 OE2 Y6 Y8 Y9Y4Y3Y1 Y2VCC16 A7 GND A8 A4A1 GND GND VCC 19 18 VCC 24 23 22 21 20 DIR GND 7 11 B7 B8 OE 9 10 11 12 9D 10D8D GND 5 6 7 8 5D 6D4D 7D 1 2 3 4 1D 2DOE 3D 24 23 22 21 20 19 18 17 16 15 14 13 7Q 10Q5Q CLK 6Q 8Q 9Q4Q3Q1Q 2QVCC Pin Assignments 212 See page 708 See page 709 See page 710 See page 711 See page 712 See page 713, 714 25244 25-Ω OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS 29825 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS 25245 25-Ω OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 29827 29828 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 25642 25-Ω OCTAL BUS TRANSCEIVER 29821 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 48 47 46 45 44 43 42 41 TOE D1 A1 GND Y1 A2 VCC D2 A3 GND Y2 A4 D3 A5 GND Y3 A6 VCC D4 A7 GND A8 Y4 LE DIR B1 Q1 GND B2 Q2 VCC B3 Q3 GND B4 Q4 B5 Q5 GND B6 Q6 VCC B7 Q7 GND Q8 B8 LOE 16973 8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH WITH FOUR INDEPENDENT BUFFERS See page 706

24 23 22 21 20 19 18 17 16 15 14 13 B7 OEAB2B5 OEAB1B6 B8 B9B4B3B1 B2VCC 9 10 11 12 A9 OEAB2A8 GND 5 6 7 8 A5 A6A4 A7 1 2 3 4 A1 A2OEAB1 A3 24 23 22 21 20 19 18 17 16 15 14 13 B7 OEAB2B5 OEAB1B6 B8 B9B4B3B1 B2VCC 123 24 22 OEA CLRA1 VCC PARITY OEB A4 A5 A6 A7 A8 ERR GND LE 213 Pin Assignments See page 718 See page 720 See page 721 29854 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER 29863 9-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 29864 9-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS 9 10 11 12 9D 10D8D GND 5 6 7 8 5D 6D4D 7D 1 2 3 4 1D 2DOE 3D 24 23 22 21 20 19 18 17 16 15 14 13 7Q 10Q5Q LE 6Q 8Q 9Q4Q3Q1Q 2QVCC 9 10 11 12 9D CLR8D GND 5 6 7 8 5D 6D4D 7D 1 2 3 4 1D 2DOC 3D 24 23 22 21 20 19 18 17 16 15 14 13 7Q PRE5Q C 6Q 8Q 9Q4Q3Q1Q 2QVCC See page 715 See page 716 29841 10-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS 29843 9-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

C 2Y2 2Y1 1V CC 1VCC 2A1 2A2 D 2Y2 2Y3 GND GND 2A3 2A4 E 3Y2 3Y1 GND GND 3A1 3A2 F 3Y4 3Y3 1V CC 1VCC 3A3 3A4 G 4Y2 4Y1 GND GND 4A1 4A2 H 4Y3 4Y4 4OE 3OE 4A4 4A3 J 5Y2 5Y1 5OE 6OE 5A1 5A2 K 5Y4 5Y3 GND GND 5A3 5A4 L 6Y2 6Y1 2V CC 2VCC 6A1 6A2 M 6Y4 6Y3 GND GND 6A3 6A4 N 7Y2 7Y1 GND GND 7A1 7A2 P 7Y4 7Y3 2V CC 2VCC 7A3 7A4 R 8Y2 8Y1 GND GND 8A1 8A2 T 8Y3 8Y4 8OE 7OE 8A4 8A3 GKE PACKAGE (TOP VIEW) 1 23456 A B C D E F G H J K L M N P R T A GKE PACKAGE (TOP VIEW) BCDEFGHJKLMNPRT 6 1A2 5 1A1 4 2OE 3 1OE 2 1Y1 1 1Y2 A 1A4 1A3 GND GND 1Y3 1Y4 B 2A2 2A1 V CC VCC 3OE 4OE 6OE 5DIR 7OE 8DIR GND GND V CC VCC 2Y1 2Y2 2A4 2A3 GND GND GND GND GND GND V CC VCC GND GND GND GND VCC VCC GND GND 2Y3 2Y4 3A2 3A1 3Y1 3Y2 3A4 3A3 3Y3 3Y4 4A2 4A1 4Y1 4Y2 4A3 4A4 4Y4 4Y3 5A2 5A1 5Y1 5Y2 5A4 5A3 5Y3 5Y4 6A2 6A1 6Y1 6Y2 6A4 6A3 6Y3 6Y4 7A2 7A1 7Y1 7Y2 7A4 7A3 7Y3 7Y4 8A2 8A1 8Y1 8Y2 8A3 8A4 8Y4 8Y3 CDEFGHJ K LMNPRT Pin Assignments 214 See page 722 See page 724 32240 32-BIT BUFFER/DRIVER 32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS

A GKE PACKAGE (TOP VIEW) BCDEFGHJKLMNPRT 6 1A2 5 1A1 4 1OE 3 1DIR 2 1B1 1 1B2 A 1A4 1A3 GND GND 1B3 1B4 B 1A6 1A5 V CC VCC 2OE 2DIR 3OE 3DIR 4OE 4DIR GND GND V CC VCC 1B5 1B6 1A8 1A7 GND GND GND GND GND GND V CC VCC GND GND GND GND VCC VCC GND GND 1B7 1B8 2A2 2A1 2B1 2B2 2A4 2A3 2B3 2B4 2A6 2A5 2B5 2B6 2A7 2A8 2B8 2B7 3A2 3A1 3B1 3B2 3A4 3A3 3B3 3B4 3A6 3A5 3B5 3B6 3A8 3A7 3B7 3B8 4A2 4A1 4B1 4B2 4A4 4A3 4B3 4B4 4A6 4A5 4B5 4B6 4A7 4A8 4B8 4B7 CDEFGHJ K LMNPRT 38 39 40 41 42 43 44 45 46 47 48 49 50 4B53OE 3DIR 4B9 4B8 4B7 GND4B6VCC GND 4B3 4B2 4B4 34 35 36 37 GND 4DIR4A9 4OE 30 31 32 33 4A6 4A74A5 4A8 26 27 28 29 4A3 4A44A2 GND 2A3 2B9 2B8 2A6 GND 2A5 2B2 2A4 VCC 2A7 2A1 1B9 GND 3B3 3B2 3B4 3B1 3B6 3B5 3B7 GND 3B9 GND 4B1 3B8 3A7 3A1 3A2 3A4 GND 3A5 3A8 3A6 VCC 3A3 3A9 4A1 GND 2A7 2A8 2A6 2A9 2A4 2A5 2A3 GND 2A1 GND 1A9 2A2 888990919293949596979899100 1B52OE 2DIR 1B1 1B2 1B3 GND1B4VCC GND 1B7 1B8 1B6 84858687 GND 1DIR1A1 1OE 80818283 1A4 1A31A5 1A2 76777879 1A7 1A61A8 GND 215 Pin Assignments See page 726 32245 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS

C12NC VCC C16 C15 C14 GNDC13GND C10 C9 C11 60 C8 LEC CLKC GND VCC 21 22 23 24 25 CLKENA A12 A13 GND A15 A16 CLKA NC A11 A14 OEB SELBLEA VCC GND A10 GND A1 SELA OEC SELCOEA CLKENC 80 7879 63646566676869707172737475 61 627677 38 39 40 B15 B9 B10 B12 B13 GND B16 B14 B11 B18 GND B17 34 35 36 37 B6 B7B5 GND 30 31 32 33 GND B3VCC B4 26 27 28 29 CLKB B1LEB B2 C12C17 VCC C16 C15 C14 GNDC13GND C10 C9 C11 60 C8 LEC CLKC GND VCC 21 22 23 24 25 A18 A12 A13 GND A15 A16 CLKA A17 A11 A14 OEB SELBLEA VCC GND A10 GND A1 SELA OEC SELCOEA C18 80 7879 63646566676869707172737475 61 627677 Pin Assignments 216 See page 728 See page 730 32316 16-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS 32318 18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS NC-No internal connection

A GKE PACKAGE (TOP VIEW) BCDEFGHJKLMNPRT 6 1D2 5 1D1 4 1LE 3 1OE 2 1Q1 1 1Q2 A 1D4 1D3 GND GND 1Q3 1Q4 B 1D6 1D5 V CC VCC 2LE 2OE 3LE 3OE 4LE 4OE GND GND V CC VCC 1Q5 1Q6 1D8 1D7 GND GND GND GND GND GND V CC VCC GND GND GND GND VCC VCC GND GND 1Q7 1Q8 2D2 2D1 2Q1 2Q2 2D4 2D3 2Q3 2Q4 2D6 2D5 2Q5 2Q6 2D7 2D8 2Q8 2Q7 3D2 3D1 3Q1 3Q2 3D4 3D3 3Q3 3Q4 3D6 3D5 3Q5 3Q6 3D8 3D7 3Q7 3Q8 4D2 4D1 4Q1 4Q2 4D4 4D3 4Q3 4Q4 4D6 4D5 4Q5 4Q6 4D7 4D8 4Q8 4Q7 CDEFGHJ K LMNPRT A B C D E F G H J K L M N P R T 23456 1OE 2OE 3OE 4OE A 1234 1CLK 2CLK 3CLK 4CLK 1Q2 1Q1 1D1 1D2 GND GND1Q4 1Q3 1D3 1D4 VCC VCC1Q6 1Q5 1D5 1D6 GND GND GND GND VCC VCC GND GND GND GND VCC VCC GND GND GND GND VCC VCC GND GND 1Q8 1Q7 1D7 1D8 2Q2 2Q1 2D1 2D2 2Q4 2Q3 2D3 2D4 2Q6 2Q5 2D5 2D6 2Q8 2Q7 2D7 2D8 3Q2 3Q1 3D1 3D2 3Q4 3Q3 3D3 3D4 3Q6 3Q5 3D5 3D6 3Q8 3Q7 4Q2 4Q1 4Q4 4Q3 4Q6 4Q5 4Q84Q7 3D7 3D8 4D1 4D2 4D3 4D4 4D5 4D6 4D74D8 B C D E F G H J K L M N P R T GKE PACKAGE (TOP VIEW) terminal assignments 217 Pin Assignments See page 732 See page 734 32373 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS 32374 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

38 39 40 41 42 43 44 45 46 47 48 49 50 1B141CLKAB 1LEAB 1B18 1B17 1B16 GND1B15VCC 1OEAB 1B12 1B11 1B13 34 35 36 37 1OEBA 1LEBA1A18 1CLKBA 30 31 32 33 1A15 1A161A14 1A17 26 27 28 29 1A12 1A131A11 GND 2A7 2B1 2B2 2A4 GND 2A5 2B8 2A6 VCC 2A3 2A9 2B10 GND 1B3 1B2 1B4 1B1 1B6 1B5 1B7 GND 1B9 GND 1B10 1B8 1A7 1A1 1A2 1A4 GND 1A5 1A8 1A6 VCC 1A3 1A9 1A10 GND 2A3 2A2 2A4 2A1 2A6 2A5 2A7 GND 2A9 GND 2A10 2A8 888990919293949596979899100 2B142CLKAB 2LEAB 2B18 2B17 2B16 GND2B15VCC 2OEAB 2B12 2B11 2B13 84858687 2OEBA 2LEBA2A18 2CLKBA 80818283 2A15 2A162A14 2A17 76777879 2A12 2A132A11 GND 2CEBA 38 39 40 41 42 43 44 45 46 47 48 49 50 2B15VCC 2LEAB 2CEAB 2B18 2B17 GND2B162LEBA 2OEAB 2B13 2B12 2B11 2B14 34 35 36 37 2A18 2OEBA 30 31 32 33 2A15 2A162A14 2A17 26 27 28 29 2A12 2A132A11 GND 1B12 1B18 1B17 1B15 GND 1B14 1B11 1B13 VCC 1B16 1B10 1B9 GND 2B3 2B2 2B4 2B1 2B6 2B5 2B7 GND 2B9 GND 2B10 2B8 2A7 2A1 2A2 2A4 GND 2A5 2A8 2A6 VCC 2A3 2A9 2A10 GND 1A16 1A17 1A15 1A18 1A13 1A14 1A12 GND 1A10 GND 1A9 1A11 888990919293949596979899100 1B51LEAB 1OEAB 1B1 1B1 1B3 GND1B4VCC 1CEAB 1B7 1B8 1B6 84858687 1CEBA 1OEBA1A1 1LEBA 80818283 1A4 1A31A5 1A2 76777879 1A7 1A61A8 GND Pin Assignments 218 See page 736 See page 738 32501 36-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 32543 36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

A 1A1 D1 1TOE 1DIR 1B1 1Q1 B 1A2 Y1 GND GND 1B2 1Q2 C 1A3 D2 V CC VCC 1B3 1Q3 D 1A4 Y2 GND GND 1B4 1Q4 E 1A5 D3 GND GND 1B5 1Q5 F 1A6 Y3 V CC VCC 1B6 1Q6 G 1A7 D4 GND GND 1B7 1Q7 H 1A8 Y4 1LE 1LOE 1B8 1Q8 J 2A1 D5 2TOE 2DIR 2B1 2Q1 K 2A2 Y5 GND GND 2B2 2Q2 L 2A3 D6 V CC VCC 2B3 2Q3 M 2A4 Y6 GND GND 2B4 2Q4 N 2A5 D7 GND GND 2B5 2Q5 P 2A6 Y7 V CC VCC 2B6 2Q6 R 2A7 D8 GND GND 2B7 2Q7 T 2A8 Y8 2LE 2LOE 2B8 2Q8 J H G F E D C B A 213 4 65 P N M L K T R GKE PACKAGE (TOP VIEW) 219 Pin Assignments See page 740 32973 16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH WITH EIGHT INDEPENDENT BUFFERS VCC CP PE (SYNC) MR TC TE P0 P1 P2 P3 1 2 3 4 5 6 7 16 15 14 13 12 11 10 GND P7 P6 P5 P4 PL See page 742 40103 8-STAGE SYNCHRONOUS DOWN COUNTERS

2A1 3A2 3A12A31A4 2A4VCC 2A2 GND VCC 3OE4A4GND3A3 4A3GND 3A4 4A1 4A21A3GND1A1 1A22OE 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 3Y11Y4 VCC 2Y2 GND 2Y3 3Y2 2Y41Y3 2Y1 4Y43Y3 3Y4 VCC 4Y1 4Y2 GND 4OE 4Y3GND 1 2 3 4 48 47 46 45 44 43 42 41 1Y1 1Y21OE GND 1OE 1234567 1Y1 GND1Y2 1Y3 V CC 2OE 1A1 GND 1A2 1A3 V CC 1Y4 1A4 2Y1 2A1 2Y2 2A2 GND GND 2Y3 2A3 2Y4 2A4 3Y1 3A1 3Y2 3A2 3Y3 3A3 3Y4 3A4 GND GND 4Y1 4A1 4Y2 4A2 VCC VCC 4Y3 4A3 4A4 33 32 GND GND 3OE 31 30 4OE4Y4 2526272829 2A1 3A2 3A12A31A4 2A4VCC 2A2 GND VCC 3OE4A4GND3A3 4A3GND 3A4 4A1 4A21A3GND1A1 1A22OE 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 3Y11Y4 VCC 2Y2 GND 2Y3 3Y2 2Y41Y3 2Y1 4Y43Y3 3Y4 VCC 4Y1 4Y2 GND 4OE 4Y3GND 1 2 3 4 48 47 46 45 44 43 42 41 1Y1 1Y21OE GND Pin Assignments 220 See page 744 See page 745 See page 746 162240 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 162241 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 162244 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 1A5 2A2 2A11A71A4 1A8VCC 1A6 GND VCC 2OE2A8GND2A3 2A7GND 2A4 2A5 2A61A3GND1A1 1A21OE 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 2B11B4 VCC 1B6 GND 1B7 2B2 1B81B3 1B5 2B82B3 2B4 VCC 2B5 2B6 GND 2DIR 2B7GND 1 2 3 4 48 47 46 45 44 43 42 41 1B1 1B21DIR GND See page 747 162245 16-BIT TRANSCEIVER WITH 3-STATE OUTPUTS

2B7 2B12 2B11GND2B6 2B10VCC 2B8 2B9 GND 1B51B61B71B11 V CC1B12 1B10 1B9 1B82B5GNDCLKENA2 2B4OEB 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 CLKCLKENA1GND 1B4 32 31 30 29 A12A6 A7 A9 GND A10 VCCA11A5 A8 1B2 GND 1B3 CLKEN2B SEL1B1 9 10 11 12 56 55 54 53 52 51 50 49 A3 GNDA2 A4 5 6 7 8 2B1 VCC2B2 A1 1 2 3 4 CLKEN1B 2B3OEA GND 1234567 GND GND 1B72B7 VCC VCCVCCVCC GNDVCC 2B6 A15 A14 A13 A12 A11 GND GND GND 2B81B8 1B9 2B9 2B10 1B10 1B11 2B11 1B12 2B12 A71B6 2B5 1B5 GND GND GND 2B4 1B15 1B4 2B3 1B3 2B2 1B2 2B1 1B1 2D2 1D2 2D1 1D1 2B15 1B16 VCC VCC 1B13 2B13 1B14 2B14 V CC 2B16 57 56 GND V CC A16 V CCGND A9 A8 A10 GND 55 5477 73787980 53 OE SELCLK DIR 221 Pin Assignments 162280 16-BIT TO 32-BIT REGISTERED BUS EXCHANGER WITH BYTE MASKS AND 3-STATE OUTPUTS See page 748 See page 750 See page 752 162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS 162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS 52 51 VCC 2B6 1B7 GNDVCC GND 2B9 2B8 4855 54 53 50 4980 2B7 2B5 1B6 2B3 1B4 V CC1B31B5 2B2 2B4 1B1 2B1 A1 A 2A 3VCC VCC 1B9 47 42 41 45 44 43 4039 4662 61 5865 64 63 60 59 57 5672 71 6875 74 73 70 69 67 667879 77 76 373231 3534333029 36161512 1918171413 20 21 22 23 24 25 26 27 2811 1B8 GND GND GND A4 A5 A6 A7 A8 A9 CLK GND1B2 SEL VCC 1B132B12GNDVCC GND 1B10 1B11 1B12 1B14 2B13 1B16 2B15 V CC2B162B14 1B17 1B15 2B18 1B18 A18 A17 A16VCC VCC2B10 2B11 GND GND GND A15 A14 A13 A12 A11 A10 OE GND2B17 DIR See page 754 162282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

1D5 2D2 2D11D71D4 1D8VCC 1D6 GND VCC 2CLK2D8GND2D3 2D7GND 2D4 2D5 2D61D3GND1D1 1D21CLK 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 2Q11Q4 VCC 1Q6 GND 1Q7 2Q2 1Q81Q3 1Q5 2Q82Q3 2Q4 VCC 2Q5 2Q6 GND 2OE 2Q7GND 1 2 3 4 48 47 46 45 44 43 42 41 1Q1 1Q21OE GND See page 761 162374 3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS 1234567 NCY1 GNDY2 Y3 V CC CLK A1 GND A2 A3 V CC GND GND Y10 A10 Y11 A11 Y12 A12 GND GND Y13 A13 Y14 A14 Y15 A15 VCC VCC Y16 A16 LE 2532 GND GND 2631 2730 OE 2829 OE1 1234567 1B1 GND1B2 1B3 V CC 8B1 GND8B2 8B3 V CC 1B4 8B4 2B1 7B1 7B2 2B2 GND GND GND 7B3 2B3 7B4 3B4 6A 6B1 6B2 3B1 6B3 3B2 3B3 3B4 4A 6B4 5A GND GND 4B1 5B1 4B2 5B2 VCC VCC 4B3 5B3 5B4 33 32 GND 31 30 OE2 OE3OE4 4B4 49545556 29 1D5 2D2 2D11D71D4 1D8VCC 1D6 GND VCC 2LE2D8GND2D3 2D7GND 2D4 2D5 2D61D3GND1D1 1D21LE 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 2Q11Q4 VCC 1Q6 GND 1Q7 2Q2 1Q81Q3 1Q5 2Q82Q3 2Q4 VCC 2Q5 2Q6 GND 2OE 2Q7GND 1 2 3 4 48 47 46 45 44 43 42 41 1Q1 1Q21OE GND Pin Assignments 222 See page 756 See page 758 See page 760 162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS 162344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS 162373 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS NC-No internal connection

1B3 2B4 2B3GND1B2 2B2VCC 1B4 2B1 GND 4B44B34B23B2 V CC3B1 3B3 3B4 4B11B1GNDOEB2 SEL0OEB1 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 OEB4OEB3GND SEL1 32 31 30 29 CLKENBACE_SEL0 CE_SEL1 4A GND CLKENAB VCCCLKENB2A 3A LEB4 GND OEA LEAB3 LEAB3LEB3 9 10 11 12 56 55 54 53 52 51 50 49 CLKAB GNDOEB 1A 5 6 7 8 LEB2 VCCLEB1 CLKBA 1 2 3 4 LEAB2 LEBALEAB1 GND B4 B9 B8GNDB3 B7 VCC B5 B6 GND B17B16B15B11 V CCB10 B12 B13 B14B2GNDCLKAB B1GND 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 GNDCLKBAGND B18 32 31 30 29 A15A9 A10 A12 GND A13 VCCA14A8 A11 A17 GND A18 OEBA LEBAA16 9 10 11 12 56 55 54 53 52 51 50 49 A6 GNDA5 A7 5 6 7 8 A3 VCCA2 A4 1 2 3 4 LEAB A1OEAB GND 1234567 A18A1 GND A2 A3 V CC CLKABGND B1 GND B2 B3 V CC GND GND A10 B10 A11 B11 A12 B12 GND GND A13 B13 A14 B14 A15 B15 VCC VCC A16 B16 B17 3353 32 GND GND B18 CLKBA GND 54 3155 30 OEBAA17 LEBA LEAB OEAB 4956 29 223 Pin Assignments 162501 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS See page 762 See page 764 See page 766 162460 4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS 162500 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS B4 B9 B8GNDB3 B7 VCC B5 B6 GND B17B16B15B11 V CCB10 B12 B13 B14B2GNDCLKAB B1SEL 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 CLK2BACLK1BAGND B18 32 31 30 29 A15A9 A10 A12 GND A13 VCCA14A8 A11 A17 GND A18 OEBA CLKENBAA16 9 10 11 12 56 55 54 53 52 51 50 49 A6 GNDA5 A7 5 6 7 8 A3 VCCA2 A4 1 2 3 4 OEAB A1CLKENAB GND See page 768 162525 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS

D3 NC D5GNDNC NC VCC NC D4 GND NCD9NCNC V CCD6 D7 NC D8D2GNDD1 NCCLK 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NCNCGND D10 32 31 30 29 8Q25Q2 6Q1 7Q1 GND 7Q2 VCC8Q15Q1 6Q2 9Q2 GND 10Q1 10Q2 2OE9Q1 9 10 11 12 56 55 54 53 52 51 50 49 4Q1 GND3Q2 4Q2 5 6 7 8 2Q2 VCC2Q1 3Q1 1 2 3 4 1Q1 1Q21OE GND See page 775 162820 3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS 1234567 1Y1 GND1Y2 1Y3 V CC 1A1 GND1A2 1A3 V CC 1Y4 1A4 1Y5 1A5 1Y6 1A6 GND GND 1Y7 1A7 1Y8 1A8 2Y1 2A1 2Y2 2A2 2Y3 2A3 2Y4 2A4 GND GND 2Y5 2A5 2Y6 2A6 2Y7 2A7 VCC VCC 2Y8 2A8 33 2532 GND GND 2631 2730 1OE1 1OE2 2OE1 2OE2 2829 B4 B9 B8GNDB3 B7 VCC B5 B6 GND B17B16B15B11 V CCB10 B12 B13 B14B2GNDCLKAB B1CLKENAB 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 CLKENBACLKBAGND B18 32 31 30 29 A15A9 A10 A12 GND A13 VCCA14A8 A11 A17 GND A18 OEBA LEBAA16 9 10 11 12 56 55 54 53 52 51 50 49 A6 GNDA5 A7 5 6 7 8 A3 VCCA2 A4 1 2 3 4 LEAB A1OEAB GND D5 D10 D9GNDD4 D8 VCC D6 D7 GND D18D17D16D12 V CCD11 D13 D14 D15D3GNDD1 D2CLK 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 CLKEND20GND D19 32 31 30 29 Q16Q10 Q11 Q13 GND Q14 VCCQ15Q9 Q12 Q18 GND Q19 Q20 NCQ17 9 10 11 12 56 55 54 53 52 51 50 49 Q7 GNDQ6 Q8 5 6 7 8 Q4 VCCQ3 Q5 1 2 3 4 Q1 Q2OE GND Pin Assignments 224 See page 770 See page 772 See page 774 162541 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 162601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS 162721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS NC-No internal connection NC-No internal connection

1A5 1A10 1A9GND1A4 1A8VCC 1A6 1A7 GND 2A82A72A62A2 V CC2A1 2A3 2A4 2A51A3GND1A1 1A21OE2 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2OE22A10GNA 2A9 32 31 30 29 2Y61Y10 2Y1 2Y3 GNA 2Y4 VCC2Y51Y9 2Y2 2Y8 GNA 2Y9 2Y10 2OE12Y7 9 10 11 12 56 55 54 53 52 51 50 49 1Y7 GNA1Y6 1Y8 5 6 7 8 1Y4 VCC1Y3 1Y5 1 2 3 4 1Y1 1Y21OE1 GNA 1A5 GND 1A9GND1A4 1A8VCC 1A6 1A7 GND 2A72A62A52A1 V CCGND 2A2 2A3 2A41A3GND1A1 1A21OE2 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2OE22A9GND 2A8 32 31 30 29 2Y5GND GND 2Y2 GND 2Y3 VCC2Y41Y9 2Y1 2Y7 GND 2Y8 2Y9 2OE12Y6 9 10 11 12 56 55 54 53 52 51 50 49 1Y7 GND1Y6 1Y8 5 6 7 8 1Y4 VCC1Y3 1Y5 1 2 3 4 1Y1 1Y21OE1 GND 1234567 1Y1GND1Y2 A5 A6VCC GND 1Y3 GND2Y3 1Y4 V CC A12 2Y4 1Y5 2Y5 GND GND 1Y6 2Y6 2Y1 2Y7 2Y2 1Y7 2Y9 1Y8 2Y8 GND GND GND 2Y11 A13 A14 GND A15 A16 GND A17 A18 2Y17 2Y18 1Y171Y18 1Y9 A10 1Y10 VCC VCC VCC VCC VCC VCC A11 2Y10 65 57 4164 GND GND GND GND GND GND 5863 5962 OE2OE1 1Y11 2Y12 1Y12 2Y13 1Y13 2Y14 1Y14 2Y15 1Y15 2Y16 1Y16 6061 1OE1CLR 1234567 2Q91Q1 GND 1Q2 1Q3 V CC 1CLKEN1CLK 1D1 GND 1D2 1D3 V CC 1Q4 1D4 1Q5 1D5 1Q6 1D6 GND GND 1Q7 1D7 1Q8 1D8 1Q9 1D9 2Q1 2D1 2Q2 2D2 2Q3 2D3 GND GND 2Q4 2D4 2Q5 2D5 2Q6 2D6 VCC VCC 2Q7 2D7 2D8 3353 32 GND GND 2D9 2CLKEN 2CLK 54 3155 30 2OE 2CLR2Q8 4956 29 225 Pin Assignments 162830 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS See page 776 See page 777 See page 778 See page 779 162823 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS 162825 18-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 162827 20-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

A7 NC GND A8 NC GND A9 NC 2Y9 4Y9 1Y93Y9 1Y5 SEL 3Y5 VCC VCC VCC VCC VCC VCC 4Y5 65 57 4164 GND GND GND GND GND GND 5863 5962 OE2OE1 1Y6 4Y6 3Y6 2Y7 1Y7 4Y7 3Y7 2Y8 1Y8 4Y8 3Y8 6061 1234567 1Y1GND3Y1 A3 VCC GND 1Y2 GND2Y2 3Y2 V CC 4Y2 1Y3 2Y3 GND GND 3Y3 4Y3 2Y1 2Y4 4Y1 1Y4 NC 2Y5 3Y4 4Y4 GND GND GND CLK 2Y6 A7GND GND 2Y7 4Y7 1Y73Y7 1Y5 SEL 3Y5 VCC VCC VCC VCC VCCVCC 4Y5 49 3348 3447 3546 3645 3744 3843 3942 404164 GND GND GND GND GND GND 5863 5962 OE2OE1 1Y6 4Y6 3Y6 6061 1234567 Y18Y1 GND Y2 Y3 V CC NCGND A1 GND A2 A3 V CC GND GND Y10 A10 Y11 A11 Y12 A12 GND GND Y13 A13 Y14 A14 Y15 A15 VCC VCC Y16 A16 A17 3353 32 GND GND A18 CLK GND 54 3155 30 OEY17 LE NC NC 4956 29 Pin Assignments 226 See page 780 See page 781 See page 782, 783 See page 784 162831 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS 162832 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS 162834 162835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS 162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS NC-No internal connection NC-No internal connection NC-No internal connection

20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS

A 1Q2 1Q1 1OE 1CLK 1D1 1D2 B 1Q4 1Q3 GND GND 1D3 1D4 C 1Q6 1Q5 V CC VCC 1D5 1D6 D 1Q8 1Q7 GND GND 1D7 1D8 E 2Q2 2Q1 GND GND 2D1 2D2 F 2Q4 2Q3 V CC VCC 2D3 2D4 G 2Q6 2Q6 GND GND 2D5 2D6 H 2Q7 2Q8 2OE 2CLK 2D8 2D7 J 3Q2 3Q1 3OE 3CLK 3D1 3D2 K 3Q4 3Q3 GND GND 3D3 3D4 L 3Q6 3Q5 V CC VCC 3D5 3D6 M 3Q8 3Q7 GND GND 3D7 3D8 N 4Q2 4Q1 GND GND 4D1 4D2 P 4Q4 4Q3 V CC VCC 4D3 4D4 R 4Q6 4Q5 GND GND 4D5 4D6 T 4Q7 4Q8 4OE 4CLK 4D8 4D7 GKE PACKAGE (TOP VIEW) J H G F E D C B A 213 4 65 P N M L K T R Pin Assignments 228 See page 787 322374 3.3-V ABT 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3- STATE OUTPUTS 1Y2 1Y1 1OE 2OE 1A1 1A2 1Y4 1Y3 GND GND 1A3 1A4 2Y2 2Y1 V CC VCC 2A1 2A2 2Y4 2Y3 GND GND 2A3 2A4 3Y2 3Y1 GND GND 3A1 3A2 3Y4 3Y3 V CC VCC 3A3 3A4 4Y2 4Y1 GND GND 4A1 4A2 4Y3 4Y4 4OE 3OE 4A4 4A3 5Y2 5Y1 5OE 6OE 5A1 5A2 5Y4 5Y3 GND GND 5A3 5A4 6Y2 6Y1 V CC VCC 6A1 6A2 6Y4 6Y3 GND GND 6A3 6A4 7Y2 7Y1 GND GND 7A1 7A2 7Y4 7Y3 V CC VCC 7A3 7A4 8Y2 8Y1 GND GND 8A1 8A2 8Y3 8Y4 8OE 7OE 8A4 8A3 J H G F E D C B A 213 46 5 P N M L K T R GKE PACKAGE (TOP VIEW) terminal assignments 34215 6 A B C D E F G H J K L M N P R T 322244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS See page 786

Logic Diagram (SN74) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. QUADRUPLE 2-INPUT POSITIVE-NAND GATES

• Y = A•B
• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) A B Y ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC SN74 HCT CD74 HCT AC

11 UNIT

IOL MAX 4 202082016 8 4 4 4 24 mA PARAMETER MAX or MIN ACT SN74 ACT CD74 ACT AHC AHCT LV LV LVC ALVC 3V UNIT IOH MAX -24 -24 -24 -8 -8 -6 -12 -24 -24 mA IOL MAX SN74 AC 0.02 -24 CD74 AC 0.08 -24 24 24 24 8 8 6 12 24 24 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC SN74 HCT tPLH A or B Y MAX 22 15 4.5 11 4.5 6 23 27 25 tPHL A or B Y A or B Y A or B Y MAX 15 15 584 5 . 3 2 32 72 5 PARAMETER INPUT OUTPUT MAX or MIN CD74 HCT AC SN74 AC CD74 AC ACT SN74 ACT CD74 ACT AHC AHCT PARAMETER INPUT OUTPUT MAX or MIN LV LV LVC ALVC tPLH A or B Y MAX 13 8.5 4.3 3 tPHL A or B Y MAX 13 8.5 4.3 3 AUC 2.3V AUC 1.8V 2.4 2.4 UNIT:ns AUC 0.01 AUC 1.8V 2.3V 0.01

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS QUADRUPLE 2-INPUT POSITIVE-NAND GATES WITH OPEN-COLLECTOR OUTPUTS

• Y = A•B ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS ALS HC UNIT ICC MAX 22 4.4 3 0.02 mA VOH MAX 5.5 5.5 5.5 V CC V IOL MAX 16 8 8 4 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS ALS HC tPLH A or B Y MAX 55 32 54 31 tPHL A or B Y MAX 15 28 28 25 UNIT:ns

Logic Diagram (SN74) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. QUADRUPLE 2-INPUT POSITIVE-NOR GATES

• Y = A + B
• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) PARAMETER MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC SN74 HCT CD74 HCT UNIT IOL MAX PARAMETER MAX or MIN AC CD74 AC ACT CD74 ACT AHC AHCT LV LV LVC 3V UNIT IOH MAX -24 -24 -24 -24 -8 -8 -6 -12 -24 mA IOL MAX 24 24 24 24 8 8 6 12 24 mA PARAMETER ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC SN74 HCT CD74 HCT tPLH A or B Y MAX 22 15 5.5 12 4.5 6.5 23 27 25 32 tPHL A or B Y MAX 15 15 5.5 10 4.5 5.3 23 27 25 32 PARAMETER INPUT OUTPUT MAX or MIN AC CD74 AC ACT CD74 ACT AHC AHCT LV LV LVC UNIT: ns A or B Y MAX A or B Y MAX PARAMETER INPUT OUTPUT MAX or MIN tPLH A or B Y MAX tPHL A or B Y MAX AUC 0.01 AUC 1.8V 2.3V 0.01 AUC 2.4 2.4 AUC 1.8V 2.3V 4202082016 8 4 4 4 mA

Logic Diagram (SN74) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS QUADRUPLE 2-INPUT POSITIVE-NAND GATES WITH OPEN-COLLECTOR OUTPUTS

• Y = A•B A B Y PARAMETER MAX or MIN TTL LS S ALS SN74 HC CD74 HC CD74 HCT UNIT ICC MAX 22 4.4 36 4 0.02 0.04 0.04 mA VOH MAX 5.5 8 5.5 8 V CC VCC VCC V IOL MAX 16 0.1 20 0.1 4 4 4 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS SN74 HC CD74 HC CD74 HCT tPLH A or B Y MAX 45 32 7.5 50 31 30 36 tPHL A or B Y MAX 15 2871 3 2 53 03 6 UNIT: ns ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS

Logic Diagram (SN74) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. HEX INVERTERS

• Y = A
• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) YA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC SN74 HCT CD74 HCT AC SN74 AC UNIT IOL MAX1 682 082 02 0 4444 2 4 2 4 m A PARAMETER MAX or MIN CD74 AC ACT SN74 ACT CD74 ACT AHC AHCT LV LV LVC ALVC AUC 1.8V AUC 2.3V UNIT IOH MAX -24 -24 -24 -24 -8 -8 -6 -12 -24 -24 -8 -9 mA IOL MAX 24 24 2 42 4 8 8 6 1 2 24 24 8 9 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC SN74 HCT tPLH A or B Y MAX 22 15 4.5 11 5 6 24 26 25 tPHL A or B Y MAX 15 1 5 584 5 . 3 2 4 26 25 PARAMETER INPUT OUTPUT MAX or MIN CD74 HCT AC SN74 AC CD74 AC ACT SN74 ACT CD74 ACT AHC AHCT PARAMETER INPUT OUTPUT MAX or MIN LV LV LVC ALVC AUC 1.8V AUC 2.3V UNIT: ns

• Y = A Y A 236 Logic Diagram (SN74) Logic Diagram (SN74) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS U04 HEX INVERTERS
• Y = A
• Unbuffered Output YA PARAMETER MAX or MIN SN74 HC CD74 HC AHC LV LV LVC AUC 1.8V AUC 2.3V UNIT IOH MAX -4 -4 -8 -6 -12 -24 -8 -9 mA IOL MAX 4486 1 2 2 4 89 m A PARAMETER INPUT OUTPUT MAX or MIN SN74 HC CD74 HC AHC LV LV LVC AUC 1.8V AUC 2.3V tPLH A or B Y MAX 20 2 181 383 . 8 2 . 0 1 . 7 tPHL A or B Y MAX 20 2 181 383 . 8 2 . 0 1 . 7 UNIT: ns ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS S ALS SN74 HC CD74 AC CD74 ACT AHC LV LV 5V UNIT IOH MAX 0.25 0.1 0.25 - - -24 -24 - - - mA IOL MAX 16 8 2 08 42 4 2 48 61 2 m A SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS SN74 HC CD74 AC CD74 ACT AHC LV LV tPLH A or B Y MAX 55 32 7.5 54 29 - - - 12 8.5 tPHL A or B Y MAX 15 28 7 14 21 - - - 12 8.5 tPZL AY MAX ----- 6 . 5 1 0 . 8 8 . 5 -- UNIT: ns

HEX INVERTER BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS

• Y = A AY 237 Logic Diagram Logic Diagram PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS LV LVC AUC 1.8V AUC 2.5V UNIT ICC MAX 51 60 - 0.0 10 . 0 10 . 0 1m A IOH MAX 0. 25 0.25 - - - - mA VOH MAX 30 30 5.5 5.5 3.6 3.6 V IOL MAX 40 40 8 24 8 9 mA 16 LV 0.02 ±0.0025 5.5 SWITCHING CHARACTERISTICS PARAMETER I NPUT OUTPUT MAX or MIN TTL LS LV LV LVC AUC 1.8V AUC 2.5V tPLH A or B Y MAX 15 15 12 8.5 3.7 2.8 1.3 tPHL A or B Y MAX 23 20 12 8.5 3.7 2.8 1.3 UNIT: ns ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS LV LVC AUC 1.8V AUC 2.5V UNIT ICC MAX 41 45 - 0.0 10 . 0 10 . 0 1m A IOH MAX 0. 25 0.25 - - - - mA VOH MAX 30 30 5.5 5.5 3.6 3.6 V IOL MAX 40 40 8 24 8 9 mA 16 LV 0.02 ±0.0025 5.5 SWITCHING CHARACTERISTICS PARAMETER I NPUT OUTPUT MAX or MIN TTL LS LV LV LVC AUC 1.8V AUC 2.5V tPLH A or B Y MAX 15 10 12 8.5 2.9 2.3 1.3 tPHL A or B Y MAX 26 30 12 8.5 2.9 2.3 1.3 UNIT: ns HEX BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS
• Y = A AY

Logic Diagram (SN74) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS A B Y QUADRUPLE 2-INPUT POSITIVE-AND GATES

• Y = A•B
• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) UNIT mA mA mA AUC 2.3V 1.8 1.8 AUC 1.8V 2.3 2.3 AUC 0.01 AUC 1.8V 2.3V 0.01 ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC SN74 HCT CD74 HCT AC

IOL MAX 1682 082 02 0 4444 2 4 m A PARAMETER MAX or MIN SN74 AC CD74 AC ACT SN74 ACT CD74 ACT AHC AHCT LV LV LVC 3.3V ALVC IOH MAX -24 -24 -24 -24 -24 -8 -8 -6 -12 -24 -24 IOL MAX 24 24 24 24 24 8 8 6 12 24 24 SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC SN74 HCT tPLH A or B Y MAX 27 1 571 4 5 . 5 6.6 25 27 30 tPHL A or B Y MAX 19 20 7. 51 05 . 5 6.3 25 27 30 PARAMETER INPUT OUTPUT MAX or MIN CD74 HCT AC SN74 AC CD74 AC ACT SN74 ACT CD74 ACT AHC AHCT tPLH Ao rB Y MAX 38 6.9 8.5 8.7 9 10 12.9 9 9 PARAMETER INPUT OUTPUT MAX or MIN LV LV LVC 3.3V ALVC tPLH A or B Y MAX 14 9 4.1 2.9 tPHL A or B Y MAX 14 9 4.1 2.9 UNIT: ns

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS S ALS F SN74 HC UNIT ICC MAX 33 8.8 57 4.2 26.3 15.3 mA IOH MAX - 0.1 0.25 0.1 - - mA IOL MAX 16 8 2 082 04 m A SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS F SN74 HC tPLH A or B Y MAX 32 35 10 54 9.6 31 tPHL A or B Y MAX 24 35 10 15 4.8 25 UNIT: ns QUADRUPLE 2-INPUT POSITIVE-AND GATES WITH OPEN-COLLECTOR OUTPUTS

• Y = A•B

Logic Diagram (SN74) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS TRIPLE 3-INPUT POSITIVE-NAND GATES

• Y = A•B•C
• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) 12 1Y 6 2Y 8 3Y ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC SN74 HCT CD74 HCT AC SN74 AC CD74 AC UNIT IOL MAX 1682 082 02 0 4444 2 4 2 4 2 4 m A PARAMETER MAX or MIN ACT SN74 ACT CD74 ACT LV LV LVC ALVC 3V UNIT IOH MAX -24 -24 -24 -6 -12 -24 -24 mA IOL MAX 24 24 24 6 12 2 42 4 m A SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC SN74 HCT CD74 HCT tPLH A, B or C Y MAX 22 15 4.5 11 4.5 6 24 30 19 36 tPHL A, B or C Y MAX 15 15 5 10 4.5 5.3 24 30 19 36 PARAMETER INPUT OUTPUT MAX or MIN AC SN74 AC CD74 AC ACT SN74 ACT CD74 ACT LV LV LVC ALVC UNIT: ns FUNCTION TABLE (each gate) INPUTS OUTPUT ABC Y HHH L LX H XL X XH XXL H

Logic Diagram (SN74) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. TRIPLE 3-INPUT POSITIVE-AND GATES

• Y = A•B•C
• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) 12 1Y 6 2Y 8 3Y ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LS S ALS AS F SN74 HC CD74 HC SN74 HCT CD74 HCT AC SN74 AC UNIT IOL MAX 82 082 02 0 4444 2 4 2 4 m A PARAMETER MAX or MIN ACT SN74 ACT LV LV 5V UNIT ICC MAX 0.04 0.02 - 0.02 mA IOH MAX -24 -24 -6 -12 mA IOL MAX 24 24 6 12 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN LS S ALS AS F SN74 HC CD74 HC SN74 HCT CD74 HCT tPLH A, B or C Y MAX 15 7 13 6 6.6 25 30 21 42 tPHL A, B or C Y MAX 20 7.5 10 5.5 6.5 25 30 21 42 PARAMETER INPUT OUTPUT MAX or MIN AC SN74 AC ACT SN74 ACT LV LV tPLH A, Bo rC Y MAX 6.5 8.5 9.6 10.5 14 9 tPHL A, Bo rC Y MAX 6.9 7.5 8.7 10.5 14 9 UNIT: ns FUNCTION TABLE (each gate) INPUTS OUTPUT ABC Y HHH H LX L XL X XL XXL L

Logic Diagram (SN74) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS HEX SCHMITT-TRIGGER INVERTERS

• Y = A
• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (Series)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) YA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 AC CD74 AC SN74 ACT CD74 ACT AHC AHCT UNIT IOL MAX 16 84444 2 4 2 4 2 4 2 4 88 m A PARAMETER MAX or MIN LV LV LVC ALVC AUC 1.8V AUC 2.5V UNIT IOH MAX -6 -12 -24 -24 -8 -9 mA IOL MAX 6 12 2 42 4 8 9m A SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 AC CD74 AC SN74 ACT CD74 ACT tPLH Ao rB Y MAX 22 22 31 41 40 57 11 10.5 12.5 14.5 tPHL Ao rB Y MAX 22 22 31 41 40 57 9.5 10.5 11 9.5 PARAMETER INPUT OUTPUT MAX or MIN AHC AHCT LV LV LVC ALVC AUC 1.8V AUC 2.5V UNIT: ns

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. HEX INVERTER BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS

• Y = A HEX SCHMITT-TRIGGER BUFFER
• Y = A AY PARAMETER MAX or MIN TTL UNIT ICC MAX 51 mA VOH MAX 15 V IOL MAX 40 mA PARAMETER INPUT OUTPUT MAX or MIN TTL tPLH AY MAX 15 tPHL AY MAX 23 UNIT: ns ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL AUC 1.8V AUC 2.5V UNIT ICC MAX 41 0.01 0.01 mA IOH MAX 0.25 -8 -9 mA IOL MAX 40 8 9 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL AUC 1.8V AUC 2.5V tPLH AY MAX 15 2. 41 . 9 tPHL AY MAX 26 2. 41 . 9 UNIT: ns

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS HEX SCHMITT-TRIGGER INVERTERS

• Y = A
• P-N-P Input Reduce System Loading (IIL = -0.05mA MAX)
• Excellent Noise Immunity with Typical Hysteresis of 0.8V ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LS UNIT ICC MAX 30 mA IOH MAX -0.4 mA IOL MAX 8 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN LS tPLH A or B Y MAX 20 tPHL A or B Y MAX 30 UNIT: ns

Logic Diagram (SN74) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. DUAL 4-INPUT POSITIVE-NAND GATES

• Y = A•B•C•D
• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) 1Y1B 2Y2B ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC CD74 HCT UNIT IOL MAX 16 8 2 082 0 2 04 4 4 m A PARAMETER MAX or MIN AC CD74 AC ACT CD74 ACT LV LV 5V UNIT IOH MAX -24 -24 -24 -24 -6 -12 mA IOL MAX 24 24 24 24 61 2 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC CD74 HCT tPLH A, B, C or D Y MAX 22 15 4.5 11 5 6 28 30 42 tPHL A, B, C or D Y MAX 15 15 5 10 4.5 5.3 28 30 42 PARAMETER INPUT OUTPUT MAX or MIN AC CD74 AC ACT CD74 ACT LV LV UNIT: ns FUNCTION TABLE (each gate) INPUTS OUTPUT ABC Y HHH L LX H XL X XH XXL D H X X XH XXXL H

DUAL 4-INPUT POSITIVE-AND GATES

• Y = A•B•C•D
• 74AC11xxx: Product Available in Reduced- Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced- Noise Advanced CMOS (11000 Series) 246 Logic Diagram (SN74) Logic Diagram (SN74) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS DUAL 4-INPUT POSITIVE-NOR GATES WITH STROBE
• Y = G (A + B + C + D) 1Y1B 2Y2B A OUTPUT Y GATE 1 OF SN5423/SN7423 ONLY B C D G XX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LS ALS AS F SN74 HC CD74 HC CD74 HCT AC ACT LV LV 5V UNIT IOL MAX 8 8 20 20 4 4 4 24 24 6 12 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN LS ALS AS F SN74 HC CD74 HC CD74 HCT AC ACT tPLH A, B, C or D Y MAX 15 15 6 5.3 28 33 41 8.8 9.8 tPHL A, B, C or D Y MAX 20 10 6 5.5 28 33 41 6.9 8.9 PARAMETER INPUT OUTPUT MAX or MIN LV LV tPLH A, B, C or D Y MAX 12 8 tPHL A, B, C or D Y MAX 12 8 UNIT: ns PARAMETER MAX or MIN TTL UNIT ICC MAX 19 mA IOH MAX -0.8 mA IOL MAX 16 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL tPLH A or B Y MAX 22 tPHL A or B Y MAX 15 UNIT: ns ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS FUNCTION TABLE (each gate) INPUTS OUTPUT ABC Y HHH H LX L XL X XL XXL D H X X XL XXXL L FUNCTION TABLE (each gate) INPUTS Expander inputs are open. H = high level, L = low level, X = irrelevant OUTPUT ABC Y HXX L XH L XX X HL XXX D X X X HL LLLL G H H H H XH XXXXL H

TRIPLE 3-INPUT POSITIVE-NOR GATES

• Y = A + B + C
• 74AC11xxx: Product Available in Reduced- Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced- Noise Advanced CMOS (11000 Series) 247 Logic Diagram Logic Diagram (SN74) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. QUADRUPLE 2-INPUT HIGH-VOLTAGE INTERFACE POSITIVE-NAND GATES
• Y = AB A C YB ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS UNIT ICC MAX 22 4.4 mA VOH MAX 15 15 V IOL MAX 16 8 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS tPLH A or B Y MAX 24 32 tPHL A or B Y MAX 17 28 UNIT: ns ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS ALS AS F SN74 HC CD74 HC CD74 HCT AC ACT LV LV 5V UNIT IOL MAX 16 8 8 20 20 4 4 4 24 24 6 12 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS ALS AS F SN74 HC CD74 HC CD74 HCT AC tPLH A, B or C Y MAX 15 15 15 5.5 5.5 23 29 35 7.7 tPHL A, B or C Y MAX 11 15 9 4.5 4.5 23 29 35 8.1 PARAMETER INPUT OUTPUT MAX or MIN ACT LV LV tPLH A, Bo rC Y MAX 10.1 14 9 tPHL A, B or C Y MAX 9.4 14 9 UNIT: ns FUNCTION TABLE (each gate) INPUTS OUTPUT ABC Y HXX L XH L XX X HL LLL H

Logic Diagram (SN74) Logic Diagram : OBSOLETED or NOT RECOMMENDED NEW DESIGNS DELAY ELEMENTS

• Delay Elements for Generating Delay Line
• Inverting and Non-inverting Elements
• Buffer NAND Elements Rated at IOL of 12/24mA
• P-N-P Inputs Reduce Fan-In (IIL = -0.2mA MAX)
• Worst Case MIN/MAX Delays Guaranteed Across Temperature and VCC Range 8-INPUT POSITIVE-NAND GATES
• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) Y A B C D E F G H Y1A1 Y2A2 (2)(1) (4)(3) (13) (15) (5) (6) (7) (10) (11) (9) (12) (14) ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC CD74 HCT AC ACT

IOL MAX 16 8 2 082 0 2 04 4 42 4 2 4 m A SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC CD74 HCT AC ACT tPLH A thru H Y MAX 22 15 6 1 055 . 5 3 3 3 94 27 .2 8.5 tPHL A thru H Y MAX 15 20 7 12 4.5 53 3 3 9 4 27 . 4 8.7 UNIT: ns ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS MAX or MIN LS UNIT ICC MAX 20 mA Y3, Y4 outputs MAX -1.2 mA All other outputs MAX -0.4 mA Y3, Y4 outputs MAX 24 mA All other outputs MAX 8 mA I OH PARAMETER IOL SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN LS tPLH 65 tPHL 45 tPLH 80 tPHL 95 tPLH A3, B3 15 tPHL A4, Y4 15 UNIT: ns MAX MAX A1, A6 A2, A5 Y1, Y6 Y2, Y5 Y3, Y4 MAX FUNCTION TABLE INPUTS A–H OUTPUT Y All inputs H L One or more inputs L H

Logic Diagram (SN74) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. QUADRUPLE 2-INPUT POSITIVE-OR GATES

• Y = A + B A B Y ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC SN74 HCT CD74 HCT AC

IOL MAX 1682 082 02 0 4444 2 4 m A PARAMETER MAX or MIN SN74 AC CD74 AC ACT SN74 ACT CD74 ACT AHC AHCT LV LV LVC ALVC 3V UNIT IOH MAX -24 -24 -24 -24 -24 -8 -8 -6 -12 -24 -24 mA IOL MAX 24 24 24 24 24 8 8 6 12 24 24 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC SN74 HCT tPLH A or B Y MAX 15 22 7 14 5.8 6.6 25 27 30 tPHL A or B Y MAX 22 22 7 12 5.8 - 25 27 30 PARAMETER INPUT OUTPUT MAX or MIN CD74 HCT AC SN74 AC CD74 AC ACT SN74 ACT CD74 ACT AHC AHCT PARAMETER INPUT OUTPUT MAX or MIN LV LV LVC ALVC tPLH A or B Y MAX 13 8.5 3.8 2.8 tPHL A or B Y MAX 13 8.5 3.8 2.8 UNIT: ns AUC 2.3V 2.1 2.1 AUC 1.8V 2.5 2.5 AUC 0.01 AUC 1.8V 2.3V 0.01

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS QUADRUPLE 2-INPUT POSITIVE-NOR BUFFERS WITH OPEN-COLLECTOR OUTPUTS

• Y = A + B HEX BUFFER GATE
• Y = A AY ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS ALS UNIT ICC MAX 16.5 13.8 9 mA VOH MAX 5.5 5.5 5.5 V IOL MAX 48 24 24 mA SWITCHING CHARACTERISTICS PARAMETER INPUT O UTPUT MAX or MIN TTL LS ALS tPLH A or B Y MAX 15 32 33 tPHL A or B Y MAX 18 28 12 UNIT: ns ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN AUC 1.8V AUC 2.5V UNIT ICC MAX 0.01 0.01 mA IOH MAX -8 -9 mA IOL MAX 8 9 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN AUC 1.8V AUC 2.5V tPLH 2.4 1.8 tPHL 2.4 1.8 UNIT: ns A MAXY FUNCTION TABLE (each gate) A Y INPUT OUTPUT L H L H

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 251 Logic Diagram35 HEX NONINVERTERS WITH OPEN-COLLECTOR OUTPUTS

• Y = A 1A 1Y 2A 2Y 3A 3Y 4A 4Y 5A 5Y 6A 6Y ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN ALS UNIT ICC MAX 63 mA VOH MAX 5.5 V IOL MAX 8 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN ALS tPLH AY MAX 50 tPHL AY MAX 14 UNIT: ns

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS

• Y = A•B ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS S ALS F UNIT ICC MAX 54 12 80 7.8 33 mA IOH MAX -1.2 -1.2 -3 -2.6 -15 mA IOL MAX 48 24 60 24 64 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS F tPLH A or B Y MAX 22 24 6.5 86 . 5 tPHL A or B Y MAX 15 24 6.5 7 5 UNIT: ns

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS WITH OPEN-COLLECTOR OUTPUTS

• Y = A•B ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS S ALS F UNIT ICC MAX 54 12 80 7.8 30 mA IOL MAX 48 24 60 24 64 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS F tPLH A or B Y MAX 22 32 10 33 13 tPHL A or B Y MAX 18 28 10 12 5.5 UNIT: ns

Logic Diagram (SN74) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 4-LINE-TO-10-LINE DECODERS (1 of 10)

• All Outputs Are High for Invalid Input Conditions
• Also for Applications as 3-Line to 8-Line Decoders 4-Line to 16-Line Decoders
• Full Decoding of Valid Input Logic Ensures That All Inputs Remain Off for All Invalid Input Conditions0 A B C D

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 255 ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS SN74 HC CD74 HC CD74 HCT UNIT ICC MAX 56 13 0.08 0.16 0.16 mA IOH MAX -0.8 -0.4 -4 -4 -4 mA IOL MAX 16 8444 m A SWITCHING CHARACTERISTICS PARAMETER INTPUT OUTPUT MAX or MIN TTL LS SN74 HC CD74 HC CD74 HCT tPLH 2Level · Logic 0-9 25 25 38 45 53 tPHL 2Level · Logic 0-9 25 25 38 45 53 tPLH 3Level · Logic 0-9 30 30 38 45 53 tPHL 3Level · Logic 0-9 30 30 38 45 53 UNIT: ns MAX MAX A, B, C or D A, B, C or D No. INPUTS D FUNCTION TABLE (SN74) CBA 0123456789 OUTPUTS L H L L L LL LL L H L H H HH LH H H H HL H L H H L H H H H H H H H H H H H H L H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H L H H H H H H H L H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H L H H H H H HH L L L H L L L L L L H L L L L L L LH L H H H H H H H H H H H L H INVALID

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS256 BCD-TO-DECIMAL DECODERS/DRIVERS

• 80-mA Sink-Current Capability
• All Outputs Are Off for Invalid BCD Input Conditions Logic Diagram (SN74) A B C D

257PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING C PARAMETER MAX or MIN TTL UNIT ICC MAX 70 mA VO (on) MAX 0.9 V IOL MAX 80 mA SWITCHING CHARACTERISTICS PARAMETER MAX or MIN TTL tPLH 25 tPHL 25 UNIT: ns MAX No. INPUTS D FUNCTION TABLE CBA 0123456789 OUTPUTS L H L L L LL LL L H L H H HH LH H H H HL H L H H L H H H H H H H H H H H H H L H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H L H H H H H H H L H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H L H H H H H HH L L L H L L L L L L H L L L L L L LH L H H H H H H H H H H H L H INVALID

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS258 Logic Diagram BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS

• Open-Collector Outputs
• Lamp-Test Provision
• Leading/Trailing Zero Suppression INPUT A INPUT B INPUT C INPUT D BI/RBO BLANKING INPUT OR RIPPLE-BLANKING OUTPUT LT LAMP-TEST INPUT RBI RIPPLE-BLANKING INPUT (7) (13) (12) (11) (10) (9) (15) (14) OUTPUT a OUTPUT b OUTPUT c OUTPUT d OUTPUT e OUTPUT f OUTPUT g (1) (2) (6) (4) (3) (5)

259PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS UNIT ICC MAX 103 13 mA IOH MAX -0.2 -0.05 mA IOL MAX 8 3.2 mA TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS toff AA t o g MAX 100 100 ton AA t o g MAX 100 100 toff RBI A to g MAX 100 100 ton RBI A to g MAX 100 100 UNIT: ns No. INPUTS D FUNCTION TABLE CBA BI/RBO OUTPUTS L L L L L L L H H L H H H H H H BI RBI LT LT H H H H H H H H H H H H H H H H X H RBI X HL L L L H H H H H L L H H L L H H H H L H L H L L H H H H H H H H H H H H L L H a ON OFF ON ON OFF OFF ON ON ON ON OFF OFF OFF ON OFF OFF OFF OFF ON H H H H H H H H X X X X X X X X X X X X X X X L XL X L X X L X X L X X L X H H H H H H H L L L L L L L L L L L L b ON ON ON ON ON ON OFF ON OFF OFF OFF OFF ON c ON OFF ON ON ON ON ON OFF OFF OFF OFF OFF ON d ON OFF ON ON OFF OFF ON ON OFF OFF ON OFF OFF OFF ON e ON OFF ON ON ON OFF OFF ON OFF OFF OFF ON f ON OFF OFF ON ON ON OFF OFF ON OFF OFF OFF ON g OFF ON ON OFF ON ON ON ON OFF OFF OFF ON ON ON OFF OFF OFF ON ON ON OFF ON OFF OFF ON ON ON ON OFF OFF OFF OFF OFF OFF ON OFF ON ON ON ON OFF ON ON ON ON ON ON OFF H = high level, L = low level, irrelevant NOTES: 1. The blanking input (BI) must be open held at high logic level when output functions 0 through 15 are desired. The ripple-blanking input (RBI) must be open or high it blanking of a decimal zero is not desired. 2. When a low logic level is applied directly to the blanking input (BI), all segment outputs are off regardless of the level of any other input. 3. When ripple-blanking input (RBI) and inputs A, B, C, and D are at a low level with the lamp test input high, all segment outp uts go off and the ripple-blanking input/ripple blanking output (BI/RBI) is open or held high and a low is applied to the lamp-test input, all segment outputs are on. † BI/RBO is wire AND logic serving as blanking input (BI) and/or ripple-blanking output (RBI).

• '51, 'S51: Y = AB + CD 1F2A ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS S F SN74 HC UNIT ICC MAX 14 2.8 22 7.5 0.08 mA IOH MAX -0.4 -0.4 -1 -1 -4 mA IOL MAX 16 8 2 02 0 4m A SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS S F SN74 HC tPLH Any Y MAX 22 20 5.5 6.5 35 tPHL Any Y MAX 15 20 5.5 4.5 35 UNIT: ns S51 Logic Diagram : OBSOLETED or NOT RECOMMENDED NEW DESIGNS LS51

ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN S F UNIT ICC MAX 16 4.7 mA IOH MAX -1 -1 mA IOL MAX 20 20 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN S F tPLH Any Y MAX 5.5 7 tPHL Any Y MAX 5.5 5.5 UNIT: ns 4-2-3-2 INPUT AND-OR INVERT GATES

• Y = ABCD + EF + GHI + JK D A B F E C I G Y H K J Logic Diagram PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.

J CLR Q K Q J K CL CL R 12 (9) Q 13 (8) Q 14 (7) CD74HC/HCT73 SN74LS73 3(10) J K 1 (5) CP 2 (6) R : OBSOLETED or NOT RECOMMENDED NEW DESIGNS DUAL J-K FLIP-FLOPS WITH CLEAR

263PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. INPUTS J FUNCTION TABLE (SN74) KQ OUTPUTS X L H L HH L H H H CLOCK X X L L H H L H L H L H TOGGLE CLEAR Q XHH X Q0 Q0 TRUTH TABLE (CD74) INPUTS OUTPUTS R CP J K Q Q LX X X L H H ↓ LL No Change H ↓ H H ↓ L L H H L L H H ↓ HH Toggle HH XX No Change NOTE: H = High Level (Steady State) L = Low Level (Steady State) X = Irrelevant ↓ = High-to-Low Transition ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS SN74 HC CD74 HC CD74 HCT UNIT ICC MAX 20 6 0.04 0.08 0.08 mA IOH MAX 16 8444 m A IOL MAX -0.4 -0.4 -4 -4 -4 mA TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN TTL LS SN74 HC CD74 HC CD74 HCT MIN 15 30 2 52 02 0 tw CLOCK"L" 20 - 20 - - CLOCK"H" 47 20 20 - - CP Pulse Wide --- 2 4 2 4 CLEAR "L" 25 20 20 24 27 tsu CLK 0 ↑ 20 ↓ 25 ↓ -- J,K to CP --- 2 4 2 4 th CLK 0 ↓ 0 ↓ 0 ↓ -- J,K to CP ---3 3 tPLH 25 20 39 44 51 tPHL -2 0 3 94 45 1 tPLH -2 0 3 94 45 1 tPHL 40 20 39 44 51 tPLH 25 20 32 - - tPHL 40 20 32 - - tPLH --- 4 8 5 7 tPHL --- 4 8 5 7 tPLH --- 4 8 5 4 tPHL --- 4 8 5 4 UNIT fmax : MHz, other : ns CP Q MAX CP Q MAX CLEAR Q MAX CLOCK Q or Q MAX MIN CLEAR Q MAX PARAMETER fmax MIN MIN

Logic Diagram (SN74) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) TG C C TG C TG C C C C TG C C PRE CLK D CLR Q Q C PRE INPUTS D FUNCTION TABLE (SN74) Q OUTPUTS X X X H LH H L L H CLOCK X H L H L L CLR Q H XHQ 0 Q0 H L H L H H X X L LH † This configuration is unstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC SN74 HCT CD74 HCT AC SN74 AC UNIT IOL MAX 1682 082 02 0 4444 2 4 2 4 m A PARAMETER MAX or MIN CD74 AC ACT SN74 ACT CD74 ACT AHC AHCT LV LV LVC AUC 1.8V AUC 2.5V UNIT IOH MAX -24 -24 -24 -24 -8 -8 -6 -1 2- 2 4 - 8 - 9 m A IOL MAX 24 24 24 24 8 8 6 12 24 8 9 mA

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 265 TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC MIN 15 2 57 53 4 1 0 5 100 25 20 tw CLOCK"H" MIN 30 25 6 14.5 4 4 20 24 CLOCK"L" MIN 37 - 7.3 14.5 5.5 5 20 24 PRE, CLR "L" MIN 30 2 571 54 42 5 2 4 tsu D ATA MIN 2 0 2 0 3 15 4.5 3 25 18 PRE, CLR INACTIVE MIN 20 - - 1 0 226- MIN 55200103 tPLH 25 25 6 13 7.5 7.1 58 60 tPHL 40 40 13.5 15 10.5 10.5 58 60 tPLH 25 25 6 13 7.5 7.1 58 60 tPHL 40 40 13.5 15 10.5 10.5 58 60 tPLH 25 25 9 16 8 7.8 44 53 tPHL 40 40 9 18 9 9.2 44 53 INPUT OUTPUT MAX or MIN SN74 HCT CD74 HCT AC SN74 AC CD74 AC ACT SN74 ACT CD74 ACT MIN 22 16 125 125 110 100 125 85 tw CLOCK"H" MIN 23 27 4 5 4.5 5 6 5.7 CLOCK"L" MIN 23 27 4 5 4.5 5 6 5.7 PRE, CLR "L" MIN 20 24 4 54565 tsu D ATA MIN 1 5 1 8 3 . 5 3 3.5 4.5 3.5 4 PRE, CLR INACTIVE MIN 0 - 1 0- 20- MIN 0 3 0 0.5 0 0 1 0 INPUT OUTPUT MAX or MIN AHC AHCT LV LV LVC AUC 1.8V AUC 2.5V MIN 75 6 54 57 5 100 300 350 tw CLOCK"H" MIN 5 5 7 5 3.3 0.5 0.5 CLOCK"L" MIN 5 5 7 5 3.3 0.5 0.5 PRE, CLR "L" MIN 5 5 7 5 3.3 1.5 1.5 tsu D ATA MIN 5 5 753 0 . 6 0.7 PRE, CLR INACTIVE MIN 3 3.5 5 3 2 0.2 0.3 tPLH 11 13 18 11 5.4 3.1 2.5 tPHL 11 13 18 11 5.4 3.1 2.5 tPLH 11 13 18 11 5.4 3 2.4 tPHL 11 13 18 11 5.4 3 2.4 UNIT fmax : MHz, other : ns MAX CLR MAX CLOCK Q or Q MAX Q or Q Q or Q PARAMETER fmax th PRE PARAMETER fmax th Q or Q PRE CLR CLOCK Q or Q Q or Q PARAMETER fmax th MAX MAX MAX MAX CLR MAX CLOCK Q or Q MAX PRE Q or Q Q or Q

3 (7) 2 (6) LATCH 0 QD LE LE 16 (10) 1 (11) E 13 (4) LATCH 1 QD LE LE 14 (8) 15 (9)

12 GND

C : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 4-BIT BISTABLE LATCHES ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS SN74 HC CD74 HC CD74 HCT UNIT ICC MAX 53 12 0.04 0.08 0.08 mA IOH MAX -0.4 -0.4 -4 -4 -4 mA IOL MAX 16 8 4 44 m A TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS SN74 HC CD74 HC CD74 HCT tw 20 20 20 24 24 tsu 20 20 2 51 81 8 th MIN MIN MIN 55533 tPLH 30 27 30 33 42 tPHL 25 17 30 33 42 tPLH 40 20 30 39 42 tPHL 15 15 30 39 42 tPLH 30 27 33 39 42 tPHL 15 25 33 39 42 tPLH 30 30 33 39 45 tPHL 15 15 33 39 45 UNIT: ns DQ MAX DQ MAX GQ MAX GQ MAX INPUTS FUNCTION TABLE (SN74) Q OUTPUTS L HL Q H Q0 Q0 D L H X H L C H

Logic Diagram (SN74) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 4-BIT MAGNITUDE COMPARATORS A = B (3) A > B (4) A < B (2) A2 (13) B2 (14) A1 (12) B1 (11) A0 (10) B0 (9) A = B(6) A < B(7) A > B(5) A3 (15) B3 (1) ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS S SN74 HC CD74 HC CD74 HCT UNIT ICC MAX 88 20 115 0.08 0.16 0.16 mA IOH MAX -0.4 -0.4 -1 -4 -4 -4 mA IOL MAX 16 8 2 0 444 m A SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT Nunber of Gate Levels MAX or MIN TTL LS S SN74 HC CD74 HC CD74 HCT A< B, A > B 3 MAX 26 36 16 58 59 56 A=B 4M A X 3 5 45 18 50 53 60 A< B, A > B 3 MAX 30 30 16.5 58 59 56 A=B 4M AX 30 45 16.5 50 53 60 tPLH A< B, A = B A > B 11 1 2 2 7 . 5 44 42 45 tPHL A< B, A = B A > B 11 7 1 7 8 . 5 44 42 45 tPLH A=B A=B 22 02 0 10.5 37 - - tPHL A=B A=B 21 7 2 6 7 . 5 3 7 - - tPLH A> B, A = B A < B 11 1 2 2 7 . 5 44 42 45 tPHL A> B, A = B A < B 11 7 1 7 8 . 5 44 42 45 UNIT: ns MAX MAX MAX t PLH tPHL Any A or B data input Any A or B data input FUNCTION TABLE (SN74) OUTPUTS LH A>BA>B X A<B A<BA=B A=B COMPARING INPUTS A2, B2 A0, B0 X X X A3, B3 A3>B3 CASCADING INPUTS A2>B2 A2<B2 A2=B2 XX L A1, B1 X A3<B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A2=B2 A2=B2 A2=B2 A2=B2 A2=B2 A2=B2 A2=B2 A2=B2 LXXX X LX LHXXX X LX LXX XX LX LHXXX X L LXXX X L LHXXX L LXXX L LHHLL L LLH L LHH L LHLL HXXH L A1>B1 A0>B0 A1<B1 A0<B0 A1=B1 A0=B0 A1=B1 A0=B0 A1=B1 A0=B0 A1=B1 A0=B0 A1=B1 A0=B0 A1=B1 A1=B1 L L L L L H H H H H H

= 1 Exclusive OR 1A 1Y (1) (3) (2) 2A 2Y (4) (6) (5) 3A 3Y (9) (8) (10) 4A 4Y (12) (11) (13) An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols. 268 Logic Diagram (SN74) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

• Y = A ⊕ B or Y = AB + AB
• 74AC11xxx : Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC CD74 HCT AC SN74 AC CD74 AC ACT

IOH MAX 16 8 2 082 0 2 04 4 42 4 24 24 24 mA PARAMETER MAX or MIN SN74 ACT CD74 ACT AHC AHCT LV LV LVC 3V UNIT IOH MAX 24 24 -10 8 6 12 24 mA IOL MAX -24 -24 10 -8 -6 -12 -24 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC CD74 HCT AC tPLH Input Low Y MAX 23 23 10.5 17 7.5 6.5 25 36 48 7.6 tPHL Input Low Y MAX 17 17 10 12 6.5 6.5 25 36 48 6.8 tPLH Input High Y MAX 30 30 10.5 17 6.5 8 25 36 48 7.6 tPHL Input High Y MAX 22 22 10 10 7 7.5 25 36 48 6.8 PARAMETER INPUT OUTPUT MAX or MIN SN74 AC CD74 AC ACT SN74 ACT CD74 ACT AHC AHCT LV LV LVC UNIT: ns A or B A or B A or B A or B

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. DECADE COUNTER J (8)Q CK QC K J (12)Q CK QA K S (11)Q Q CK QD R0(1) (2) R J (9)Q CK QB K R0(2) (3) R9(1) (6) R9(2) CKA CKB (7) (14) (1) QB BCD COUNT SEQUENCE OUTPUTS L L QCQD Count H H QA FUNCTION TABLE L L L L L L L L L L L L H H H H L L H H L L H H L L L H L H L H L H L H QC BI-QUINARY OUTPUTS L L QDQA Count H H QB L L L L L L L L H L L H H L L H H L L H L H L H L H L H H H H L L L LL QB RESET/COUNT OUTPUTS L L QCQD QA H L L Count L L L L L H R9(1) RESET INPUTS H H R0(2)R0(1) R9(2) X X L L X L Count Count Count H HX X X L L X L X L X L H X L H X L X L ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS UNIT ICC MAX 39 15 mA IOH MAX -0.8 -0.4 mA IOL MAX 16 8 mA TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN TTL LS AQ A 3 2 3 2 BQ B 1 6 1 6 A1 5 1 5 B3 0 3 0 RESET 15 30 t PLH 16 16 tPHL 18 18 tPLH 48 48 tPHL 50 50 tPLH 16 16 tPHL 21 21 tPLH 32 32 tPHL 35 35 tPLH 32 32 tPHL 35 35 tPHL Set to 0 Any MAX 40 40 tPLH QA, QD 30 30 tPHL QB, QC 40 40 UNIT fmax : MHz, other : ns tsu MIN 25 25RESET INACTIVE PARAMETER fmax tw MAX A A B B Set to 9 QC QD MIN QC MIN MAX MAX QA MAX BQ B MAX MAX

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS DIVIDE-BY-TWELVE DECODE COUNTERS QA (12) QB (11) QC (9) QD (8) JQ CK K JQ CK K JQ Q CK K JQ CK K R0(1) (6) (7)R0(2) CKA CKB (1) (14) QB FUNCTION TABLE COUNT SEQUENCE RESET/COUNT OUTPUTS L L QCQD COUNT H H QA L L L L L L L L L L H H L L H H L L L L L H L H L H L H L HQB OUTPUTS L QCQD QA L COUNT LL RESET INPUTS H L R0(2)R0(1) X COUNT H L X H H L L L L L H H H H H H H ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS UNIT ICC MAX 39 15 mA IOH MAX -0.8 -0.4 mA IOL MAX 16 8 mA TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN TTL LS AQ A 3 2 3 2 BQ B 1 6 1 6 A1 5 1 5 B3 0 3 0 RESET 15 30 t PLH 16 16 tPHL 18 18 tPLH 48 48 tPHL 50 50 tPLH 16 16 tPHL 21 21 tPLH 16 16 tPHL 21 21 tPLH 32 32 tPHL 35 35 tPHL Set to 0 Any MAX 40 40 UNIT fmax : MHz, other : ns B A MAX MIN MIN MIN MAX MAXQD QB QC A B B PARAMETER fmax tw tsu RESET INACTIVE 25 25 QD QA MAX MAX

Logic Diagram (SN74) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 4-BIT BINARY COUNTERS QA (12) (9) (8) (11) QB QC QD JQ CK K JQ CK K JQ CK K JQ CK K R0(1) (2) (3)R0(2) CKA CKB (1) (14) QB FUNCTION TABLE (SN74) COUNT SEQUENCE OUTPUTS L L QCQD COUNT H H QA L L L L L L L L H H L L H H L H L H L H L H L H QB OUTPUTS L QCQD QA L COUNT LL RESET INPUTS H L R0(2)R0(1) X COUNT H L X H H L L L H H12 H H13 H H14 H H15 H L L H H L L L L H H L L H H L L H H L H L H RESET/COUNT ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS CD74 HC CD74 HCT UNIT ICC MAX 39 15 0.16 0.16 mA IOH MAX -0.8 -0.4 -4 -4 mA IOL MAX 16 8 4 4 mA TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN TTL LS CD74 HC CD74 HCT A (CD74:CP0) QA (CD74:Q 0) 32 32 20 20 B (CD:74CP1) QB (CD74:Q 1) 16 16 20 20 A (CP0) 15 15 24 24 B (CP1) 30 30 24 24 RESET 15 30 24 24 tPLH 16 16 38 51 tPHL 18 18 38 51 tPLH 70 70 - - tPHL 70 70 - - tPLH 16 16 41 51 tPHL 21 21 41 51 tPLH 32 32 56 69 tPHL 35 35 56 69 tPLH 51 51 74 87 tPHL 51 51 74 87 tPHL Set to 0 ANY MAX 40 40 - - UNIT fmax : MHz, other : ns CKB (CP1) QA (Q0) QD (Q3) QC (Q2) QD (Q3) CKA (CP0) CKA (CP0) CKB (CP1) QB (Q1) CKB (CP1) MAX MAX MAX MAX MAX MIN MIN 25RESET INACTIVE PARAMETER fmax tw tsu --MIN 25

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS272 Logic Diagram SYNCHRONOUS 6-BIT BINARY RATE MULTIPLIERS

• Perform Fixed-Rate or Variable-Rate Frequency Division
• Typical Maximum Clock Frequency: 32MHz G CLEAR T QF QF G CLEAR T QE QE G CLEAR T QD QD G CLEAR T QC QC G CLEAR T QB QB G CLEAR T QA QA ENABLE OUTPUT RATE INPUT B0 (7) (4)RATE INPUT B1 (1)RATE INPUT B2 RATE INPUT B3 UNITY/CASCADE INPUT Z OUTPUT Y OUTPUT RATE INPUT B4 ENABLE INPUT CLEAR CLOCK STROBE RATE INPUT B5 (14) (12) (5) (6) (15)(2)(3) (13) (11) (9) (10)

273PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. OUTPUTS H L B5CLEAR Y FUNCTION TABLE L L L L L L X L L L H H H H L H L L L L L L 8L H L STROBE L L L L L L L L L X L ENABLE L L L L L L L L L NUMBER OF CLOCK PULSES X UNITY/ CASCADE H H 64 H 64 H 64 H 64 H 64 H 64 H 64 H 64 L 64 H BINARY RATE B X L L L H L H L L X L L L H H H L L X L L L H L H L L X L L H L H L L L X L L H L H L L L LLLLL H H H H H INPUTS Z H H ENABLE H LOGI LEVEL OR NUMBER OF PULSES ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL UNIT ICC MAX 120 mA IOH MAX 16 mA IOL MAX -0.4 mA TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN TTL AQ A M I N 2 5 tw CLK MIN 20 CLR MIN 15 tsu Positive MIN 25 Negative MIN 0 th Positive MIN 0 Negative MIN 20 tPLH MAX 20 tPHL MAX 21 tPLH MAX 18 tPHL MAX 23 tPLH MAX 39 tPHL MAX 30 tPLH MAX 18 tPHL MAX 26 tPLH MAX 10 tPHL MAX 14 tPLH MAX 14 tPHL MAX 10 tPLH MAX 30 tPHL MAX 33 tPLH MAX 30 tPHL MAX 33 tPLH Y MAX 36 tPHL Z MAX 23 tPLH MAX 23 tPHL MAX 23 UNIT fmax : MHz, other : ns CLR RATE Y Y STRB Y CLK ENABLE UNITY /CAS CLK Z RATE Z STRB Z CLK Y PARAMETER fmax ENABLE ENABLE

J K CL CL R 3 (5) Q 2 (6) Q 1 (8) 4(11) J K 12 (9) CP 13 (10) R K QQ CLR J CLK : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 107 DUAL J-K FLIP-FLOPS WITH CLEAR Logic Diagram CD74HC/HCT

275PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS SN74 HC CD74 HC CD74 HCT UNIT ICC MAX 20 6 0.04 0.08 0.08 mA IOH MAX -0.4 -0.4 -4 -4 -4 mA IOL MAX 16 8444 m A TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN TTL LS SN74 HC CD74 HC CD74 HCT MIN 15 30 2 52 01 9 tw CLK H MIN 20 20 20 - - CLK L MIN 47 - 20 - - CP MIN - - - 24 27 CLR L (or R) MIN 25 25 2 02 43 6 tsu J, K MIN 02 0 2 53 03 0 CLR INACTIVE MIN 0 25 25 - - MIN 00035 Q MAX 25 20 39 47 57 Q MAX 40 20 39 47 57 Q MAX 25 20 32 - - Q MAX 40 20 32 - - MAX - - - 51 65 MAX - - - 51 65 MAX - - - 51 60 MAX - - - 51 60 UNIT fmax : MHz, other : ns PARAMETER th t PLH fmax tPHL CLR (or R) tPLH CLKtPHL CP QtPHL tPLH CP QtPHL tPLH FUNCTION TABLES (SN74LS107A) INPUTS JK Q OUTPUTS X L H L HH L H H H CLK X X L L H H L QO H L H L H TOGGLE CLR Q QO XHX QO QOH

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS C C C C K J PRE CLK TG CLR C C TG C C TG C C Q TG Q SJ K CL CL R Q Q 6(10) 7(9) Q Q 5(11) S 2(14) J 3(13) K 4(12) CP 1(15) R FF VCC GND 276 Logic Diagram SN74, CD74AC/ACT Logic Diagram CD74HC/HCT 109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET PRE INPUTS J FUNCTION TABLE (SN74, CD74AC/ACT) Q OUTPUTS X X X L HH H L L H CLOCK X H L L CLR Q H LH Q0 Q0 H L H L H H X X HH XHQ 0 Q0 H H L TOGGLE HL X X X L H X L H K LH † The output levels in this configuration are not guaranteed to meet the minimum levels for VOH. Furthermore, this configuration is nonstable; that is, it will not persist when either PRE or CLR returns to its inactive (high) level. ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS ALS AS F SN74 HC CD74 HC CD74 HCT CD74 AC CD74 ACT UNIT IOL MAX 16 4 8 20 20 4 4 4 24 24 mA

277PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN TTL LS ALS AS F SN74 HC CD74 HC CD74 HCT MIN 25 25 34 105 90 25 20 18 tw CLK H MIN2 02 5 14.5 4 4 20 - - CLK L MIN 20 - 14.5 5.5 5 20 - - CP MIN - - - --- 2 4 2 7 PRE L MIN 20 2 51 5 4 4 2 5 - - CLR L MIN 20 2 51 5 4 4 2 5 - - tsu J, K MIN 10 2 51 55 . 53 2 5 - - PRE, CLR MIN 10 - 10 226- - MIN 65001033 Q MAX 15 25 13 8 8 58 - - Q MAX 35 40 15 10.5 10.5 58 - - Q MAX 15 25 13 8 8 58 - - Q MAX 25 40 15 10.5 10.5 58 - - MAX 16 25 16 9 8 44 - - MAX 28 40 18 9 9.2 44 - - INPUT OUTPUT MAX or MIN CD74 AC CD74 ACT MIN 100 100 tw CLK H MIN 5 5 CLK L MIN 5 5 CP MIN - - PRE L MIN 4.5 5.5 CLR L MIN 4.5 5.5 R MIN - - tsu J, K MIN 5.5 5.5 PRE, CLR MIN - 5.5 J, K to CP MIN - - MIN 0 0 Q MAX 12.2 12.2 Q MAX 12.2 12.2 Q MAX 12.2 12.2 Q MAX 12.2 12.2 MAX 10.3 10.3 MAX 10.3 10.3 MAX - - MAX - - MAX - - MAX - - MAX - - MAX - - MAX - - MAX - - UNIT fmax : MHz, other : ns t PHL tPLH CP Q RQtPHL tPHL tPLH CP Q tPHL tPLH CLK Q,Q tPHL tPLH CLR tPLH tPHL tPLH th PRE PARAMETER fmax fmax PARAMETER th tPLH PREtPHL tPLH CLRtPHL tPLH CLK Q,QtPHL tPLH CP QtPHL tPLH CP QtPHL tPLH RQtPHL tPLH tPHL RQ tPLH RQtPHL

Logic Diagram (SN74HC112) PRE CLK J CLR Q Q C C C C K TG TG TG TG C C C C C C PRE CLK K Q Q CLR J : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET Logic Diagram (SN74LVC112A)

279PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE (SN74) INPUTS OUTPUTS PRE CLR CLK J K Q Q LHX X X H L HL X X L H LL X XX X H † H† HH LL Q 0 Q0 HH HLHL HH LHLH HH HH Toggle HH H X X Q 0 Q0 †The output levels in this configuration may not meet the minimum levels for VOH. Furthermore, this configuration is nonstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level. ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LS S ALS F SN74 HC CD74 HC CD74 HCT CD74 AC CD74 ACT LVC 3V UNIT IOL MAX 8 2 082 04 4 42 4 2 4 2 4 m A TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN LS S ALS F SN74 HC CD74 HC CD74 HCT CD74 AC CD74 ACT LVC MIN 30 8 03 0 1 0 0 20 20 20 100 100 150 tw PRE, CLR MIN 25 8 10 52 5 2 42 7 4.5 4.5 - CLK H MIN 20 6 1 6.5 5 25 - - 4.5 4.5 3.3 tsu DATA MIN 20 7 22 52 5 2 42 4 4 4 2.3 PRE INACTIVE MIN 25 - 20 5 2 5- - - - 1 . 1 CLR INACTIVE MIN 20 - 20 5 2 5- - - - 1 . 1 MIN 000000300 0 . 7 MAX 20 71 5 7.5 41 - - 10.3 10.3 4.8 MAX 20 71 8 7.5 41 - - 12.2 12.2 4.8 MAX 20 71 5 7.5 31 - - 10.3 10.3 5.9 MAX 20 71 9 7.5 31 - - 12.2 12.2 5.9 UNIT fmax : MHz, other : ns PARAMETER fmax Q or Q th tPLH tPHL PRE or CLR tPLH CLK Q or QtPHL tPLH CP Q or QtPHL tPLH SQ o r QtPHL tPLH RQ o r QtPHL

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 121 MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS

• Internal Timing Resistors (2kΩ)
• Programmable Output Pulse Width with Rext/Cext: 40ns to 28s B (3) (10) (4) (5) (1) (6) (11) Cext Rint = 2 kΩ NOM C Q (9) Rint Rext / Cext NOTES: 1. An external capacitor may be connected between Cext (positive) and Rext/Cext. 2. To use the internal timing resistor, connect Rint to VCC. For improved pulse width accuracy and repestability, connect an external resistor between Rext/Cext and VCC with Rint open-circuited. ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL UNIT ICC MAX 40 mA IOH MAX -0.4 mA IOL MAX 16 mA TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL tw (out) Pulse width obtained with zero timing capacitance MIN 50 tPLH A7 0 tPHL B8 0 tPLH A5 5 tPHL B6 5 UNIT: NS Q MAX Q MAX INPUTS FUNCTION TABLE X L X L X X H Q OUTPUTS L L† H† Q H B H H L† H† L† H† H L X X L H H H L X H H ↓ ↓ See explanation of function table on page † These lines of the functional tables assume that the indicated steady-state conditions at the A and B inputs have been set up long enough to complete any pulse started before the set up.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 122 RETRIGGERABLE MONOSTABLE MULTIVIBRATORS

• Retriggerable for Very Long Output Pulse, Up to 100% Duty Cycle
• Internal Timing Resistors (5kΩ) B1 (3) A2 (2) Q(6) Q R (8) Rext/Cext (13) A1 (1) B2 (4) CLR (5) Cext (11) Rint Rint (9) Rint is nominally 10 kΩ for '122 and 'LS122 ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS UNIT ICC MAX 66 11 mA IOH MAX -0.8 -0.4 mA IOL MAX 16 8 mA TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS tw MIN 40 40 A3 3 3 3 B2 8 4 4 A4 0 4 5 B3 6 5 6 t PLH Q2 7 2 7 tPHL Q 40 45 UNIT: NS MAX MAX MAX tPLH tPHL CLEAR Q Q INPUTS FUNCTION TABLE X H Q OUTPUTS L L† H† Q H B L† H† L† H† L X CLEAR L X X X H H H H H H L L X X H H X X X H X X X X H L L ↓ ↓ X L XX XX X X HH HH HH HH H H H HH H L L See explanation of function table on page † These lines of the functional tables assume that the indicated steady-state conditions at the A and B inputs have been set up long enough to complete any pulse started before the set up.

Logic Diagram (SN74) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 123 DUAL RETRIGGERABLE MONOSTABLE MULTIVIBARATORS WITH SCHMITT-TRIGGER INPUTS

• Retriggerable for Very Long Output Pulse, Up to 100% Duty Cycle CLR Cext Rext/Cext R B A Q Q ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS CD74 HC CD74 HCT AHC AHCT LV LV 5V UNIT IOL MAX 16 844886 1 2 m A TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS CD74 HC CD74 HCT AHC A HCT LV LV tw MIN 4 04 03 03 0 5 5 5 5 A (A) 33 33 90 90 16 12 27.5 16 B2 8 4 49 09 01 61 2 2 7 . 5 1 6 A (A) 40 45 96 102 16 12 27.5 16 B3 6 5 69 6 102 16 12 27.5 16 tPLH Q4 0 4 56 57 21 31 42 21 3 tPHL Q 27 27 65 72 13 14 22 13 UNIT: NS MAX tPLH tPHL MAX MAX Q Q CLEAR (R) INPUTS FUNCTION TABLE (SN74) A (A) X H Q OUTPUTS L L† H† Q H B L† H† L CLEAR L X X H H L X X X H H L See explanation of function table on page † These lines of the functional tables assume that the indicated steady-state conditions at the A and B inputs have been set up long enough to complete any pulse started before the set up.

283PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Block Diagram 124 DUAL VOLTAGE-CONTROLLED OSCILLATORS

• Frequency Spectrum: 1Hz to 60MHz
• Typical fmax: 85MHz
• Typical Power Dissipation: 525mW FREQCONT RNG Cext Cext (2)

1 FREQUENCY CONTROL

1 RANGE

1 Cext

(3) Y EN (4) (5) (6) (7) 1Y FREQCONT RNG Cext Cext (1)

2 FREQUENCY CONTROL

2 RANGE

2 Cext

(14) Y EN (12) (13) (11) (10) 2Y ELECTRICAL CHARACTERISTICS AND RECOMMENDED OP PARAMETER MAX or MIN S UNIT ICC MAX 150 mA IOH MAX -1 mA IOL MAX 20 mA TIMING REQUREMENTS AND SWITCHING CHARACTERIST PARAMETER MAX or MIN S fo MIN 60 UNIT: NS

Logic Diagram (SN74) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

• Y = A 2A 2Y 2OE 1A 1Y 1OE 4A 4Y 4OE 3A 3Y 3OE ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS F SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 BCT SN64 BCT UNIT ICC MAX 54 20 40 0.08 0.16 0.08 0.16 49 49 mA IOH MAX -5.2 -2.6 -15 -6 -6 -6 -6 -15 -15 mA IOL MAX 16 24 64 6666 6 4 6 4 m A PARAMETER MAX or MIN LVT LVTH 3V AHC AHCT LV LV LVC ALVC 3V UNIT IOH MAX -32 -32 -8 -8 -8 -16 -24 -24 mA IOL MAX 64 64 8 8 8 16 24 24 mA ABT -32 LV-AT 0.02 -16 LV-AT 10.5 10.5 9.5 SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS F SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 BCT SN64 BCT tPLH MAX 13 15 6.5 3 03 03 33 85 . 76 tPHL MAX 18 18 8 30 3 03 33 87 . 78 tPZH MAX 17 20 8.5 30 38 35 38 10.3 11.1 tPZL MAX 25 2593 03 83 53 8 11.7 12.8 tPHZ MAX 8 2 063 0 3 8 3 34 2 8.9 9.4 tPLZ MAX 12 20 6 30 38 3 34 2 8.6 9.9 PARAMETER INPUT OUTPUT MAX or MIN LVT LVTH 3V AHC AHCT LV LV LVC ALVC tPZH MAX 4.7 4 8 8 13 85 . 4 3.5 tPZL MAX 4.7 4 8 8 13 85 . 4 3.5 tPHZ MAX 5.1 4.5 10 1 01 51 0 4 . 6 4 tPLZ MAX 4.5 4.5 10 1 01 51 0 4 9.5 9. 6 4 2.3 2.3 2.3 2.3 2.8 2.8 3.4 3.4 UNIT: NS AY GY AY GY AUC 0.01 AUC 1.8V 2.3V 0.01 ABT 4.9 4.9 5.9 6.8 6.2 6.2 AUC 2.3V 2.1 2.1 AUC 1.8V 2.6 2.6 FUNCTION TABLE (SN74) (each buffer) INPUTS OUTPUT OE A Y LH H LL L HX Z

Logic Diagram (SN74) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

• Y = A 11OE 21A 1Y 3 42OE 52A 2Y 6 103OE 93A 3Y 8 134OE 124A 4Y 11 ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS F SN74 HC CD74 HC CD74 HCT SN74 BCT SN64 BCT ABT UNIT ICC MAX 62 22 48 0.08 0.16 0.16 51 51 30 mA IOH MAX -5.2 -2.6 -15 -6 -6 -6 -15 -15 -32 mA IOL MAX 16 24 64 6 6 6 64 64 64 mA PARAMETER MAX or MIN LVTH 3V AHC AHCT LV LV LVC ALVC 3V UNIT IOH MAX -32 -8 - 8- 8 -16 -24 -24 mA IOL MAX 64 8 8 8 16 24 24 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS F SN74 HC CD74 HC CD74 HCT SN74 BCT SN64 BCT ABT tPLH MAX 13 15 7 30 30 3 66 . 3 6.3 6.3 tPHL MAX 18 18 8.5 30 3 03 67 . 4 7.4 5.7 tPZH MAX 18 25 8.5 30 3 83 87 . 9 7.9 6.5 tPZL MAX 25 35 8.5 30 38 38 10.5 10.5 6.5 tPHZ MAX 16 25 7.5 3 03 84 21 01 06 . 8 tPLZ MAX 18 25 83 03 84 2 12.3 12.3 6.7 PARAMETER INPUT OUTPUT MAX or MIN LVTH 3V AHC AHCT LV LV LVC ALVC tPZH MAX 5.4 8 8 13 85 . 7 3.3 tPZL MAX 5.2 8 8 13 85 . 7 3.3 tPHZ MAX 3.8 10 10 15 10 6 3.7 tPLZ MAX 5.5 10 10 15 10 6 3.7 UNIT: ns A G Y Y AY GY 2.2 2.2 2.2 2.2 2.7 2.7 3.3 3.3 AUC 0.01 AUC 1.8V 2.3V 0.01 AUC 2.3V 2.1 2.1 AUC 1.8V 2.6 2.6 FUNCTION TABLE (SN74) (each buffer) INPUTS OUTPUT OE A Y HH H HL L LX Z

Logic Diagram (SN74) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 128 50-Ω LINE DRIVERS

• Y = A + B 132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT TRIGGER INPUTS
• Y = A•B Y B A A B Y ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL UNIT ICC MAX 57 mA IOH MAX -42.4 mA IOL MAX 48 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL tPLH A, B Y MAX 9 tPHL A, B Y MAX 12 UNIT: ns ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS S SN74 HC CD74 HC CD74 HCT AHC AHCT LV LV 5V UNIT IOL MAX 1682 0 444886 1 2 m A SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS S SN74 HC CD74 HC CD74 HCT AHC AHCT tPLH A, BY MAX 22 22 10.5 31 38 50 11 10 tPHL A, B Y MAX 22 22 13 31 38 50 11 8 PARAMETER INPUT OUTPUT MAX or MIN LV LV tPLH A, BY MAX 17.5 11 tPHL A, BY MAX 17.5 11 UNIT: ns

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 133 13-INPUT POSITIVE-NAND GATES 136 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES WITH OPEN COLLECTOR OUTPUTS

• Y = A ⊕ B = AB + AB ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS ALS AS UNIT ICC MAX 50 10 5.9 31 mA VOH MAX 5.5 5.5 5.5 5.5 V IOL MAX 16 8 8 20 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS ALS AS tPLH A or BY (Other Output = L) MAX 18 30 50 12.5 tPHL A or B Y (Other Output = L) MAX 50 30 15 7.1 tPLH A or BY (Other Output = L) MAX 22 30 50 11.4 tPHL A or BY (Other Output = L) MAX 55 30 15 10.7 UNIT: ns ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN S ALS SN74 HC UNIT ICC MAX 10 0.34 0.02 mA IOH MAX -1 -0.4 -4 mA IOL MAX 20 8 4 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN S ALS SN74 HC tPLH A to M Y MAX 6 11 38 tPHL A to M Y MAX 7 25 38 UNIT: ns FUNCTION TABLE INPUTS L L BA L H OUTPUT Y H HH H L H L L FUNCTION TABLE INPUTS A–H OUTPUT Y All inputs H L One or more inputs L H Y A B C D E K L M F G H I J

Logic Diagram (SN74ALS) LE C B A Output Enables Latch Enable Select Inputs Data Outputs : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES

• Incorporates Two Output Enables To Simplify Cascading

289PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. INPUTS FUNCTION TABLE (SN74) G1 Y0 OUTPUTS H L B LH H L X X X H H L ENABLE SELECT H H H H H H H L L L L L L L L X H L H H L L X C X X L L H H X X X H L H L X L L A H L H L H H H H H H H H H H H L H H H H H H H H L H H H H H H H H L H H H H H H H H L H H H H H H H H L H H H H H H H H L H H H H H H H H L H H H H H H H HHHHHHH X X H L L L L L L L L LE Depends upon the address previously applied while LE was at a logic low. ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LS ALS AS SN74 HC CD74 HC SN74 HCT CD74 HCT LVC 3V UNIT IOL MAX 88 2 0 4444 2 4 m A SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN LS ALS AS SN74 HC CD74 HC SN74 HCT CD74 HCT LVC tPLH MAX 24 20 12.5 48 54 48 57 - tPHL MAX 38 20 12.5 48 54 48 57 - tPLH MAX 21 12 8 3 64 43 65 6 - tPHL MAX 27 15 8.5 36 4 43 65 6 - tPLH MAX 21 17 10 36 44 36 53 - tPHL MAX 27 15 9 3 64 43 65 3 - tPLH MAX 27 22 13.5 48 57 52 66 - tPHL MAX 38 20 14 48 57 52 66 - UNIT:ns LVC:Preview LE (CD74: LE) SELECT Y (CD74: Y) Y (CD74: Y) Y (CD74: Y) Y (CD74: Y)

Logic Diagram (SN74, CD74AC/ACT) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXRS

• 3 Enable Inputs to Simplify Cascading and /or Data Reception
• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) G2B G2A C B A Data Outputs Select Inputs Enable Inputs

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 291 FUNCTION TABLE (SN74) ENABLE INPUTS SELECT INPUTS OUTPUTS G1 G2A G2B CBA Y 0 Y 1 Y 2 Y 3Y 4Y 5Y 6Y 7 XHXXXXHH HHHHHH XX LX HL HL HL HL HL HL HL H X L L L L L L L HL L X X H H L L H H L L X X L L H H X X H L H L L L H L H L H H H L H H H H H H H H H L H H H H H H H H L H H H H H H H H L H H H H H H H H L H H H H H H H H L H H H H H H H H L H H H H H H H H L H H H H H H H HHHHHHH ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LS S ALS AS F SN74 HC CD74 HC SN74 HCT CD74 HCT UNIT ICC MAX 10 74 10 20 20 0.08 0.16 0.08 0.16 mA IOL MAX 8 2 082 0 2 04 4 4 4 m A PARAMETER MAX or MIN AC CD74 AC ACT CD74 ACT AHC AHCT LV LV LVC 3V UNIT IOH MAX -24 -24 -24 -24 -8 -8 -6 -12 -24 mA IOL MAX 24 24 24 24 8 8 6 12 24 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN LS S ALS AS F SN74 HC CD74 HC SN74 HCT CD74 HCT tPLH MAX 27 12 22 10 8.5 45 45 45 53 tPHL MAX 39 12 18 9.5 9 45 45 45 53 tPLH MAX 26 11 17 7.5 8 39 53 42 53 tPHL MAX 38 11 17 8.5 7.5 39 53 42 53 tPLH MAX 26 11 17 10 9 39 53 42 53 tPHL MAX 38 11 17 10 8.5 39 53 42 53 PARAMETER INPUT OUTPUT MAX or MIN AC CD74 AC ACT CD74 ACT AHC AHCT LV LV LVC UNIT: ns Y (CD74:Y ) Y (CD74:Y ) A, B, C G1 Y (C D74:Y ) A, B, C Y (CD74:Y ) G2 Y (C D74:Y ) G1 Y (C D74:Y ) LV-AT 0.01 LV-AT

Logic Diagram (SN74, CD74AC/ACT) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 139 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

• Incorporate Two Enable Inputs to Simplify Cascading and /or Data Reception
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 4 (12) 5 (11) 6 (10) 7 (9) 2 (14) 3 (13) 1 (15) E Logic Diagram (CD74HC/HCT)

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 293 INPUTS FUNCTION TABLE (SN74) OUTPUTS H LL ENABLE SELECT G L L H X H A L H H H H L H H H L H H HH L L L H H H H H H B L X H L ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LS S ALS SN74 HC CD74 HC SN74 HCT CD74 HCT CD74 AC ACT IOL MAX 82 0 84444 2 4 2 4 m A PARAMETER MAX or MIN CD74 ACT AHC AHCT LV LV LVC 3V UNIT IOH MAX -24 -8 - 8- 6 -12 -24 mA IOL MAX 24 8 8 6 12 24 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN LS S ALS SN74 HC CD74 HC SN74 HCT CD74 HCT CD74 AC ACT tPLH SELECT Y (CD74: Y) MAX 29 12 14 44 44 43 51 10.5 8.5 tPHL SELECT Y (CD74: Y) MAX 38 12 14 44 44 43 51 10.5 8.5 tPLH GY ( C D 7 4: Y) MAX 24 8 14 4 44 14 35 1 1 0 . 5 7 . 9 tPHL GY ( C D 7 4: Y) MAX 32 10 15 44 41 43 51 10.5 7.5 PARAMETER INPUT OUTPUT MAX or MIN CD74 ACT AHC AHCT LV LV LVC tPHL GY ( C D 7 4: Y) (CD74: E) (CD74: E) (CD74: E) UNIT: ns

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS294 Logic Diagram 1B 1Y 2B 2Y 140 DUAL 4-INPUT POSITIVE-NAND 50-Ω LINE DRIVERS

• Y = ABCD ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN S UNIT ICC MAX 44 mA IOH MAX -40 mA IOL MAX 60 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN S tPLH MAX 6.5 tPHL MAX 6.5 UNIT: ns A, B, C, D Y

295PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram 145 BCD-TO-DECIMAL DECODERS/DRIVERS

• Sink-Current Capability: 80mA
• Low Power Dissipation (SN74LS): 35mW (typ) INPUT D (12) OUTPUT 0 (1) OUTPUT 1 (2) OUTPUT 2 (3) OUTPUT 3 (4) OUTPUT 4 (5) OUTPUT 5 (6) OUTPUT 6 (7) OUTPUT 7 (9) OUTPUT 8 (10) OUTPUT 9 (11) INPUT B (14) INPUT C (13) INPUT A (15) ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERAT PARAMETER MAX or MIN TTL LS UNIT ICC MAX 70 13 mA Vo (O FF) MAX 15 15 mA SWITCHING CHARACTERISTICS PARAMETER MAX or MIN TTL LS tPLH MAX 50 50 tPHL MAX 50 50 UNIT: ns No. INPUTS D FUNCTION TABLE CBA 0123456789 OUTPUTS L H L L L L L L L L L L L L L L H H H H L L L H H L L H H L H L H L L H H H L H H H H H H H L L H H H H H H L L H H H L L H H L H H H H H H H H H H H H L H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H L H H H H H H H L H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H L H H H H H INVALID

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS296 147 10-LINE TO 4-LINE BCD PRIORITY ENCODER Logic Diagram (12) (11) (13) (1) (2) (3) (4) (5) (10) (7) (6) (14) (9)

297PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. INPUTS Y0 Y1 Y2 Y3I1 I2 I3 I4 I5 I6 I7 I8 I9 OUTPUTS H L L LL L L L L L H H H H L H H H H L H HL L H H H L H L H H H LH H H LH H H H LH L H H H H L H H H H H H L H H H H H L H H H H H H H L H H H H H H HH H H HH H H H H H H X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X H HHL H FUNCTION TABLE ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS SN74 HC CD74 HC CD74 HCT UNIT ICC MAX 70 20 0.08 0.16 0.16 mA IOH MAX -0.8 -0.4 -4 -4 -4 mA IOL MAX 16 8 4 44 m A SWITCHING CHARACTERISTICS PARAMETER MAX or MIN TTL LS SN74 HC CD74 HC CD74 HCT tPLH MAX 19 33 48 48 53 tPHL MAX 19 23 48 48 53 UNIT:ns

Logic Diagram (SN74) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 148 8-LINE TO 3-LINE PRIORITY ENCODERS GS14 EO15 122 133 5EI 100

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 299 INPUTS FUNCTION TABLE (SN74) A1 A0 GS1234567EI 0 OUTPUTS LL L L L L H H H L H H L H HL L H H H L H L H H H LH H H L H H H H LH L H H H H L H H H H H H L H H H L H H H H H H X X X X X X X X X X X X X X X X X X X X X X X X X X X X HHL H EO L H H H H H X XXXXXXXL H H H H H H H L L L L L L L LH HH H L L L L H H L L L L H H H H ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS SN74 HC UNIT ICC MAX 60 20 0.08 mA IOL MAX 16 8 4 mA IOH MAX -0.8 -0.4 -4 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT WAVEFORM MAX or MIN TTL LS SN74 HC tPLH 15 18 45 tPHL 14 25 45 tPLH 19 36 45 tPHL 19 29 45 tPLH 10 18 38 tPHL 25 40 38 tPLH 30 55 48 tPHL 25 21 48 tPLH 15 25 49 tPHL 15 25 49 tPLH 12 17 36 tPHL 15 36 36 tPLH 15 21 41 tPHL 30 35 41 UNIT: ns EO In-phase output MAX 1 to 7 A0, A1 or A2 Out-of-phase output MAX In-phase outputA0, A1 or A21 to 7 MAX 0 to 7 GS In-phase output MAX 0 to 7 E0 Out-of-phase output MAX MAX EI GS In-phase output MAX EI A0, A1 or A2 I n-phase output EI

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS300 150 16-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER Logic Diagram E2 (6) E3 (5) E4 (4) E5 (3) E6 (2) DATA INPUTS (1) E8 (23) E9 (22) E10 (21) E11 (20) E12 (19) E13 (18) E14 (17) OUTPUTS(10) E0 (8) STROBE (ENABLE) (9) E15 (16) A (15) BDATA SELECT (BINARY) (14) C (13) D (11) E1 (7) D D C C B B A A

301PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. INPUTS OUTPUT L SELECT STROBE G L L HX H A L H W LL H H B L X H L H C L X H L H D L X H L E10 E11 E12 E13 E14 E15 L H L L L L H H L H L L L H L L H H L H H H H H L H H H H H L H L L L L H L H L H L H L H L H L L L L L L L L L L L L L FUNCTION TABLE NOTES: H = High Level, L = Low Level, X = irrelevant E0, E1 ... E15 = the complement of the level of the respective E input D0, D1 ... D7 = the level of the D respective input ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL UNIT ICC MAX 48 mA IOH MAX -0.8 mA IOL MAX 16 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL tPLH 35 tPHL 33 tPLH 24 tPHL 30 tPLH 14 tPHL 20 UNIT:ns E0 thru E15 or E0 thru D7 W MAX Strobe G A, B, C or D W MAX W MAX

Logic Diagram (SN74ALS, AS, F, CD74AC/ACT) G A B C Y W Data Inputs Data Select (binary) Y TG TG TG TG TG TG TG TG G A B C : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 151 8-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS Logic Diagram (SN74HC)

303PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. INPUTS FUNCTION TABLE (SN74) OUTPUTS L SELECT G L L HX H A L L Y LL H H B L X H L H C L X H L L H L L H H L H H L H L L L L L H W ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC CD74 HCT CD74 AC CD74 ACT UNIT IOL MAX 16 8 20 2 44 82 4 6 4 4 2 42 4 m A SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC CD74 HCT tPLH 38 43 18 18 14.5 12 63 56 62 tPHL 38 30 18 24 15 9 63 56 62 tPLH 26 23 15 24 12 9.5 63 62 65 tPHL 30 32 13.5 23 12 7.5 63 62 65 tPLH 20 32 16.5 10 1 0.5 7.5 49 51 57 tPHL 27 26 18 15 11 7.5 49 51 57 tPLH 14 21 13 15 6.5 7 49 56 54 tPHL 14 20 12 15 4.5 5 49 56 54 tPLH 33 42 12 18 14 10.5 32 42 44 tPHL 33 32 12 19 11 7.5 32 42 44 tPLH 21 24 7 1 96 73 2 4 4 5 4 tPHL 23 30 7 23 1 063 2 4 45 4 PARAMETER INPUT OUTPUT MAX or MIN CD74 AC CD74 ACT tPLH 18.2 20.2 tPHL 18.2 20.2 tPLH 19.6 21.6 tPHL 19.6 21.6 tPLH 13.5 15.5 tPHL 13.5 15.5 tPLH 14.9 16.9 tPHL 14.9 16.9 tPLH 12.2 12.1 tPHL 12.2 12.1 tPLH 13.5 13.5 tPHL 13.5 13.5 UNIT: ns Y MAX W (CD74HC: Y) MAX Y MAX W (CD74HC: Y) MAX Y MAX W (CD74HC: Y) MAX G Y MAX G W (CD74HC: Y) MAX D0 to D7 Y MAX D0 to D7 W (CD74HC: Y) MAX A, B or C Y MAX A, B or C W (CD74HC: Y) MAX (CD74HC/HCT: Sn) (CD74HC/HCT: Sn) (CD74HC/HCT: In) (CD74HC/HCT: In) (CD74HC/HCT: E) (CD74HC/HCT: E) G G D0 to D7 D0 to D7 A, B or C A, B or C (CD74HC/HCT: Sn) (CD74HC/HCT: Sn) (CD74HC/HCT: In) (CD74HC/HCT: In) (CD74HC/HCT: E) (CD74HC/HCT: E)

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS304 Logic Diagram (SN74ALS, AS, F, LS) 153 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS Data 2 Select Data 1 2C3 2C2 2C1 2C0 A B 1C3 1C2 1C1 1C0 2Y9 TG TG TG TG TG TG TG TG TG TG TG TG A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 Logic Diagram (SN74HC, HCT, CD74AC, ACT)

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 305 DATA INPUTS FUNCTION TABLE (SN74) OUTPUTS L SELECT INPUTS G L L HX A H Y LL H H B L X H L X H X L H L H H L L L L STROBE H L X L X H L C2 C3 L L H H X X X X X X L X L X X X X X X X X X X X X X X X X X H L L H L H L H L ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC CD74 HCT CD74 AC CD74 ACT UNIT IOL MAX 16 8 20 2 44 82 0 6 4 4 2 42 4 m A SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC CD74 HCT tPLH MAX 18 15 9 10 7 83 5 4 45 1 tPHL MAX 23 26 9 15 8 7.5 35 44 51 tPLH MAX 34 29 18 21 12.5 12 38 48 51 tPHL MAX 34 38 18 21 11 10.5 38 48 51 tPLH MAX 30 24 15 18 11.5 10.5 24 36 41 tPHL MAX 23 32 13.5 18 9 8 24 36 41 PARAMETER INPUT OUTPUT MAX or MIN CD74 AC CD74 ACT tPLH MAX 13.3 18 tPHL MAX 13.3 18 tPLH MAX 20 22 tPHL MAX 20 22 tPLH MAX 11.8 12.6 tPHL MAX 11.8 12.6 UNIT: ns DATA Y SELECT Y STROBE Y DATA SELECT STROBE Y Y Y

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS306 154 4-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS Logic Diagram (1) A0 A1 A2 A3 E (2) (3) (4) (18) (19) (23) (5) (6) (8) (9) (10) Y10 (11) Y11 (13) Y12 (14) Y13 (15) Y14 (16) Y15 (17) OUTPUTS (7) (22)A1 E A3(20)A3 A2(21)A2 INPUTS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 307 ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL ALS SN74 HC CD74 HC CD74 HCT UNIT ICC MAX 56 23 0.08 0.16 0.16 mA IOH MAX -0.8 24 -4 -4 -4 mA IOL MAX 16 -0.4 4 4 4 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL ALS SN74 HC CD74 HC CD74 HCT tPLH 36 12 45 53 53 tPHL 33 12 45 53 53 tPLH 30 12 45 53 51 tPHL 27 12 45 53 51 UNIT: ns MAX MAX Adress Enable 0 to 15 (CD74: Y0 to Y15) 0 to 15 (CD74: Y0 to Y15) INPUTS FUNCTION TABLE A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 OUTPUTS L L L L L L L L L H H H H L H H L H H L L H H H L H H HHHHHHHH H H H H H H H H L L H H E 1 E2 LL H L H H L L L L H H H H X X X X X X X X X X X X L L L LL LL LL LL LL LL LL LL LL LL LL LL LL L H L L L L L L L L L H L L H H L H L H H H H L H L H L H L H L H L H L H L H HHHHHHH H H H H H H H H H HHHHHH H H H H H H H H H HHHHH H H H H H H H H H HHHH H H H H H H H H H HHH H H H H H H H H H HH H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H Y H L H H H H H H H H H H H H H H H H H Y10 H H H H L H H H H H H H H H H H H H H Y11 H H H H H H L H H H H H H H H H H H H Y12 H H H H H H H H L H H H H H H H H H H Y13 H H H H H H H H H H L H H H H H H H H Y14 H H H H H H H H H H H H L H H H H H H Y15 H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H HH

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS308 155 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

• Individual Strobes Simplify Cascading for Decoding or Demultiplexing Lager Words
• Outputs: Totem Pole Logic Diagram (7) OUTPUT 1Y0 (2)STROBE (3)SELECT B DATA (6) OUTPUT 1Y1 (5) OUTPUT 1Y2 (4) OUTPUT 1Y3 (9) OUTPUT 2Y0 (10)OUTPUT 2Y1 (11)OUTPUT 2Y2 (12)OUTPUT 2Y3 (15) (14) DATA (13)SELECT A STROBE

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 309 L L L HX H L H L X H L H L H L L H L H L HH L H L XXX H H H H H H H H HH HH H H H H HH X L L L HX L H L X H L H L H L L H L H L H H L H L XXX H H H H H H HH HH H H H H HH X L L L L L L HX H L H L X H L H L H L L H L H L H H LH L H H H H H H H H HH HH H H H H HH X H L H L L LH H H H H H H HH HH H HH L L L H L H LH L H L L L L L HHHH HH HH HHHH HHHH HHHH HHHH HHH H DATA OUTPUTS SELECT 1GA 1CB 1Y11Y0 STROBE 1Y2 1Y3 INPUTS FUNCTION TABLES DATA OUTPUTS SELECT 2GA 2CB 2Y12Y0 STROBE 2Y2 2Y3 INPUTS OUTPUTS SELECT G‡AC† B 2Y1 2Y0 STROBE or DATA 2Y2 2Y3 INPUTS 1Y11Y0 1Y2 1Y3 2-LINE TO 4-LINE DECODER OR 1-LINE TO 4-LINE DEMULTIPLEXER 3-LINE TO 8-LINE DECODER OR 1-LINE TO 8-LINE DEMULTIPLEXER † C = inputs 1C and 2C connected together ‡ G = inputs 1G and 2G connected together ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS ALS UNIT ICC MAX 40 10 13 mA IOH MAX -0.8 -0.4 -0.4 mA IOL MAX 16 8 8 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS ALS tPLH A or B 32 26 14 tPHL A or B 32 30 12 tPLH 1C 24 27 12 tPHL 1C 30 27 14 UNIT: ns Y Y MAX MAX

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS310 156 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS WITH OPEN-COLLECTOR OUTPUTS

• Individual Strobes Simplify Cascading for Decoding or Demultiplexing Lager Words
• Outputs: Open-Collector Logic Diagram 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 Strobe 2G Strobe 1G Data 1C Data 2C A B Select

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 311 DATA OUTPUTS L SELECT L L HX A H L H B L X H L 1Y1 H 1Y0 L STROBE H L L H L 1Y2 1Y3 H L HH L INPUTS H L XXX H H H H H H H H H H HH H H H H HH X FUNCTION TABLES DATA OUTPUTS L SELECT L L HX A 2C L H B L X H L 2Y1 H 2Y0 L STROBE H L L H L 2Y2 2Y3 H L H H L INPUTS H L XXX H H H H H H H H H H H H H H HH X L L L OUTPUTS L SELECT L L HX A H L H B L X H L 2Y1 H 2Y0 L STROBE or DATA H L L H L 2Y2 2Y3 H L H H L INPUTS H L H H H H H H H H HH HH H H H H HH X 1Y1 H 1Y0 L H L L L 1Y2 1Y3 H H H H H H H HH HH H HH L L L H L H LH L H L L L L L HHHH HHHH HHHH HHH H HHHH HHHH HHHH 2-LINE TO 4-LINE DECODER OR 1-LINE TO 4-LINE DEMULTIPLEXER 3-LINE TO 8-LINE DECODER OR 1-LINE TO 8-LINE DEMULTIPLEXER † C = inputs 1C and 2C connected together ‡ G = inputs 1G and 2G connected together ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS ALS UNIT ICC MAX 40 10 9 mA IOL MAX 16 8 8 mA VOH MAX 5.5 5.5 5.5 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS ALS tPLH 23 40 38 tPHL 30 51 22 tPLH A or B 34 46 55 tPHL A or B 34 51 25 tPLH 1C 27 48 50 tPHL 1C 33 48 23 UNIT: ns Y MAX Y MAX2C 1G or 2G Y MAX

Logic Diagram (SN74LV/SN74HC) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 157 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS G A/B

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 313 ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC SN74 HCT UNIT ICC MAX 48 16 78 11 28 23 0.08 0.16 0.08 mA IOL MAX 16 8 2 082 0 2 06 4 6 m A PARAMETER MAX or MIN CD74 HCT CD74 AC CD74 ACT AHC AHCT LV LV LVC 3V UNIT IOH MAX -4 -24 -24 -8 -8 -6 -12 - 24 mA IOL MAX 4 24 24 886 1 2 24 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC SN74 HCT tPLH 14 14 7.5 14 6 6.5 32 38 35 tPHL 14 14 6.5 12 5.5 7 32 38 35 tPLH 20 20 12.5 20 10.5 11 29 41 33 tPHL 21 21 12 13 7.5 7 29 41 33 tPLH 23 23 15 24 11 11 31 44 40 tPHL 27 27 15 17 10 8 31 44 40 PARAMETER INPUT OUTPUT MAX or MIN CD74 HCT CD74 AC CD74 ACT AHC AHCT LV LV LVC tPLH 41 13.5 13.5 12 12 19.5 12 6.5 tPHL 41 13.5 13.5 12 12 19.5 12 6.5 UNIT: ns SELECT Y MAXSELECT Y STROBE Y MAX DATA Y MAX MAX DATA Y MAX STROBE Y MAX OUTPUT L SELECT L L H X B L H A X L H L STROBE H L H INPUTS H H X FUNCTION TABLE (SN74) L L X X X X L L

Logic Diagram (SN74HC, ALS, LS) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 158 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS

• Buffered Inputs and Outputs G A/B A G Logic Diagram (SN74AS)

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 315 OUTPUT L SELECT L L H X B L H A X L H L STROBE H L H INPUTS H H X FUNCTION TABLE (SN74) L L X X X X L H ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN LS S ALS AS F SN74 HC CD74 HC CD74 HCT UNIT ICC MAX 11 81 10 22.5 15 0.08 0.16 0.16 mA IOL MAX 8 2 082 0 2 06 4 4 m A PARAMETER MAX or MIN CD74 AC CD74 ACT AHC AHCT UNIT ICC MAX 0.16 0.16 0.04 0.02 mA IOH MAX -24 -24 -8 -8 mA IOL MAX 24 24 8 8 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN LS S ALS AS F SN74 HC CD74 HC CD74 HCT tPLH 1261 55 73 2 4 2 4 2 tPHL 15 6 8 4.5 4.5 32 42 42 tPLH 17 11 .5 18 6.5 7 29 48 48 tPHL 24 12 18 10 6.5 29 48 48 tPLH 20 12 18 9.5 9.5 31 45 45 tPHL 24 12 18 10.5 7 31 45 45 PARAMETER INPUT OUTPUT MAX or MIN CD74 AC CD74 ACT AHC AHCT tPLH 89 . 2 9.5 9.8 tPHL 89 . 2 9.5 9.8 tPLH 11.9 12.4 12 12 tPHL 11.9 12.4 12 12 tPLH 12.9 13.5 11.5 12 tPHL 12.9 13.5 11.5 12 UNIT: ns MAX MAX STROBE Y MAX SELECT Y MAX Y MAX SELECT STROBE DATA Y DATA Y Y MAX

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS316 159 4-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH OPEN-COLLECTOR OUTPUTS Logic Diagram 0(1) A B C D D D G A B C 1(2) 2(3) 3(4) (18) (19) (23) 4(5) 5(6) 7(8) 8(9) 9(10) 10(11) 11(13) 12(14) 13(15) 14(16) 15(17) OUTPUTS (7) A A B B A (22)B A A B B C C D G D D(20)D C C(21)C INPUTS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 317 INPUTS D FUNCTION TABLE CBA 0 23456789 OUTPUTS L L L L L L L L L H H H H L H H L H H L L H H H L H H HHHHHHHH H H H H H H H L L H H LL H L H H L L L L H H H H X X X X X X X X X X X X L L L LL LL LL LL LL LL LL LL LL LL LL LL LL L H L L L L L L L L L H L L H H L H L H H H H L H L H L H L H L H L H L H L H HHHHHHH H H H H H H H H H HHHHHH H H H H H H H H H HHHHH H H H H H H H H H HHHH H H H H H H H H H HHH H H H H H H H H H HH H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H HH L H L H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H HHHHHHH ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL UNIT ICC MAX 56 mA IOL MAX 16 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL tPLH 36 tPHL 36 tPLH 25 tPHL 36 UNIT: ns MAX MAX INPUT STROBE ANY ANY

Logic Diagram (SN74) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 161 4-BIT SYNCHRONOUS BINARY COUNTERS

• Asynchronous Clear Function
• Carry Output for n-Bit Cascading CLR LOAD ENT ENP CLK A RCO QA † For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown on the logic diagram of the D/T flip-flops. 1, 2T/1C3 B QB , 2T/1C3 C QC , 2T/1C3 D QD 1, 2T/1C3 LD† CK† CK R LD FUNCTION TABLE (SN74) INPUTS FUNCTION OUTPUTS CLR LOAD ENP ENT CLK QA QB QC QD LX XX XL LL LR eset to “0” HL X XA BC D Preset Data HH XL No Change No Count HH LX No Change No Count HH HH Count up Count HX XX No Change No Count

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 319 ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS ALS AS F SN74 HC CD74 HC CD74 HCT CD74 AC CD74 ACT LV LV 5V UNIT IOL MAX 16 8 8 20 20 -4 4 4 24 24 -6 12 mA TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN TTL LS ALS AS F SN74 HC CD74 HC CD74 HCT MIN 25 2 54 07 59 02 52 02 0 tw CLOCK 25 25 - - 7 20 24 24 CLEAR 20 20 15 8 5 20 30 30 tsu INPUT 20 20 15 8 5 38 18 15 ENABLE ENABLE INPUT ENABLE ENABLE 20 20 15 8 11.5 43 15 20 LOAD 25 20 15 8 11.5 34 18 18 CLEAR INACTIVE 20 25 10 8 - 31 - - MIN 03002035 35 35 20 16.5 15 54 56 63 35 35 20 12.5 15 54 56 63 25 24 15 7 9.5 51 56 59 29 27 20 13 11 51 56 59 16 14 13 9 8.5 49 36 48 16 14 13 8.5 8.5 49 36 48 ANY Q MAX 38 28 24 13 13 53 63 75 MAX -- 23 12.5 11.5 55 63 75 INPUT OUTPUT MAX or MIN CD74 AC CD74 ACT LV LV MIN 90 8 05 08 5 tw CLOCK 5.5 6.2 5 5 CLEAR 5 6 5 5 tsu 55 6.5 4.5 --9 6 LOAD 6 6 9.5 6 CLEAR INACTIVE - - 2.5 1.5 MIN 0011 16.7 16.7 23.5 14 16.7 16.7 23.5 14 16.5 16.5 18.5 11.5 16.5 16.5 18.5 11.5 10.3 10.8 18 11.5 10.3 10.8 18 11.5 ANY Q MAX 16.5 16.5 19.5 12.5 MAX 16.5 16.5 19 12 UNIT fmax : MHz, other : ns t PHL MAXtPHL tPLH tPLH CLOCK ANY Q MAXtPHL MIN MIN tPLH CLOCKtPHL PARAMETER th fmax tPHL PARAMETER fmax tPLH tPHL tPHL tPLH ANY Q th tPLH CLOCK RIPPLE CARRY (CD74HC/HCT: TC) RIPPLE CARRY (CD74HC/HCT: TC) RIPPLE CARRY (CD74HC/HCT: TC) tPHL CLEAR CLEAR MIN MIN MAX MAX MAX CLOCK MAX RIPPLE CARRY (CD74HC/HCT: TC) RIPPLE CARRY (CD74HC/HCT: TC) RIPPLE CARRY (CD74HC/HCT: TC)

Logic Diagram (SN74LV) CLR LOAD ENT ENP CLK A RCO QA † For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown on the logic diagram of the D/T flip-flops. 1, 2T/1C3 B QB , 2T/1C3 C QC , 2T/1C3 D QD 1, 2T/1C3 LD† CK† CK R LD : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 163 4-BIT SYNCHRONOUS BINARY COUNTERS

• Synchronous Clear Function
• Carry Output for n-Bit Cascading

321PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC CD74 HCT CD74 AC CD74 ACT LV LV 5V UNIT IOL MAX 16 8 2 082 0 2 0 - 44 42 4 2 4 - 6 1 2 m A TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74 HC MIN 25 2 54 04 07 59 02 5 tw CLOCK 25 25 10 - - 7 20 CLEAR 20 20 10 12.5 6.7 - - tsu INPUT 20 20 4 15 8 5 38 ENABLE INPUT ENABLE ENABLE ENABLE 20 20 12 15 8 11.5 43 LOAD 25 20 14 15 8 11.5 34 CLEAR 20 20 14 15 12 - 40 MIN 0330020 35 35 25 20 16.5 15 54 35 35 25 20 12.5 15 54 25 24 15 15 7 9.5 51 29 27 15 20 13 11 51 16 14 15 13 9 8.5 49 16 14 15 13 8.5 8.5 49 INPUT OUTPUT MAX or MIN CD74 HC CD74 HCT CD74 AC CD74 ACT LV LV MIN 20 2 09 08 05 08 5 tw CLOCK 24 24 5.5 6.2 5 5 tsu 18 15 5 5 6.5 4.5 15 20 5 6 9 6 LOAD 18 18 6 7 .5 9.5 6 CLEAR 20 20 6 7.5 4 3.5 MIN 350011 56 63 16.7 16.7 23.5 14 56 63 16.7 16.7 23.5 14 56 59 16.5 16.5 18.5 11.5 56 59 16.5 16.5 18.5 11.5 36 48 10.3 10.8 18 11.5 36 48 10.3 10.8 18 11.5 UNIT fmax : MHz, other : ns MAX MAX MIN MIN MAX MAX MAX ANY Q RIPPLE CARRY CLOCK RIPPLE CARRY ANY QCLOCK RIPPLE CARRY PARAMETER fmax CLOCK t PLH tPHL tPLH tPHL tPLH tPHL tPHL tPLH tPHL tPLH PARAMETER fmax th MIN MIN th tPLH CLOCK RIPPLE CARRY MAXtPHL FUNCTION TABLE (SN74) INPUTS OUTPUTS FUNCTION CLR LOAD ENP ENT CLK QA QB QC QD FUNCTION LX XX XL LL LR eset to “0” HL X XA BC D Preset data HH XL No change No count HH LX No change No count HH HH Count up Count HX XX No change No count

Logic Diagram (SN74) R R QA QB R R QC QD R R QE QF R R QG QH 3456 1 0 1 1 1 2 1 3 CLK A B CLR : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS

• AND-Gated (Enable/Disable) Serial Inputs
• Fully Buffered Clock and Serial Inputs

323PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS ALS SN74 HC CD74 HC CD74 HCT CD74 AC CD74 ACT LV LV 5V UNIT IOL MAX 888444 2 4 2 4 6 1 2 m A TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN TTL LS ALS SN74 HC CD74 HC CD74 HCT CD74 AC CD74 ACT MIN 25 2 55 02 52 01 87 57 0 tw CLR "L" MIN 20 20 1 62 51 82 74 . 5 4 . 5 CLK "H" MIN 20 20 10 20 24 27 6.7 7.1 CLK "L" MIN 20 20 10 20 24 27 6.7 7.1 tsu DATA MIN 15 15 6 2 51 81 82 . 5 2 . 5 CLEAR INACTIVE MIN 20 2 082 5 1 81 8 2.5 2.5 MIN 552544 2 . 5 3 CLEAR Q MAX 42 36 20 51 42 57 13.9 15.8 30 27 16 44 51 54 12.5 14.9 37 32 17 44 51 54 12.5 14.9 INPUT OUTPUT MAX or MIN LV LV MIN 45 75 tw CLR "L" MIN 5 5 CLK "H" MIN 5 5 CLK "L" MIN 5 5 tsu DATA MIN 6 4.5 CLEAR INACTIVE MIN 2.5 2.5 MIN 0 1 CLEAR Q MAX 18.5 12.5 18.5 12.5 18.5 12.5 UNIT fmax : MHz, other : ns MAXQCLOCK PARAMETER t PLH tPHL fmax th tPHL PARAMETER fmax th tPHL tPLH CLOCK Q MAXtPHL INPUTS A FUNCTION TABLE (SN74) B QA OUTPUTS X H L H L H H H CLOCK X X L H L QA0 H L CLEAR XX X X L L QB L QB0 QH L QH0 QAn QGn QAn QGn QAn QGn . . .

Logic Diagram (SN74LV, ALS, LS) S R S R S R S R S R S R S R S R SH/LD CLK INH CLK SER QH QH 11 12 13 14 3 4 5 6 AB CDEFG H S R S R S R S R S R S R S R S R SH/LD CLK INH CLK SER QH QH 11 12 13 14 3 4 5 6 AB CD EFG H : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 165 PARALLEL-LOAD 8-BIT SHIFT REGISTERS

• Complementary Outputs: Serial (QH, QH)
• Direct Overriding Load (Data) Inputs
• Parallel-to-Serial Data Conversion Logic Diagram (SN74HC)

325PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS ALS SN74 HC CD74 HC CD74 HCT LV LV 5V UNIT ICC MAX 63 30 24 0.08 0.16 0.16 - 0.02 mA IOL MAX 16 884446 1 2 m A TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN TTL LS ALS SN74 HC CD74 HC CD74 HCT LV LV MIN 20 2 54 52 52 01 85 08 5 tw MIN 25 1 51 12 02 42 7 7 4 MIN 25 2 51 12 02 42 7 7 4 MIN 15 1 71 22 02 43 0 9 6 tsu CLK INH 30 30 11 25 24 30 5 3.5 DATA 10 10 10 25 24 30 8.5 5 SER 20 20 10 10 24 30 6 4 SH/ LD "H" 45 45 10 20 - - 6 4 MIN 0045 1 1 1 1 0 . 5 1 24 25 13 38 50 60 16.9 13.5 31 25 14 38 50 60 16.9 13.5 31 35 20 38 53 60 22 13.5 40 35 22 38 53 60 22 13.5 17 25 13 38 45 53 20 12.5 36 30 16 38 45 53 20 12.5 27 30 15 38 45 53 20 12.5 27 25 16 38 45 53 20 12.5 UNIT fmax : MHz, other : ns CLOCK SH/ LD PARAMETER tPHL tPLH fmax CLOCK High Low SH/ LD "L" tPHL tPLH QH MAXH (CD74: D 7) tPHL tPLH MAX MAX QH or QH High Low MIN th tPLH H (CD74: D 7) QH MAXtPHL (CD74: CP) (CD74: CP) (CD74: PL) (CD74: PL) (CD74: Q7 or Q7) (CD74: CE) (CD74: DS) QH or QH (CD74: Q7 or Q7) (CD74: Q7) (CD74: Q7) INPUTS CLOCK FUNCTION TABLE (SN74) SERIAL OUTPUT X H L H H H CLOCK INHIBIT X X L H X XX L h QH0 QGn QGn QH a QA0 H L QA b QB0 QB X L L L H X X X QAn QH0QA0 QB0 QAn PARALLELSHIFT/ LOAD A...H a...h INTERNAL OUTPUTS

Logic Diagram (SN74LV, HC) SH/LD CLR CLK CLK INH QH 23451 0 1 1 1 2 1 4 SER ABCDEFGH R R R R R R R R R R R R R R R R SH/LD CLR CLK CLK INH QH 1 23451 0 1 1 1 2 1 4 SER A B C D E F G H : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 166 8-BIT PARALLEL-LOAD SHIFT REGISTERS

• Synchronous Load
• Direct Overriding Clear
• Parallel-to-Serial Conversion Logic Diagram (SN74ALS, LS)

327PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS ALS F SN74 HC CD74 HC CD74 HCT LV LV 5V UNIT ICC MAX 127 32 24 60 0.08 0.16 0.16 - 0.02 mA IOL MAX 16 88 2 0 4446 1 2 m A TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN TTL LS ALS F SN74 HC CD74 HC CD74 HCT LV LV MIN 25 2 54 5 1 1 0 2 5 20 16 50 85 tw CLO (CD74: CP) (CD74: MR) CK 20 20 10 3.5 20 24 30 7 4 CLEAR 20 25 9 4 25 30 53 7 5 tsu Mode Control 30 30 16 4 36 44 45 6 4 DATA 20 20 7 3 20 24 24 6 4.5 MIN 003001001 CLEAR QH MAX 35 30 14 9.5 30 48 60 18.5 12 30 25 13 14 38 48 60 21.5 13.5 26 20 12 93 84 86 02 1.5 13.5 UNIT fmax : MHz other : ns fmax PARAMETER tPLH tPHL tPHL th MAXCLOCK QH MIN MIN INPUTS CLOCK FUNCTION TABLE (SN74) SERIAL OUTPUT X H L H H H CLOCK INHIBIT X X L H X X L A...H a...h h QH0 QGn QGn QH a QA0 H L QA b QB0 QB INTERNAL OUTPUTS XL H X X X QAn QH0QA0 QB0 QAn PARALLELSHIFT/ LOAD H H X X X XL L L L X H L L L CLEAR

A B C D QA QB QC QD RCO : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 169 SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS

• Fully Synchronous Operation for Counting and Programming
• Internal Carry Look-Ahead Circuitry for Fast Counting
• Carry Output for n-Bit Cascading

329PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS MAX or MIN LS S ALS AS F UNIT ICC MAX 45 160 25 63 52 mA RCO MAX -0.4 -1 -0.4 -2 -1 mA RCO MAX 8 2 082 0 2 0 m A QM A X 2 4 2082 0 2 0 m A IOH IOL PARAMETER TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN LS S ALS AS F MIN 20 40 4 07 59 0 40 21 20 16.5 17 25 28 20 13 12.5 25 15 15 13 9.5 25 15 20 7 13 25 12 13 9 7 20 25 16 9 9 35 15 19 12 12.5 25 22 19 13 12 UNIT fmax : MHz, other : ns CLK CLK ENT U/D RCO RCO MAX MAX MAX MAX RCO ANY Qt PLH tPHL tPLH tPHL tPLH tPHL PARAMETER fmax tPLH tPHL

D G QD (9) OUTPUTS (1) G QD G QD G QD G Q D G QD (7) (2) G QD G QD G QD G Q D G QD (6) (3) G QD G QD G QD G (12) GW Q D G QD (10) (15) G QD G QD G QD WORD 0 WORD 1 WORD 2 WORD 3 G Q (13) WB WRITE INPUT (14) WA DATA INPUTS (11) GR (5) RA READ INPUT (4) RB : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 170 4-BY-4-REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS

• Separate Read/Write Addressing Permits Simultaneous Reading and Writing
• Fast Access Times: Typically 20ns
• Expandable to 1024 Words of 4 Bits

331PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS UNIT ICC MAX 150 40 mA VOH MAX 5.5 5.5 V IOL MAX 16 8 mA TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN TTL LS MIN MIN 25 25 tsu D 10 10 W1 5 1 5 th D 15 15 W5 5 15 30 30 30 35 40 40 40 40 45 45 40 30 45 45 35 UNIT fmax : MHz, other : ns MAX Q Q Q Q MAX MAX t PHL MAX READ ENABLE READ SELECT WRITE ENABLE tPHL MIN MIN tPLH tPLH DATA PARAMETER tPLH tPHL fmax tw tPLH tPHL WRITE INPUTS WRITE FUNCTION TABLE OUTPUTS Q = DL H H WA X QO L H WB GW X L L H L H L L L QO QO Q = D Q O QO Q = D Q O Q = D QO QO QO QO QO QO QO QO QOQO READ INPUTS READ FUNCTION TABLE Q2 Q3 OUTPUTS W0B1L H H RA X L H RB GR X L L H L HL L L HHHH W1B1 W2B1 W3B1 W0B2 W1B2 W2B2 W3B2 W0B3 W1B3 W2B3 W3B3 W0B4 W1B4 W2B4 W3B4

Logic Diagram (SN74LS) R R R R M N CLR CLK Output Control Data Enable : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 173 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

• 3-State Outputs Interface Directly
• Fully Independent Clock Virtually

333PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS SN74 HC CD74 HC CD74 HCT UNIT ICC MAX 72 24 0.08 0.16 0.16 mA IOH MAX -5.2 -2.6 -6 -6 -6 mA IOL MAX 16 24 666 m A TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN TTL LS SN74 HC CD74 HC CD74 HCT MIN 25 25 2 52 01 3 MIN 20 25 2 02 43 8 tsu DATA ENABLE 17 35 25 18 18 DATA 10 17 25 18 27 CLR INACTIVE MIN 10 10 23 - - th DATA ENABLE 20000 DAT A1 0 3030 CLEAR Q MAX 27 35 38 53 66 43 25 38 60 60 31 30 38 60 60 30 23 38 45 45 30 27 38 45 45 14 20 38 45 - 20 17 38 45 - UNIT fmax : MHz, other : ns MAX MAX CLOCK Q ENABLE Q DISABLE Q MIN MIN MAXt PLH tPHL tPHL PARAMETER fmax tw tPZH tPZL tPHZ tPLZ (CD74: CP) INPUTS D FUNCTION TABLE (SN74LS) Q OUTPUT X H L H L CLOCK X L H L L H CLEAR L X L X X Q0X LX LX L L DATA H L X L X ENABLE X DATA

Logic Diagram (SN74) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS R To Five Other Channels CLR CLK 174 HEX D-TYPE FLIP-FLOPS WITH CLEAR

• Buffered Clock and Direct Clear Inputs
• Fully Buffered Outputs for Maximum Isolation from External Disturbances ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC UNIT ICC MAX 65 26 144 19 45 55 0.08 0.16 mA IOL MAX 16 8 2 082 0 2 04 4 m A PARAMETER MAX or MIN CD74 HCT CD74 AC CD74 ACT AHC AHCT LV LV 5V UNIT IOH MAX -4 -24 -24 -8 -8 -6 -12 mA IOL MAX 4 24 24 8 8 6 12 mA TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC MIN 25 30 7 55 0 100 80 25 20 tw CLR (MR) LOW MIN 20 2 01 01 0 5 5 2 02 4 CLK (CP) HIGH 20 20 7 10 4 42 0 2 4 CLK (CP) LOW 20 20 7 1 06 62 0 2 4 tsu DATA INPUT MIN 20 20 5 10 4 4.5 25 18 CLR (MR) INACTIVE MIN2 52 5 5665 2 5 - MIN5 5301105 25 - - 18 - - 40 45 35 35 22 23 14 15 40 45 30 30 12 15 8 9 40 50 35 30 17 17 10 11 40 50 INPUT OUTPUT MAX or MIN CD74 HCT CD74 AC CD74 ACT AHC AHCT LV LV MIN 17 9 58 08 06 55 08 0 tw MIN3 8 445555 30 5.2 6.2 5555 30 5.2 6.2 5555 tsu MIN 24 2 24 . 55 6 4.5 MIN - - - 2. 53 . 5 3 2 . 5 MIN 5 3 2.5 0.5 0 0 0.5 66 14.5 15.5 - - 17 11 66 14.5 15.5 11 13 17 11 60 13.5 14 10.5 10 16.5 10.5 60 13.5 14 10.5 10 16.5 10.5 UNIT fmax : MHz, other : ns t PLH ANY Q MAXtPHL tPLH ANY Q MAXtPHL PARAMETER fmax MIN th MAX MAX MIN CLR CLK ANY Q ANY Q tPLH tPHL th PARAMETER fmax tPLH tPHL (MR) (CP) CLR (MR) LOW CLK (CP) HIGH CLK (CP) LOW DATA INPUT CLR (MR) INACTIVE CLR CLK (MR) (CP) INPUTS D FUNCTION TABLE (SN74) Q OUTPUT X H L L H H L CLOCK X L H L CLEAR L X

Logic Diagram (SN74) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. CLR CLK R 1Q To Three Other Channels 4 2 INPUTS D FUNCTION TABLE (SN74) Q OUTPUTS X H L L H H H CLOCK X L H L H L H CLEAR Q Q0L X ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC CD74 HCT AC CD74 AC CD74 ACT UNIT IOL MAX 16 8 2 082 0 2 04 4 4 24 24 24 mA PARAMETER MAX or MIN LV LV 5V UNIT ICC MAX - 0.02 mA IOH MAX -6 -12 mA IOL MAX 6 12 mA TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74 HC CD74 HC MIN 25 3 07 55 0 1 0 0 100 25 20 tw 20 20 10 10 5 5 20 24 20 20 7 1 04 42 0 2 4 20 20 7 1 05 52 0 2 4 tsu 20 20 5 10 3 3 25 24 25 25 5665 2 5 - MIN 55301105 25 30 15 18 9 9 38 53 35 30 22 23 13 13 38 53 30 25 12 15 7.5 7.5 38 53 35 25 17 17 10 9.5 38 53 INPUT OUTPUT MAX or MIN CD74 HCT AC CD74 AC CD74 ACT LV LV MIN 16 125 100 114 45 75 tw 30 44455 30 45555 30 4 5 555 tsu 30 5.5 2254 -5 . 5- - 5 5 MIN5 0.5 2211 53 6.8 12.2 13 15.5 9.5 53 9.3 12.2 13 15.5 9.5 50 6.9 12.2 11.5 17 10.5 50 9.3 12.2 11.5 17 10.5 UNIT fmax : MHz, other : ns MAX MAXt PLH ANY Q or QtPHL th tPLH ANY Q or QtPHL PARAMETER fmax MIN MIN MIN ANY Q or Q PARAMETER fmax th tPLH tPHL tPLH tPHL MIN MAX MAXANY Q or Q CLR (MR) LOW CLK (CP) HIGH CLK (CP) LOW DATA INPUT CLR (MR) INACTIVE CLR CLK (MR) (CP) CLR (MR) LOW CLK (CP) HIGH CLK (CP) LOW DATA INPUT CLR (MR) INACTIVE CLR CLK (MR) (CP) 175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

• Complementary Outputs (Q, Q)
• Buffered Clock and Direct Clear Inputs
• Asynchronous Clear Function

P G Cn + 4 M A = B : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS

• Full Look-Ahead for High-Speed Operations on Long Words
• Input Clamping Diodes Minimize Transmission-Line Effects

337PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE (ACTIVE LOW) M = L; ARITHMETIC OPERATIONS SELECTION ACTIVE-LOW DATA L L L L L L L F = A + B F = 1 F = A + B Cn = L (no carry) Cn = H (with carry) F = AB F = A M = H LOGIC FUNCTIONS3 S2 L L L H L H L L L L H H H H L L F = BH L F = A ⊕ BL L F = A + BH HF = ABL HF = A ⊕ BH H H H H H H H H L L H H L L LH F = B F = A + B F = 0 F = AB F = AB F = A F = AB MINUS 1 F = MINUS 1(2's COMP) F = A PLUS (A + B) F = AB MINUS 1 F = A MINUS 1 F = AB PLUS (A + B) F = A MINUS B MINUS 1 F = A + B F = A PLUS (A + B) F = A PLUS B F = AB PLUS (A + B) F = (A + B) F = A PLUS A* F = AB PLUS A F = AB PLUS A F = A F = AB F = 0 F = A PLUS (A + B) PLUS 1 F = AB F = A F = AB PLUS (A + B) PLUS 1 F = A MINUS B F = (A + B) PLUS 1 F = A PLUS (A + B) PLUS 1 F = A PLUS B PLUS 1 F = AB PLUS (A + B) PLUS 1 F = (A + B) PLUS 1 F = A PLUS A PLUS 1 F = AB PLUS A PLUS 1 F = AB PLUS A PLUS 1 F = A PLUS 1 L H L H L L H H H H L L H HHH FUNCTION TABLE (ACTIVE HIGH) M = L; ARITHMETIC OPERATIONS SELECTION ACTIVE-HIGH DATA L L L L L L L F = AB F = 0 F = AB Cn = H (no carry) Cn = L (with carry) F = A + B F = A M = H LOGIC FUNCTIONS3 L L L H L H L L L L H H H H L L F = BH L F = A ⊕ BL L F = ABH H F = A + BL H F = A ⊕ BH H H H H H H H H L L H H L L LH F = B F = AB F = 1 F = A + B F = A + B F = A F = A + B F = MINUS 1(2's COMPL) F = A PLUS AB F = A + B F = A F = (A + B) PLUS AB F = A MINUS B MINUS 1 F = AB MINUS 1 F = A PLUS AB F = A PLUS B F = (A + B) PLUS AB F = AB MINUS 1 F = A PLUS A* F = (A + B) PLUS A F = (A + B) PLUS A F = A MINUS 1 F = (A + B) PLUS 1 F = 0 F = A PLUS AB PLUS 1 F = (A + B) PLUS 1 F = A PLUS 1 F = (A + B) PLUS AB PLUS 1 F = A MINUS B F = AB F = A PLUS AB PLUS 1 F = A PLUS B PLUS 1 F = (A + B) PLUS AB PLUS 1 F = AB F = A PLUS A PLUS 1 F = (A + B) PLUS A PLUS 1 F = (A + B) PLUS A PLUS 1 F = A L H L H L L H H H H L L H HHH *Each bit is shifted to the next more significant position. *Each bit is shifted to the next more significant position. ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS MAX or MIN TTL LS S AS UNIT MAX 150 37 220 200 mA --- - 3 m A IOL 1682 0 2 0 m A 1682 0 4 8 m A PARAMETER ICC All outputs except A = B MAX G All outputs except G MAX G SWITCHING CHARACTERISTICS PARAMETER MAX or MIN TTL LS S AS tPLH 18 27 10.5 9 tPHL 19 20 10.5 9 tPLH 43 38 18.5 12 tPHL 41 38 18.5 12 tPLH 19 26 12 9 tPHL 18 20 12 9 tPLH 42 32 1 6.5 9.5 tPHL 32 20 16.5 8 UNIT: ns Cn F INPUT OUTPUT Cn Cn + 4 Cn + 4 MAX A, B MAX MAX Ai , B i Fi MAX

(9) (15)P2 or X2 (14)G2 or Y2 (10) (6) (7) P3 or X3 P or X G or Y (5)G3 or Y3 (11) (2)P1 or X1 (1)G1 or Y1 (12) (4)P0 or X0 (3)G0 or Y0 (13)Cn or Cn : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 182 LOOK-AHEAD CARRY GENERATOR

339PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. INPUTS G OUTPUTS P3 P0 OUTPUT X X L X L X X X L X X X X X X L X X X L L L H L G3 G L X L L L X X L L INPUTS Cn+y OUTPUTS G1 G0 P1 P0 C n Cn+y OUTPUT X L L L X X X L X X X L X X H H H H L INPUTS Cn+z OUTPUTS P2 P1 OUTPUT X X L L L X X X X X X L X X X H H H H L P0 Cn Cn+z H X L X X X X L X X L L L P OUTPUTS OUTPUT L H INPUTS LLL P0P2P3 P1 L P INPUTS Cn+x OUTPUTS Cn OUTPUT X HH Cn+x H L L X X L All other combinations All other combinations All other combinations All other combinations All other combinations FUNCTION TABLE ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL S AS UNIT ICC MAX 72 109 36 mA IOH MAX -0.8 -1 -2 mA IOL MAX 16 20 20 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL S AS tPLH 10 10 10 tPHL 10.5 10.5 9.5 tPLH 77 1 0 .5 tPHL 776 tPLH 7.5 7.5 12 tPHL 10.5 10.5 8 tPLH 6.5 6.5 7.5 tPHL 10 10 6 UNIT: ns Cn Cn + X, Cn + Y or Cn + Z MAX P or G MAX Cn + X, Cn + Y or Cn + Z MAX MAX P or G P G P

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS340 190 SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS Logic Diagram QC b c d e f g h i j k l m n o p C QD D RCO MAX/MIN Q Q P PL FF2 T CL Q P PL FF3 T CL Q b LOAD QA D/U CLK P PL FF0 T CL Q A QB CTEN c de f g h i j k l m n o p P PL FF1 T CL Q B QQ

341PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS ALS SN74 HC CD74 HC UNIT ICC MAX 105 35 22 0.08 0.16 mA IOH MAX -0.8 -0.4 -0.4 -4 -4 mA IOL MAX 16 8 8 4 4 mA TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS ALS SN74 HC CD74 HC fmax MIN 20 20 25 17 20 tw 25 25 20 30 30 35 35 20 30 24 tsu MIN 20 20 20 38 18 th MIN 0 5552 tPLH 33 33 30 66 59 tPHL 50 50 30 66 59 tPLH 22 32 21 60 53 tPHL 50 40 21 60 53 tPLH 20 20 20 30 38 tPHL 24 24 20 30 38 tPLH 24 24 18 48 51 tPHL 36 36 18 48 51 tPLH 42 42 31 63 63 tPHL 52 52 31 63 63 tPLH 45 45 37 57 45 tPHL 45 45 28 57 45 tPLH 33 33 25 48 50 tPHL 33 33 25 48 50 UNIT fmax : MHz other : ns CLK D/U RCO RCO MAX/ MIN D/U CLK Q CLK MAX/MIN CLK LOAD Q DATA Q Data , high or low Data hold time LOAD MAX MIN MAX MAX MAX MAX MAX MAX FUNCTION TABLE INPUTS FUNCTION LOAD CTEN D/U CLK HLL Count up HLH Count down LX XX Asynchronous preset HH XX No change D/U or CTEN should be changed only when clock is high. X = Don't care Low-to-high clock transition

Logic Diagram (SN74HC) S R S R S R S R QA QB QC QD RCO CTEN D/U LOAD MAX/MIN CLK A B C D : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS

• Count Enable Control Input
• Ripple Clock Output for Cascading
• Asynchronously Presentable with Load Control

343PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS ALS SN74 HC CD74 HC CD74 HCT UNIT ICC MAX 105 35 22 0.08 0.16 0.16 mA IOL MAX 16 88444 m A TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN TTL LS ALS SN74 HC CD74 HC CD74 HCT MIN 20 20 3 01 72 02 0 tw CLK 25 25 1 6.5 30 30 30 LOAD low 35 35 20 30 24 24 tsu DATA MIN 20 20 20 38 18 18 th DAT AM IN 055522 33 33 30 66 59 60 50 50 30 66 59 60 22 32 21 60 53 57 50 40 21 60 53 57 20 20 20 30 38 53 24 24 20 30 38 53 24 24 18 48 51 41 36 36 18 48 51 41 42 42 31 63 63 63 52 52 31 63 63 63 45 45 37 57 45 45 45 45 28 57 45 45 33 33 25 48 50 57 33 33 25 48 50 57 UNIT fmax : MHz, other : ns t PHL tPLH MAX or MIN tPHL tPLH tPHL D/U RIPPLE CLK tPLH tPHL PARAMETER tPLH tPHL tPLH fmax tPHL tPLH tPHL tPLH MAX MIN MAX MAX MAX MAX MAXMAX or MIN MAX CLK D/U QA, QB QC, QD QA, QB QC, QD LOAD DATA A, B, C, D CLK CLK RIPPLE CLK QA, QB QC, QD

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS344 192 PRESETTABLE SYNCHRONOUS 4-BIT UP/DOWN COUNTERS Logic Diagram (2) (4) OUTPUT Q1 CPD (5)CPU (14)MR (1)DATA (10)DATA (15)DATA (6) OUTPUT Q2 (3) OUTPUT Q0 (12) TCU T S R T S R T S R T S R (11)PL (13) TCD (9)DATA (7) OUTPUT Q3

345PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. TRUE TABLE CLOCK UP RESET FANCTION CLOCK DOWN PARALLEL LOAD LX H X X X LH L H L X H H Load Preset inputs Reset Count Up Count Down NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don't Care, ↑ = Transition from Low to High Level ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN CD74 HC UNIT ICC MAX 0.16 mA IOH MAX -4 mA IOL MAX 4 mA TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN CD74 HC t su MIN 24 tPLH 38 tPHL 38 tPLH 38 tPHL 38 tPLH 65 tPHL 65 tPLH 65 tPHL 65 tPLH 66 tPHL 66 tPHL MR Qn MAX 60 UNIT:ns MINtw CPU, CPD PL MR MAX MAX th Pn to PL Pn to PL CPD to CPU, CPD to CPU MIN CPU CPD TCU TCD QnPL MAX CPU CPD Qn Qn MAX MAX

Logic Diagram (SN74) S R QD BO LOAD CO CLR D S R QC C S R QB B S R 315 QA A UP DOWN S R : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 193 4-BIT SYNCHRONOUS UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)

• Parallel Asynchronous Load for Modulo-N Count Lengths
• Asynchronous Clear

347PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS ALS F SN74 HC CD74 HC CD74 HCT UNIT ICC MAX 102 34 22 54 0.08 0.16 0.16 mA IOL MAX 16 8 8 20 444 m A TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN TTL LS ALS F SN74 HC CD74 HC CD74 HCT fmax MIN 25 25 30 85 17 17 15 tw MIN 2 02 02 0 4 3 03 03 5 tsu DATA MIN 20 20 20 3.5 28 22 22 th DATA MIN 0 5 5 2.5 5 0 0 tPLH 26 26 16 9 41 38 41 tPHL 24 24 18 9 41 38 41 tPLH 24 24 16 9 41 38 41 tPHL 24 24 18 9 41 38 41 tPLH 38 38 19 9 63 65 60 tPHL 47 47 17 13 63 65 60 tPLH 40 40 30 11 65 66 69 tPHL 40 40 28 13 65 66 69 tPHL CLR ANY Q MAX 35 35 17 12 60 60 65 UNIT fmax : MHz, other : ns DOWN UP or DOWN (CD74: CPU) (CD74: CPD) (CD74: CPU or CPD) (CD74: PL) (CD74: MR) LOAD PARAMETER UP ANY Q MAX ANY Q MAX CO MAX BO MAX

Logic Diagram (SN74) Two Identical Channels Not Shown† SR SER SL SER QA QD 1CLR CLK R R A D 15 12 Parallel Inputs Parallel Outputs † I/O ports not shown: QB (14) and QC (13) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS

• Direct Overriding Clear
• Parallel-to-Serial, Serial-to-Parallel Conversions
• Left or Right Shifts

349PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS S AS SN74 HC CD74 HC CD74 HCT UNIT ICC MAX 63 23 135 53 0.1 0.16 0.16 mA IOL MAX 16 8 20 2 0 444 m A TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN TTL LS S AS SN74 HC CD74 HC CD74 HCT MIN 25 2 57 08 02 52 01 8 tw CLR (MR) 20 20 12 4.5 20 24 24 CLK (CP) "H" 20 20 7 4 20 24 24 CLK (CP) "L" 20 20 7 7 20 24 24 tsu Mode Control 30 30 11 9.5 25 24 30 DATA MIN 20 20 5 42 5 2 1 2 1 CLR (MR) INACTIVE 25 25 9 6 - - - MIN 0 0 3 0.5 0 0 0 CLEAR (MR) ANYM AX 30 30 18.5 12 38 42 60 22 22 12 7 36 53 56 26 26 16.5 7 36 53 56 UNIT fmax : MHz, other : ns PARAMETER fmax th t PHL tPLH tPHL MIN MAXCLOCK (CP) ANY LEFT FUNCTION TABLE (SN74) OUTPUTSINPUTS X X MODE SERIAL PARALLEL H L H H H CLEAR H H RIGHT H L L H X L X X X X X X H L X H L X X X X A X X X a X X X B X X X b X X X C X X X c X X X D X X X d X X X QC L H QCn d QD0 QCn L QA L QBn L a QA0 H QBn QB L QCn QAn b QB0 QAn QCn L QDn QBn c QC0 QBn QDnH CLOCK QD H X XX X X X QD0QA0 QB0 QC0L X S1 S0 X H H H L L L

Serial Inputs Parallel Inputs Parallel Outputs : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 195 4-BIT PARALLEL-ACCESS SHIFT REGISTERS

• Direct Overriding Clear
• Parallel-to-Serial, Serial-to-Parallel Conversions

351PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS S AS SN74 HC CD74 HC UNIT ICC MAX 63 21 109 57 0.1 0.16 mA IOH MAX -0.8 -0.4 -1 -2 -4 -4 mA IOL MAX 16 8 20 2 04 4 m A TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUT OUTPUT MAX or MIN TTL LS S AS SN74 HC CD74 HC fmax MIN 30 30 70 70 25 20 tw Clock 16 16 7 4 20 24 MR 12 12 12 7.2 20 24 tsu PE 25 25 11 8 25 30 Serial & Pararel Data MIN 20 15 5 3.5 25 - Clear Inactive Data 25 25 9 6 25 - MAX 10 20 6 - - - MIN 003103 MR MAX 30 30 18.5 11.5 38 45 22 22 12 8.5 36 53 26 26 16.5 10.5 36 53 UNIT fmax : MHz, other : ns TRELEASE t PHL tPLH tPHL th PARAMETER MIN Clock QA, QD MAX TRUTH TABLE OPERATING MODES INPUTS OUTPUT MR CP PE J KD n Q 0 Q1 Q2 Q3 Q3 Asynchronous Reset L X X X X X LLLL H Shift, Set First Stage H h h h X H q0 q1 q2 q2 Shift, Reset First Stage H h l lX L q 0 q1 q2 q2 Shift, Toggle First Stage H h h h l l X q0 q0 q1 q2 q2 Shift, Retain First Stage H h X q 0 q0 q1 q2 q2 Parallel Load H l X Xd n d 0 d1 d2 d3 d2 H = High Voltage Level L = Low Voltage Level, X = Don’t Care = Transition from Low to High Level l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition h = Low Voltage Level One Set-up Time prior to the High to Low Clock Transition, dn (q n) = Lower Case Letters Indicate the State of the Referenced Input (or output) One Set-up Time Prior to the Low to High Clock Transition.

Logic Diagram (SN74LV) CLR Cext Rext/Cext R B A Q Q 1 (9) A 2 (10) B S QM QM R S MASK FF MAIN FF QQ Q R 3 (11) 4 (12) (13) 5 C P Q R QD C C VCC R D C CQ RESET FF VCC PP PULLDOWN FFN MIRROR VOLTAGE VCC P OP AMP P N GND 15 (7) RXCX VCC CX CX 14 (6) OP AMP R RXN : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 221 DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS

• Overriding Clear Terminates Outputs Pulse Logic Diagram (CD74HC/HCT)

353PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE (each monostable multivibrator) INPUTS OUTPUTS CLR ABQQ LXXLH XH LH XX X LLH HL ↑ † † H ↓ H † † ↑‡ LH † † † Pulsed-output patterns are tested during AC switching at 25°C with Rext = 2 kΩ, and Cext = 80 pF. ‡ This condition is true only if the output of the latch formed by the two NAND gates has been conditioned to the logic 1 state prior to CLR going high. This latch is conditioned by taking either A high or B low while CLR is inactive (high). ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN TTL LS CD74 HC CD74 HCT LV LV 5V UNIT ICC MAX 80 27 0.16 0.16 0.28 0.65 mA IOH MAX -0.8 -0.4 -4 -4 -6 -12 mA IOL MAX 16 8446 1 2 m A SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN TTL LS CD74 HC CD74 HCT LV LV A (HC, LV: A) 70 70 63 63 27.5 16 B5 55 56 36 3 27.5 16 A (HC, LV: A) 80 80 51 51 27.5 16 B6 56 55 15 1 27.5 16 tPHL Q2 7 5 54 85 72 21 3 tPLH Q 40 65 54 56 22 13 UNIT: ns Clear MAX tPLH tPHL MAX MAXQ Q

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS354 Logic Diagram Y0(15) Y1(14) Y2(13) Y3(12) Y4(11) Y5(10) Y6(9) Y7(7) OE1 (5) OE0 (6) (3) LE (4) TG TG (2) TG TG (1) TG TG 237 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES

355PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE INPUTS OE0 Y0 OUTPUTS L H LH H L X X X H H L OE1 H H H H H H H L L L L L L L L X H L H H L L X X X L L H H X X X H L H L X L L H L H L H H L L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L LLLLLLL X X H L L L L L L L L LE Depends upon the address previously applied while LE was at a logic low. ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN SN74 HC CD74 HC CD74 HCT UNIT ICC MAX 0.08 0.16 0.16 mA IOH MAX -4 -4 -4 mA IOL MAX 4 4 4 mA TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN SN74 HC CD74 HC CD74 HCT tw MIN 20 1 51 5 tsu MIN 19 1 51 5 th MIN 595 tPLH 48 48 57 tPHL 48 48 57 tPLH 44 44 60 tPHL 44 44 60 tPLH 44 44 53 tPHL 44 44 53 UNIT:ns An to LE Y LE Pulse Width An to LE MAX MAXOE0 An OE1 Y MAX Y

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS356 238 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS Logic Diagram (CD74AC/ACT) Data Outputs Select Inputs Enable Inputs

357PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE INPUTS ENABLE E2 E1 A2 ADDRESS A1 A0 OUTPUTS Y1 Y2 Y3 Y4 Y5 Y6 XXH LXX XHX HLL HLL HLL HLL HLL HLL HLL H Note: H = High Voltage Level, L = Low Volltage Level, X = Don’t Care LL XXX LLL LL L XXX XXX L L H H H H H H H H H L L H H H L H H H H H H H L H LLLLLLLL LLLLLLLL L L L L L L L L L L L L L L L L L L L L L L L L L L L LL LLLLLLL L L LLLLLLL LLLLLL LLLLL LLLL LLL LL L Y7Y0 ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS PARAMETER MAX or MIN CD74 HC CD74 HCT CD74 AC CD74 ACT UNIT ICC MAX 0.16 0.16 0.16 0.16 mA IOH MAX -4 -4 -24 -24 mA IOL MAX 4 4 24 24 mA SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN CD74 HC CD74 HCT CD74 AC CD74 ACT tPLH 45 53 15 15.6 tPHL 45 53 15 15.6 tPLH 60 60 11.9 14.2 tPHL 60 60 11.9 14.2 tPLH 60 60 16.6 13.6 tPHL 60 60 16.6 13.6 UNIT:ns E1, E2 (G2A, G2B) (G1) MAXYAddress MAX MAX Y Y

Logic Diagram (SN74) 21 8 1Y1 1OE 1A1 41 6 1Y21A2 61 4 1Y31A3 81 2 1Y41A4 11 9 2Y1 2OE 2A1 13 7 2Y22A2 15 5 2Y32A3 17 3 2Y42A4 : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 240 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

• 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
• PNP Inputs Reduce DC Loading
• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• CD74AC/ACT240 TA: –40 to 85°C PARAMETER MAX or MIN LS S ALS ALS A-1 AS F SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 BCT ABT UNIT ICCL MAX 44 150 23 23 75 75 0.08 0.16 0.08 0.16 71 30 mA IOH MAX -15 -15 -15 -15 -15 -15 -6 -6 -6 -6 -15 -32 mA IOL MAX 24 64 24 48 64 64 6 6 6 6 64 64 mA PARAMETER MAX or MIN LVT LVTH AC SN74 AC CD74 AC ACT SN74 ACT CD74 ACT AHC A HCT LV LV 5V UNIT IOH MAX -32 -32 -24 -24 -24 -24 -24 -24 -8 -8 -8 -16 mA IOL MAX 64 64 24 24 24 24 24 24 8 8 8 16 mA PARAMETER MAX or MIN LVC LVCZ AUC 1.8V AUC 2.3V AUCH 1.8V AUCH 2.3V UNIT IOH MAX -24 -24 -8 -9 -8 -9 mA IOL MAX 24 24 8989 m A ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS FUNCTION TABLE (each 4-bit buffer) AOE Y INPUTS OUTPUT L L H L H Z H X L

359PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER INPUT OUTPUT MAX or MIN LS S ALS ALS A-1 AS F SN74 HC CD74 HC SN74 HCT CD74 HCT tPLH 14 7 9 9 6.5 8 25 30 32 33 tPHL 18 7 9 9 6.5 5.7 25 30 32 33 tPZH 23 10 13 13 6.4 6.1 38 - 44 - tPZL 30 15 18 18 9 10 38 - 44 - tPHZ 2591 0 1 05 6 . 3 3 8-4 4- tPLZ 20 15 12 12 9.5 9.5 38 - 44 - PARAMETER INPUT OUTPUT MAX or MIN SN74 BCT ABT LVT LVTH AC SN74 AC CD74 AC ACT SN74 ACT CD74 ACT 6.5 6.5 10.9 10.9 10.9 10.9 7.8 7.8 12.2 12.2 12.2 12.20.8 10.5 PARAMETER INPUT OUTPUT MAX or MIN AHC AHCT LV LV LVC LVCZ AUC 1.8V AUC 2.3V AUCH 1.8V AUCH 2.3V t tPZH 10.5 13 16 10.5 8 8 2.7 2 2.7 2 tPZL 10.5 13 16 10.5 8 8 2.7 2 2.7 2 tPHZ 10.5 13 17 15.5 774242 tPLZ 10.5 13 17 15.5 774242 UNIT: ns OE Y (CD74: Y) MAX MAX MAX MAX MAX Y (CD74: Y) MAX Y (CD74: Y) Y (CD74: Y) Y (CD74: Y) OE OE A AY (CD74: Y) OE OE Y MAX AY MAX OE Y MAX SWITCHING CHARACTERISTICS

Logic Diagram (SN74) 21 8 1Y1 1OE 1A1 41 6 1Y21A2 61 4 1Y31A3 81 2 1Y41A4 11 9 2Y1 2OE 2A1 13 7 2Y22A2 15 5 2Y32A3 17 3 2Y42A4 : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 241 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

• 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
• PNP Inputs Reduce DC Loading
• CD74AC/ACT241 TA: –40 to 85°C FUNCTION TABLE (each buffer) AOE Y INPUTS OUTPUT L L H H L Z H X L

361PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN LS S ALS AS F SN74 HC CD74 HC CD74 HCT SN74 BCT ABT LVTH SN74 AC UNIT ICCL MAX 46 180 26 90 90 0.08 0.16 0.16 85 30 5 0.04 mA IOH MAX -15 -15 -15 -15 -15 -6 -6 -6 -15 -32 -32 -24 mA IOL MAX 24 64 24 64 64 6 6 6 64 64 64 24 mA PARAMETER MAX or MIN CD74 AC SN74 ACT CD74 ACT UNIT ICCH MAX 0.16 0.04 0.08 mA ICCL MAX 0.16 0.04 0.08 mA ICCZ MAX 0.16 0.04 0.08 mA IOH MAX -24 -24 -24 mA IOL MAX 24 24 24 mA PARAMETER INPUT OUTPUT MAX or MIN LS S ALS AS F SN74 HC CD74 HC CD74 HCT SN74 BCT tPLH 18 9 11 6.2 6.2 29 33 38 4.9 tPHL 18 9 10 6.2 6.5 29 33 38 5.9 tPZH 23 12 21 9 6.7 38 - - 8.7 tPZL 30 15 21 7.5 8 38 - - 9.4 tPHZ 2591 06 73 8- - 8 . 1 tPLZ 20 15 15 9 7 38 - - 9.9 tPZH 23 12 21 10.5 6.7 38 - - 8.7 tPZL 30 15 21 8.5 8 38 - - 9.4 tPHZ 2591 07 73 8- - 8 . 1 tPLZ 20 15 15 12 7 38 - - 9.9 PARAMETER INPUT OUTPUT MAX or MIN ABT LVTH SN74 AC CD74 AC SN74 ACT CD74 ACT tPLZ 5.9 4.7 10. 5 10.9 8.7 8.7 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.210.5 UNIT: ns 2OE Y (CD74: Y) MAX 2OE Y (CD74: Y) MAX 1OE Y (CD74: Y) MAX 1OE Y (CD74: Y) MAX AY (CD74: Y) MAX 2OE Y (CD74: Y) MAX Y (CD74: Y) MAX 1OE 1OE Y (CD74: Y) MAX 2OE Y (CD74: Y) MAX MAXY (CD74: Y)A ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

Logic Diagram (SN74ALS) OEBA OEAB GBA GAB : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 243 QUADRUPLE BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

• Two-Way Asynchronous Communication Between Data Buses
• PNP Inputs Reduce DC Loading Logic Diagram (SN74LS)

363PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. GBA FUNCTION TABLE (SN74) INPUTS GAB L H LH OPERATION B to A A to B Isolation Latch A and B (A = B) HH L L PARAMETER MAX or MIN LS ALS AS SN74 HC CD74 HC CD74 HCT UNIT ICCH MAX 38 25 44 0.08 0.16 0.16 mA ICCL MAX 50 30 74 0.08 0.16 0.16 mA ICCZ MAX 54 32 56 0.08 0.16 0.16 mA IOH MAX -15 -15 - - -6 -6 mA IOL MAX 24 24 64 6 6 6 mA PARAMETER INPUT OUTPUT MAX or MIN LS ALS AS SN74 HC CD74 HC CD74 HCT tPLH A or B A or B MAX 18 11 7.5 25 27 33 tPHL A or B A or B MAX 18 11 6.5 25 27 33 tPZH 23 20 9 3 84 55 1 tPZL 30 20 7.5 38 45 51 tPHZ 25 14 6.5 38 45 53 tPLZ 20 22 9 3 84 55 3 tPZH 23 20 10.5 38 45 51 tPZL 30 20 8.5 38 45 51 tPHZ 25 14 7 3 84 55 3 tPLZ 20 22 11 38 45 53 UNIT: ns MAX MAXB BGAB GAB GAB GAB A A MAX MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

Logic Diagram (SN74) 21 8 1Y1 1OE 1A1 41 6 1Y21A2 61 4 1Y31A3 81 2 1Y41A4 11 9 2Y1 2OE 2A1 13 7 2Y22A2 15 5 2Y32A3 17 3 2Y42A4 : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 244 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

• 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
• PNP Inputs Reduce DC Loading
• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• CD74AC/ACT244 TA: –40 to 85°C PARAMETER MAX or MIN LS S ALS ALS C-1 AS F SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 BCT SN64 BCT UNIT ICCH MAX 27 160 17 17 34 60 0.08 0.16 0.08 0.16 40 40 mA ICCL MAX 46 180 24 24 90 90 0.08 0.16 0.08 0.16 80 80 mA ICCZ MAX 54 180 27 27 54 90 0.08 0.16 0.08 0.16 10 10 mA IOH MAX -15 -15 -15 -15 -15 -15 -6 -6 -6 -6 -15 -15 mA IOL MAX 24 64 24 48 64 64 6 6 6 6 64 64 mA PARAMETER MAX or MIN ABT LVT LVTH AC SN74 AC CD74 AC ACT SN74 ACT CD74 ACT AHC AHCT LV 3V UNIT IOH MAX -32 -32 -32 -24 -24 -24 -24 -24 -24 -8 -8 -8 mA IOL MAX 64 64 64 LVTZ 0.225 0.225 -32 64 24 24 24 24 24 24 8 8 8 mA PARAMETER MAX or MIN LV LVC LVCH LVCZ ALVC ALVCH AUC 1.8V AUC 2.3V AUCH 1.8V AUCH 2.3V UNIT IOH MAX -16 -24 -24 -24 -24 -24 -8 -9 -8 -9 mA IOL MAX 16 24 LV-AT 0.02 0.02 0.02 -16 16 24 24 24 24 8989 m A ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS FUNCTION TABLE (each buffer) AOE Y INPUTS OUTPUT L L H H L Z H X L

365PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER INPUT OUTPUT MAX or MIN LS S ALS ALS C-1 AS F SN74 HC CD74 HC SN74 HCT tPLH 1891 0 1 0 6 .2 6.2 29 33 35 tPHL 1891 0 1 0 6 .2 6.5 29 33 35 tPZH 23 12 20 20 9 6.7 38 - 44 tPZL 30 15 20 20 7.5 8 38 - 44 tPHZ 2591 0 1 06 73 8-4 4 tPLZ 20 15 13 13 9 7 38 - 44 PARAMETER INPUT OUTPUT MAX or MIN CD74 HCT SN74 BCT SN64 BCT ABT LVT LVTH AC SN74 AC CD74 AC LVTZ 4.1 4.1 5.2 5.2 5.6 5.1 LV-AT 9.5 9.5 8.7 8.7 12.2 12.2 12.2 12.2 7.5 7.5 10.9 10.9 10.9 10.98.2 9.5 PARAMETER INPUT OUTPUT MAX or MIN ACT SN74 ACT CD74 ACT AHC AHCT LV LV LVC LVCH t PARAMETER INPUT OUTPUT MAX or MIN LVCZ ALVC ALVCH AUC 1.8V AUC 2.3V AUCH 1.8V AUCH 2.3V UNIT: ns OE Y MAX OE Y MAX OE Y MAX AY MAX AY MAX OE Y MAX A OE OE MAX Y MAX Y MAX Y OE Y MAX AY MAX OE Y MAX SWITCHING CHARACTERISTICS

Logic Diagram (SN74) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS DIR OE To Seven Other Channels 245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

• 3-State Outputs Drive Bus Lines Directly
• PNP Inputs Reduce DC Loading on Bus Lines
• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) PARAMETER MAX or MIN LS ALS ALS A-1 AS F SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 BCT SN64 BCT ABT ABTH UNIT ICCL MAX 90 55 55 143 120 0.08 0.16 0.08 0.16 90 90 30 30 mA IOH (A port) MAX -15 -15 -15 -15 -3 -6 -4 -6 -4 -3 -3 -32 -32 mA IOH (B port) MAX -15 -15 -15 -15 -15 6 -4 -6 -4 -15 -15 -32 -32 mA IOL (A port) MAX 24 24 48 64 24 -6 4 6 4 24 24 64 64 mA IOL (B port) MAX 24 24 48 64 64 6 4 6 4 64 64 64 64 mA PARAMETER MAX or MIN LVT LVTH LVTR AC SN74 AC CD74 AC ACT SN74 ACT CD74 ACT AHC AHCT LV LV 5V UNIT IOH (A port) MAX -32 -32 -12 -24 -24 -24 -24 -24 -24 -8 -8 -8 -16 mA IOH (B port) MAX -32 -32 -32 -24 -24 -24 -24 -24 -24 -8 -8 -8 -16 mA IOL (A port) MAX 64 64 32 24 24 24 24 24 24 8 8 8 16 mA IOL (B port) MAX 64 64 32 24 24 24 24 24 24 8 8 8 16 mA PARAMETER MAX or MIN LVLV-AT C LVCH LVCZ ALVC ALVCH AUC 1.8V AUC 2.3V AUCH 1.8V AUCH 2.3V UNIT IOH (A port) MAX -24 -24 -24 -24 -24 -8 -9 -8 -9 mA IOH (B port) MAX -24 -24 -24 -24 -24 -8 -9 -8 -9 mA IOL (A port) MAX 24 24 24 24 24 8989 m A IOL (B port) MAX 24 0.02 0.02 0.02 -16 -16 16 24 24 24 24 8989 m A ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS FUNCTION TABLE OPERATION L L H ENABLE G L H X B data to A bus A data to B bus Isolation DIRECTION CONTROL DIR

367PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER INPUT OUTPUT MAX or MIN LS ALS ALS A-1 AS F SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 BCT tPLH 12 10 10 7.5 7 26 33 28 39 7 tPHL 12 10 10 7 7 26 33 28 39 7 tPZH 40 20 20 98 58 45 58 48 10.9 tPZL 40 20 20 8.5 9 58 45 58 48 11.6 tPHZ 28 10 10 5.5 7.5 50 45 50 45 9.3 tPLZ 25 15 15 9.5 7.5 50 45 50 45 9.1 PARAMETER INPUT OUTPUT MAX or MIN SN64 BCT ABT ABTH LVT LVTH AC SN74 AC CD74 AC ACT SN74 ACT PARAMETER INPUT OUTPUT MAX or MIN CD74 ACT AHC AHCT LV LV LLV-AT VC LVCH LVCZ ALVC ALVCH 3.4 3.4 tPZH 14 12 16 19 12 8. 5 8.5 8.5 5.5 5.5 tPZL 14 12 16 19 12 8. 5 8.5 8.5 5.5 5.5 5.5 tPLZ 14.4 11 16.5 22 16 7 9.5 9.5 16.5 5.5 PARAMETER INPUT OUTPUT MAX or MIN AUC 1.8V AUC 2.3V AUCH 1.8V AUCH 2.3V t PLH 2.2 1.8 2.2 1.8 tPHL 2.2 1.8 2.2 1.8 tPZH 3 2.4 3 2.4 tPZL 3 2.4 3 2.4 tPHZ 4 2.6 4 2.6 tPLZ 4 2.6 4 2.6 PARAMETER INPUT OUTPUT MAX or MIN LVTR AB 4.2 BA 4.4 AB 4.6 BA 4.1 B 5.5 B 6.6 A 6.4 B 6.1 A 5.8 B 5.2 A 5.2 UNIT: ns t PHZ OE MAX tPLZ OE MAX tPZH OE MAX tPZL OE MAX tPLH MAX tPHL MAX OE A, B MAX A, B B, A MAX OE A, B MAX OE A, B MAX OE A, B MAX OE A, B MAX A, B B, A MAX A, B B, A MAX OE A, B MAX OE A, B MAX MAX MAX A, B OE B, A A, B SWITCHING CHARACTERISTICS

d (10) OUTPUT c (11) INPUT A (7) OUTPUT b (12) OUTPUT a (13) OUTPUT f (15) OUTPUT e (9) OUTPUT g (14) INPUT B (1) INPUT C (2) (4) (5) INPUT D (8) LAMP TEST INPUT (3) BI/RBO BLANKING INPUT OR RIPPLE-BLANKING OUTPUT RBI RIPPLE-BLANKING INPUT : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 247 BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS

• Open-Collector Outputs Drive Indicators Directly
• Lamp-Test Provision
• Leading/Trailing Zero Suppression

369PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. DECIMAL OR FUNCTION INPUTS D FUNCTION TABLE CBA BI/RBO OUTPUTS L L L L L L L H H L H H H H H H BI RBI LT LT H H H H H H H H H H H H H H H H X H RBI X HL L L L H H H H H L L H H L L H H H H L H L H L L H H H H H H H H H H H H L L H a ON OFF ON ON OFF ON ON ON ON ON OFF OFF OFF ON OFF OFF OFF OFF ON H H H H H H H H X X X X X X X X X X X X X X X L XL X L X X L X X L X X L X H H H H H H H L L L L L L L L L L L L b ON ON ON ON ON ON OFF ON OFF OFF OFF OFF ON c ON OFF ON ON ON ON ON OFF OFF OFF OFF OFF ON d ON OFF ON ON OFF OFF ON ON ON OFF ON OFF OFF OFF ON e ON OFF ON ON ON OFF OFF ON OFF OFF OFF ON f ON OFF OFF ON ON ON OFF OFF ON OFF OFF OFF ON g OFF ON ON OFF ON ON ON ON OFF OFF OFF ON ON ON OFF OFF OFF ON ON ON OFF ON OFF OFF ON ON ON ON OFF OFF OFF OFF OFF OFF ON OFF ON ON ON ON OFF ON ON ON ON ON ON OFF MAX or MIN TTL LS UNIT MAX 103 13 mA VO (off) MAX 15 15 V IO (on) MAX 40 24 mA IOH MAX -0.2 -0.05 mA IOL MAX 8 3.2 mA PARAMETER ICC a thru g BI/RBO MAX or MIN TTL LS toff 100 100 ton 100 100 toff 100 100 ton 100 100 UNIT: ns MIN MIN PARAMETER INPUT A INPUT RBI ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

A B C D OE W Data Inputs Data Selects A B C D A B C D : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 250 1-OF-16 DATA GENERATORS/MULTIPLEXERS WITH 3-STATE OUTPUTS

• 4-Line to 1-Line Multiplexers That Can Select 1-of-16 Data Inputs
• Applications: Boolean Function Generator Parallel-to-Serial Converter Data Source Selector
• Buffered 3-State Bus Driver Inputs Permit Multiplexing From n Lines to One Line
• 3-State Outputs

371PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN AS UNIT ICC MAX 50 mA IOH MAX -15 mA IOL MAX 48 mA PARAMETER INPUT OUTPUT MAX or MIN AS tPLH 8 tPHL 7 tPLH 13 tPHL 10.5 tPZH 7 tPZL 9 tPHZ 6 tPLZ 6.5 UNIT: ns W MAX OE OE MAX MAX MAX SELECT W W W DATA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS C FUNCTION TABLE L H BA L L L L L OE L L L L D L L H L H L L H H H H L L L L L L H H H H L L L L H L L L L L Ei W E6L H L INPUTS OUTPUT L L L L L L L H L H L L L H H L L L H H H H H H H H H E10 E13 E14 E11 E12 E10 E13 E14 E11 E12L H H X L H HH H XX E15 X E15 Z H X

Logic Diagram (SN74ALS,F) OE A B C Y W Data Inputs Data Select (binary) TG TG TG TG TG TG TG TG OE A B C D7: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 251 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS

• 3-State Version of '151
• 3-State Outputs Interface Directly with System Bus
• Perform Parallel-to-Serial Conversion
• Complementary Outputs Provide True and Inverted Data Logic Diagram (SN74HC)

373PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE (SN74) OUTPUTS WOE SELECT STROBE INPUTS X L BC Y L L L H H X L H L H L L Z HH A X H H L L H L LD 6 HHH H L L L L L L L LD 7 Z PARAMETER MAX or MIN TTL LS S ALS F SN74 HC CD74 HC CD74 HCT SN74 AC CD74 AC UNIT IOL MAX 16 8 20 2 42 4 6 4 4 24 24 mA PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS F SN74 HC CD74 HC CD74 HCT SN74 AC CD74 AC tPLH 45 45 18 18 9.5 51 74 63 18.2 18.2 tPHL 45 45 19.5 24 7.5 51 74 63 18.2 18.2 tPLH 33 33 15 24 12.5 51 74 63 19.6 19.6 tPHL 33 33 13.5 23 9 51 74 63 19.6 19.6 tPLH 28 28 12 10 74 95 35 31 3.5 13.5 tPHL 28 28 12 15 54 95 35 31 3.5 13.5 tPLH 15 1571 58 49 53 53 14.9 14.9 tPHL 15 1571 58 49 53 53 14.9 14.9 tPZH 27 45 19.5 15 7 36 42 45 13.5 13.5 tPZL 40 40 21 15 6.5 36 42 45 13.5 13.5 tPZH 27 27 19.5 15 6 36 42 45 13.5 13.5 tPZL 40 40 21 15 4.5 36 42 45 13.5 13.5 tPHZ 84 5 8 . 5 1 0 8.5 49 42 45 13.5 13.5 tPLZ 23 25 14 10 84 94 24 51 3.5 13.5 tPHZ 85 5 8 . 5 1 0 5.5 49 42 45 13.5 13.5 tPLZ 23 25 14 10 4.5 49 42 45 13.5 13.5 A, B, C MAXYA, B, (CD74: S0, S1, S2) (CD74: ANYI) (CD74: ANYI) (CD74: S0, S1, S2) C G ANY D ANY D G G G MAX MAX Y W (CD74: Y) Y W (CD74: Y) Y W (CD74: Y) MAX MAX MAX MAX MAXW (CD74: Y) UNIT: ns ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

Logic Diagram (SN74ALS, AS, F) Data 2 Select Data 1 2OE 2C3 2C2 2C1 2C0 A B 1C3 1C2 1C1 1C0 1OE 2Y9 TG TG TG TG TG TG TG TG TG TG TG TG 1OE A B 1C0 1C1 1C2 1C3 2OE 2C0 2C1 2C2 2C3 : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 253 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS

• 3-State Version of '153
• Perform Parallel-to-Serial Conversion Logic Diagram (SN74HC)

375PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN LS ALS AS F SN74 HC CD74 HC CD74 HCT CD74 AC CD74 ACT UNIT IOH MAX -2.6 -2.6 -15 -3 -6 -6 -4 -24 -24 mA IOL MAX 8 24 4 82 4 664 2 4 24 mA PARAMETER INPUT OUTPUT MAX or MIN LS ALS AS F SN74 HC CD74 HC CD74 HCT CD74 AC CD74 ACT tPLH 25 10 7.5 8 35 53 57 13.3 18 tPHL 20 14 87 35 53 57 13.3 18 tPLH 45 21 13.5 13 38 53 60 20 22 tPHL 32 21 11.5 10 38 53 60 20 22 tPZH 28 14 12.5 9 25 33 45 11.5 12.6 tPZL 23 16 11.5 9 25 33 45 11.5 12.6 tPHZ 41 10 66 38 45 45 11.5 12.6 tPLZ 27 14 77 38 45 45 11.5 12.6 UNIT: ns DATA SELECT OE OE Y MAX Y MAX Y MAX Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE (SN74) OUTPUTOUTPUT CONTROL SELECT INPUTS X L C1C0 L X L L L B H X H H H H X L L H A L L H H H X X X X X X L X X H X X X X X X L H X X X X X L H X X X X Y Z L H L H L H L H OE H L L L L L L L LX X X DATA INPUTS

Logic Diagram (SN74) A/B OE 1A 4 : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 257 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS

• 3-State Outputs Interface Directly with System Bus
• Provides Bus Interface from Multiple Sources in High-Performance Systems

377PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN LS S ALS AS F SN74 HC CD74 HC SN74 HCT CD74 HCT AC CD74 AC ACT IOL MAX 24 20 24 48 24 6666 2 4 2 4 2 4 m A PARAMETER MAX or MIN CD74 ACT LVC 3V UNIT ICC MAX 0.16 0.01 mA IOH MAX -24 -24 mA IOL MAX 24 24 mA PARAMETER INPUT OUTPUT MAX or MIN LS S ALS AS F SN74 HC CD74 HC SN74 HCT CD74 HCT tPLH 13 7.5 10 5.5 7 25 45 38 50 tPHL 15 6.5 12 6 6.5 25 45 38 50 tPLH 21 15 18 11 15 25 53 38 57 tPHL 24 15 22 10 9.5 25 53 38 57 tPZH 30 19.5 16 7.5 8.5 38 45 38 45 tPZL 30 21 18 9.5 8.5 38 45 38 45 tPHZ 30 8.5 10 6.5 7 38 45 38 45 tPLZ 25 14 15 7 7 38 45 38 45 PARAMETER INPUT OUTPUT MAX or MIN AC CD74 AC ACT CD74 ACT LVC UNIT: ns OE Y MAX OE Y MAX DATA ANY MAX SELECT ANY MAX ANYSELECT MAXANYDATA MAX OE OE MAX MAX Y Y ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE (SN74) OUTPUT X L A H L Z L H H L L L LH L H H X X X X BY X L H L X SELECT INPUTS OUTPUT CONTROL OE A/B

Logic Diagram (SN74) A/B OE : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 258 QUADRUPLE 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS

• 3-State Outputs Interface Directly with System Bus
• Provides Bus Interface from Multiple Sources in High-Performance Systems

379PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN LS S ALS AS F SN74 HC CD74 HC CD74 HCT CD74 ACT UNIT IOL MAX 8 20 2 44 82 4 6 6 6 2 4 m A PARAMETER INPUT OUTPUT MAX or MIN LS S ALS AS F SN74 HC CD74 HC CD74 HCT CD74 ACT tPLH 12 6856 2 5 2 4 3 4 10.7 tPHL 17 674 5 . 5 2 5 2 43 4 10.7 tPLH 21 12 25 9.5 9.5 25 35 43 15.4 tPHL 24 12 20 10 11 25 35 43 15.4 tPZH 30 19.5 18 8 8.5 38 35 35 16.1 tPZL 30 21 18 10 8.5 38 35 35 16.1 tPHZ 30 8.5 10 6 7 38 38 38 16.1 tPLZ 25 14 18 6.5 7 38 38 38 16.1 UNIT: ns GY MAX GY MAX DATA Y MAX SELECT Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE X L H H Z H L H L L L LL L H H X X X X X L H L X OUTPUT AB YSELECT INPUTS OUTPUT CONTROL OE A/B

Logic Diagram (SN74ALS) D CLR : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 259 8-BIT ADDRESSABLE LATCHES

• 8-Bit Parallel-Out Storage Register Performs Serial-to-Parallel Conversion with Storage
• Asynchronous Parallel Clear
• Active-High Decoder
• Enable/Disable Input Simplifies Expansion
• Expandable for n-Bit Applications
• Four Distinct Functional Modes

381PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. INPUTS H H GCLEAR L L L LH H D D L Qi0 Qi0 L L Qi0 FUNCTION TABLE (SN74)LATCH SELECTION CBA LLL LLH LHL LHH HLL HLH HHL HHH SELECT INPUTS LATCH ADDRESSED FUNCTION Addressable latch Memory 8-line demultiplexer Clear OUTPUT OF ADDRESSED LATCH EACH OTHER OUTPUT PARAMETER MAX or MIN TTL LS ALS SN74 HC CD74 HC CD74 HCT UNIT ICC MAX 90 36 22 0.08 0.16 0.16 mA IOH MAX 16 88444 m A INPUT OUTPUT MAX or MIN TTL LS ALS SN74 HC CD74 HC CD74 HCT tw G (CDHC/HCT: LE) 15 17 15 20 21 27 CLR (CDHC/HCT: MR) 15 10 10 20 21 27 tsu DATA 15 20 15 19 24 26 ADDRESS 51 7 1 51 92 42 6 th DATA 000500 ADDRESS 20 00500 tPLH CLEAR (CDHC/HCT: MR) Any QM A X 2 5 18 12 38 47 59 tPHL 24 30 19 33 56 59 tPLH 20 20 12 33 - 59 tPHL 28 27 22 50 56 61 tPLH 28 20 12 50 - 61 tPHL 20 24 20 43 51 57 tPHL 20 24 13 43 - 57 UNIT: ns MIN MIN MIN MAX MAX MAX Any Q Any Q Any Q DATA ADDRESS ENABLE PARAMETER ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS A B YC D E 265 QUADRUPLE COMPLEMENTARY-OUTPUT ELEMENTS

• Y = A, W = A
• Y = AB, W = AB PARAMETER INPUT OUTPUT MAX or MIN TTL tPLH (W) A or B W MAX 18 tPHL (Y) A or B Y MAX 18 tPLH (W) A or B W MAX 18 tPHL (Y) A or B Y MAX 18 UNIT: ns tPLH (W) -tPHL (Y) tPHL (W) -tPLH (Y) A or B A or B MAX MAX W w ith respect Y W w ith respect Y PARAMETER MAX or MIN TTL UNIT ICC MAX 34 mA IOH MAX -0.8 mA IOL MAX 16 mA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS 260 DUAL 5-INPUT POSITIVE-NOR GATES
• Y = A + B + C + D + E PARAMETER INPUT OUTPUT MAX or MIN S F tPLH 5.5 6.5 tPHL 6 4.5 UNIT: ns A, B, C, D, E Y MAX PARAMETER MAX or MIN S F UNIT ICC MAX 45 9.5 mA IOH MAX -1 -1 mA IOL MAX 20 20 mA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS A Y W A B Y W ELEMENTS 1 and 4 ELEMENTS 2 and 3

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 266 QUADRUPLE 2-INPUT EXCLUSIVE-NOR GATES WITH OPEN-DRAIN OUTPUTS

• Y = A ⊕ B A B Y PARAMETER MAX or MIN LS SN74 HC UNIT ICC MAX 13 0.02 mA VOH MAX 5.5 Vcc V IOL MAX 8 4 mA PARAMETER INPUT OUTPUT MAX or MIN LS SN74 HC tPLH A or B Other INPUT Low YM A X 30 31 tPHL A or B Other INPUT Low YM A X 30 25 tPLH A or B Other INPUT High YM A X 30 31 tPHL A or B Other INPUT High YM A X 30 25 UNIT: ns ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS INPUTS FUNCTION TABLE OUTPUT L Y H A L L H L LL HHH B H

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS Logic Diagram (SN74) 384 273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR

• Contain Eight Flip-Flops with Single-Rail Outputs
• Buffered Clock and Direct-Clear Inputs CLK CLR R R R R R R R R 34 78 1 3 14 17 18 2569 1 2 15 16 19 CLOCK FUNCTION TABLE (SN74) INPUTS CLEAR D L H H X X OUTPUT Q H L L H L H X L

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 385 PARAMETER MAX or MIN TTL LS ALS SN74 HC CD74 HC SN74 HCT CD74 HCT ABT LVTH CD74 AC CD74 ACT UNIT IOL MAX 1682 4 4444 6 4 6 4 2 4 2 4 m A PARAMETER MAX or MIN AHC AHCT LV LV 5V UNIT ICC MAX 0.04 0.04 - 0.02 mA IOH MAX -8 -8 -6 -12 mA IOL MAX 8 8 6 12 mA INPUT OUTPUT MAX or MIN TTL LS ALS SN74 HC CD74 HC SN74 HCT CD74 HCT ABT MIN 30 30 3 52 12 01 61 6 1 5 0 MIN 16.5 20 1 42 02 42 53 0 3 . 3 tsu DATA INPUT MIN 20 20 10 25 18 25 18 2.5 CLR INACVIVE MIN 25 25 1 52 5 - 2 5 - 2 MIN 5500303 1 . 2 CLEAR ANY Q MAX 27 27 18 40 45 42 48 7.4 27 27 12 40 45 42 45 6.5 27 27 15 40 45 42 45 7.3 INPUT OUTPUT MAX or MIN LVTH CD74 AC CD74 ACT AHC AHCT LV LV MIN 150 100 85 70 45 45 70 MIN 3.3 5 6 5 6.5 6.5 5 tsu DATA INPUT MIN 2.3 2 2 4.5 5 6.5 4.5 CLR INACVIVE MIN 2.3 - - 2 2.5 2.5 2 MIN 0221011 UNIT fmax : MHz, other : ns t PLH tPHL ANY Q MAXCLOCK CLOCK ANY Q MAX fmax tw PARAMETER tPHL th PARAMETER fmax tw th tPHL tPLH tPHL ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

Q J CK 1Q 1CLK 1K K PR (5) (1) (2) (3) (4) CLR Q J 2CLK 2K K PR (6) (9) (8) (7) CLR Q J 3CLK 3K K PR (15) (12) (13) (14) CLR Q J 4CLK 4K K PR (16) (19) (18) (17) PRESET (11) CK CK CK : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 276 QUADRUPLE J-K FLIP-FLORS

• Separate Negative-Edge-Triggered Clocks
• Fully Buffered Outputs PARAMETER MAX or MIN TTL UNIT ICC MAX 81 mA IOH MAX -0.8 mA IOL MAX 16 mA INPUT OUTPUT MAX or MIN TTL MIN 35 tw CLOCK high 13.5 CLOCK low 15 tsu J, K 3 CLR, PRE 10 MIN 10 PRESET QM A X 2 5 CLEAR QM A X 3 0 UNIT fmax : MHz, other : ns MIN PARAMETER MIN MAXQCLOCK t PLH tPHL fmax th tPLH tPHL ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE KCLOCK INPUTS OUTPUTCOMMON INPUTS L H CLEARPRESET J L H H H H H L H H H H L X X X H L H L HH X X X HX Q H L H TOGGLE L X X X H H L L X † The output levels in this configuration are not guaranteed to meet the minimum levels for VOH. Furthermore, this configuration is nonstable; that is, it will not persist when either PRE or CLR returns to its inactive (high) level.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. R QS1 (latches 1 and 3) R Q S (latches 2 and 4) 279 QUADRUPLE S-R LATCHES PARAMETER INPUT OUTPUT MAX or MIN TTL LS tW MIN 20 20 tPLH 22 22 tPHL Q1 5 2 1 tPHL R MAX 27 27 UNIT: ns S MAX PARAMETER MAX or MIN TTL LS UNIT ICC MAX 30 7 mA IOH MAX -0.8 -0.4 mA IOL MAX 16 8 mA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS H = high level L = low level †For latches with double S inputs: Q0 = the level of Q before the indicated input conditions were established. ‡This configuration is nonstable: that is, it may not persist when the S and R inputs return to their inactive (high) level. H = both S inputs high L = one or both S inputs low INPUTS OUTPUT QS† R HH Q 0 LH H HL L LL H ‡ FUNCTION TABLE (each latch)

Logic Diagram (SN74) A B C D E F G H I Σ EVEN Σ ODD : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 280 9-BIT PARITY GENERATORS/CHECKERS

• Generate Either Odd or Even Parity for Nine Data Lines
• Cascadable for n-Bit Parity

389PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER INPUT OUTPUT MAX or MIN LS S ALS AS F SN74 HC CD74 HC CD74 HCT CD74 AC CD74 ACT tPLH 50 21 20 12 10 52 60 63 20 21.6 tPHL 45 18 20 11 11 52 60 63 20 21.6 tPLH 35 21 20 12 10 52 60 68 21 21.6 tPHL 50 18 22 11.5 11 52 60 68 21 21.6 UNIT: ns DATA Σ EVEN (CD74: ΣE) Σ ODD (CD74: ΣO) MAX DATA MAX PARAMETER MAX or MIN LS S ALS AS F SN74 HC CD74 HC CD74 HCT CD74 AC CD74 ACT UNIT IOL MAX 8 20 2 42 02 0 4 4 4 2 42 4 m A ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS Σ EVEN OUTPUTS Σ ODD LH HL NO. OF INPUTS A–I THAT ARE HIGH FUNCTION TABLE (SN74) 0, 2, 4, 6, 8 1, 3, 5, 7, 9

Logic Diagram (SN74) C0 7 C49 : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 283 4-BIT BINARY FULL ADDERS WITH FAST CARRY

• Full-Carry Look-Ahead Across the Four Bits

391PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. WHEN C2 = L WHEN C0 = L WHEN C2 = H WHEN C0 = H A3 B4 FUNCTION TABLE (SN74) Σ3 Σ4 LL H L H L H L H L H L L L L L L H H L H H H H H H L H L H L H H L H L H L L L H H L L L H H H L LL H H L L H L H L H L L L H H H H L L H L L H L H H H H H L L H H L H L H L H L H L H L L L L L L L H L L L H H H H L L L L H H H H H L H L L H H H L H L L L H H L L H L L H H A1 B2 Σ1 Σ2B1 A2 Σ1C2 Σ2C 2 L L L H H L H H H H H H L L H L H L LH H H INPUTS OUTPUTS MAX or MIN TTL LS S F CD74 HC CD74 HCT CD74 AC CD74 ACT UNIT MAX 110 39 160 55 0.16 0.16 0.16 0.16 mA Any OUTPUT except C4 MAX -0.8 -0.4 -1 -1 -4 -4 -24 -24 C4 MAX -0.4 -0.5 Any OUTPUT except C4 MAX 16 8 20 20 4 4 24 24 C4 MAX 8 10 mA PARAMETER ICC IOL IOH mA PARAMETER INPUT OUTPUT MAX or MIN TTL LS S F CD74 HC CD74 HCT CD74 AC CD74 ACT tPLH MAX 21 24 18 10.5 69 80 17.6 17.6 tPHL MAX 21 24 18 10.5 69 80 17.6 17.6 tPLH MAX 24 24 18 10.5 63 74 18.2 18.2 tPHL MAX 24 24 18 10.5 63 74 18.2 18.2 tPLH MAX 14 17 11 8.5 59 6 91 7 . 6 1 7 . 6 tPHL MAX 16 22 11 85 96 9 17.6 17.6 tPLH MAX 14 17 12 8.5 59 7 21 7 . 6 1 7 . 6 tPHL MAX 16 17 12 85 97 2 17.6 17.6 UNIT: ns C4 (CD74:C OUT) Any Σ (CD74:S 3) Σn (CD74:Sn) C0 (CD74:C IN) An or Bn C0 (CD74:C IN) An or Bn ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

Logic Diagram (SN74AS) PARITY ERROR A B C D E F G H I PARITY I/O XMIT : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 286 9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS WITH BUS DRIVER PARITY I/O PORT

• Generate Either Odd or Even Parity for Nine Data Lines
• Cascadable for n-Bit Parity
• Direct Bus Connection for Parity Generation or Checking by Using the Parity I/O Port
• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)

393PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE (SN74AS) PARITY ERROR PARITY I/O H L h l h H H H L XMIT NUMBER OF INPUTS (A–I) THAT ARE HIGH 0, 2, 4, 6, 8 1, 3, 5, 7, 9 1, 3, 5, 7, 9 0, 2, 4, 6, 8 l l l h h h hH L h = high input level l = low input level H = high output level L = low output level MAX or MIN AS AC ACT ICC MAX 50 0.08 0.08 mA Parity error MAX -2 -24 -24 mA Parity I/O MAX -15 -24 -24 mA Parity error MAX 20 24 24 mA Parity I/O MAX 48 24 24 mA PARAMETER IOH IOL PARAMETER INPUT OUTPUT MAX or MIN AS AC ACT tPLH 15 9 10.4 tPHL 14 107 12 tPLH 16.5 10 11.3 tPHL 16.5 12 12.9 tPLH 9 6.2 7.7 tPHL 9 7.9 9.1 tPZH 13 5.3 7.3 tPZL 16 8.9 11.4 tPHZ 11.5 6.5 8.5 tPLZ 10 6.3 7.8 UNIT: ns MAXA to I Parity I/O MAX MAX Parity I/O Parity error MAX XMIT Par ity I/O A to I Parity error ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

TP2(6) 2D R R A (10) (1) C4(15) D8(14) E1 6(2) T TP1(3) 2D R R 2T0 X/Y CLK1 (4) CLR (11) CLK2 (5) T R T R T R T TP3(13) 2D R R T 2D R Q(7) 2D R T R T 2D R S : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 292 PROGRAMMABLE FREQUENCY DIVIDERS/DIGITAL TIMERS

• Digitally Programmable from 22 to 231
• Easily Expandable
• Applications: Frequency Division Digital Timing

395PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN LS UNIT ICC MAX 75 mA IOH (Q only) MAX -1.2 V IOL (Q only) MAX 24 mA PARAMETER INPUT OUTPUT MAX or MIN LS fmax CLK MIN 30 tPLH CLK Q MAX 90 tPHL CLK Q MAX 120 tPHL CLR Q MAX 65 UNIT fmax : MHz, other : ns ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS Q OUTPUT MODE L H CLK 1 CLK 2CLEAR H X L HH X X L Cleared to L Count Inhibit HX H Inhibit Count FUNCTION TABLE

J (4)Q CK QC K J (9)Q CK QA K J (8)Q CK QD R0(1) (12) K J (5)Q CK QB K R0(2) (13) INPUT A INPUT B (10) (1) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 293 4-BIT BINARY COUNTERS

397PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. QB COUNT SEQUENCE OUTPUTS L L QCQD COUNT H H QA RESET/COUNT FUNCTION TABLE L L L L L L L L L L L L H H H H L L H H L L H H L L L H L H L H L H L H H10 L H L H11 LH H H12 HL L H13 HL H H14 HHL H15 H H H QB OUTPUTS L QCQD QA L COUNT LL RESET INPUTS H L R0(2)R0(1) X COUNT H L X NOTE: Output QA is connected to input B. PARAMETER MAX or MIN TTL LS UNIT ICC MAX 39 15 mA IOH MAX -0.8 -0.4 mA IOL MAX 16 8 mA INPUT OUTPUT MAX or MIN TTL LS AQ A M I N 32 32 BQ B M I N 16 16 tw A1 5 1 5 B3 0 3 0 Reset 15 15 tsu MIN 25 25 16 16 18 18 70 70 70 70 16 16 21 21 32 32 35 35 51 51 51 51 UNIT fmax : MHz, other : ns B A, B MIN A AQ A MAX QC QD QB MAX MAX MAX MAXQB B B PARAMETER fmax t PLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS398 Logic Diagram Q(7) 2D R A B 1(2) (1) C (15) D (14) 8 TP(3) X/Y CLK1 (4) CLR (11) CLK2 (5) R T R T 3D S 2D R 294 PROGRAMMABLE FREQUENCY DIVIDERS/DIGITAL TIMERS

• Digitally Programmable from 22 to 215
• Easily Expandable
• Applications Frequency Division Digital Timing

399PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. A FUNCTION TABLE FREQUENCY DIVISIONPROGRAMMING INPUTS L L BCD L L L L L L L L L BINARY H L L H H L L H H H H L L L H L H L H L H Inhibit Inhibit L DECIMAL Inhibit 128 256 Inhibit DECIMAL Inhibit 512 512 Inhibit 512 512 512 BINARY Inhibit Disabled Low Inhibit 29H H L LH 2 9L 512 8 23H LH 210H 1024 16 24L LH 211H 2048 32 25H HH 212L 4096 6426L HH 213L 8192 12827H HH 214H 16384 25628L HH2 15H 32768 51229H QT P PARAMETER MAX or MIN LS UNIT ICC MAX 50 mA IOH MAX -1.2 V IOL MAX 24 mA INPUT OUTPUT MAX or MIN LS CLK MIN 30 CLK 1 or 2 MIN 16 CLR MIN 35 120 CLR Q MAX 65 UNIT fmax : MHz, other : ns MAXCLK 1 or 2 Q PARAMETER tPLH tPHL tPLH fmax tw ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

Logic Diagram (SN74LS) D8(14)C4 K COUNTER TO MODE CONTROLS 12-2 (11-STAGES NOT SHOWN) X/Y (15)B2(1)A1(2) ENCTR (3) I/D CLK (5) fB (10) fA2 (13) fA1 (9) EXCLUSIVE-OR PHASE DETECTOR I/D CIRCUIT EDGE CONTROLLED PHASE DETECTOR S R XORPD OUT (11) I/D OUT(7) D/U (6) KCLK (4) ECPD OUT (12) 21D 21D C21 C21 S R 21J 21K C21 DECREMENT INCREMENT T RR 21D 21D C21 21D C21 C21C21 21D 21D21D C21 C21 1T T RR T R T R POWER-UP RESET I = 1 T R T R M13 13D 13T R M13 13D 13T R M14 14D 14T R M14 14D 14T R 20D C20 20D C20 14 13 1201 11 0 987654321 : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 297 DIGITAL PHASE-LOCKED-LOOP FILTERS

401PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. K COUNTER FUNCTION TABLE (DIGITAL CONTROL) EXCLUSIVE OR PHASE DETECTOR L LLL HLLL 24LLLH 25HLLH 26LHLL 27HHLL 28LHLH 29HHLH 210LLHL 211HLHL 212LLHH 213HLHH 214LHHL 215HHHL 216LHHH 217HHHH ACDB Inhibited A1 B FUNCTION TABLES (SN74LS) XORPD OUT H LL L H L LH LHH H EDGE-CONTROLLED PHASE DETECTOR A2 B ECPD OUT H φφ φφ ↓ L No change No change MODULO (K) H or L H or L H or L H or L PARAMETER MAX or MIN LS CD74 HC CD74 HCT CD74 ACT UNIT ICC MAX 120 0.16 0.16 0.08 mA IOH I/D OUT MAX -1 -6 -4 -24 mA XOR, ECPD MAX -0.4 IOL I/D OUT MAX 24 44 2 4 mA XOR, ECPD MAX 8 OUTPUT MAX or MIN LS CD74 HC CD74 HCT CD74 ACT I/D OUT 32 20 20 45 I/D OUT 16 13 13 35 tw K CLK (KCP)1 6 2 4 2 4 8 I/D CLK (I/DCP)3 3 3 8 3 8 9 tsu D/U 30 30 30 17 ENCLR (ENCTR)3 1 3 0 3 01 6 th D/U 0007 ENCLR (ENCTR)0 0 0 6 25 53 53 24 35 53 53 24 other INPUT low 15 45 45 22 other INPUT high 25 45 45 22 other INPUT low 25 45 45 22 other INPUT high 25 45 45 22 ECPD OUT 30 60 60 30 ECPD OUT 30 60 60 30 UNIT fmax : MHz, other : ns INPUT fmax K CLK (K CP) MINI/D CLK (I/DCP) PARAMETER MIN MIN MIN t PLH I/D CLK ↑ I/D OUT MAXtPHL XORPD OUT MAX tPHL XORPD OUT tPLH φφ φ φ A1 or B φφA1 or B tPLH B ↓ MAXtPHL A2 ↓ ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 298 QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE

• Outputs Storage Register

403PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. INPUTS FUNCTION TABLE OUTPUTS QD QB QB0 QC0 QD0 QA QA0 CLOCK H SELECT WORD L H X QC † a1, a2, etc. = the level of steady-state input at A1, A2, etc. QA0, QB0, etc. = the level of QA, QB, etc. entered on the most recent O transition of CLK PARAMETER MAX or MIN TTL LS AS SN74 HC UNIT ICC MAX 65 21 36 0.08 mA IOL MAX 16 8 2 04 m A IOH MAX -0.8 -0.4 -2 -4 mA PARAMETER INPUT OUTPUT MAX or MIN TTL LS AS SN74 HC tw MIN 2 02 082 7 Data 15 15 4.5 21 Word Select 25 25 13 21 Data 5 5 3.5 0 Word Select 0 0 1 0 tPLH 27 2 793 1 tPHL 32 32 11 31 UNIT: ns tsu th GA to GDCLK MIN MIN MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

Logic Diagram (SN74) Six Identical Channels Not Shown† SR (shift right serial input) CLK QA′ OE1 OE2 SL (shift left serial input) QH′ 71 6 A/QA H/QH 9CLR RR † I/O ports not shown: B/QB (13), C/QC (6), D/QD (14), E/QE (5), F/QF (15), and G/QG (4). : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS

• Multiplexed I/O Ports Provide Improved Bit Density
• Four Modes of Operation: Hold (Store) Shift Right Shift Left Load Data
• Operate with Outputs Enabled or at High Impedance
• 3-State Outputs Drive Bus Lines Directly
• Can Be Cascaded for n-Bit Word Lengths

405PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. INPUTS I/O PORTS OUTPUTS MODE CLR S1 S0 OE1 † OE2† CLK SL SR A/Q A B/Q B C/Q C D/Q D E/Q E F/Q F G/Q G H/Q H Q A' Q H' Clear L L L X L H L X H L L X L L X X X X X X X X X X L L X L L X L L X L L X L L X L L X L L X L L X L L L L L L Hold H H L X L X L L L L X L X X X X Q A0 Q A0 Q B0 Q B0 Q C0 Q C0 Q D0 Q D0 Q E0 Q E0 Q F0 Q F0 Q G0 Q G0 Q H0 Q H0 Q A0 Q A0 Q H0 Q H0 Shift Right H H L L H H L L L L ↑ X X H L H L Q An Q An Q Bn Q Bn Q Cn Q Cn Q Dn Q Dn Q En Q En Q Fn Q Fn Q Gn Q Gn H L Q Gn Q Gn Shift Left H H H H L L L L L L ↑ H L X X Q Bn Q Bn Q Cn Q Cn Q Dn Q Dn Q En Q En Q Fn Q Fn Q Gn Q Gn Q Hn Q Hn H L Q Bn Q Bn H L Load H H H X X ↑ XX a b c d e f g h a h FUNCTION TABLE (SN74) † When one or both output-enable inputs are high, the eight I/O terminals are disabled to the high-impedance state; however, sequential operationor clearing of the register is not affected. MAX or MIN LS S ALS F CD74 HC CD74 HCT CD74 AC CD74 ACT UNIT MAX 53 225 40 95 0.16 0.16 0.16 0.16 mA QA thru QH 24 20 24 24 6 4 24 24 QA' or QH' 868 2 0 44 24 24 PARAMETER ICC mA mA IOH MAX IOL MAX INPUT OUTPUT MAX or MIN LS S ALS F CD74 HC CD74 HCT CD74 AC CD74 ACT MIN 20 50 3 07 02 01 69 59 0 tw CLK (CP) high 30 10 16.5 7 24 30 5.2 5.5 CLK (CP) low 10 10 16.5 7 24 30 5.2 5.5 CLR (MR) 20 10 10 7 15 22 5 5 DATA "H" 2 0 7 1 6 5.5 36 30 4.5 4.5 DATA "L" 2 0 5 6 5.5 36 30 4.5 4.5 SELECT 35 15 20 8.5 36 41 9 9 CLR (MR) INACTIVE (CD74: CP) (CD74: CP) 20 10 15 7 - - - - DATA 05020000 SELECT 10 5000000 33 20 15 10 60 68 12.9 12.9 39 20 18 9.5 60 68 12.9 12.9 25 21 13 10 60 68 13.5 14.5 39 21 19 12 60 68 13.5 14.5 CLR 40 21 22 10.5 60 69 11.2 12.2 CLR 40 24 22 15 60 69 13.9 18.6 21 18 16 94 74 81 4.9 14.9 30 18 22 11 39 45 14.9 14.9 20 12 87 56 56 14.9 14.9 15 12 15 6.5 47 48 14.9 14.9 UNIT fmax : MHz, other : ns CLK Q A'or QH' (CD74: Q0 or Q7) QA thru QH (CD74: I/O0 thru I/O7) QA'or QH' (CD74: Q0 or Q7) QA thru QH (CD74: I/O0 thru I/O7) fmax tsu MAX MIN MIN th PARAMETER MIN tPHL tPLH tPHL tPLH CLK MAXtPHL MAX tPHL tPZH OE1, OE2 QA thru QH QA thru QH MAXtPZL OE1, OE2 MAXtPLZ tPHZ ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

T DRIVER SECTION (6) F/2(13) T'LS321 ONLY OSC F(10) VCC F(7) F(12) FFQ1D (4)FFD (5) TANK 2 (2) XTAL 1 (14) TANK 1 (1) XTAL 2 (15) F(9) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 321 CRYSTAL-CONTROLLED OSCILLATORS

• Crystal-Controlled Oscillator Operation from 1MHz to 20MHz
• Complementary Outputs

407PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. MAX or MIN LS UNIT MAX 75 mA F' or F' MAX -24 mA F, F, F/2, F/4 MAX -0.4 mA F' or F' MAX 24 mA F, F, F/2, F/4 MAX 8 mA PARAMETER ICC IOL IOH PARAMETER INPUT OUTPUT MAX or MIN LS F/2 MIN 10 fmax F/4 MAX 5 ANY MIN 20 F',F' MAX 14 ANY MAX 40 F',F' MAX 10 ANY MAX 20 UNIT fmax : MHz, other : ns tr tf ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

Logic Diagram (SN74ALS) Six Identical Channels Not Shown† CLR SR (shift right serial input) CLK QA′ OE1 OE2 SL (shift left serial input) QH′ 71 6 A/QA H/QH † I/O ports not shown: B/QB (13), C/QC (6), D/QD (14), E/QE (5), F/QF (15), and G/QG (4). : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 323 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS

• Multiplexed I/O Ports Provide Improved Bit Density
• Four Modes of Operation: Hold (Store) Shift Right Shift Left Load Data
• 3-State Outputs Drive Bus Lines Directly
• Can Be Cascaded for n-Bit Word Lengths

409PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. MAX or MIN LS ALS CD74 AC CD74 ACT UNIT MAX 225 40 0.16 0.16 mA IOH QA' or QH' -0.5 -0.4 -24 -24 mA QA thru QH -6.5 -2.6 -24 -24 mA QA' or QH' 68 2 4 24 mA QA thru QH 20 24 24 24 mAIOL MAX PARAMETER ICC MAX INPUT OUTPUT MAX or MIN LS ALS CD74 AC CD74 ACT MIN 25 1 79 59 0 tw CLK 30 16.5 5 .2 5.5 CLR 20 - 5 5 tsu DATA H 20 16 4.5 4.5 DATA L 20 6 4.5 4.5 SELECT - 20 9 9 CLR -2 0 5 .5 5.5 th SELECT - 0 0 0 DAT A 0000 33 15 12.9 12.9 39 18 12.9 12.9 25 13 13.5 14.5 39 19 13.5 14.5 21 16 14.9 14.9 30 22 14.9 14.9 20 8 14.9 14.9 15 15 14.9 14.9 21 16 14.9 14.9 30 22 14.9 14.9 20 8 14.9 14.9 15 15 14.9 14.9 UNIT fmax : MHz, other : ns t PHZ OE2 QA thru QH MAXtPLZ tPZH OE2 QA thru QH MAXtPZL tPHZ OE1 QA thru QH MAXtPLZ tPZH OE1 QA thru QH MAXtPZL tPLH tPHL tPLH fmax PARAMETER CLK CLKtPHL MIN QA' or QB' MAX QA thru QH MAX MIN MIN ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE (SN74) MODE Clear H OUTPUTS QA0Hold L LL H H H H INPUTS L QBn a H H CLR OE1†S1 L L L X SL L H X X X X X CLK X I/O BORD QH0 L L h QGn H/QH QC0 L L QDn c QBn C/QC QA0 L L QCn b QAn B/QB QA0 L L QBn a A/QA H XX H H X LH SELECT L L L L L HH L L L L L X L L X OUTPUT CONTROL OE2† L L L L L L L L X L X SR L H X X X X X X X SEREAL QA' QH0 L L QGn h QGn QH0 QH' QD0 L L QEn d QCn C/QD QE0 L L QFn e QDn C/QE QF0 L L QGn f QEn C/QF QG0 L L QHn g QFn C/QG L H L H L H QBnQDnQCnQBn QEn QFn QGn QHn L H QA0QH0 QGn QC0 QBn QB0 QAn QA0 QD0 QCn QE0 QDn QF0 QEn QG0 QFn Shift Right Shift Left Load † a . . .h = t he level of the steady-state input at inputs A through H, respectively. This data is loaded into the flip-flops while the flip-flop outputsare isolated from the I/O terminals.

A1(7) A0(9) GS(14) A2(6) EO(15) (10) (11) (5) (12) (13) (1) (2) (3) (4) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 348 8-LINE TO 3-LINE PRIORITY ENCODERS WITH 3-STATE OUTPUTS

• 3-State Outputs Drive Bus Lines Directly
• Encodes 8 Data Lines to 3-Line Binary (Octal)

411PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE INPUTS H L 0E1 H X OUTPUTS L X L XL XL XL XL XL L H X L X H X X X X H X L X H X X X X H X L X H X X X H X L X H X X H X L X H X H X L X H H L X HXL X HHHHHH HHHHH HHHH HHH HH H L Z H L H L HHH HH H HH H H GS H L H L H H H H H H H L L L L L L L L L Z Z Z Z Z H H L L L L L L LPARAMETER MAX or MIN LS UNIT MAX 25 mA A0, A1, A2 MAX -2.6 mA E0, ES MAX -0.4 mA A0, A1, A2 MAX 24 mA E0, ES MAX 8 mA ICC IOL IOH PARAMETER INPUT OUTPUT MAX or MIN LS tPLH MAX 35 tPHL MAX 35 tPLH MAX 18 tPHL MAX 40 tPLH MAX 55 tPHL MAX 21 UNIT: ns 0 to 7 0 to 7 GS A0, A1, A21 to 7 ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS412 Logic Diagram (CD74) D A T A R E G I S T E R S O F S E L E C T O R ADDRESS DECODE AR D D R E S S E G I S T E R OE1 OE2 OE3 E LE Y Y BUFFERS ENABLE LOGIC 354 8-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS/TRANSPARENT/REGISTERS WITH 3-STATE OUTPUTS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 413 PARAMETER MAX or MIN LS SN74 HC CD74 HC CD74 HCT UNIT ICC MAX 46 0.08 0.16 0.16 mA IOH MAX -2.6 -6 -6 -4 mA IOL MAX 24 6 6 4 mA PARAMETER INPUT OUTPUT MAX or MIN LS SN74 HC CD74 HC CD74 HCT tsu MAX 15 19 15 15 th MAX 15 5 14 14 tPLH MAX 36 59 63 71 tPHL MAX 35 59 63 71 tPLH MAX 27 59 63 71 tPHL MAX 44 59 63 71 tPLH MAX 42 68 75 81 tPHL MAX 39 68 75 81 tPLH MAX 33 68 75 81 tPHL MAX 50 68 75 81 UNIT:ns DC (CD74: E) DC (CD74: E) D0 thru D7 D0 thru D7 Y W (CD74: Y) Y W (CD74: Y) ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS TRUTH TABLE (CD74) INPUTS OUTPUTS SELECT (NOTE 3) ENABLE DATA OUTPUT ENABLES S2 S1 S0 E OE1 OE2 OE3 Y Y XXXX HXX Z Z XXXX XHX Z Z XXXX XXL Z Z LLLL LLH D 0 D 0 LLL H LLH D 0 n D0n LL H L LLH D 1 D 1 LL H H LLH D 1 n D1n LHLLLLH D 2 D 2 LHLH LLH D 2 n D2n LH HLLLH D 3 D 3 LH H H LLH D 3 n D3n HLLLLLH D 4 D 4 HLLH LLH D 4 n D4n HLHLLLH D 5 D 5 HH HLLL H D 5 n Dn5 HHLLL LH D 6 D 6 HHLHL LH D 6 n D6n HHHLL LH D 7 D 7 HHHHL LH D 7 n D7n H= High Voltage Level (Steady State); L = Low Voltage Level (Steady State); X = Don’t Care; Z= High Impedance State (Off State); D0n...D7n = the level of steady-state inputs D0 through D7, respectively, before the most recent low-to-high transition ofdata control. NOTE: 1. This column shows the input address setup with LE low. OUTPUTS INPUTS X X SELECT† OUTPUT ENABLES L X X X L L L X L L L X X H L L X X L L X L L X H L L X H H L X H H W Z Z Z Y Z Z Z L L LLHH X S2 S1 S0 X X L L H H X L L L H L L L L H HH LL L HH L H H H H L L L L L H HL HL L HL L L H H H LL L L L H HH H LLHH H L L H LLHH H LLH D1n D0n D2n D3n D4n D5n D6n D7nH H H D7n D6n D5n D4n D3n D2n D1n D0n D0L H L H L H L H L H L H L H L H DC FUNCTION TABLE (SN74) NOTES: H = High Voltage Level (Steady State), L = Low Voltage Level (Steady State), X = Don’t Care, Z = High Impedance State (Off State), D0 n ... D7n = the level of steady-state inputs D0 through D7, respectively, before the most recent low-to-high transition of data control. † This column shows the input address setup with LE low.

(CD74) D A T A R E G I S T E R S O F S E L E C T O R ADDRESS DECODE AR D D R E S S E G I S T E R OE1 OE2 OE3 CP LE Y Y BUFFERS ENABLE LOGIC : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 356 8-INPUT MULTIPLEXER/REGISTER, 3-STATE

415PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN LS SN74 HC CD74 HCT UNIT ICC MAX 46 0.08 0.16 mA IOH MAX -2.6 -6 -4 mA IOL MAX 24 6 4 mA PARAMETER INPUT OUTPUT MAX or MIN LS SN74 HC CD74 HCT tsu MIN 15 1 91 1 th MIN 0 5 14 tPLH 27 64 77 tPHL 50 64 77 tPLH 36 64 77 tPHL 27 64 77 tPLH 45 71 89 tPHL 48 71 89 tPLH 54 71 89 tPHL 45 71 89 UNIT: ns D0 thru D7 D0 thru D7 CLK Y S0, S1, S2 S0, S1, S2 W (CD74 : Y ) Y W (CD74 : Y ) CLK MAX MAX MAX MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS OUTPUTS INPUTS X X SELECT† OUTPUT ENABLES L X X X L L L X L L L X X H L L X X L L X L L X H L L X H H L X H H W Z Z Z D1n Y Z Z Z D0n L CLK LL L H D2H X C2 C1 C0 X X L L H H X H or L H or L L L L H H or L L L L L H H D2n D3H LL L H D3nH L H H or L H H H LL L L L H H D4nL HL L H D5L L LH or L H H H L H or L L L L L H H D5n D6H HL L H D6nH H L H or L L H H or L L ↑ LH D7H HL L H D7n D1n D0n D2n D3n D4n D5n D6n D7nH H H FUNCTION TABLE (SN74) NOTES: H = High Voltage Level (Steady State), L = Low Voltage Level (Steady State), = Transition form Low to High Level, X = Don’t Care, Z = High Impedance State (Off State), D0 n ... D7 n = the level of steady-state inputs D0 through D7, respectively, before the most recent low-to-high transition of data control. † This column shows the input address setup with LE low. TRUTH TABLE (CD74) INPUTS OUTPUTS SELECT (NOTE 3) CLOCK OUTPUT ENABLES S2 S1 S0 CP OE1 OE2 OE3 Y Y XH X X Z Z XH X Z Z X X X X X X X X X X X XXLZ Z LLL L H D 0 D 0 LLL H or L H or L H or L H or L H or L H or L H or L LL H D 0 n D0n LL H L H D 1 D 1 LL H LL H D 1 n D1n LHL L H D 2 D 2 LHL LLH D 2 n D2n LH HL H D 3 D 3 LH H LLH D 3 n D3n HLL L H D 4 D 4 HLL LLH D 4 n D4n HLH L H D 5 D 5 HLH LLH D 5 n D5n HHL ↑ L L L L L L L LH D 6 D6 HHL LLH D 6 n D6n ↑HHH LLH D7 D7 H or LHHH LLH D 7 n D7n H = High Voltage Level (Steady State); L = Low Voltage Level (Steady State); ↑ = Transition from Low to High Level; X= Don’t Care; Z = High-Impedance State (Off State); D0n...D7n = the levelof steady-state inputs D0 through D7, respectively,before the most recent low-to-high transition of data control. NOTE: 1. This column shows the input address setup with LE low.

Logic Diagram (SN74) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 365 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS OE1 OE2 To Five Other Channels A1 Y1 PARAMETER MAX or MIN TTL LS SN74 HC CD74 HC CD74 HCT UNIT ICC MAX 85 24 0.08 0.16 0.16 mA IOH MAX -5.2 -2.6 -6 -6 -4 mA IOL MAX 32 24 664 m A PARAMETER INPUT OUTPUT MAX or MIN TTL LS SN74 HC CD74 HC CD74 HCT tPLH MAX 16 15 24 32 38 tPHL MAX 22 18 24 32 38 tPZH MAX 35 35 48 45 53 tPZL MAX 37 45 48 45 53 tPHZ MAX 11 32 48 45 53 tPLZ MAX 27 35 48 45 53 UNIT: ns G Y G (CD74: OE) (CD74: OE) AY Y ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE (SN74) (each buffer/driver) INPUTS OUTPUT OE1 OE2 A Y HXX X Z XH Z LL H H LLL L

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. NOTE: Inverter not included in HC/HCT365. FIGURE 1. LOGIC DIAGRAM FOR THE HC/HCT365 AND HC366 (OUTPUTS FOR HC/HCT365 ARE COMPLEMENTS OF THOSE

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS418 Logic Diagram (SN74) 367 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS 1OE To Three Other Channels 1A1 1Y1 2OE To One Other Channel 2A1 2Y1 12 11 PARAMETER MAX or MIN TTL LS SN74 HC CD74 HC CD74 HCT AHC AHCT LV LV 5V UNIT IOL MAX 32 24 664888 1 6 m A PARAMETER INPUT OUTPUT MAX or MIN TTL LS SN74 HC CD74 HC CD74 HCT AHC AHCT LV LV tPLH MAX 16 16 24 32 38 9 6.5 13.5 9 tPHL MAX 22 22 24 32 38 9 6.5 13.5 9 tPZH MAX 35 35 48 45 53 10.5 9.5 16 10.5 tPZL MAX 47 40 48 45 53 10.5 8.5 16 10.5 tPHZ MAX 11 30 48 45 53 10.5 9.5 15.5 10.5 tPLZ MAX 27 35 48 45 53 10.5 8.5 15.5 10.5 UNIT: ns OE Y AY OE Y ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE (SN74) (each buffer/driver) INPUTS OUTPUT OE A Y HX H Z LH LL L

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 419 Logic Diagram (SN74) 368 HEX INVERTING BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS 1OE To Three Other Channels 1A1 1Y1 2OE To One Other Channel 2A1 2Y1 12 11 PARAMETER MAX or MIN TTL LS SN74 HC CD74 HC CD74 HCT UNIT ICC MAX 77 21 0.08 0.16 0.16 mA IOH MAX -5.2 -2.6 -6 -6 -4 mA IOL MAX 32 24 664 m A PARAMETER INPUT OUTPUT MAX or MIN TTL LS SN74 HC CD74 HC CD74 HCT tPLH MAX 17 15 24 32 45 tPHL MAX 16 18 24 32 45 tPZH MAX 35 35 48 45 53 tPZL MAX 37 45 48 45 53 tPHZ MAX 11 32 48 45 53 tPLZ MAX 27 35 48 45 53 UNIT: ns OE Y OE Y AY ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE (SN74) (each buffer/driver) INPUTS OUTPUT OE A Y HX H Z LL LH L

Logic Diagram (SN74) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

• 3-State Bus-Driving True Outputs
• Buffered Control Inputs
• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) OE To Seven Other Channels LE LE D Q L L L H H L X X H L X H H L Z FUNCTION TABLE (SN74) OUTPUT CONTROL INPUTS OUTPUT PARAMETER MAX or MIN LS S ALS AS F SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 BCT ABT LVTH 3V UNIT ICC MAX 40 190 27 100 55 0.08 0.16 0.08 0.16 60 30 5 mA IOL MAX 24 20 24 48 24 6666 6 4 6 4 6 4 m A PARAMETER MAX or MIN AC SN74 AC CD74 AC ACT SN74 ACT CD74 ACT AHC AHCT LV LV LVC ALVCH 3V UNIT IOH MAX -24 -24 -24 -24 -24 -24 -8 -8 -8 -16 -24 -24 mA IOL MAX 24 24 24 24 24 24 8 8 8 16 LV-AT 0.02 -16 16 24 24 mA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS

421PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. INPUT OUTPUT MAX or MIN LS S ALS AS F SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 BCT ABT tw High MIN 15 6 10 4.5 6 20 24 25 24 7.5 3.3 MIN 5 0 1 02 21 3 1 5 1 3 2 02 1 . 9 MIN 20 10 733 1 2 5 1 0 1 5 5 . 5 1 MAX 18 12 12 6 8 38 45 44 48 9.3 5.9 MAX 18 12 16 6 6 38 45 44 48 9.5 6.2 MAX 30 14 22 11.5 13 44 53 44 53 9.3 6.6 MAX 30 18 23 7.5 8 44 53 44 53 8.8 7.2 MAX 28 15 18 6.5 12 38 45 44 53 11.8 5.2 MAX 36 18 20 9.5 8.5 38 45 44 53 12 6.7 MAX 25 9 10 6 .5 7.5 38 45 44 53 7 6.9 MAX 20 12 12 7 6 38 45 44 53 7.4 6.5 INPUT OUTPUT MAX or MIN LVTH AC SN74 AC CD74 AC ACT SN74 ACT CD74 ACT AHC AHCT LV LV tw High MIN 3 4 4.5 4 5 8 4 5 6.5 5 5 Low MIN - - - 4--4 ---- MIN 1.4 2 1 3 3.5 1 3 1 3.5 1 1 INPUT OUTPUT MAX or MIN LVC ALVCH tw High MIN 3.3 3.3 Low MIN - - MIN 2 0.5 MIN 1.5 1.2 MAX 6.8 3.6 MAX 6.8 3.6 MAX 7.6 3.3 MAX 7.6 3.3 MAX 7.7 4.8 MAX 7.7 4.8 MAX 7 4.4 MAX 7 LV-AT 8.5 1.5 3.5 12.5 12.5 4.4 UNIT fmax : MHz, other : ns t PHZ OE QtPLZ tPZH OE QtPZL tPHL tPLH LE QtPHL PARAMETER tsu th t PLH PARAMETER tPZH tPZL tPHZ tPLZ tPLH tPHL tPHL OE Q Q tsu th tPLH DQ LE Q OE DQ LE DQ PARAMETER tsu th t PLH tPHL tPLH QtPHL tPZH OE QtPZL tPHZ OE QtPLZ TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

Logic Diagram (SN74) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

• Buffered Control Inputs
• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) OE To Seven Other Channels CLK FUNCTION TABLE (SN74) CLK D Q OUTPUT CONTROL INPUTS OUTPUT L L L H H L X X L X H L Z PARAMETER MAX or MIN LS S ALS AS F SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 BCT ABT LVTH 3V UNIT ICC MAX 40 160 31 128 86 0.08 0.16 0.08 0.16 60 30 5 mA IOL MAX 24 20 24 48 24 6666 6 4 6 4 6 4 m A PARAMETER MAX or MIN AC SN74 AC CD74 AC ACT SN74 ACT CD74 ACT AHC AHCT LV LV LVC ALVCH 3V UNIT IOH MAX -24 -24 -24 -24 -24 -24 -8 -8 -8 -16 -24 -24 mA IOL MAX 24 24 24 24 24 24 8 8 8 16 24 24 mA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS

423PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. INPUT OUTPUT MAX or MIN LS S ALS AS F SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 BCT ABT MIN 35 75 35 125 70 24 20 25 20 70 150 tw High MIN 15 6 14 4 7 20 24 20 24 7 3.3 Low MIN 15 7.3 14 3 6 20 24 20 24 - 3.3 MIN 2 051 02 22 5 1 8 2 5 1 8 6 . 5 1 . 9 MIN0 202255 1 0 50 2 . 1 MAX 28 15 12 8 10 4 55 04 55 0 1 0 . 6 6 . 2 MAX 28 17 16 9 10 45 5 04 55 01 0 7 . 1 MAX 26 15 17 6 12.5 38 45 38 45 12.3 5.2 MAX 28 18 18 10 8.5 38 45 38 45 12.7 6.7 MAX 28 9 1 06 83 8 4 1 3 84 2 6.8 6.7 MAX 20 12 18 6 6.5 38 41 38 42 6.8 6.5 INPUT OUTPUT MAX or MIN LVTH AC SN74 AC CD74 AC ACT SN74 ACT CD74 ACT AHC AHCT LV LV MIN 150 95 10 0 12.5 55 90 110 75 75 50 75 INPUT OUTPUT MAX or MIN LVC ALVCH MIN 100 150 tw High MIN 3.3 3.3 Low MIN 3.3 3.3 MIN 2 1.8 MIN 1.5 0.5 MAX 7 3.6 MAX 7 3.6 MAX 7.5 5.2 MAX 7.5 5.2 MAX 6.5 4.5 MAX 6.5 4.5 UNIT fmax : MHz, other : ns t PHZ OE QtPLZ tPZH OE QtPZL tPLH CLK QtPHL PARAMETER fmax tsu th tPLZ tPZL OE Q PARAMETER tPZH tPLH tPHL tsu th fmax tPHZ CLK Q OE Q PARAMETER fmax tsu th t PLH CLK (CD74: CP) (CD74: CP) QtPHL tPZH OE QtPZL tPHZ OE QtPLZ TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS Logic Diagram 424 375 4-BIT BISTABLE LATCHES

• Complementary Outputs (Q, Q) TO OTHER LATCH ENABLE DATA Q Q FUNCTION TABLE CD Q INPUTS OUTPUTS L H X L H H L H H L PARAMETER MAX or MIN LS SN74 HC UNIT ICC MAX 12 0.04 mA IOH MAX -0.4 -4 mA IOL MAX 8 4 mA PARAMETER INPUT OUTPUT MAX or MIN LS SN74 HC tw MIN 20 20 tsu MIN 20 25 th MIN 0 5 t PLH MAX 27 30 tPHL MAX 17 30 tPLH MAX 20 30 tPHL MAX 15 30 tPLH MAX 27 33 tPHL MAX 25 33 tPLH MAX 30 33 tPHL MAX 15 33 UNIT: ns CQ CQ DQ DQ ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 425 1Q1D CLK CLKEN To Seven Other Channels CLKEN 1 3 2 CLK 1D 1Q Logic Diagram (SN74ABT) 377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE

• Individual Data Input to Each Flip-Flop
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) PARAMETER MAX or MIN LS F SN74 HC CD74 HC SN74 HCT CD74 HCT ABT AC

IOH MAX -0.4 -1 -4 -4 -4 -4 -32 -24 mA IOL MAX 82 0 4444 6 4 2 4 m A INPUT OUTPUT MAX or MIN LS F SN74 HC CD74 HC SN74 HCT CD74 HCT ABT AC MIN 30 110 20 20 17 16 150 100 MIN 2 052 5 2 42 53 0 3 . 3 5 tsu DATA MIN 20 2 25 1 81 51 8 2 . 5 4 CLKEN ACTIVE MIN 25 2.5 25 - 15 - 3 6 CL *K E N I N ACTIVE MIN 10 4.5 25 18 15 18 3 6 MIN 515555 1 . 8 0 MAX 27 10 40 53 45 57 6.5 11.3 MAX 27 10.5 40 53 45 57 7.3 12.9 UNI *CD74: E T fmax : MHz, other : ns PARAMETER CLK (CD74: CP) QtPLH tPHL th fmax tw ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS Logic Diagram (SN74HC) FUNCTION TABLE (SN74) CLOCKCLKEN QQ INPUTS OUTPUTS H L X H X L DATA X X HL LL L ↑ H Q0 Q0

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS426 378 HEX D-TYPE FLIP-FLOPS WITH CLOCK ENABLE FUNCTION TABLE CLOCKG QQ INPUTS OUTPUTS H L X H X L DATA X X HL LL L ↑ H Q0 Q0 PARAMETER MAX or MIN LS F SN74 HC UNIT ICC MAX 22 45 0.08 mA IOH MAX -0.4 -1 -4 mA IOL MAX 8 2 04 m A INPUT OUTPUT MAX or MIN LS F SN74 HC MIN 30 110 20 tw CLK H MIN 20 4 25 CLK L MIN 20 6 25 tsu DATA MIN 20 5 25 G ACTIVE MIN 25 3.5 25 G INACTIVE MIN 10 5 25 MIN 5 ↑ 05 MAX 27 6.7 40 MAX 27 6.1 40 UNIT fmax : MHz, other : ns CLK Q fmax th tPLH tPHL PARAMETER ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS Logic Diagram Q ('LS379 ONLY) CLOCK Q Q DCK EN TO 7('LS377) 5('LS378) 3('LS379) OTHER FILIP-FLOPS CK D QENABLE G

427PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram (CD74) nQ0 nQ2 nQ3 3(13) 6(10) 7(9) Q R Φ Q R Φ Q R Φ Q R Φ nQ1 5(11) VCC = 16 GND = 8 4(12) nCP1 1(15) nCP0 2(14) nMR 390 DUAL 4-BIT DECADE COUNTERS

• Individual Clock for A and B Flip-Flops Provide Dual ÷ 2 and ÷ 5 Counters
• All Have Direct Clear for Each 4-Bit Counter
• Typical maximum Count Frequency: 35MHz
• Buffered Outputs Reduce Possibility of Collector Commutation BCD COUNT SEQUENCE FOR 1/2 OUTPUTS L L Q2Q3 COUNT H H FUNCTION TABLE (CD74) L L L L L L L L L L L L H H H H L L H H L L H H L L L H L H L H L H L H BI-QUINARY COUNT SEQUENCE FOR 1/2 OUTPUTS L L Q1Q0 COUNT H H L L L H H H L L L L L H L L H L L L H H L L L H H L L H L L H H L L H L PARAMETER MAX or MIN TTL LS SN74 HC CD74 HC CD74 HCT UNIT ICC MAX 69 26 0.08 0.16 0.16 mA IOH MAX -0.8 -0.4 -4 -4 -4 mA IOL MAX 16 8 4 44 m A INPUT OUTPUT MAX or MIN TTL LS SN74 HC CD74 HC CD74 HCT MIN 25 25 2 52 01 8 MIN2 0 12.5 25 20 18 tw MIN 20 20 2 02 42 9 MIN 25 40 2 02 42 9 *CLR H MIN 20 20 2 01 52 0 MIN 25 25 5 - - MAX 20 2 03 05 36 0 MAX 20 2 03 05 36 0 MAX 60 6 07 2 - 126 MAX 60 6 07 2 - 126 MAX 21 2 13 35 66 5 MAX 21 2 13 35 66 5 MAX 39 3 94 67 48 3 MAX 39 3 94 67 48 3 MAX 21 2 13 35 46 3 MAX 21 2 13 35 46 3 *CLR Q MAX 39 39 41 57 63 UNIT fmax : MHz, other : ns *CD74: MR tPLH fmax tsu tPLH tPHL nCKA (CD74: nCP0) nQA (CD74: nQ0) nCKA (CD74: nCP0)n QC (CD74: nQ2) nCKB (CD74: nCP1) nQB (CD74: nQ1) nQA (CD74: nQP0) nQB (CD74: nQP1) nCKB (CD74: nCP1)n QC (CD74: nQ2) tPHL nCKB (CD74: nCP1) nQD (CD74: nQ3) PARAMETER tPHL tPLH tPHL tPLH tPHL tPLH tPHL nCKA (CD74: nCP0) nCKB (CD74: nCP1) nCKA (CD74: nCP0) nCKB (CD74: nCP1) ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS428 Logic Diagram (SN74)393 DUAL 4-BIT BINARY COUNTERS

• Dual 4-Bit Binary Counter with Individual Clock
• All Have Direct Clear for Each 4-Bit Counter
• Typical maximum Count Frequency: 35MHz
• Buffered Outputs Reduce Possibility of Collector Commutation R T QA CLR CLK R T QB R T QC R T QD Q Q Q Q QB INPUTS L L QCQD COUNT H H QA FUNCTION TABLE (SN74) L L L L L L L L L L L L H H H H L L H H L L H H L L H L H L H L L H L H H H H H H H H H H H L L H H L L H H L H L H L H PARAMETER MAX or MIN TTL LS SN74 HC CD74 HC CD74 HCT LV LV 5V UNIT ICC MAX 64 26 0.08 0.16 0.16 - 0.02 mA IOH MAX -0.8 -0.4 -4 -4 -4 -6 -12 mA IOL MAX 16 84446 1 2 m A INPUT OUTPUT MAX or MIN TTL LS SN74 HC CD74 HC CD74 HCT LV LV MIN 25 2 52 52 01 83 57 5 tw AM I N 2 0 2 0 20 24 29 5 5 BM I N 2 5 40 20 24 29 5 5 CLR H CLK MIN 20 2 02 02 42 4 5 5 MIN 25 25 5 - - 5 4 MAX 20 20 30 59 48 19 12 MAX 20 20 30 59 48 19 12 MAX 60 60 72 86 93 26.5 16.5 MAX 60 60 72 86 93 26.5 16.5 CLR Q MAX 39 39 41 41 48 18 11.5 UNIT fmax : MHz, other : ns CLKA (CD74:nCP) QA CLKB (CD74:nCP) QD tPHL fmax tsu PARAMETER tPLH tPHL tPLH tPHL ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

429PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram (7) (10) R D CLR (6) QD (12) QD' CASCADE OUTPUT (11) Q S CK Q R C CLR (5) QC (13) Q S CK Q R B DATA INPUTS 3-STATE OUTPUTS CLR (4) QB (14) Q S CK Q R A CLR (3) QA (15) Q LD/SH (2) SER (1) CLR (9) OC CLK S CK Q 395 CASCADABLE SHIFT REGISTERS

• 3-State Outputs
• Parallel-In, Parallel-Out Registers
• Low Power Dissipation: 75mW Typical (Enable) FUNCTION TABLE 3-STATE OUTPUTSINPUTS X H LOAD/SHIFT CONTROL SERIAL PARALLEL H L H H HH CLEAR H CASCADE OUTPUT QD H L L L X H X X X X H L L d A X X X a X X B X X X b X X C X X X c X X D X X X d X X QC L QDn QCn d QD0 QD0 QCn QA L QA0 L a QA0 H QB L QBn QAn b QB0 QAn L QCn QBn c QC0 QBn QDO QCn QCn CLOCK QD PARAMETER MAX or MIN LS UNIT MAX 34 mA QA, QB, QC, QD MAX -2.6 mA QD' MAX -0.4 mA QA, QB, QC, QD MAX 24 mA QD' MAX 8 mAIOL ICC IOH INPUT OUTPUT MAX or MIN LS MIN 30 MIN 16 tsu LD/SH MIN 40 OTHER MIN 20 MIN 10 MAX 30 MAX 30 UNIT fmax : MHz, other : ns PARAMETER t PHL CLK Q fmax tw th tPLH ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 399 QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE

• Single-Rail Outputs (Q, Q)
• Select One of Two 4-Bit Data Sources and Stores Data Synchronously with System Clock FUNCTION TABLE CLOCKWORD SELECT QC QD INPUTS OUTPUTS L X QC0L QB B2 D2H QA QD0QA0 QB0 C1 D1 PARAMETER MAX or MIN LS UNIT ICC MAX 13 mA IOH MAX -0.4 mA IOL MAX 8 mA INPUT OUTPUT MAX or MIN LS MIN 20 tsu DATA MIN 25 WORD SELECT MIN 45 th DATA MIN 0 WORD SELECT MIN 0 MAX 27 MAX 32 UNIT: ns CLK Q PARAMETER t PLH tPHL tw ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

431PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram (SN74LS) CLR B A Q Q R Rext/Cext Cext 423 RETRIGGERABLE MONOSTABLE MULTIVIBRATORS

• Will Not Trigger from Clear FUNCTION TABLE (SN74LS) B INPUTS OUTPUTS L X ACLR Q X H H X L L L H X L X X L ↑ H Q H H H PARAMETER MAX or MIN LS CD74 HC CD74 HCT UNIT ICC MAX 20 0.16 0.16 mA IOH MAX -0.4 -4 -4 mA IOL MAX 8 4 4 mA PARAMETER INPUT OU TPUT MAX or MIN LS CD74 HC CD74 HCT tw MIN 4 03 03 0 A (CD74: A) 33 90 90 B4 4 9 09 0 A (CD74: A) 45 96 102 B5 6 9 6 102 tPLH Q MAX 27 65 72 tPHL Q MAX 45 65 72 UNIT: ns CLR (CD74: R) tPLH tPHL MAX MAX Q Q ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS432 442 QUADRUPLE TRIDIRECTIONAL BUS TRANSCEIVERS Logic Diagram B TRANSCEIVERS COMMON CONTROLS A C CS GA GB GC FUNCTION TABLE INPUTS L H X X S1 GA X X X H TRANSFERS BUSESS0 L X H X X X X H X X H X X H GB H GC H None LX HHXH None HX L L H L L H L L H L HHX XLL LXL L X H L X L H L L X H H X L X H L X L H X None L L A → B, A → C L LB → C, B → A L L L L H L L H L L H C → A, C → B A → B B → C C → A L A → C L B → A L C → B None None None CS PARAMETER MAX or MIN LS UNIT ICC MAX 95 mA IOH MAX -15 mA IOL MAX 24 mA PARAMETER INPUT OUTPUT MAX or MIN LS AB o r C BA o r C CA o r B AB o r C BA o r C CA o r B Any G 33 S0, S1 A, B, C 42 CS 36 t PZH G, S, CS A, B, C MAX 32 tPLZ G, S, CS A, B, C MAX 35 tPHZ G, S, CS A, B, C MAX 25 UNIT:ns MAX MAX MAX t PLH tPHL tPZL ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

PARAMETER MAX or MIN LS ALS UNIT ICC MAX 37 33 mA IOH MAX -2.6 -15 mA IOL MAX 24 24 mA PARAMETER INPUT OUTPUT MAX or MIN LS ALS tPLH MAX MAX MAX 15 13 t PHL 18 12 tPZH 40 23 tPZL 45 25 tPHZ 40 10 tPLZ 45 18 UNIT:ns Y G G AY ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS 433 Logic Diagram Logic Diagram PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 465 OCTAL BUFFERS WITH 3-STATE OUTPUTS Y817 Y715 Y613 Y511 Y49 Y37 Y25 Y13 18A8 16A7 14A6 12A5 8A4 6A3 4A2 2A1 19G2 G1 1 † These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 518 OCTAL BINARY/BCD IDENTITY COMPARATORS WITH ENABLE

• Open-Collector Outputs
• 20-kΩ Pullup Resistors on Q Inputs FUNCTION TABLE INPUTS OUTPUT P = Q P > Q ENABLE G DATA P, Q P = Q P < Q X L L HL L H L L PARAMETER MAX or MIN ALS UNIT ICC MAX 17 mA IOL MAX 24 mA VOH MAX 5.5 V PARAMETER INPUT OUTPUT MAX or MIN ALS tPLH 33 tPHL 15 tPLH 33 tPHL 15 UNIT: ns MAX MAX P or Q G P = Q P = Q ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS P = Q G

P = Q G : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 520 OCTAL BINARY/BCD IDENTITY COMPARATORS WITH ENABLE

• 20-kΩ Pullup Resistors on Q Inputs
• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) PARAMETER MAX or MIN ALS F AC

IOH MAX -2.6 -1 -24 mA IOL MAX 24 20 24 mA PARAMETER INPUT OUTPUT MAX or MIN ALS F AC tPLH 12 8.7 12.6 tPHL 20 10.3 11.3 tPLH 12 6.4 7.4 tPHL 22 10 .4 7.8 UNIT: ns MAX MAX P or Q OE P = Q P = Q ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS OUTPUT P = Q P > Q ENABLE G DATA P, Q P = Q P < Q X L L HH L L H H

435PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram P = Q G 521 8-BIT IDENTITY COMPARATORS WITH OPEN-COLLECTOR OUTPUTS

• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) PARAMETER MAX or MIN ALS F AC

ICC MAX 19 32 0.08 mA IOH MAX -2.6 -1 -24 mA IOL MAX 24 20 24 mA PARAMETER INPUT OUTPUT MAX or MIN ALS F AC tPLH 12 11 13 tPHL 20 11 11.4 tPLH 12 7.5 7.9 tPHL 22 10 8.1 UNIT: ns P or Q G P = Q P = Q MAX MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS OUTPUT P = Q P > Q ENABLE G DATA P, Q P = Q P < Q X L L HH L L H H

Logic Diagram (SN74) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS OE LE To Seven Other Channels 533 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

• 3-State Bus-Driving Inverting Outputs
• Functionally Equivalent to '373, Except for Having Inverted Outputs
• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) PARAMETER MAX or MIN ALS AS SN74 HC CD74 HC SN74 HCT CD74 HCT ABT AC SN74 AC ACT SN74 ACT UNIT IOH MAX -2.6 -15 -6 -6 -6 -6 -32 -24 -24 -24 -24 mA IOL MAX 24 48 6666 6 4 2 4 2 4 2 4 2 4 m A PARAMETER INPUT OUTPUT MAX or MIN ALS AS SN74 HC CD74 HC SN74 HCT CD74 HCT ABT AC SN74 AC ACT SN74 ACT tw MIN 15 2 20 24 25 24 3.3 4 5 5 6 tsu MIN 15 2 1 31 51 31 5 2 . 1 3.5 4.5 3.5 4 th MIN 7 3 5 11 5 12 2.1 2 1 3.5 2.5 t tPHL 1373 8 5 04 45 1 6 . 6 8 1 0.5 9.5 11 tPLH 2394 45 34 45 7 7.3 11.3 11.5 13 11.5 tPHL 1884 45 34 45 7 7.3 10.3 11 12.2 11.5 tPZL 18 9.5 38 45 44 53 6.7 9.7 10.5 12 11 tPHZ 10 6.5 38 45 44 45 6.9 11.4 11 12.8 11 tPLZ 1673 84 54 44 5 6.5 8.9 11 10.3 11 UNIT: ns MAX MAX MAX MAX D LE (CD74: LE) OE OE Q Q Q Q ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE (SN74) INPUTS OUTPUT L L DOE Q L H H X XZ L L H ENABLE LE H L X H

Logic Diagram (SN74) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 534 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

• 3-State Bus-Driving Inverting Outputs
• '534 Have Inverted Outputs, But Otherwise Are Functionally Equivalent to '374
• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) OE CLK To Seven Other Channels PARAMETER MAX or MIN ALS AS SN74 HC CD74 HC SN74 HCT CD74 HCT ABT AC SN74 AC CD74 AC ACT SN74 ACT UNIT IOH MAX -2.6 -15 -6 -6 -6 -6 -32 -24 -24 -24 -24 -24 mA IOL MAX 24 48 6 6 6 6 64 24 24 24 24 24 mA INPUT OUTPUT MAX or MIN ALS AS SN74 HC CD74 HC SN74 HCT CD74 HCT ABT AC SN74 AC CD74 AC MIN 35 1 25 25 20 25 16 125 75 140 125 tw CLK "H" 14 4 20 24 20 30 3.5 6.5 4 4 CLK "L" 14 3 20 24 20 30 3.5 6.5 4 4 1022 5 18 25 30 1.6 3.5 4 2 025 5 5 5 2 4.5 1.5 2 1284 5 50 45 53 6.7 11.7 12 11.3 1694 5 50 45 53 7.6 12.1 11 11.3 17 6 38 45 37 53 5 10.4 11.5 14.5 18 10 38 45 37 53 6.8 10.4 11.5 14.5 10 6 38 45 37 45 7.3 11.6 12.5 14.5 14 6 38 45 37 45 6.5 9.2 11 14.5 INPUT OUTPUT MAX or MIN ACT SN74 ACT MIN 55 120 tw CLK "H" 9 3.5 CLK "L" 9 3.5 5.5 1.5 14.5 12.5 15 12 13.3 12.5 13.5 11.5 13.5 13.5 12 10.5 UNIT fmax : MHz, other : ns t PHZ OE Q MAXtPLZ tPZH OE Q MAXtPZL tPLH CLK (CD74: CP) Q MAXtPHL PARAMETER fmax MIN tsu MINth PARAMETER tPHZ tPLZ fmax tsu th t PLH tPHL tPZH tPZL MAX MIN MAX MIN MAX CLK (CD74: CP) OE OE Q Q Q ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE (SN74) INPUTS OUTPUT L L DOE Q L H H X XZ L L H CLK H or L X

Logic Diagram (SN74) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 540 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

• 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
• P-N-P Inputs Reduce D-C Loading
• Schmitt-Triggered Inputs (SN74LS540) OE1 OE2 To Seven Other Channels A1 Y1 21 8 PARAMETER MAX or MIN LS ALS ALS-1 SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 BCT ABT LVTH CD74 AC CD74 ACT AHC UNIT IOH MAX -15 -15 -15 -6 -6 -6 -6 -15 -32 -32 -24 -24 -8 mA IOL MAX 24 24 48 6 6 6 6 64 6 46 42 42 4 8m A PARAMETER MAX or MIN AHCT LV LV LVC 3V UNIT ICC MAX 0.04 - 0.02 0.01 mA IOH MAX -8 -8 -16 -24 mA IOL MAX 8 8 16 24 mA PARAMETER INPUT OUTPUT MAX or MIN LS ALS ALS-1 SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 BCT ABT tPLH 15 12 12 25 33 25 36 6.9 4.8 tPHL 15 9 9 25 33 25 36 4 4.8 tPZH 25 15 15 38 -3 8- 10.1 5.9 tPZL 38 20 20 38 -3 8- 11.3 6.4 tPHZ 25 10 10 38 48 38 53 9 7.3 tPLZ 18 12 12 38 48 38 53 8.5 6.2 PARAMETER INPUT OUTPUT MAX or MIN LVTH CD74 AC CD74 ACT AHC A HCT LV LV LVC tPLH 3.8 68 7.2 8 10 12 8 5.3 tPHL 3.8 68 7.2 8 10 12 8 5.3 tPHZ 5.6 12 13.4 10 12 17.5 10 7.4 tPLZ 51 2 13.4 10 12 17.5 10 7.4 UNIT: ns A OE OE MAX Y (CD74: Y) MAX Y (CD74: Y) MAX Y (CD74: Y) A Y (CD74: Y) MAX OE Y (CD74: Y) MAX OE Y (CD74: Y) MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE (SN74) (each buffer/driver) INPUTS OUTPUT OE1 OE2 A Y LLL H H LL L HX Z X XHX Z

Logic Diagram (SN74) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 541 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

• 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
• P-N-P Inputs Reduce D-C Loading
• Schmitt-Triggered Inputs (SN74LS541) OE1 OE2 To Seven Other Channels A1 Y1 21 8 PARAMETER MAX or MIN LS ALS ALS-1 F SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 BCT ABT LVTH CD74 AC UNIT IOH MAX -15 -15 -15 -15 -6 -6 -6 -6 -15 -32 -32 -24 mA IOL MAX 24 24 48 64 6666 6 4 6 4 6 4 2 4 m A PARAMETER MAX or MIN CD74 ACT AHC AHCT LV LV LVC 3V UNIT IOH MAX -24 -8 -8 -8 -16 -24 mA IOL MAX 24 8 8 LV-AT LV-AT 0.02 -16 1681 6 2 4 m A PARAMETER INPUT OUTPUT MAX or MI NL SA LS ALS-1 F SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 BCT tPLH 15 14 14 6 29 35 29 42 6 tPHL 18 10 10 6 29 3 52 94 2 8 . 2 tPZH 32 15 15 9.5 38 - 38 - 10.7 tPZL 38 20 20 9.5 38 - 38 - 11.5 tPHZ 29 10 10 6.5 38 48 38 53 8.6 tPLZ 18 12 12 6 38 4 83 85 3 8 . 6 PARAMETER INPUT OUTPUT MAX or MIN ABT LVTH CD74 AC CD74 ACT AHC AHCT LV LV LVC tPZH 4 5.2 12 13.4 10.5 12 16 10.5 7 tPHZ 5.8 5.6 12 13.4 10 12 17.5 10 7 tPLZ 4.4 5 12 13.4 10 12 17.5 10 13.5 13.5 7 UNIT: ns MAX A OE OE Y AY MAX MAX Y MAX Y OE Y MAX OE Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE (SN74) (each buffer/driver) INPUTS OUTPUT OE1 OE2 A Y LLL H L LL H HX Z X XHX Z

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 543 OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

• Back-to-Back Registers for Storage
• 3-State True Outputs
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)

441PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. INPUTS OUTPUT CEAB LEAB OEAB A B HX X XZ XX XZ LH X B 0‡ LL H L LL L LL L H H † A-to-B data flow is shown; B-to-A flow control is the same except that it uses CEBA, LEBA, and OEBA. ‡O utput level before the indicated steady-state input conditions were established FUNCTION TABLE† MAX or MIN F SN74 BCT ABT LVTH ACT LVC LVT LVT V UNIT MAX 100 8 0.25 0.19 0.08 0.01 mA MAX 125 71 30 5 0.08 0.01 mA MAX 125 15 0.25 0.19 0.08 0.01 mA A MAX -3 -15 -32 -32 -24 -24 mA B MAX -15 -15 -32 -32 -24 -24 mA A MAX 24 64 64 64 24 24 mA B MAX 64 64 64 0.19 0.19 -32 -32 64 64 24 24 mA PARAMETER I OL ICCH ICCL ICCZ IOH INPUT OUTPUT MAX or MIN F SN74 BCT ABT LVTH ACT LVC tw MIN 57 3 . 5 3.3 4 3.3 LE ↑ before "L" 3.5 4.5 3 1 2.5 1.6 CE ↑ before "H" -- 3 . 5 0 .2 3 1.6 CE ↑ before "L" --3 0 . 7 3 1 . 6 9 8.1 8.4 5.3 10.4 7 8.5 7.2 8 5.3 10.5 7 10 12 6.4 5.3 12.2 8 12 13.5 7.5 5.3 16 8 98 . 5 8.4 5.4 11 7 8.5 7.6 8 5.4 3.3 0.8 0.9 1.7 1.7 1.8 1.8 4.7 4.6 5.9 5.7 5.9 5.7 5.8 6.4 6.5 5.8 6.7 6.4 5.4 11.1 7 UNIT: ns t PHL A or B tPLZ tPZH PARAMETER tPHL tPZH tPZL tPHZ tPLH tPLH tPHL MAX A B MIN MIN MAXB or A LEAB LEBAtPLH MAX OE A or B OE A or B MAX MAX CE A or B MAXtPZL tPHZ CE A or B MAXtPLZ ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

R S R S R S R S CCO RCO QA QB QC QD OE ENT ENP SCLR SLOAD CLK ACLR ALOAD A B C D : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 561 SYNCHRONOUS 4-BIT COUNTERS WITH 3-STATE OUTPUTS

• 3-State Outputs
• Choice of Asynchronous or Synchronous Clearing and Loading
• Internal Look-Ahead Circuitry for Fast Cascading

443PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE ACLROE INPUTS H L L X ALOAD X H X LL L H LH ENP X X X X X LH LH H H H H SCLR X L X X H H H ENT X X X X X H L H X CLK X X X X SLOAD X X X X L H H LH HH XLXH OPERATION Q outputs disabled Asynchronous clear Asynchronous load Synchronous clear Synchronous load Count Inhibit counting Inhibit counting MAX or MIN ALS UNIT MAX 36 mA OUTPUT Q MAX -2.6 mA CCO & RCO MAX -0.4 mA OUTPUT Q MAX 24 mA CCO & RCO MAX 8 mA PARAMETER ICC IOL IOH INPUT OUTPUT MAX or MIN ALS MIN 30 tw 16.5 16.5 tsu H 20 L2 0 L1 5 H3 0 L1 5 H3 0 MIN 0 ACLR Q MAX 22 UNIT fmax : MHz, other : ns t PHL tPLH tPHL tPHL tPHL tPLH tPHL tPLH th tPLH tPHL tPLH A, B, C, D SCLR SLOAD PARAMETER fmax CLK "H" CLK "L" ENP or ENT CLK CLK ALOAD ALOAD ENT RCO CCO Q RCO Q MAX MAX MIN MAX MAX MAX MIN ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

Logic Diagram (SN74) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS OE LE To Seven Other Channels 563 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

• 3-State Buffer-Type Outputs Drive Bus Lines Directly
• Bus-Structured Pinout FUNCTION TABLE (SN74) INPUTS OUTPUT L L DOE Q L H H X XZ L L H ENABLE LE H L X H PARAMETER MAX or MIN ALS SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 AC CD74 AC SN74 ACT UNIT IOH MAX -2.6 -6 -6 -6 -6 -24 -24 -24 mA IOL MAX 24 6666 2 4 2 4 2 4 m A PARAMETER INPUT OUTPUT MAX or MIN ALS SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 AC CD74 AC SN74 ACT tw 15 20 24 25 24 5 4 3 tsu 10 13 1 51 31 5 2 .5 2 4.5 th 10 54 1 0 5230 tPLH 18 44 45 44 45 11.5 10.5 12.5 tPHL 14 44 45 44 45 11 10.5 11 tPLH 22 44 50 44 53 11 12 11.5 tPHL 21 44 50 44 53 9.5 12 10.5 tPZH 18 38 45 44 53 10 10.5 10 tPZL 18 38 45 44 53 9.5 10.5 9.5 tPHZ 10 38 45 44 53 12 11.5 11.5 tPLZ 15 38 45 44 53 9 11.5 8.5 UNIT: ns OE Q OE Q MAX Q Q MAX MIN MAX MAX D LE (CD74: LE) ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

Logic Diagram (SN74) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 564 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

• 3-State Buffer-Type Inverting Outputs Drive Bus Lines Directly
• Bus-Structured Pinout OE CLK To Seven Other Channels FUNCTION TABLE (SN74) INPUTS OUTPUT L L DOE Q L H H X XZ L L H CLK L X PARAMETER MAX or MIN ALS SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 AC SN74 ACT UNIT IOH MAX -2.6 -6 -6 -6 -6 -24 -24 mA IOL MAX 24 6 6 6 6 24 24 mA PARAMETER INPUT OUTPUT MAX or MIN ALS SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 AC SN74 ACT fmax MIN 30 25 20 25 16 85 75 tw CLK "H" 14 20 24 20 30 53 . 5 CLK "L" 14 20 24 20 30 5 3.5 tsu CLK ↑ 15 25 18 25 30 2.5 3 th CLK ↑ 05 5 5 3 21 tPLH 14 45 50 45 53 11.5 11.5 tPHL 14 45 50 45 53 10.5 10.5 tPZH 18 38 45 38 53 9.5 9.5 tPZL 18 38 45 38 53 9.5 9.5 tPHZ 10 38 41 38 45 11.5 11.5 tPLZ 15 38 41 38 45 9 8.5 UNIT fmax : MHz, other : ns OE OE CLK Q Q Q MAX MAX MIN MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

R R R R CCO RCO QA QB QC QD OE U/D CLK ENT ENP SCLR LOAD ACLR A B C D : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 569 SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS WITH 3-STATE OUTPUTS

• 3-State Q Outputs Drive Bus Lines Directly
• Fully Synchronous Clear, Count, and Load
• Asynchronous Clear Is Also Provided
• Fully Cascadable

447PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE ACLROE H L L X SCLR X H X LL L H LH U/D X X X X H LH LH H H H H LOAD X L X X H H H ENP X X X X L L X L X CLK X X X ENT X X X X L L H LH HHH X X X INPUTS Q outputs disabled Asynchronous clear Synchronous clear Load Count up Count down Inhibit count Inhibit count OPERATION MAX or MIN ALS UNIT ICC MAX 32 mA IOH OUTPUT Q -2.6 mA CCO & RCO -0.4 mA IOL OUTPUT Q 24 mA CCO & RCO 8m A PARAMETER MAX MAX INPUT OUTPUT MAX or MIN ALS fmax MIN 30 tw 15 16.5 16.5 tsu 20 High 30 Low 20 High 15 Low 30 High 15 Low 30 th MIN 0 ACLR Q MAX 20 UNIT fmax : MHz, other : ns PARAMETER ACLR, LOAD MINCLK "H" CLK "L" Data at A, B, C, D MIN ENP, ENT SCLR LOAD UD ACLR t PLH CLK AN Y Q MAXtPHL tPLH RCO MAXtPHL CLK tPHL tPLH RCO MAXtPHL ENT MAXtPZL tPHZ OE Q MAXtPLZ tPZH OE Q ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

Logic Diagram (SN74) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

• 3-State Buffer-Type Outputs Drive Bus Lines Directly
• Bus-Structured Pinout OE To Seven Other Channels LE FUNCTION TABLE (SN74) INPUTS OUTPUT L L DOE Q L H H X XZ L H L ENABLE LE H L X H PARAMETER MAX or MIN ALS AS F SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 BCT ABT LVTH SN74 AC CD74 AC UNIT IOH MAX -2.6 -15 -3 -6 -6 -6 -6 -15 -32 -32 -24 -24 mA IOL MAX 24 48 24 6666 6 4 6 4 6 LVT -32 64 4 2 42 4 m A PARAMETER MAX or MIN SN74 ACT CD74 ACT AHC AHCT LV LV LVC 3V UNIT IOH MAX -24 -24 -8 -8 -8 -16 -24 mA IOL MAX 24 24 8 8 8 16 24 m LV-AT 0.02 -16 16 A ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS

449PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. INPUT OUTPUT MAX or MIN ALS AS F SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 BCT tw LE 10 4.5 6 20 2 42 52 4 4 tsu LE ↓ MIN 10 2 21 3 1 51 32 0 1 th LE ↓ 7335 1 2 5 1 5 4 tPLH 14 8 8 44 53 44 53 8.4 tPHL 14 7 6 44 53 44 53 9.6 tPLH 20 13 13 44 53 44 53 8.1 tPHL 19 7.5 8 44 5 34 45 3 7 . 8 tPZH 18 6.5 12 38 45 44 53 10.4 tPZL 18 9.5 8.5 38 4 54 45 31 1 tPHZ 10 6.5 7.5 38 4 54 45 3 6 tPLZ 15 7 6 38 45 44 53 6 INPUT OUTPUT MAX or MIN ABT LVTH LVT 3V V SN74 AC CD74 AC SN74 ACT CD74 ACT AHC AHCT tw LE 3. 33 5 4 445 3.5 th LE ↓ 1.8 1.5 2 3 0 3 1.5 1.5 7.5 tPHL 6.2 3.9 11 8.5 12 10.4 10 tPLH 6.6 4.2 11 12 12 12.5 11 8.5 tPHL 7.2 4.2 10 12 10.5 12.5 11 tPZH 5.2 5.1 10 10.5 11 13.5 11 tPLZ 6.5 3.3 0.7 1.6 4.2 4.3 5.6 6.5 5.1 5.5 5.7 10.5 INPUT OUTPUT MAX or MIN LV LV LVC tw LE 55 3.3 tsu LE ↓ MIN 3.5 3.5 2 th LE ↓ 1.5 1.5 1.5 tPLH 16.5 10 6.9 tPHL 16.5 10 6.9 tPLH 17.5 11 7.7 tPHL 17.5 11 7.7 tPZH 17 11 7.5 tPZL 17 11 7.5 tPHZ 16.5 11 6.5 tPLZ 16.5 11 LV-AT 8.5 1.5 3.5 10.5 10.5 14.5 14.5 13.5 13.5 12 6.5 UNIT: ns MAX PARAMETER OE OE LE D PARAMETER DQ Q Q Q Q MAX MAX MAX MAX LE (CD74AC/ACT: LE) Q MAX Q MAX OE Q MAX OE PARAMETER DQ MAX LE (CD74AC/ACT: LE) Q MAX OE Q MAX OE Q MAX TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

Logic Diagram (SN74) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

• 3-State Buffer-Type Noninverting Outputs Drive Bus Lines Directly
• Bus-Structured Pinout OE CLK To Seven Other Channels FUNCTION TABLE (SN74) INPUTS OUTPUT L L DOE Q L H H X XZ L H L CLK L X PARAMETER MAX or MIN ALS AS F SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 BCT ABT LVTH SN74 AC UNIT IOH MAX -2.6 -15 -3 -6 -6 -6 -6 -15 -32 -32 -24 mA IOL MAX 24 48 24 6666 6 4 6 4 6 4 2 4 m A PARAMETER MAX or MIN CD74 AC SN74 ACT CD74 ACT AHC AHCT LV LV LVC 3V UNIT IOH MAX -24 -24 -24 -8 -8 -8 -16 -24 mA IOL MAX 24 24 24 8 8 8 16 24 mA LVT -32 ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS

451PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. INPUT OUTPUT MAX or MIN ALS AS F SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 BCT fmax MIN 35 125 100 24 20 24 20 77 tw MIN 14 5.5 7 2 02 42 02 4 6 . 5 tsu MIN 15 5.5 2 2 51 82 51 8 6 th MIN 00255550 tPLH 1481 0 4 55 04 55 01 0 tPHL 1491 0 4 55 04 55 0 8 . 9 tPZH 18 6 12.5 38 45 38 45 10.4 tPZL 18 10 8.5 38 45 38 45 10.9 tPHZ 10 6 8 38 41 38 42 7.5 tPLZ 12 6 6.5 38 41 38 42 6.4 INPUT OUTPUT MAX or MIN ABT LVTH LVT 3V V SN74 AC CD74 AC SN74 ACT CD74 ACT AHC AHCT fmax MIN 150 150 85 125 85 110 75 tw MIN 3.3 3.3 5 4 4 4.5 5 5.5 tsu MIN 1.5 222 2 . 5 23 3.5 th MIN 1.8 0.3 1.5 2 1 3 1.5 1.5 tPLH 6.8 4.5 11 10.8 12 11.2 12 12.5 12.5 11.5 11.5 INPUT OUTPUT MAX or MIN LV LV LVC fmax MIN 45 75 150 tw MIN 5 5 3.3 tsu MIN 3.5 3.5 2 th MIN 1.5 1.5 1.5 tPLH 19 12 7 tPHL 19 12 7 tPZH 18.5 12.5 7.5 tPZL 18.5 12.5 7.5 tPHZ 17 11.5 6.4 tPLZ 17 11.5 6.4 UNIT fmax : MHz, other : ns PARAMETER MAXQ Q PARAMETER CLK (CD74: CP) OE MAX Q MAX OE Q MAX PARAMETER OE Q MAX OE Q MAX OE Q MAX CLK (CD74: CP) Q MAX OE Q MAX 150 3.3 0.3 5.4 5.9 4.8 5.1 5.5 4.5 CLK (CD74: CP) TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 575 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

• 3-State Buffer-Type Noninverting Outputs Drive Bus Lines Directly
• Bus-Structured Pinout
• Synchronous Clear OE CLK To Seven Other Channels CLR FUNCTION TABLE INPUTS OUTPUT L L DOE Q L L X L X L H L H CLK L L H CLR H H H XZXX PARAMETER MAX or MIN ALS AS UNIT ICC MAX 30 142 mA IOH MAX -2.6 -15 mA IOL MAX 24 48 mA INPUT OUTPUT MAX or MIN ALS AS fmax MIN 30 90 tw CLK H 5.5 CLK L 5.5 tsu 5.5 CLR L 6.5 th 3 tPLH 14 8 tPHL 14 9 tPZH 18 6 tPZL 18 10 tPHZ 10 6 tPLZ 13 6 UNIT fmax : MHz, other : ns MIN 16.5 MAXQCLK Q MAX Q MAX DATA DATA CLR PARAMETER OC OC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 576 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

• 3-State Buffer-Type Inverting Outputs Drive Bus Lines Directly
• Bus-Structured Pinout
• Functionally Equivalent to '576, Except for Having Inverted Outputs OE CLK To Seven Other Channels FUNCTION TABLE INPUTS OUTPUT L L DOE Q L H H X XZ L L H CLK L X PARAMETER MAX or MIN ALS AS UNIT ICC MAX 30 135 mA IOH MAX -2.6 -15 mA IOL MAX 24 48 mA INPUT OUTPUT MAX or MIN ALS AS fmax MIN 30 125 tw 4 tsu 15 2 th 02 tPLH 14 8 tPHL 14 9 tPZH 18 6 tPZL 18 10 tPHZ 10 6 tPLZ 15 6 UNIT fmax : MHz, other : ns Q Q 16.5 CLK MIN MAXQ OE MAX MAX DATA OE PARAMETER H L DATA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 577 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

• 3-State Buffer-Type Inverting Outputs Drive Bus Lines Directly
• Bus-Structured Pinout
• Synchronous Clear OE CLK To Seven Other Channels CLR FUNCTION TABLE INPUTS OUTPUT L L DOE Q L L X L X H H H L CLK L L H CLR H H HX Z XX PARAMETER MAX or MIN ALS AS UNIT ICC MAX 30 142 mA IOH MAX -2.6 -15 mA IOL MAX 24 48 mA INPUT OUTPUT MAX or MIN ALS AS fmax MIN 30 125 tw 16.5 4 tsu DATA MIN 15 2 th CLR 02 tPLH 14 8 tPHL 14 9 tPZH 18 6 tPZL 18 10 tPHZ 10 6 tPLZ 15 6 UNIT fmax : MHz, other : ns MAX MAX MAX Q Q Q PARAMETER CLK OE OE ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 580 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

• 3-State Buffer-Type Outputs Drive Bus Lines Directly
• Inverting-Logic Outputs
• Bus-Structured Pinout OE LE To Seven Other Channels FUNCTION TABLE INPUTS OUTPUT L L DOE LE Q L H H X XZ L L H ENABLE H L X H PARAMETER MAX or MIN ALS AS UNIT ICC MAX 29 115 mA IOH MAX -2.6 -15 mA IOL MAX 24 48 mA INPUT OUTPUT MAX or MIN ALS AS tw C 15 2 tsu C ↓ MIN 10 2 th C ↓ 10 3 tPLH 18 7.5 tPHL 14 7 tPLH 22 9 tPHL 21 8 tPZH 18 6.5 tPZL 18 9.5 tPHZ 10 6.5 tPLZ 15 7 UNIT: ns DQ MAX LE Q MAX OE Q MAX OE Q MAX PARAMETER ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

T R T R T R T R T R T R T R T R OE RCLK CCKEN CCLK CCLR RCO QA QB QC QD QE QF QG QH : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 590 8-BIT BINARY COUNTERS WITH 3-STATE OUTPUT REGISTERS

• Parallel Register Outputs
• Counter Has Direct Clear
• 3-State Outputs
• Guaranteed Counter Frequency: DC to 20MHz

457PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. MAX or MIN LS SN74 HC UNIT ICC MAX 65 0.08 mA RCO MAX -1 -4 mA Q MAX -2.6 -6 mA RCO MAX 16 4 mA Q MAX 24 6 mA PARAMETER IOH IOL INPUT OUTPUT MAX or MIN LS SN74 HC fmax CCK RCO MIN 20 13 tw CCK 25 31 CCLR MIN 20 25 RCK 20 31 tsu CCLR ↑ bofore CCK ↑ CCK ↑ bofore RCK ↑ tPLH 22 45 tPHL 30 45 tPLH CCLR ↓ RCO MAX 45 39 tPLH 18 42 tPHL 33 42 tPZH 38 37 tPZL 45 37 tPHZ 30 37 tPLZ 38 37 UNIT fmax : MHz, other : ns QOE ↓ OE ↓ RCK ↑ Q Q MAX MAX MAX MAX MIN CCK ↑ RCO PARAMETER ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

S R T RCO(9) S R T S R T S R T S R T S R T S R T S R T CCLR (10) (12) (11) (14) CCKEN CCK CLOAD RCK (13) A (15) B (1) C (2) D (3) E (4) F (5) G (6) H (7) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 592 8-BIT BINARY COUNTERS WITH INPUT REGISTERS

• Parallel Register Inputs
• Counter Has Directly Overriding Load and Clear
• Accurate Counter Frequency: DC to 20MHz

459PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN LS UNIT ICC MAX 60 mA IOH MAX -1 mA IOL MAX 16 mA INPUT OUTPUT MAX or MIN LS fmax CCK RCO MIN 20 tw CCK 25 CCLR 20 RCK 20 CLOAD 40 tsu CCLR ↑ bofore CCK ↑ CLOAD ↑ bofore CCK ↑ RCK ↑ bofore CLOAD ↑ A to H bofore RCK th MIN 0 t PLH 23 tPHL 30 tPLH 47 tPHL 17 tPLH CCLR ↓ RCO MAX 45 tPLH 53 tPHL 45 UNIT fmax : MHz, other : ns MIN MAX MAX MAX MIN PARAMETER RCO RCO RCO Q CCK CLOAD ↓ RCK ↑ ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

S R T RCO(11) Gating for RCK is similar in detail to that shown for CCK. S R T S R T S R T S R T S R T S R T S R T CCLR G G (12) (15) (19) (18) (14) (13) (9) CCKEN CCKEN CCK CLOAD RCKEN RCK (17) (16) A/Q A (1) B/QB (2) C/QC (3) D/QD (4) E/QE (5) F/QF (6) G/QG (7) H/QH (8) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 593 8-BIT BINARY COUNTERS WITH INPUT REGISTERS

• Parallel 3-State I/O: Register Inputs/Counter Outputs
• Counter Has Directly Overriding Load and Clear
• Accurate Counter Frequency: DC to 20MHz
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)

461PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. MAX or MIN LS ACT ICC MAX 85 0.08 mA RCO MAX -1 -24 mA Q MAX -2.6 -24 mA RCO MAX 16 24 mA Q MAX 24 24 mA PARAMETER IOH IOL INPUT OUTPUT MAX or MIN LS ACT fmax CCK RCO MIN 20 52 tw CCK 25 9.6 CCLR 20 7.6 RCK 20 5.8 CLOAD 40 6.2 tsu CCLR ↑ bofore CCK ↑ CLOAD ↑ bofore CCK ↑ RCK ↑ bofore CLOAD ↑ A to H bofore RCK th MIN 0 0.8 t PLH 21 15.1 tPHL 39 15 tPLH 51 19.1 tPHL 42 21.7 tPHL CCLR ↓ Q MAX 38 16 UNIT fmax : MHz, other : ns CLOAD ↓ CCK ↑ MIN MIN MAX MAX Q Q 20 1.2 5.120 30 7.4 2.420 PARAMETER ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

R R R R R R R R R R R R R R R R 14 15 QA QB QC QD QE QF QG QH QH′ RCLR SRCLR RCLK SRCLK SER Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 594 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS

• 8-Bit Serial-In, Parallel-Out Shift Registers with Storage
• Independent Direct Overriding Clears on Shift and Storage Registers
• Independent Clocks for Shift and Storage Registers
• Guaranteed Shift Frequency: DC to 20MHz

463PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. MAX or MIN LS SN74 HC AHC AHCT LV LV 5V UNIT ICC MAX 65 0.08 0.04 0.02 - 0.02 mA QH' MAX -1 -4 -4 -4 -6 -12 mA Q MAX -2.6 -6 -8 -8 -6 -12 mA QH' MAX 16 4 4 4 6 12 mA QA to QH MAX 24 6 8 8 6 12 mA PARAMETER IOH IOL INPUT OUTPUT MAX or MIN LS SN74 HC AHC AHCT LV LV tw SRCK 25 20 5 5.5 5.5 5 RCK 20 20 5 5 .5 5.5 5 tsu SRCLR ↑ to SRCK ↑ 20 10 3.3 3 .3 4.8 3.3 SER to SRCK ↑ 20 22 3 3 3.5 3 SRCK ↑ to RCK ↑ 40 22 5 5 8.5 5 SRCLR ↓ to RCK ↑ 40 13 5595 RCLR ↑ to RCK ↑ 20 5 3.7 3.8 5.3 3.7 th MIN 0522 1 . 5 2 tPLH 18 37 9.1 9.1 12.4 9.1 tPHL 23 37 10.1 10.1 13.9 10.1 tPLH 18 37 8.3 8.3 11.1 8.3 tPHL 30 37 9.7 9.7 13.1 9.7 tPHL SRCLR ↓ QH' 33 37 10.1 10.1 14 10.1 tPHL RCLR ↓ QA to QH 57 31 10.7 10.7 14.4 10.7 UNIT: ns MAX QA to QH QH' MIN MIN PARAMETER SRCK ↑ RCK ↑ MAX MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUTS FUNCTION SER SRCLK SRCLR RCLK RCLR FUNCTION XX LX X Shift register is cleared. LH X X First stage of shift register goes low. Other stages store the data of previous stage, respectively. HH X X First stage of shift register goes high. Other stages store the data of previous stage, respectively. LH X X Shift register state is not changed. XX XX L Storage register is cleared. XX X H Shift register data is stored in the storage register. XX X H Storage register state is not changed. FUNCTION TABLE

R R R R R R R R QA QB QC QD QE QF QG QH QH′ OE SRCLR RCLK SRCLK SER Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS

• 8-Bit Serial-In, Parallel-Out Shift Registers with Storage
• 3-State Outputs
• Shift Register Has Direct Clear
• Accurate Shift Frequency: DC to 20MHz

465PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. MAX or MIN LS SN74 HC AHC AHCT LV LV 5V UNIT ICC MAX 65 0.08 0.04 0.04 - 0.02 mA QH' MAX -1 -4 -8 -8 -8 -16 mA QA to QH MAX -26 -6 -8 -8 -8 -16 mA QH' MAX 16 4 8 881 6 m A QA to QH MAX 24 6 CD74 HC 0.16 6888 1 6 m A PARAMETER I OH IOL INPUT OUTPUT MAX or MIN LS CD74 HC AHC AHCT LV LV tw SRCK 25 20 5 5.5 5.5 5 RCK 20 20 5 5 .5 5.5 5 tsu SRCLR ↑ to SRCK ↑ 20 12 2.5 3 .8 3 2.5 SER to SRCK ↑ 20 25 3 3 3.5 3 SRCK ↑ to RCK ↑ 40 19 5 5 8.5 5 SRCLR ↓ to RCK ↑ 40 13 5 5 9 5 th MIN 0 0 2 2 1.5 2 tPLH 18 48 11.4 11.4 18.5 11.4 tPHL 25 48 11.4 11.4 18.5 11.4 tPLH 18 45 10.5 10.5 17 10.5 tPHL 35 45 10.5 10.5 17 10.5 tPHL SRCLR ↓ QH' MAX 35 44 SN74 HC 44 11.1 11.1 17.2 11.1 UNIT: ns MAXRCK ↑ QA to QH QH' PARAMETER MIN MAXSRCK ↑ MIN ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUTS SER SRCLK SRCLR RCLK OE XX XX HO utputs QA-QH are disabled. XX XX LO utputs QA-QH are enabled. XX LX X Shift register is cleared. LH X X First stage of the shift register goes low. Other stages store the data of previous stage, respectively. HH X X First stage of the shift register goes high. Other stages store the data of previous stage, respectively. XH XX Shift-register state is not changed. XX Shift-register data is stored in the storage register. XX X XX X Storage-register state is not changed. FUNCTION FUNCTION TABLE

(1) R QA (15) QC (2) R QD (3) R QE (4) R QF (5) R QG (6) R QH (7) QH' (9) R SRCK SRCLR RCK G (14) (11) (10) (12) (13) R : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 596 8-BIT SHIFT REGISTERS WITH OUTPUT LATCHES

• 8-Bit Serial-In, Parallel-Out Shift Registers with Storage
• Open-Collector Parallel Outputs
• Shift Register Has Direct Clear
• Accurate Shift Frequency: DC to 20MHz

467PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. MAX or MIN LS UNIT ICC MAX 55 mA QH' MAX 16 mA Q MAX 24 mA IOL QH' MAX -1 mA VOH QA to QH MAX 5.5 V PARAMETER IOH INPUT OUTPUT MAX or MIN LS tw SRCK 25 RCK 20 tsu SRCLR ↑ to SRCK ↑ SER to SRCK ↑ SRCK ↑ to RCK ↑ SRCLR ↓ to RCK ↑ th MIN 0 tPLH 21 tPHL 30 tPLH 42 tPHL 35 tPHL SRCLR ↓ QH' MAX 35 UNIT: ns RCK ↑ MIN MIN MAX MAX PARAMETER QA to QH QH'SRCK ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

Logic Diagram (SN74LS) QH'(9) A RCK SRLOAD (15) (12) SER (14) (13) SRCK (11) SRCLR (10) S R B (1) 1D S R C (2) 1D S R D (3) 1D S R E (4) 1D S R F (5) 1D S R G (6) 1D S R H (7) 1D S R : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 597 SERIAL-OUT SHIFT REGISTERS WITH INPUT LATCHES

• 8-Bit Parallel Storage Registers Inputs
• Shift Register Has Direct Overriding Load and Clear
• Accurate Shift Frequency: DC to 20MHz

469PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN LS CD74 HC CD74 HCT UNIT ICC MAX 53 0.16 0.16 mA IOH MAX -1 -4 -4 mA IOL MAX 16 4 4 mA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS PARAMETER INPUT OUTPUT MAX or MIN LS CD74 HC CD74 HCT SRCK Q MIN 20 -- SRCK QH' MIN 20 -- MIN - 20 16 MIN 15 - - MIN 35 - - MIN 20 - - MIN 20 - - MIN 40 - - MIN - 20 30 MIN - 15 20 MIN - 20 27 MIN - 18 24 MIN 20 - - MIN 25 - - MIN 30 - - MIN 40 - - MIN 20 - - MIN - 30 36 MIN - 15 15 MIN - 15 15 0-- -00 - 33 -33 t PLH 23 - - tPHL 23 - - tPLH 57 - - tPHL 44 - - tPHL SRCLR ↓ QH' MAX 36 - - tPLH 60 - - tPHL 48 - - tPLH -5 3 5 7 tPHL -5 3 5 7 tPLH -6 0 7 2 tPHL -6 0 7 2 tPLH -7 2 8 4 tPHL -7 2 8 4 tPLH -5 3 6 6 tPHL -5 3 6 6 UNIT fmax : MHz, other : ns fmax tw tsu SRCK low RCK SRCLR SRLOAD SHCP SRLOAD inactive before SRCK ↑ RCK ↑ brfore SRLOAD ↑ SHCP SRCK high Data before RCK ↑ LS597 only STCP MR PL SRCLR inactive beforeSRCK ↑ SER before SRCK ↑ STCP to SHCP Ds to SHCP Dn to STCP QH' Dn to STCP th MINSTCP to SHCP Ds to SHCP MAX SRCK ↑ QH' MAX SHCP Q7 MAX SRLOAD ↓ QH' RCK ↑ MAX MAX MR Q7 MAX PL Q7 MAX ST CP Q7

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS470 598 8-BIT SHIFT REGISTERS WITH INPUT LATCHES Logic Diagram QH'(11) A/QA RCK SRLOAD (1) (15) DS (19) SER1 (17) SER0 (18) (9) SRCK (13) SRCLR (12) S R B/QB (2) 1D S R C/QC (3) 1D S R D/QD (4) 1D S R E/QE (5) 1D S R F/QF (6) 1D S R G/QG (7) 1D S R H/QH (8) 1D S R G (16) SRCKEN (14)

471PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN LS UNIT ICC MAX 85 mA IOH MAX -2.6 mA IOL MAX 24 mA PARAMETER INPUT OUTPUT MAX or MIN LS SRCK Q MIN 20 SRCK QHB MIN 20 MIN 15 MIN 35 MIN 20 MIN 20 MIN 40 MIN 20 MIN 30 MIN 20 MIN 25 MIN 30 MIN 40 MIN 20 t h MIN 0 tPLH 17 tPHL 23 tPLH 42 tPHL 39 tPHL SRCLR ↓ QHB MAX 27 tPLH 48 tPHL 36 tPLH 18 tPHL 28 UNIT fmax : MHz, other : ns SRCK high Data before RCK ↑ SRCLR inactive beforeSRCK ↑ SRCK low RCK SRCLR SRLOAD MAXSHCP Q7 RCK ↑ QHB fmax tw tsu MAX SRLOAD ↓ QHB MAX DS before RCK ↑ SRLOAD inactive before SRCK ↑ SRCKEN iow before SRCK ↑ SRCK ↑ QHB MAX RCK ↑ brfore SRLOAD ↑ SER before SRCK ↑ ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 620 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

• Local Bus-Latch Capability
• 3-State Inverting Outputs
• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) To Seven Other Channels 21 8 OEBA OEAB PARAMETER MAX or MIN LS ALS ALS-1 AS SN74 HC SN74 BCT ABT AC ACT

ICCZ MAX 95 47 47 77 0.08 10 0.25 0.08 0.008 mA ICCL MAX 90 44 44 122 0.08 84 30 0.08 0.008 mA IOH (A port) MAX -15 -15 -15 -15 -6 -3 -32 -24 -24 mA IOH (B port) MAX -15 -15 -15 -15 -6 -15 -32 -24 -24 mA IOL (A port) MAX 24 24 48 64 6 24 64 24 24 mA IOL (B port) MAX 24 24 48 64 6 64 64 24 24 mA PARAMETER INPUT OUTPUT MAX or MIN LS ALS ALS-1 AS SN74 HC SN74 BCT ABT AC ACT tPLH 10 10 10 7 26 5 .8 4.8 7.4 9.4 tPHL 15 10 10 6 26 3 .6 4.8 7.1 8.6 tPLH 10 10 10 7 26 6 .9 4.8 7.4 9.4 tPHL 15 10 10 6 26 3 .9 4.8 7.1 8.6 tPZH 40 17 17 85 31 0.6 5.5 8.9 10.3 tPZL 40 25 25 95 31 1.1 7.1 8.5 10.1 tPHZ 25 12 12 63 81 07 8.1 10.4 tPLZ 25 18 18 12 38 7.8 5.8 8.7 10.9 tPZH 40 18 18 8 53 7.4 6.8 8.8 11.3 tPZL 40 25 25 9 53 9 6.4 8.8 11 tPHZ 25 12 12 6 38 8 .1 6.5 8.2 9.4 tPLZ 25 18 18 13 38 5.9 5.6 8.6 9.6 UNIT: ns A B OEBA OEBA OEAB OEAB B B A B MAX MAX MAX MAX MAX MAX A A ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE ENABLE INPUTS OPERATION L H OEBA H L L L H H B data to Abus A data to B bus B data to Abus Isoration A data to B bus OEAB

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 621 OCTAL BUS TRANSCEIVERS

• Local Bus-Latch Capability
• Open-Collector True Outputs
• Schmitt-Triggered Inputs (SN74LS621) To Seven Other Transceivers OEBA OEAB PARAMETER MAX or MIN LS ALS ALS A-1 AS UNIT ICC MAX 90 48 48 189 mA VOH MAX 5.5 5.5 5.5 5.5 V IOL MAX 24 24 48 64 mA PARAMETER INPUT OUTPUT MAX or MIN LS ALS ALS A-1 AS tPLH 25 33 33 24 tPHL 25 20 20 21 tPLH 25 33 33 7.5 tPHL 25 20 20 7.5 tPLH 40 39 39 21 tPHL 50 35 35 9 tPLH 40 39 39 22 tPHL 50 35 35 10 UNIT: ns B MAX B A A MAX MAX MAX A B OEBA OEAB ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE ENABLE INPUTS OPERATION L H OEBA H L L L H H B data to Abus A data to B bus B data to Abus Isoration A data to B bus OEAB

Logic Diagram (SN74) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 623 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

• Local Bus-Latch Capability
• 3-State True Outputs
• Schmitt-Triggered Inputs (SN74LS623)
• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) A1 B1 OEBA OEAB To Seven Other Channels 21 8 PARAMETER MAX or MIN LS ALS AS F SN74 HC SN74 HCT SN74 BCT ABT AC ACT CD74 AC CD74 ACT UNIT IOH (A port) MAX -15 -15 -15 -3 -6 -6 -3 -32 -24 -24 -24 -24 mA IOH (B port) MAX -15 -15 -15 -15 -6 -6 -15 -32 -24 -24 -24 -24 mA IOL (A port) MAX 24 24 64 24 6 6 24 64 24 24 24 24 mA IOL (B port) MAX 24 24 64 64 6 6 64 64 24 24 24 24 mA PARAMETER INPUT OUTPUT MAX or MIN LS ALS AS F SN74 HC SN74 HCT SN74 BCT ABT AC ACT CD74 AC CD74 ACT UNIT: ns OEAB B OEAB B OEBA A OEBA A MAX MAX AB BA MAX MAX MAX MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE (SN74) ENABLE INPUTS OPERATION L H OEBA H L L L H H B data to Abus A data to B bus B data to Abus Isoration A data to B bus OEAB

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 475 Logic Diagram 624 VOLTAGE-CONTROLLED OSCILLATORS

• This Voltage Oscillators (VCOs) is Improved Versions of The Original VCO Family: SN74124, 324, 325, 326, 327
• Separate Supply Voltage Pins for Isolation of Frequency Control Inputs and Oscillators from Outputs Circuitry
• Highly Stable Operation over Specified Temperature and / or Supply Voltage Ranges Cx FC RC EN (’LS624, ’LS628, ’LS629 only) G Z Y FC RC EN T R PARAMETER MAX or MIN LS UNIT ICC MAX 35 mA IOL MAX 24 mA IOH MAX -1.2 mA PARAMETER MAX or MIN LS fo MAX 25 UNIT: MHz ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPE TIMING REQUREMENTS AND SWITCHING CHARACTERIST

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 628 VOLTAGE-CONTROLLED OSCILLATORS

• This Voltage Oscillators (VCOs) is Improved Versions of The Original VCO Family: SN74124, 324, 325, 326, 327
• Separate Supply Voltage Pins for Isolation of Frequency Control Inputs and Oscillators from Outputs Circuitry
• Highly Stable Operation over Specified Temperature and / or Supply Voltage Ranges
• Two Rexternal Pins Can Offer More Precise Temprature Compensation Cx FC RC EN (’LS624, ’LS628, ’LS629 only) G Z Y FC RC EN T R PARAMETER MAX or MIN LS UNIT ICC MAX 35 mA IOH MAX -1.2 mA IOL MAX 24 mA PARAMETER MAX or MIN LS fo MAX 25 UNIT: MHz ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPER TIMING REQUREMENTS AND SWITCHING CHARACTERISTIC

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 477 Logic Diagram 629 DUAL VOLTAGE-CONTROLLED OSCILLATORS

• This Voltage Oscillators (VCOs) is Improved Versions of The Original VCO Family: SN74124, 324, 325, 326, 327
• Separate Supply Voltage Pins for Isolation of Frequency Control Inputs and Oscillators from Outputs Circuitry
• Highly Stable Operation over Specified Temperature and / or Supply Voltage Ranges Cx FC RC EN (’LS624, ’LS628, ’LS629 only) G Z Y FC RC EN T R PARAMETER MAX or MIN LS UNIT ICC MAX 55 mA IOH MAX -1.2 mA IOL MAX 24 mA PARAMETER MAX or MIN LS fo MAX 25 UNIT: MHz ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPER TIMING REQUREMENTS AND SWITCHING CHARACTERISTIC

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 638 OCTAL BUS TRANSCEIVERS

• Bidirectional Bus Tranceivers
• Inverting Logic
• Outputs A-Bus: Open-Collector 3-State
• Schmitt-Triggered Inputs (SN74LS638) To Seven Other Transceivers OE DIR FUNCTION TABLE OPERATION B data to A bus A data to B bus CONTROL INPUTS L L DIROE H Isoration L X H PARAMETER MAX or MIN LS ALS ALS A-1 AS UN IT ICCZ MAX 95 30 30 61 mA ICCL MAX 90 41 41 122 mA IOH (B) MAX -15 -15 -15 -15 mA VOH (A) MAX 5.5 5.5 5.5 5.5 V IOL MAX 24 24 48 64 mA PARAMETER INPUT OUTPUT MAX or MIN LS ALS ALS A-1 AS tPLH 10 12 12 7 tPHL 15 12 12 6.5 tPLH 25 25 25 20 tPHL 25 30 30 7 tPLH 40 25 25 19 tPHL 60 45 45 9 tPZH 40 20 20 8 tPZL 40 22 22 10 tPHZ 25 10 10 7 tPLZ 25 15 15 10 UNIT: ns OE A B OE OE MAX B A A B B MAX MAX MAX MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 639 OCTAL BUS TRANSCEIVERS

• Bidirectional Bus Tranceivers
• True Logic
• Outputs A-Bus: Open-Collector 3-State
• Schmitt-Triggered Inputs (SN74LS638) To Seven Other Transceivers OE DIR FUNCTION TABLE OPERATION B data to A bus A data to B bus CONTROL INPUTS L L DIROE H Isoration L X H PARAMETER MAX or MIN LS ALS ALS A-1 AS UNIT ICCZ MAX 95 54 54 100 mA ICCL MAX 90 50 50 154 mA IOH (B) MAX -15 -15 -15 -15 mA VOH (A) MAX 5.5 5.5 5.5 5.5 V IOL MAX 24 24 48 64 mA PARAMETER INPUT OUTPUT MAX or MIN LS ALS ALS A-1 AS tPLH 15 12 12 9.5 tPHL 15 12 12 9 tPLH 25 30 30 22 tPHL 25 22 22 9 tPLH 40 30 30 21.5 tPHL 50 35 35 11.5 tPZH 40 21 21 10.5 tPZL 40 25 25 10.5 tPHZ 25 10 10 7 tPLZ 25 16 16 10.5 UNIT: ns OE MAX B A B OE OE B A A B MAX MAX MAX MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

Logic Diagram (SN74) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 640 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

• Bidirectional Bus Tranceivers
• Inverting Logic
• 3-State Outputs
• Schmitt-Triggered Inputs (SN74LS640, 640-1)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) A1 B1 OE DIR To Seven Other Transceivers 21 8 FUNCTION TABLE (SN74) OPERATION B data to A bus A datato B bus CONTROL INPUTS L L DIROE H Isoration L X H PARAMETER MAX or MIN LS LS-1 ALS ALS B-1 AS SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 BCT ABT ACT

IOH (A port) MAX -15 -15 -15 -15 -15 -6 -6 -6 -6 -3 -32 -24 mA IOH (B port) MAX -15 -15 -15 -15 -15 -6 -6 -6 -6 -15 -32 -24 mA IOL (A port) MAX 24 48 24 48 64 6 6 6 6 24 64 24 mA IOL (B port) MAX 24 48 24 48 64 6 6 6 6 64 64 24 mA PARAMETER INPUT OUTPUT MAX or MIN LS LS-1 ALS ALS B-1 AS SN74 HC CD74 HC SN74 HCT tPLH 10 10 11 11 7 26 27 28 tPHL 15 15 10 10 6 26 27 28 tPLH 10 10 11 11 7 26 27 28 tPHL 15 15 10 10 6 26 27 28 tPZH 40 40 21 21 8 58 45 58 tPZL 40 40 24 24 10 58 45 58 tPHZ 25 25 10 10 8 38 45 50 tPLZ 25 25 15 15 13 38 45 50 tPZH 40 40 21 21 8 58 45 58 tPZL 40 40 24 24 10 58 45 58 tPHZ 25 25 10 10 8 38 45 50 tPLZ 25 25 15 15 13 38 45 50 PARAMETER INPUT OUTPUT MAX or MIN CD74 HCT SN74 BCT ABT ACT tPLH 33 6.5 4.9 10.5 tPHL 33 3.7 4.9 9.5 tPLH 33 6.5 4.9 10.5 tPHL 33 3.7 4.9 9.5 tPZH 45 10.2 5.8 13.4 tPZL 45 10.7 7.3 13.6 tPHZ 45 10.2 6.8 13.9 tPLZ 45 7.8 5.5 14.2 tPZH 45 10.2 5.8 13.4 tPZL 45 10.7 7.3 13.6 tPHZ 45 10.2 6.8 13.9 tPLZ 45 7.8 5.5 14.2 UNIT: ns B B OE OE OE MAX MAXA MAX MAX AB MAX BA MAX OE A AB MAX BA MAX OE A MAX OE A MAX OE B MAX OE B MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 641 OCTAL BUS TRANSCEIVERS

• Bidirectional Bus Tranceivers
• True Logic
• 3-State Outputs
• Schmitt-Triggered Inputs (SN74LS641) OE DIR To Seven Other Transceivers PARAMETER MAX or MIN LS LS-1 ALS ALS A-1 AS UNIT ICCZ MAX 95 95 --- m A ICCL MAX 90 90 47 47 136 mA IOL MAX 24 48 24 48 64 mA PARAMETER INPUT OUTPUT MAX or MIN LS LS-1 ALS ALS A-1 AS tPLH 25 25 25 25 21 tPHL 25 25 18 18 7.5 tPLH 25 25 25 25 21 tPHL 25 25 18 18 7.5 tPLH 40 40 30 30 21 tPHL 50 50 30 30 9 tPLH 40 40 32 32 22 tPHL 50 50 32 32 10 UNIT: ns OE DIR A,B A,B B AB A MAX MAX MAX MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE OPERATION B data to A bus A datato B bus CONTROL INPUTS L L DIRG H Isoration L X H

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 642 OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS

• Bidirectional Bus Tranceivers
• Inverting Logic
• 3-State Outputs
• Schmitt-Triggered Inputs (SN74LS642) A1 OE DIR To Seven Other Transceivers PARAMETER MAX or MIN LS LS-1 ALS ALS A-1 AS UNIT ICCZ MAX 95 95 --- m A ICCL MAX 90 90 28 28 104 mA IOL MAX 24 48 24 48 64 mA PARAMETER INPUT OUTPUT MAX or MIN LS LS-1 ALS ALS A-1 AS tPLH 25 25 30 30 24 tPHL 25 25 22 22 7.5 tPLH 25 25 30 30 24 tPHL 25 25 22 22 7.5 tPLH 40 40 30 30 23.5 tPHL 60 60 38 38 11.5 tPLH 40 40 30 30 23.5 tPHL 60 60 38 38 11.5 UNIT: ns B OE, DIR OE, DIR MAX A A B MAX MAX B MAXA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE OPERATION B data to A bus A data to B bus CONTROL INPUTS L L DIROE H Isoration L X H

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 645 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

• Bidirectional Bus Tranceivers
• True Logic
• 3-State Outputs
• Schmitt-Triggered Inputs (SN74LS645, 645-1) A1 B1 OE DIR To Seven Other Transceivers 21 8 PARAMETER MAX or MIN LS LS-1 ALS ALS A-1 AS SN74 HC SN74 HCT UNIT ICCZ MAX 95 95 58 58 123 0.08 0.08 mA ICCL MAX 90 90 55 55 149 0.08 0.08 mA IOH MAX -15 -15 -15 -15 -15 -6 -6 mA IOL MAX 24 48 24 48 64 6 6 mA PARAMETER INPUT OUTPUT MAX or MIN LS LS-1 ALS ALS A-1 AS SN74 HC SN74 HCT tPLH 15 15 10 10 9.5 26 28 tPHL 15 15 10 10 9 26 28 tPLH 15 15 10 10 9.5 26 28 tPHL 15 15 10 10 9 26 28 tPZH 40 40 20 20 11 58 58 tPZL 40 40 20 20 10 58 58 tPHZ 25 25 10 10 7 50 50 tPLZ 25 25 15 15 12 50 50 tPZH 40 40 20 20 11 58 58 tPZL 40 40 20 20 10 58 58 tPHZ 25 25 10 10 7 50 50 tPLZ 25 25 15 15 12 50 50 UNIT: ns OE A B OE B A A A MAX MAX MAX MAX OE OE MAX MAX B B ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE OPERATION B data to A bus A data to B bus CONTROL INPUTS L L DIROE H Isoration L X H

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS484 Logic Diagram (SN74) 646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

• Bidirectional Bus Tranceivers
• Independent Registers for A and B Buses
• Multiplexed Real-Time and Stored Data
• True Data Paths
• 3-State Outputs
• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) One of Eight Channels SAB CLKAB SBA CLKBA DIR OE To Seven Other Channels PARAMETER MAX or MIN LS ALS ALS A-1 AS SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 BCT ABT ABT Ver.A UNIT ICC MAX 165 88 88 211 0.08 0.16 0.08 0.16 67 30 30 mA IOH MAX -15 -15 -15 -15 -6 -6 -6 -6 -15 -32 -32 mA IOL MAX 24 24 48 48 6666 6 4 6 4 6 4 m A PARAMETER MAX or MIN LVTH AC CD74 AC ACT CD74 ACT LVC 3V UNIT IOH MAX -32 -24 -24 -24 -24 -24 mA IOL MAX 64 24 24 24 24 24 mA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS

485PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER INPUT OUTPUT MAX or MIN LS ALS ALS A-1 AS SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 BCT fmax MIN - 40 40 90 27 20 27 17 83 15 12.5 12.5 5 19 24 19 38 6 30 12.5 12.5 6 19 24 19 38 6 15 10 10 6 25 - 25 18 6 15 10 10 6 25 - 25 18 6 t h MIN 00005 1 1 55 0 . 5 tPLH 25 30 30 8.5 45 66 45 66 11.2 tPHL 35 17 17 9 45 66 45 66 10.6 tPLH 18 20 20 9 34 4 13 45 6 9 . 5 tPHL 20 12 12 7 34 41 34 56 10.5 tPLH 40 25 25 11 48 51 48 69 13.8 tPHL 35 20 20 9 48 5 14 86 9 9 . 1 tPLH 50 35 35 11 48 51 48 69 12 tPHL 25 20 20 9 48 51 48 69 12.9 tPZH 55 17 17 9 61 53 61 68 13.2 tPZL 65 20 20 14 61 53 61 68 14.4 tPHZ 35 10 10 9 61 53 61 53 10.9 tPLZ 35 16 16 9 61 53 61 53 10.5 tPZH 45 30 30 16 61 53 61 - 13.1 tPZL 60 25 25 18 61 53 61 - 14.6 tPHZ 30 10 10 10 61 53 61 - 12.6 tPLZ 30 16 16 10 61 53 61 - 11.8 PARAMETER INPUT OUTPUT MAX or MIN ABT ABT Ver.A LVTH AC CD74 AC ACT CD74 ACT LVC fmax MIN 125 125 150 100 125 105 110 150 44 3 . 3 54 4 .8 4.5 3.3 44 3 . 3 54 4 .8 4.5 3.3 th MIN 0 0 0.8 12 2 . 52 1.7 UNIT fmax : MHz other : ns A,B A,B MAXOE A,B MAXOE MAXSAB,SBA (sored data low) tsu CLKBA,CLKAB "H" MINCLKBA,CLKAB "L" A,B SAB,SBA (sored data high) SAB,SBA (sored data high) SAB,SBA (sored data low) A,B CLOCK MIN MIN tsu CLKBA,CLKAB "H" CLKBA,CLKAB "L" CLKBA,CLKAB DIR DIR A,B OE OE A,B tw CLKBA,CLKAB "H" CLKBA,CLKAB "L" DATA MAX MAX MAX A,B A,B A,B A,B MAXB,A A,B MAX MAX MAX MAX DIR A,B MAX t w CLKBA,CLKAB "H" MINCLKBA,CLKAB "L" DATA A,B MAX DIR A,B MAX CLKBA,CLKAB CLOCK B,A MAX A,B MAX TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE (SN74) DIROE INPUTS OPERATION OR FUNCTION H L CLKAB X H to L H X X LX CLKBA X H to L H to L LX LH to L L L H H X X SAB X X X X L H SBA L X X H X X A1–A8 B1–B8 DATA I/O† Input Input Isolation Input Input Store A and B data Output Input Real-time B data to A bus Output Input Stored B data to A bus Input Output Real-time A data to B bus Input Output Stored A data to B bus † The data output functions can be enabled or disabled by various signals at OE and DIR. Data input functions are always enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs. CD74HC: NOT RECOMMENDED FOR NEW DESIGNS

G CBA (20) (4) (21) DIR (3) (23) TO 7 OTHER CHANNELS SBA (22) CAB (1) SAB (2) I OF 8 CHANNELS : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 647 OCTAL BUS TRANSCEIVERS AND REGISTERS

• Bidirectional Bus Tranceivers
• Independent Registers for A and B Buses
• Multiplexed Real-Time and Stored Data
• True Data Paths
• Open-Collector Outputs

487PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN LS UNIT ICC MAX 150 mA VOH MAX 5.5 V IOL MAX 24 mA PARAMETER OUTPUT MAX or MIN LS tw MIN 30 tsu MIN 15 th MIN 0 tPLH 35 tPHL 45 tPLH 26 tPHL 27 tPLH 50 tPHL 45 tPLH 60 tPHL 30 tPLH 40 tPHL 50 tPLH 35 tPHL 40 UNIT: ns MAX A,B MAX MAX B,A MAX MAX MAX A,B INPUT G DIR CLOCK A,B SAB,SBA (With Bus Input High) SAB,SBA (With Bus Input Low) A,B A,B A,B A,B A,B ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE DIRG INPUTS OPERATION OR FUNCTION H L CAB X H to L H X X LX CBA X H to L H to L LX LH to L L L H H X X SAB X X X X L H SBA L X X H X X A1–A8 B1–B8 DATA I/O† Input Input Isolation Input Input Store A and B data Output Input Real-time B data to A bus Output Input Stored B data to A bus Input Output Real-time A data to B bus Input Output Stored A data to B bus † The data output functions can be enabled or disabled by various signals at OE and DIR. Data input functions are always enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 648 OCTAL BUS TRANSCEIVERS AND REGISTERS

• Bidirectional Bus Tranceivers
• Independent Registers for A and B Buses
• Multiplexed Real-Time and Stored Data
• Inverting Data Paths
• 3-State Outputs

489PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN LS ALS AS SN74 HC SN74 HCT UNIT ICC MAX 180 88 195 0.08 0.08 mA IOH MAX -15 -15 -15 -6 -6 mA IOL MAX 24 24 48 6 6 mA PARAMETER OUTPUT MAX or MIN LS ALS AS SN74 HC SN74 HCT fmax MIN - 40 90 27 27 MIN1 5 12.5 5 19 19 MIN3 0 12.5 6 19 19 MIN3 0 ---- tsu MIN 15 1 062 5 2 5 th MIN 00055 tPLH 25 33 8.5 45 45 tPHL 40 2 094 5 4 5 tPLH 18 1 783 4 3 4 tPHL 25 1 073 4 3 4 tPLH 55 25 11 48 48 tPHL 40 2 194 8 4 8 tPLH 40 39 11 48 48 tPHL 40 2 294 8 4 8 tPZH 50 2 296 1 6 1 tPZL 55 22 15 61 61 tPHZ 45 1 096 1 6 1 tPLZ 35 1 596 1 6 1 tPZH 40 27 16 61 61 tPZL 45 19 18 61 61 tPHZ 35 14 10 61 61 tPLZ 30 15 10 61 61 UNIT fmax : MHz other : ns A,B CLKAB, CLKBA "H" CLKAB, CLKBA "L" DATA CLKAB, CLKBA A,B CLKAB, CLKBA B,A A,B MAX MAX MAX MAX CLOCK A,B SAB,SBA (With Bus Input High) SAB,SBA (With Bus Input Low) MAX MAX DIR A,B A,B MAX MAX DIR OE A,B A,B t w OE INPUT ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE DIROE INPUTS OPERATION OR FUNCTION H L CLKAB X H to L H X X LX CLKBA X H to L H to L LX LH to L L L H H X X SAB X X X X L H SBA L X X H X X A1–A8 B1–B8 DATA I/O† Input Input Isolation Input Input Store A and B data Output Input Real-time B data to A bus Output Input Stored B data to A bus Input Output Real-time A data to B bus Input Output Stored A data to B bus † The data output functions can be enabled or disabled by various signals at OE and DIR. Data input functions are always enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.

Logic Diagram (SN74) OEBA One of Eight Channels SAB CLKAB SBA CLKBA OEAB To Seven Other Channels : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 651 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

• Bus Tranceivers / Registers
• Independent Registers and Enables for A and B Buses
• Multiplexed Real-Time and Stored Data
• Inverting Data Paths
• 3-State Outputs

491PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER OUTPUT MAX or MIN LS ALS ALS A-1 AS SN74 HC SN74 HCT SN74 BCT ABT CD74 ACT fmax MIN - 40 40 90 27 20 85 125 110 MIN1 5 12.5 12.5 5 19 25 4.8 4 4.5 MIN 15 12.5 12.5 6 19 25 7 4 4.5 tsu MIN 15 1 01 0 6 2 51 9 6 32 . 5 th MIN 000055102 tPLH 24 32 32 8.5 45 45 11.7 5.6 15.5 tPHL 35 17 17 94 54 51 1.8 5.6 15.5 tPLH 18 18 18 93 43 41 2.6 6.2 12.5 tPHL 30 10 10 73 43 49 .8 5.4 12.5 tPLH 47 38 38 11 48 48 9.8 6.5 15.5 tPHL 33 21 21 94 84 81 5.5 5.9 15.5 tPLH 35 25 25 11 48 48 14.6 6.5 15.5 tPHL 30 21 21 94 84 81 2.8 5.9 15.5 tPZH 44 20 20 10 61 61 12 5.8 15.5 tPZL 60 18 18 16 61 61 13.1 8.5 15.5 tPHZ 38 999 61 61 10.2 5 15.5 tPLZ 30 12 12 96 16 19 .6 4.1 15.5 tPZH 29 22 22 11 61 61 8.3 6.5 15.5 tPZL 40 21 21 16 61 61 9.7 7.4 15.5 tPHZ 38 12 12 10 61 61 15 5.5 15.5 tPLZ 30 14 14 11 61 61 12.3 5.1 15.5 UNIT fmax : MHz other : ns MAX MAX MAX OEBA OEBA tw MAX MAX MAX CLOCK A,B SAB,SBA (With Bus Input High) A,B MAX A,B B,A A,B A,B A A B B MAX INPUT OEAB SAB,SBA (With Bus Input Low) OEAB CLKBA, CLKAB "H" CLKBA, CLKAB "L" DATA A,B PARAMETER MAX or MIN LS ALS ALS A-1 AS SN74 HC SN74 HCT SN74 BCT ABT CD74 ACT UNIT ICC MAX 165 82 82 195 0.08 0.08 62 30 160 mA IOH MAX -15 -15 -15 -15 -6 -6 -15 -32 -24 mA IOL MAX 24 24 48 48 6 6 64 64 24 mA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE (SN74) OEBAOEAB INPUTS OPERATION OR FUNCTION L X CLKAB H to L L H H H CLKBA H to L H to L L L H to L H H X L SAB X X X X X X SBA X X X X X X A1–A8 B1–B8 DATA I/O LX LX L L X H to L X X L H HX HH to L H H X X L H X X H H to L H to LL HH Input Input Isolation Input Input Store A and B data Input Unspecified Store A, hold B Input Output Store A in both registers Unspecified Input Hold A, store B Output Input Store B in both registers Output Input Real-time B data to A bus Output Input Stored B data to A bus Input Output Real-time A data to B bus Input Output Stored A data to B bus Output Output Stored A data to B bus and stored B data to A bus

Logic Diagram (SN74) OEBA One of Eight Channels SAB CLKAB SBA CLKBA OEAB To Seven Other Channels : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 652 OCTAL BUS TRANSCEIVERS AND REGISTERS

• Bus Tranceivers / Registers
• Independent Registers and Enables for A and B Buses
• Multiplexed Real-Time and Stored Data
• True Data Paths
• 3-State Outputs
• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) FUNCTION TABLE (SN74) OEBAOEAB INPUTS OPERATION OR FUNCTION L X CLKAB H to L L H H H CLKBA H to L H to L L L H to L H H X L SAB X X X X X X SBA X X X X X X A1–A8 B1–B8 DATA I/O LX LX L L X H to L X X L H HX HH to L H H X X L H X X H H to L H to LL HH Input Input Isolation Input Input Store A and B data Input Unspecified Store A, hold B Input Output Store A in both registers Unspecified Input Hold A, store B Output Input Store B in both registers Output Input Real-time B data to A bus Output Input Stored B data to A bus Input Output Real-time A data to B bus Input Output Stored A data to B bus Output Output Stored A data to B bus and stored B data to A bus

493PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER INPUT OUTPUT MAX or MIN LS ALS ALS A-1 AS SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 BCT fmax MIN - 40 40 90 27 20 20 17 77 MIN1 5 12.5 12.5 5 19 24 25 38 6.5 MIN1 5 12.5 12.5 6 19 24 25 38 6.5 MIN 15 1 01 0 6 2 51 81 91 8 5 MIN 15 10 10 6 25 18 19 18 5 th MIN 0 0005 1 15 5 1 tPLH 25 30 30 8.5 45 66 45 66 10.5 tPHL 36 17 17 9 45 66 45 66 9.9 tPLH 18 18 18 9 34 41 34 56 8.9 tPHL 20 12 12 7 34 41 34 56 9.8 tPLH 35 35 35 11 48 51 48 69 13.1 tPHL 32 20 20 9 48 51 48 69 8.5 tPLH 50 25 25 11 48 51 48 69 11.3 tPHL 23 20 2094 85 14 86 9 12.5 tPZH 45 17 17 10 61 53 61 68 10.6 tPZL 54 18 18 16 61 53 61 68 12 tPHZ 38 10 10 9 61 5 36 15 31 0 tPLZ 30 16 16 9 61 53 61 53 9.5 tPZH 30 22 22 11 61 53 61 68 8.1 tPZL 38 18 18 16 61 53 61 68 9.3 tPHZ 38 10 10 10 61 53 61 53 11.6 tPLZ 30 16 16 11 61 53 61 53 11.3 PARAMETER INPUT OUTPUT MAX or MIN ABT ABT Ver.A LVTH AC CD74 AC ACT CD74 ACT LVC fmax MIN 125 125 150 105 125 105 110 100 th MIN 0 0 0.8 1 2 2.5 2 1.7 UNIT fmax : MHz other : ns A,B B,A MAX A B B OEBA OEAB OEAB DATA A,B SAB,SBA (With Bus Input High) SAB,SBA (With Bus Input Low) OEBA B,A A,B A,B A MAX MAX OEAB B OEAB B MAX MAX OEBA A OEBA A MAX MAX SAB,SBA (With Bus Input High) A,B SAB,SBA (With Bus Input Low) A,B CLOCK A,B MAX A,B High A,B Low A,B t w CLKBA, CLKAB "H" CLKBA, CLKAB "L" DATA MAX MAX MAX MAX MAX MAX MAX MAX t su tsu tw CLKBA, CLKAB "H" CLKBA, CLKAB "L" A,B High A,B Low A,B CLOCK A,B PARAMETER MAX or MIN LS ALS ALS A-1 AS SN74 HC CD74 HC SN74 HCT CD74 HCT SN74 BCT ABT UNIT ICC MAX 180 88 88 211 0.08 0.16 0.08 0.16 69 30 mA IOH MAX -15 -15 -15 -15 -6 -6 -6 -6 -15 -32 mA IOL MAX 24 24 48 48 6666 6 4 6 4 m A PARAMETER MAX or MIN ABT Ver.A LVTH AC CD74 AC ACT CD74 ACT LVC 3V UNIT IOH MAX -32 -32 -24 -24 -24 -24 -24 mA IOL MAX 64 64 24 24 24 24 24 mA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS494 653 OCTAL BUS TRANSCEIVERS AND REGISTERS

• Bus Tranceivers / Registers
• Independent Registers and Enables for A and B Buses
• Multiplexed Real-Time and Stored Data
• Inverting Data Paths
• Outputs A Bus: Open-Collector B Bus: 3-State Logic Diagram OEBA One of Eight Channels SAB CLKAB SBA CLKBA OEAB To Seven Other Channels

495PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER INPUT OUTPUT MAX or MIN LS ALS CLK "H" MIN 15 14.5 CLK "L" MIN 30 14.5 DATA MIN 30 - tsu A, B MIN 15 10 th A, B MIN 0 0 tPLH 38 64 tPHL 39 22 tPLH 23 30 tPHL 36 17 tPLH 18 18 tPHL 30 15 tPLH 32 56 tPHL 24 15 tPLH SBA 57 62 tPHL (B "H") 39 25 tPLH SBA 51 62 tPHL (B "L") 35 25 tPLH SAB 48 35 tPHL (A "H") 33 22 tPLH SAB 36 25 tPHL (A "L") 30 22 tPLH 35 30 tPHL 55 24 tPZH 29 22 tPZL 38 22 tPHZ 39 14 tPLZ 29 16 UNIT:ns B A CLKBA CLKAB OEAB OEAB OEBA B A B B A A A B MAX MAX MAX MAX MAX MAX MAX MAX t w MAX MAX MAX B A B PARAMETER MAX or MIN LS ALS UNIT ICC MAX 165 88 mA IOH MAX -15 -15 mA IOL MAX 24 24 mA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS OEBAOEAB INPUTS OPERATION OR FUNCTION L X CLKAB H or L L H H H CLKBA H or L H or L Store A, hold B Store A in both registers Hold A, store B Store B in both registers Isolation Store A and B data L L H or L H H X L SAB X X X X X SBA X X X X X A1–A8 Inpu Input Input Output Unspeciffied‡ B1–B8 Input DATA I/O† Real-time B data to A bus Stored B data to A bus LX LX L L X H or L X X L H Output Input Real-time A data to B bus Stored A data to B bus HX HH or L H H X X L H X X Input Output Stored A data to B bus and stored B data to A busH H or L H or LL HH Output Output Output Unspeciffied‡ Input Input FUNCTION TABLE NOTES: † The data output functions can be enabled or dissabled by a variety of level combinations at GAB or GBA. Data input functions always are enabled; i.e., data at the bus teminals is storedd on evry low-to-high transition on the clock inputs. ‡S elect control = L: clocks can occur simultaneously. Select control = H: clock must be staggered to load both registers.

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 654 OCTAL BUS TRANSCEIVERS AND REGISTERS

• Bus Tranceivers / Registers
• Independent Registers and Enables for A and B Buses
• Multiplexed Real-Time and Stored Data
• True Data Paths
• Outputs A Bus: Open-Collector B Bus: 3-State

497PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN LS ALS UNIT ICC MAX 180 88 mA IOH MAX -15 -15 mA IOL MAX 24 24 mA PARAMETER OUTPUT MAX or MIN LS ALS MIN1 5 14.5 MIN3 0 14.5 MIN 30 - tsu MIN 15 10 th MIN 0 0 tPLH 33 64 tPHL 36 22 tPLH 21 30 tPHL 33 17 tPLH 18 18 tPHL 30 15 tPLH 27 56 tPHL 21 21 tPLH 48 62 tPHL 32 25 tPLH 54 62 tPHL 29 25 tPLH 35 25 tPHL 27 22 tPLH 45 35 tPHL 21 22 tPLH 35 30 tPHL 53 24 tPZH 29 22 tPZL 33 22 tPHZ 39 14 tPLZ 29 16 UNIT: ns MAX MAX MAX MAX MAX MAX MAX MAX MAX MAX MAXB B A B B A A A B B A OEAB CLKBA, CLKAB "H" CLKBA, CLKAB "L" DATA A,B A,B SBA (B "H") SBA (B "L") SAB (A "H") SAB (A "L") t w INPUT OEBA OEAB CLKBA CLKAB A B ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE OEBAOEAB INPUTS OPERATION OR FUNCTION L X CLKAB H to L L H H H CLKBA H to L H to L L L H to L H H X L SAB X X X X X X SBA X X X X X X A1–A8 B1–B8 DATA I/O LX LX L L X H to L X X L H HX HH to L H H X X L H X X H H to L H to LL HH Input Input Isolation Input Input Store A and B data Input Unspecified Store A, hold B Input Output Store A in both registers Unspecified Input Hold A, store B Output Input Store B in both registers Output Input Real-time B data to A bus Output Input Stored B data to A bus Input Output Real-time A data to B bus Input Output Stored A data to B bus Output Output Stored A data to B bus and stored B data to A bus

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 657 OCTAL BUS TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS

• Combines SN74F245 and SN74F280B Functions in One Package
• 3-State Outputs
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)

499PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER INPUT OUTPUT MAX or MIN F SN74 BCT ABT ACT tPLH MAX 8 6.6 4.6 9.4 tPHL MAX 8 9 4.3 9.4 tPLH MAX 16 15 .4 8.1 14.4 tPHL MAX 16 1 5.9 7.7 15 tPLH MAX 12 7.1 4 .9 10.7 tPHL MAX 12 .5 9 4.9 11.3 tPLH MAX 22.5 15.3 7.9 23.6 tPHL MAX 22.5 15.5 7.8 24.6 tPLH MAX 16.5 13.2 7.7 14.6 tPHL MAX 17 13 .9 7.5 14.7 tPZH MAX 9 9.1 6.5 12.1 tPZL MAX 11 16 .3 6.5 13.8 tPZH MAX 9 9.1 6.6 12.1 tPZL MAX 11 16 .3 9.2 13.8 tPHZ MAX 8 9.1 6.2 12.1 tPLZ MAX 6.5 8 7.8 11.6 UNIT: ns ERR A, B, PARITY, ERR ERR PA RITY, ERR ERR A, B, PARITY A,B A ODD/EVEN B PARITY OE OE OE B,A PARITY PARAMETER MAX or MIN F SN74 BCT ABT ACT ICCH MAX 125 2 0.25 0.08 mA ICCL MAX 150 90 40 0.08 mA ICCZ MAX 145 1 0.25 0.08 mA IOH A1-A9 MAX -3 -3 -32 -24 mA IOH B1-B9, PA RITY, ERR MAX -12 -15 -32 -24 mA IOL A1-A8 MAX 24 24 64 24 mA IOL B1-B8, PA RITY, ERR MAX 64 64 64 24 mA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

S R To Seven Other Channels OE1 OE2 OERB PRE CLR LE 1D 1Q : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 666 8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES WITH 3-STATE OUTPUTS

• 3-State I/O-Type Read-Back Inputs
• True Outputs
• Bus-Structured Pinout INPUT OUTPUT MAX or MIN ALS LE "H" MIN 10 CLR "L" MIN 10 PRE "L" MIN 10 DATA (LE) MIN 10 DATA (OERB) MIN 10 th DATA (LE) MIN 5 tPLH 14 tPHL 18 tPLH 21 tPHL 27 Q2 9 D3 2 t PLH Q2 2 tPHL D2 8 UNIT: ns t dis OE1 , OE2 tPHL ten tdis ten OERB MAXQD MAX MAXQ D MAX MAX MAX PRE PARAMETER LE CLR Q t su tw MAX or MIN ALS UNIT ICC MAX 73 mA Q MAX -2.6 mA D MAX -0.4 mA Q MAX 24 mA D MAX 8 mA PARAMETER IOL IOH ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

501PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram 667 8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES WITH 3-STATE OUTPUTS

• 3-State I/O-Type Read-Back Inputs
• Inverted Outputs
• Bus-Structured Pinout S R To Seven Other Channels OE1 OE2 OERB PRE CLR LE 1D 1Q INPUT OUTPUT MAX or MIN ALS LE "H" MIN 10 CLR "L" MIN 10 PRE "L" MIN 10 DATA (LE) MIN 10 DATA (OERB) MIN 10 th DATA (LE) MIN 5 tPLH 20 tPHL 15 tPLH 28 tPHL 22 Q 24 D 26 tPLH Q 25 tPHL D 28 UNIT: ns t w tsu ten tdis tdis tPHL CLR PRE OERB MAX MAX Q Q MAX MAX MAX MAX PARAMETER D Q LE D OE1 , OE2t en MAX or MIN ALS UNIT ICC MAX 79 mA Q MAX -2.6 mA D MAX -0.4 mA Q MAX 24 mA D MAX 8 mA PARAMETER IOL IOH ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

(14) QA (13) QB (12) QC (11) QD (15) RCO (2) CLOCK (1) U/D (9) LOAD DATA A (7)ENABLE P (10) (3) DATA B (4) DATA C (5) DATA D (6) ENABLE T : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 669 SYNCHRONOUS 4-BIT UP/DOWN COUNTERS

• Fully Synchronous Operation for Counting and Programming
• Internal Look-Ahead for Fast Counting
• Carry Output for n-Bit Cascading

503PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. INPUT OUTPUT MAX or MIN LS fmax MIN 25 tw MIN 20 A,B,C,D MIN 25 ENP , ENT MIN 40 LOAD MIN 30 U/D MIN 45 th MIN 0 tPLH 40 tPHL 60 tPLH 27 tPHL 27 tPLH 17 tPHL 45 tPLH 35 tPHL 40 UNIT fmax : MHz other : ns tsu MAXCLOCK RCO RCO MAX MAX MAX Q RCO PARAMETER U/D CLOCK ENT PARAMETER MAX or MIN LS UNIT ICC MAX 34 mA IOH MAX -0.4 mA IOL MAX 8 mA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

Logic Diagram (SN74LS) D2 (1) GW Q2(9) D G QD G QD G QD G Q D1 (15) WORD 0 WORD 1 WORD 2 WORD 3 Q1(10) D G QD G QD G QD G Q D3 (2) Q3(7) D G QD G QD G QD G Q (12) GR (11) WB WRITE INPUT (13) WA (14) (3) Q4(6) D G QD G QD G QD G Q RB READ INPUT OUTPUTS DATA INPUTS (4) RA (5) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 670 4-BY-4 REGISTER FILES WITH 3-STATE OUTPUTS

• Separate Read / Write Addressing Permits Simultaneous Reading and Writing
• Organized as 4 Words of 4 Bits
• Expandable to 512 Words of n-Bits
• 3-State Outputs

505PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN LS CD74 HC CD74 HCT UNIT ICC MAX 50 0.16 0.16 mA IOH MAX -2.6 -6 -6 mA IOL MAX 8 66 mA PARAMETER INPUT OUTPUT MAX or MIN LS CD74 HC CD74 HCT tw MIN 25 2 43 0 10 18 18 15 18 27 15 5 5 555 t latch MIN 25 3 03 8 tPLH 40 59 53 tPHL 45 59 53 tPLH 45 75 75 tPHL 50 75 75 tPLH 45 75 75 tPHL 40 75 75 tPZH 35 45 57 tPZL 40 45 57 tPHZ 50 45 53 tPLZ 35 45 53 UNIT : ns MAX MAX MAX MAX Read Enable Q Read Disable Q Write Enable Q Data Q Read Select Q MAX Write select with respect to write enable tsu th MIN MIN Width of write-enable or read-enable pulse Data input with respect to write enable Write select with respect to write enable Data input with respect to write enable ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE (SN74) WRITE INPUTS WORD L L L H GWWB 3 H H L L L L Q = D Q0Q0 Q0Q0Q0 Q = D Q = D Q0Q0Q0Q0 Q0Q0Q0 WA L H X H Q = D X READ INPUTS OUTPUTS L L L H GRRB Q4 H H L L L L W2B4 W2B3 W1B4W1B3 W2B2 W0B4W0B3W0B2 W1B2 W0B1 W2B1 ZZZZ W3B3W3B2W3B1 W1B1 RA L H X H W3B4 X

(2) STRCLR CS (4) Q15 Q0-Q15 CLK PE† 16-BIT SHIFT REGISTER SER/Q15 P0-P15 SER IN Y0-Y15 Y0-Y15 CLK CLR D0-D15 (6) (7-11, 13-23) 16BIT STORAGE REGISTER MODE/STRCLK (5) (1) R/W (3) † When PE is active, data synchronously parallel loaded into the shift registers form the 16 P inputs and no shifting takes place. : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 673 16-BIT SHIFT REGISTERS

• 16-Bit Serial-In, Serial-Out Shift Register with 16-Bit Parallel-Out Storage Register
• Performs Serial-to-Parallel Conversion

507PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. INPUT OUTPUT MAX or MIN LS fmax MIN 20 CLK MIN 20 CLR MIN 20 SER/Q15 MIN 20 Y0-Y15 MIN 20 Mode MIN 35 R/W,CS MIN 35 SER/Q15 MIN 0 Y0-Y15 MIN 0 Mode MIN 0 t PLH STRCLR Y0-Y15 MAX 40 tPLH 45 tPHL 45 tPLH 33 tPHL 40 UNIT fmax : MHz other : ns MAX MAX MODE/ STRCLK SH CLK SER/Q15 Y0-Y15 tw tsu th PARAMETER MAX or MIN LS UNIT ICC MAX 80 mA SER/Q15 MAX -2.6 mA Y0-Y15 MAX -0.4 mA SER/Q15 MAX 24 mA Y0-Y15 MAX 8 mA PARAMETER IOH IOL ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE R/WCS INPUTS H L SH CLK X X X XX L L STRCLR X L L L HX H H MODE/ STRCLK X X X X L X X X X L SER/ Q15 Z Z Q15 Q14n L WRITE INTO SERIAL INPUT SHIFT REGISTER FUNCTIONS L LX H L H H X Y15n Z SHIFT YES NO YES NO NO READ FROM SERIAL INPUT NO NO YES YES YES YES NO YES NO NO NO PARALLEL LOAD NO NO NO YES YES CLEAR YES YES; NO NO LOAD NO NO NO NO NO YES STORAGE REGISTER FUNCTIONS

(2) CS Q15 CLK PE† 16-BIT SHIFT REGISTER P0-P15 P0-P15 SER IN (6) SER/Q15 (7-11, 13-23) MODE (5) (1) R/W (3) † When PE is active, data synchronously parallel loaded into the shift registers form the 16 P inputs and no shifting takes place. : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 674 16-BIT SHIFT REGISTERS

• 16-Bit Parallel-In, Serial-Out Shift Register
• Performs Parallel-to-Serial Conversion

509PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. INPUT OUTPUT MAX or MIN LS fmax MIN 20 CLK 20 CLR 20 SER/Q15 20 P0-P15 20 Mode 35 R/W,CS 35 SER/Q15 0 P0-P15 0 Mode 0 tPLH 33 tPHL 40 tPZH 45 tPZL 45 tPHZ 40 tPLZ 40 UNIT fmax : MHz other : ns MAX MAX SER/Q15 SER/Q15 CS, R/W CS, R/W tw PARAMETER MIN SER/Q15 th CLK tsu MIN MAX MIN MAX or MIN LS UNIT ICC MAX 40 mA SER/Q15 MAX -2.6 mA P0-P15 MAX -0.4 mA SER/Q15 MAX 24 mA P0-P15 MAX 8 mA PARAMETER IOH IOL ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE MODE SER/ Q15 INPUTS H L R/WCS CLK L L L H H XX H X L X Z Q14n Z P15 OPERATION Do nothing Shift and read Shift and write (serial load) parallel load

Y G 13A12 : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 679 12-BIT ADDRESS COMPARATOR

• 12-Bit Address Comparator with Enable

511PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER INPUT OUTPUT MAX or MIN ALS SN74 HC tPLH 25 375 tPHL 35 375 tPLH 22 78 tPHL 30 78 tPLH 13 31 tPHL 25 31 UNIT: ns GY MAX Y MAX Any P Y MAX Any A PARAMETER MAX or MIN ALS SN74 HC UNIT ICC MAX 28 0.08 mA IOH MAX -2.6 -4 mA IOL MAX 24 4 mA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE OUTPUTINPUTS L L P0P2GP 3 L L LL L L H L H L H H L H L L Y L L L H H H H H H H H H H H H H H H H H H H H H A10 H H H A11 H H H A12 H H H L L L LL H H L L LLH HHHHHHHHL H H L L LH L L H L H L L L L L L L L L L L L L L L L H L L H H L H H H H H H H H H H H H H H H H H H L L L LH H H LL LLL LLLH H H H HL L L L L LL L L H L H L L L L L L L L L L L L L L L L L L L L L L L L L L L L H L L H H L H H H H H H H H H LL H H LL LLL LLLLLLLHH H H L L LH L L H L H L L L L L L L L L L L L L L L L L L L L L L L L L L L L H L L H H L H H H L L L H H H LH H H LL L H H LL LLLLLLLLH L All other combinations H Any combination

P=Q P>Q : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 682 8-BIT MAGNITUDE COMPARATORS

• Totem-Pole Outputs
• Hysteresis at P and Q Inputs
• 20kΩ Pullup Resistors on the Q Inputs

513PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER INPUT OUTPUT MAX or MIN LS SN74 HC tPLH 25 69 tPHL 25 69 tPLH 25 69 tPHL 25 69 tPLH 30 69 tPHL 30 69 tPLH 30 69 tPHL 30 69 UNIT: ns P = Q P > Q P = Q P > Q MAX Q P Q P MAX MAX MAX PARAMETER MAX or MIN LS SN74 HC UNIT ICC MAX 70 0.11 mA IOH MAX -0.4 -4 mA IOL MAX 24 4 mA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE INPUT DATA OUTPUTS P=Q P>Q P=QP, Q P>Q P<Q L H H H H L

P=Q P>Q : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 684 8-BIT MAGNITUDE COMPARATORS

• Totem-Pole Outputs
• Hysteresis at P and Q Inputs

515PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER INPUT OUTPUT MAX or MIN LS SN74 HC tPLH 25 69 tPHL 25 69 tPLH 25 69 tPHL 25 69 tPLH 30 69 tPHL 30 69 tPLH 30 69 tPHL 30 69 UNIT: ns P > Q MAX P > Q MAX P = Q MAX P = Q MAX P Q P Q PARAMETER MAX or MIN LS SN74 HC UNIT ICC MAX 65 0.08 mA IOH MAX -0.4 -4 mA IOL MAX 24 4 mA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE INPUT DATA OUTPUTS P=Q P>Q P=QP, Q P>Q P<Q L H H H H L

P = Q (17) (19) Q7 (18) P6 (15) Q6 (16) P5 (13) Q5 (14) P4 (11) Q4 (12) P3 (8) Q3 (9) P2 (6) Q2 (7) P1 (4) Q1 (5) P0 (2) Q0 (3) P > Q(1) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 686 8-BIT MAGNITUDE/IDENTITY COMPARATORS

• Totem-Pole Outputs
• Hysteresis at P and Q Inputs

517PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER INPUT OUTPUT MAX or MIN LS tPLH 25 tPHL 30 tPLH 25 tPHL 30 tPLH 20 tPHL 30 tPLH 30 tPHL 30 tPLH 30 tPHL 30 tPLH 30 tPHL 25 UNIT: ns MAX MAX MAX MAX QP > Q G2 P > Q G1 P = Q PP > Q PP = Q MAX QP = Q MAX PARAMETER MAX or MIN LS UNIT ICC MAX 75 mA IOH MAX -0.4 mA IOL MAX 24 mA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS DATA ENABLE OUTPUTS P=Q P>Q P=QP, Q P>Q P<Q L L L L L L L H H H H XHHH H L

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS518 Logic Diagram (SN74ALS) P = Q G P = Q G 688 8-BIT IDENTITY COMPARATORS

• Totem-Pole Outputs
• Hysteresis at P and Q Inputs (SN74LS)

519PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER INPUT OUTPUT MAX or MIN LS ALS SN74 HC CD74 HC CD74 HCT tPLH 18 12 53 51 51 tPHL 23 20 53 51 51 tPLH 18 12 53 51 51 tPHL 23 20 53 51 51 tPLH 18 12 30 36 36 tPHL 20 22 30 36 36 UNIT: ns P (CD74: A) Q (CD74: B) G (CD74: E) MAX P = Q (CD74: Y) MAX P = Q (CD74: Y) MAX P = Q (CD74: Y) PARAMETER MAX or MIN LS ALS SN74 HC CD74 HC CD74 HCT UNIT ICC MAX 65 19 0.08 0.16 0.16 mA IOH MAX -0.4 -2.6 -4 -4 -4 mA IOL MAX 24 24 444 m A ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS DATA ENABLE OUTPUT P=Q P>Q P=QP, Q P<Q L L G L L H H XH H

(18) (17) (15) (19) (16) (12) (11) (9) (8) (1) (13) (7) (14) (2) (6) D (4) B (3) A G QA QB QC QD RCO R R/C RCK CCLR U/D LOAD ENP ENT CCK R R R (5) C : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 697 SYNCHRONOUS UP/DOWN COUNTERS WITH OUTPUT REGISTERS AND MULTIPLEXED 3-STATE OUTPUTS

• Multiplexed Outputs for Counter or Latched Data
• 3-State Outputs Drive Bus Lines Directly
• Binary Counter, Direct Clear

521PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. INPUT OUTPUT MAX or MIN LS CCK 25 RCK 25 A thru D 30 ENT, ENP 30 U/D 35 th MIN 0 tPLH 40 tPHL 40 tPLH 20 tPHL 20 tPLH 20 tPHL 25 tPLH 20 tPHL 25 tPHL CCLR ↓ Q MAX 40 tPLH 25 tPHL 25 UNIT: ns MAX MAX MAX MIN MIN MAX MAX RCK ↓ R / C RCO Q Q Q CCK ↑ RCO CCK ↓ tsu tw PARAMETER ENT MAX or MIN LS UNIT ICC MAX 70 mA Q -2.6 mA RCO -0.4 mA Q 24 mA RCO 8m AMAX MAX PARAMETER IOH IOL ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

1D (18) (17) (15) (19) (16) (12) (11) (9) (8) (1) (13) (7) (14) (2) (3) (4) (5) (6) D C B A G QA QB QC QD RCO C1 C2 R/C RCK CCLR U/D LOAD ENP ENT CCK : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 699 SYNCHRONOUS UP/DOWN COUNTERS WITH OUTPUT REGISTERS AND MULTIPLEXED 3-STATE OUTPUTS

• Multiplexed Outputs for Counter or Latched Data
• 3-State Outputs Drive Bus Lines Directly
• Binary Counter, Synchronous Clear

523PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. INPUT OUTPUT MAX or MIN LS CCK 25 RCK 25 A thru D 30 ENT, ENP 30 U/D 35 CCLR 30 th MIN 0 tPLH 40 tPHL 40 tPLH 20 tPHL 20 tPLH 20 tPHL 25 tPLH 20 tPHL 25 tPLH 25 tPHL 25 UNIT: ns MAX RCK ↑ MIN MAX MAX MAX MAX Q Q ENT CCK ↑ RCO RCO R/C CCK ↑ Q MIN tsu tw PARAMETER MAX or MIN LS UNIT ICC MAX 70 mA Q MAX -2.6 mA RCO MAX -0.4 mA Q MAX 24 mA RCO MAX 8 mA PARAMETER IOL IOH ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 756 OCTAL BUFFER/DRIVER WITH OPEN-COLLECTOR OUTPUTS

• Eliminate the Need for 3-State Overlap Protection
• pnp Inputs Reduce dc Loading
• Open-Collector Versions of SN74AS240A 2 18 1OE 1A1 1Y1 4 16 1A2 1Y2 6 14 1A3 1Y3 8 12 1A4 1Y4 11 9 2OE 2A1 2Y1 13 7 2A2 2Y2 15 5 2A3 2Y3 17 3 2A4 2Y4 PARAMETER MAX or MIN AS SN74 BCT UNIT ICC MAX 80 86 mA VOH MAX 5.5 5.5 V IOL MAX 64 64 mA PARAMETER INPUT OUTPUT MAX or MIN AS SN74 BCT tPLH 19 11.3 tPHL 6 4.2 tPLH 19.5 16.5 tPHL 7.5 10.3 UNIT:ns A OE Y MAX Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 757 OCTAL BUFFER/DRIVER WITH OPEN-COLLECTOR OUTPUTS

• Eliminate the Need for 3-State Overlap Protection
• pnp Inputs Reduce dc Loading
• Open-Collector Versions of SN74AS241 PARAMETER MAX or MIN AS SN74 BCT SN64 BCT UNIT ICC MAX 95 77 77 mA VOH MAX 5.5 5.5 5.5 V IOL MAX 64 64 64 mA PARAMETER INPUT OUTPUT MAX or MIN AS SN74 BCT SN64 BCT tPLH 18.5 10.1 10.1 tPHL 6 6.6 6.6 tPLH 20 19.7 19.7 tPHL 7 6.9 6.9 tPLH 21 18 18 tPHL 7.5 8.5 8.5 UNIT:ns AY MAX MAX 1OE 2OE MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS 17 3 1A1 1A2 1A3 1A4 1Y1 2OE 2A1 2A2 2A3 2A4 2Y1 1Y2 1Y3 1Y4 2Y2 2Y3 2Y4 1OE

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 760 OCTAL BUFFERS/DRIVERS WITH OPEN-COLLECTOR OUTPUTS

• Open-Collector Outputs Drive Bus Lines or Buffer Memory Address Registers
• pnp Inputs Reduce dc Loading
• Open-Collector Versions of SN74ALS244 and SN74AS244 17 3 181A1 1A2 1A3 1A4 1Y1 2A1 2A2 2A3 2A4 2Y1 1Y2 1Y3 1Y4 2Y2 2Y3 2Y4 2OE1OE PARAMETER MAX or MIN ALS AS SN74 BCT UNIT ICC MAX 19 94 76 mA VOH MAX 5.5 5.5 5.5 V IOL MAX 24 64 64 mA PARAMETER INPUT OUTPUT MAX or MIN ALS AS SN74 BCT tPLH 15 18.5 10 tPHL 12 6 7.2 tPLH 16 18.5 17.5 tPHL 13 7 9.9 UNIT:ns AY Y MAX MAXOE ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 527 804 HEX 2-INPUT NAND DRIVERS

• Y = A•B
• High Capacitive-Drive Capability Logic Diagram PARAMETER MAX or MIN ALS AS SN74 HC UNIT ICC MAX 12 27 0.08 mA IOH MAX -15 -48 -6 mA IOL MAX 24 48 6 mA PARAMETER INPUT OUTPUT MAX or MIN ALS AS SN74 HC tPLH MAX 7 4 25 tPHL MAX 8 4 25 UNIT:ns A, B Y ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS A H L X B L H X OUTPUT L H H Y

ICC MAX 0.0833 mA IOH MAX -6 -48 mA IOL MAX 6 48 mA PARAMETER INPUT OUTPUT MAX or MIN SN74 HCAS tPLH MAX 25 6 tPHL MAX 25 6 UNIT:ns A, B Y ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS PARAMETER MAX or MIN ALS AS SN74 HC UNIT ICC MAX 14 32 0.08 mA IOH MAX -15 -48 -6 mA IOL MAX 24 48 6 mA PARAMETER INPUT OUTPUT MAX or MIN ALS AS SN74 HC tPLH MAX 7 4.3 24 tPHL MAX 8 4.3 24 UNIT:ns A, B Y ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 805 HEX 2-INPUT NOR DRIVERS

• Y = A + B
• High Capacitive-Drive Capability 808 HEX 2-INPUT AND DRIVERS
• Y = A + B
• High Capacitive-Drive Capability 528 Logic Diagram Logic Diagram INPUTS OUTPUT L Y L A H X L X LH B H FUNCTION TABLE INPUTS OUTPUT L Y H A H L X H LL B X FUNCTION TABLE

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN AS ABT LVC 3V UNIT ICC MAX 113 38 0.01 mA IOH MAX -24 -32 -24 mA IOL MAX 48 64 24 mA PARAMETER INPUT OUTPUT MAX or MIN AS ABT LVC MIN 8 2.9 3.3 MIN 8 3.8 3.3 tsu MIN 6 2.1 1.9 th MIN 0 1.3 1.5 tPLH 7.5 6.2 7.3 tPHL 13 6.7 7.3 tPZH 11 5.8 7.6 tPZL 12 6.3 7.6 tPHZ 8 6.7 6.2 tPLZ 8 6.5 6.2 UNIT: ns CLK tw OE OE High Low MAX MAX MAX Q Q Q ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUTS FUNCTION TABLE OUTPUT L Q H OE L L L H XQ 0 H CLK L XX Z D L OE CLK To Nine Other Channels 821 10-BIT BUS-INTERFACE FLIP FLOPS WITH 3-STATE OUTPUTS

• Outputs Have Undershoot-Protection Circuitry
• Power-Up High-Impedance State

R C1 23 : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 823 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

• Functionally Equivalent to AMD’s AM29823 and AM29824
• Outputs Have Undershoot-Protection Circuitry
• Power-Up High-Impedance State FUNCTION TABLE OUTPUT H Q L OE L L L X LL L CLK X XX Q 0 D H CLR L H H H CLKEN INPUTS X L L H HX X Z XX PARAMETER MAX or MIN AS ABT LVC 3V UNIT ICC MAX 103 38 0.01 mA IOH MAX -24 -32 -24 mA IOL MAX 48 64 24 mA INPUT OUTPUT MAX or MIN AS ABT LVC CLK "H" 8 2.9 3.3 CLK "L" 8 3.8 3.3 CLR inactive 82 . 51 DATA 6 2.1 1.3 CLKEN "H" 7.5 2 - CLKEN "L" 7.5 3.3 1.8 DATA - 1.3 2 CLKEN "H" -1- CLKEN "L" 02 1.3 tPLH 7.5 6.8 8 tPHL 13 6.7 8 tPHL CLR Q MAX 15.5 7.1 7.9 tPZH 11 6 7.2 tPZL 12 6.5 7.2 tPHZ 8 7.5 6 tPLZ 8 6.9 6 UNIT: ns OE OE PARAMETER th tw tsu Q MAX MAX MAX Q MIN MIN MIN CLK Q ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

531PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram To Seven Other Channels R CLKEN CLK OE1 CLR OE2 OE3 825 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

• Improved IOH Specifications (Max: -24mA)
• Outputs Have Undershoot-Protection Circuitry
• Power-Up High-Impedance State PARAMETER MAX or MIN AS UNIT ICC MAX 95 mA IOH MAX -24 mA IOL MAX 48 mA INPUT OUTPUT MAX or MIN AS CLR "L" 4 CLK "H" 8 CLK "L" 8 CLR 8 DATA 6 CLKEN 6 th MIN 0 tPLH 7.5 tPHL 13 tPHL CLR Q MAX 15.5 tPZH 11 tPZL 12 tPHZ 8 tPLZ 8 UNIT: ns PARAMETER tw tsu OE OE MIN MIN CLK Q MAX Q MAX MAX Q ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE OUTPUT H Q L OE L L L X LL L CLK X XX Q 0 D H CLR L H H H CLKEN INPUTS X L L H HX X Z XX

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 827 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

• 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) 828 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
• 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
• 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
• 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) To Nine Other Channels OE1 OE2 22 3 To Nine Other Channels OE1 OE2 22 3 PARAMETER MAX or MIN ABT AC ACT LVC 3V UNIT ICC MAX4 0 0.08 0.08 0.01 mA IOH MAX -32 -24 -24 -24 mA IOL MAX 64 2 42 42 4 m A PARAMETER INPUT OUTPUT MAX or MIN ABT AC ACT LVC tPLH 4.8 8.7 9.2 6.7 tPHL 4.7 9.7 11.2 6.7 tPZH 5.9 9.7 11.3 7.3 tPZL 6.9 13 14 7.3 tPHZ 6.8 9.1 12 6.7 tPLZ 6.9 8.8 11.6 6.7 UNIT: ns MAX MAX MAX YOE OE A ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE OUTPUT L Y H OE1 L L L L X H XZ H OE2 INPUTS H XX Z A L PARAMETER MAX or MIN AC ACT LVC 3V UNIT ICC MAX 0.08 0.08 0.01 mA IOH MAX -24 -24 -24 mA IOL MAX 24 24 24 mA PARAMETER INPUT OUTPUT MAX or MIN AC ACT LVC tPLH 9.5 10.2 6.7 tPHL 10.4 11.7 6.7 tPZH 10.7 12.1 7.3 tPZL 13.2 14.7 7.3 tPHZ 9.6 12.3 6.7 tPLZ 9.2 11.7 6.7 UNIT: ns OE Y MAX MAX MAX A OE ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE OUTPUT H Y L OE1 L L L L X H X ZH OE2 INPUTS H XX Z A L

PARAMETER MAX or MIN ALS AS SN74 HC UNIT ICC MAX 16 36 0.08 mA IOH MAX -15 -48 -6 mA IOL MAX 24 48 6 mA PARAMETER INPUT OUTPUT MAX or MIN ALS AS SN74 HC tPLH MAX 9 6.3 25 tPHL MAX 8 6.3 25 UNIT:ns A, B Y ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 533 Logic Diagram 1112 INPUTS OUTPUT H Y H A H X L X LL B H FUNCTION TABLE 832 HEX 2-INPUT OR DRIVERS

• Y = A + B
• High Capacitive-Drive Capability

R EN EN A1–A8 CLK PARITY B1–B8 2–9 16–23 : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

535PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. CLR † The state of ERR before any changes at CLR, CLK, or point P A data to B bus and generate parity A data to B bus and generate inverted parity INPUTS OUTPUTS AND I/O FUNCTIONCLK Ai Σ OF H’s Bi Σ OF H’s B PARITY ERROEA X Odd Even Odd Even Odd Even X X X X XX X X X XX X L H NAAH H HH H H H OEB L NALL H LA NC L L H H L H No No Isolation Check error flag register B data to A bus and check parity L H A NA NA NA HNA NA NA ZZZ B NA Odd Even NA NAL CLR Clear INPUTS INTERNAL TO DEVICE OUTPUT PRE-STATE OUTPUT ERR FUNCTION CLK POINT P ERRn-1† XX X X H H H L H H HH L L X L H Sample FUNCTION TABLE PARAMETER MAX or MIN ABT UNIT ICC MAX 38 mA IOH MAX -32 mA IOL MAX 64 mA PARAMETER INPUT OUTPUT MAX or MIN ABT tPLH 5.3 tPHL 5.3 tPLH 11.2 tPHL 11 tPZH 10.5 tPZL 10 tPLH CLR 5.2 tPHL CLK 6.2 tPZH 6.5 tPZL 6.5 tPHZ 7.9 tPLZ 8.1 UNIT: ns A A or B PARITY OE OE OE PARITY ERR A,B, or PARITY A,B, or PARITY MAX B or A MAX MAX MAX MAX MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 841 10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

• 3-State Buffer-Type Outputs Drive Bus Lines Directly
• Bus-Structured Pinout
• Provide Extra Bus-Driving Latches Necessary for Wider Address/Data Paths or Buses with Parity
• Power-Up High-Impedance State PARAMETER MAX or MIN ALS AS ABT LVC 3V UNIT ICC MAX 62 94 38 0.01 mA IOH MAX -2.6 -24 -32 -24 mA IOL MAX 24 48 64 24 mA PARAMETER INPUT OUTPUT MAX or MIN ALS AS ABT LVC tw 20 4 3 .3 3.3 tsu 10 2.5 2.5 2.1 tsu 10 2.5 1.5 2.1 th 5 2.5 1.5 1 tPLH 13 6.5 6.2 6.7 tPHL 13 10.5 6.2 6.7 tPLH 21 12 6.5 7.6 tPHL 26 12 6.7 7.6 tPZH 12 14 5.3 7.2 tPZL 12 16 6.3 7.2 tPHZ 10 8 7 .1 5.9 tPLZ 12 8 6 .5 5.9 UNIT: ns LE Q MAX MIN DQ MAX High Low OE OE Q MAX Q MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE OUTPUT H Q L OE L L H H L H XQ 0 H LE INPUTS L XX Z D L

537PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram OE PRE CLR LE To Eight Other Channels R 843 9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

• 3-State Buffer-Type Outputs Drive Bus Lines Directly
• Bus-Structured Pinout
• Provides Extra Bus-Driving Latches Necessary for Wider Address/Data Paths or Buses with Parity
• Power-Up High-Impedance State PARAMETER MAX or MIN ALS AS ABT UNIT ICC MAX 67 92 34 mA IOH MAX -2.6 -24 -32 mA IOL MAX 24 48 64 mA INPUT OUTPUT MAX or MIN ALS AS ABT CLR "L" 35 4 5.5 PRE "L" 35 4 4.5 LE "H" 20 4 - LE "L" -4 3 . 4 LE "L" 10 2. 52 . 5 LE "H" 10 2.5 3 PRE inactive -1 5 1 . 6 CLR inactive -1 42 LE "L" 52 . 51 LE "H" 52 . 5 1.5 tPLH 13 6.5 6.7 tPHL 18 9 7.2 tPLH 21 12 7.2 tPHL 26 12 6.9 tPLH -- 7.1 tPHL 23 13 8 tPLH 22 10 7.4 tPHL -- 7.2 tPZH 12 10.5 5.7 tPZL 14 13.5 6.5 tPHZ 10 8 6.8 tPLZ 12 8 5.9 UNIT: ns PARAMETER tw MIN tsu MIN Q MAXOE MIN DQ MAX Q MAX Q th MAX Q MAX MAX Q LE CLR PRE OE ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUTS FUNCTION TABLE OUTPUT L H PRE OECLR L H X X L X XH H LE X HL L HH H H HL X Q 0 D X X H L L H H H X L L L L L L HXX Z

B1–B8 A1–A8 LE OEA OEB EN EN MUX1 P 2–9 23–16 : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

539PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ABT UNIT ICC MAX 38 mA IOH MAX -32 mA IOL MAX 64 mA PARAMETER INPUT OUTPUT MAX or MIN ABT tPLH 5.3 tPHL 5.3 tPLH 11.2 tPHL 11 tPLH 10.5 tPHL 10 tPLH CLR ERR MAX 6.2 tPLH 6 tPHL 6.6 tPLH 11.7 tPHL 12.8 tPZH 6.7 tPZL 6.7 tPHZ 7.9 tPLZ 8.1 UNIT: ns MAX ERR OE OE ERR MAX MAX MAX MAX MAX A PARITY MAX A or B B or A OE PARITY LE A or B or PARITY B or RARITY A or B or PARITY ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS CLR A data to B bus and generate parity A data to B bus and generate inverted parity INPUTS OUTPUT AND I/Os FUNCTIONLE Ai Σ OF H Bi† Σ OF H B PARITY ERR ‡OEA X Odd Even L Odd H Even Odd Even X XX X X X XX X L H NAAH H HH H H H OEB L NALL H LA NC NC L L HL H H L L H Isolation§ (parity check) Store error flag B data to A bus and check parityH HH H A NA NA NA XX XX XH Clear error flag registerL NA NA HNA NA NA ZZZ B NA Odd Even NA NALL HL CLR Clear INPUTS INTERNAL TO DEVICE OUTPUT PRE-STATE OUTPUT ERR FUNCTION LE POINT P ERRn-1† X X X H HH H H L L L L H HHH L LL L H L X L H L Sample Pass StoreX H L X FUNCTION TABLE ERROR-FLAG FUNCTION TABLE The state of ERR before changes at CLR, LE, or point P NA = not applicable, NC = no change, X = don't care † Summation of high-level inputs includes PARITY along with Bi inputs. ‡ Output states shown assume ERR was previously high. § In this mode, ERR (when clocked) shows inverted parity of the A bus.

OPER = 0 : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 857 HEX 2-TO-1 UNIVERSAL MULTIPLEXERS WITH 3-STATE OUTPUTS

• Select True or Complementary Data
• Perform AND/NAND (Masking) of A or B Operand
• Cascadable to Expand Number of Operands
• Detect Zeros on A or B Operands
• 3-State Outputs Interface Directly with System Bus

541PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. MAX or MIN ALS AS UNIT ICCZ MAX 36 135 mA ICCL MAX 33 175 mA Y MAX -2.6 -15 mA OPER = 0 MAX -2.6 -2 mA Y MAX 24 48 mA OPER = 0 MAX 24 20 mA PARAMETER IOL IOH PARAMETER INPUT OUTPUT MAX or MIN ALS AS tpd S0 or S1 Y 33 13 tpd COMP Y 18 13 tpd A or B OPER = 0 37 14 tpd S0 to S1 OPER = 0 23 18 ten 35 12 tdis 23 11 ten 24 12 tdis 21 9 ten 20 12 tdis 27 9 ten 25 12 tdis 19 9 ten 25 13 tdis 20 9 UNIT: ns tpd tpd MAX MAXY inverting Y non-inverting COMP A or B (COMP = "H") A or B (COMP = "L") MAX MAX COMP OPER = 0 Y Y OPER = 0 OPER = 0 S0 to S1 1214 MAX MAX MAX MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS OUTPUTS COMP S1 S0 Y OPER = 0 LL LA H = all A inputs L LL HB H = all B inputs L LH L A•B A•B Z LH H L L HL LH = all A inputs L HL H A BH = all B inputs L HH L Z HH H Z Z

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 861 10-BIT TRANSCEIVERS WITH 3-STATE OUTPUTS PARAMETER MAX or MIN ABT LVC 3V UNIT ICC MAX 38 0.01 mA IOH MAX -32 -24 mA IOL MAX 64 24 mA PARAMETER INPUT OUTPUT MAX or MIN ABT LVC tPLH 5.2 6.4 tPHL 4.9 6.4 tPZH 5.9 7 tPZL 6.9 7 tPHZ 7.5 5.9 tPLZ 7.1 5.9 UNIT: ns MAX MAX MAXOEAB or OEBA B or A A or B B or A OEAB or OEBA B or A ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS A data to B bus B data to A bus Isolation INPUTS OPERATION H OEBAOEAB L HH H L LL Latch A and B (A = B) FUNCTION TABLE A1 B1 OEBA OEAB To Nine Other Channels 22 3

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. A1 B1 OEBA2 OEAB2 To Eight Other Channels OEAB1 OEBA1 1 22 3 863 9-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

• 3-State Outputs PARAMETER MAX or MIN ABT LVC 3V UNIT ICC MAX 38 0.01 mA IOH MAX -32 -24 mA IOL MAX 64 24 mA PARAMETER INPUT OUTPUT MAX or MIN ABT LVC tPLH 5.7 6.1 tPHL 3.9 6.1 tPZH 5.5 7.2 tPZL 5.4 7.2 tPHZ 6.7 6.3 tPLZ 6.9 6.3 UNIT: ns OE A or B MAX MAXA or B B or A OE A or B MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS L OPERATION B to AL Latch A and B OEAB1 X IsolationX X X X X L H X H H X X X A to BX LL L OEAB2 L OEBA1 L OEBA2 L L X L L H H H H H H H H H

A R C1 22 QA B R C1 21 QB4 C R C1 20 QC5 D R C1 19 QD6 E R C1 18 QE7 ENP CLK F R C1 17 QF8 G R

16 QG9

H R

15 QH10

13 RCO

(asynchronous clear) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 867 SYNCHRONOUS 8-BIT UP/DOWN COUNTERS

• Fully Programmable with Synchronous Counting and Loading
• Asynchronous Clear
• Ripple-Carry Output for n-Bit Cascading

545PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ALS AS UNIT ICC MAX 45 195 mA IOH MAX -0.4 -2 mA IOL MAX 8 20 mA PARAMETER INPUT OUTPUT MAX or MIN ALS AS fmax MIN 35 50 tw 14 10 10 10 t su 10 4 15 8 12 10 -1 0 12 40 12 40 t h tPLH 14 22 tPHL 14 16 tPLH 16 11 tPHL 16 15 tPLH 14 10 tPHL 91 7 tPLH -1 4 tPHL -1 7 tPHL S0, S1 (clear mode) Any Q MAX 26 - tPLH 16 - tPHL 16 - tPHL UNIT fmax : MHz other : ns S0 or S1 (count up/down) S0 or S1 (clear mode) S0 and S1 low (clear) S0 high and S1 low (count down) S0 and S1 high (count up) S0 high after S1 ↑ or S1 high after S0 ↑ CLK CLK ENT ENP Data input A-H ENP or ENT S0 low and S1 high (load) Data input A-H RCO RCO RCO RCO Any Q RCO MAX MAX MAX S0 and S1 (clear) MIN MAX MAX 16MAX MIN MIN CLK (clock) ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE L H H L FUNCTION Count down Clear Count up Load L H H L

A R C1 22 QA B R C1 21 QB4 C R C1 20 QC5 D R C1 19 QD6 E R C1 18 QE7 ENP CLK F R C1 17 QF8 G R H R (asynchronous clear) : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 869 SYNCHRONOUS 8-BIT UP/DOWN COUNTERS

• Fully Programmable with Synchronous Counting and Loading
• Synchronous Clear
• Ripple-Carry Output for n-Bit Cascading

547PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ALS AS UNIT ICC MAX 45 195 mA IOH MAX -0.4 -2 mA IOL MAX 8 20 mA PARAMETER INPUT OUTPUT MAX or MIN ALS AS fmax MIN 35 45 tw MIN 14 11 tsu 10 5 15 9 13 11 13 11 13 50 13 50 t h tPLH 14 35 tPHL 14 18 tPLH 16 11 tPHL 16 15 tPLH 14 15 tPHL 91 7 tPLH -1 9 tPHL -1 8 tPLH 15 - tPHL 15 - tPLH 16 - tPHL 12 - UNIT fmax : MHz other : ns CLK Data input A-H ENP or ENT S0 low and S1 high (load) RCO MAX RCO MAX RCO MIN Any Q MAX RCO MAX Data input A-H S0 and S1 low (clear) S0 high and S1 low (count down) S0 and S1 high (count up) S0 high after S1 ↑ or S1 high after S0 ↑ MAX MIN CLK RCO MAX CLK ENT ENP (count up/down) (clear/load) ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE L H H L FUNCTION Count down Clear Count up Load L H H L

Three Identical Channels Not Shown 2A0 2A1 2A2 2A3 DQB1 1A0 1A1 1A2 1A3 DQA1 RAM 16×1 A A,D A A A,D A RAM 16×1 : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 870 DUAL 16-BY 4-BIT REGISTER FILES

• 3-State Buffer-Type Outputs Drive Bus Lines Directly
• Each Register File Has Individual Write-Enable Controls and Address Lines

549PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE FILE SELECT H L S1S0 H L 1R to A, 1R to B H L H L FILE SEL 2R to A, 1R to B 1R to A, 2R to B 2R to A, 2R to B H L H L A to 1R, 1R to B H L H L A to 2R, 1R to B A to 1R, 2R to B A to 2R, 2R to B H L H L H L H L H L H L H L H L 1R to A, B to 1R B to 1R A to 2R, B to 1R A to 1R, B to 2R B to 2R 2R to A, B to 1R 1R to A, B to 2R 2R to A, B to 2R L S3S2 LA out B A out, B out I/O SEL HA in B A in, B outL HL H H A out B A out, B in A in Bin A in, B INPUT/OUTPUT PARAMETER INPUT OUTPUT MAX or MIN ALS AS tw MIN 12 12 tsu 55 15 15 12 12 t h 00 12 12 ta(A) Any A Any DQ MAX 19 15 ta(S) S0 Any DQA 15 13 S1 Any DQB 15 13 tdis S2 Any DQA 14 11 S3 Any DQB 14 11 ten S2 Any DQA 17 12 S3 Any DQB 17 12 tpd W Any DQ 23 19 DA DQB 26 22 DQB DQA 26 22 UNIT: ns MAX MAX MAX MAX Select before write Data before write ↑ Address before write ↓ MIN MIN Select before write ↓ Data before write ↑ Address before write ↓ write PARAMETER MAX or MIN ALS AS UNIT ICC MAX 110 190 mA IOL MAX 24 48 mA IOH MAX -2.6 -15 mA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

PARAMETER MAX or MIN ALS AS UNIT ICC MAX 31 129 mA IOH MAX -2.6 -15 mA IOL MAX 24 48 mA INPUT OUTPUT MAX or MIN ALS AS CLR low 15 5 LE high 10 5 tsu 10 2 th 7 4.5 tPLH 14 9.5 tPHL 14 7.5 tPLH 22 13 tPHL 21 7.5 tPHL CLR Q MAX 20 9 tPZH 18 6.5 tPZL 18 10.5 tPHZ 10 7.5 tPLZ 15 7.5 UNIT: ns MAX LE OE OE D PARAMETER tw MIN Q MAX Q MAX Q MAX Q ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS 550 Logic Diagram : OBSOLETED or NOT RECOMMENDED NEW DESIGNS R 1DD1 R 1DD2 R 1DD3 R 1DD4 OE LE CLR 873 DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS

• 3-State Buffer-Type Outputs Drive Bus Lines Directly
• Bus-Structured Pinout
• Asynchronous Clear FUNCTION TABLE INPUTS L L ENABLE LE H OUTPUT H L L L XH CLR L Z OE D L L X H H H X X X LX H H

PARAMETER MAX or MIN ALS AS UNIT ICC MAX 32 160 mA IOH MAX -2.6 -15 mA IOL MAX 24 48 mA PARAMETER INPUT OUTPUT MAX or MIN ALS AS fmax MIN 3 0 125 tw 10 2 16.5 3 16.5 4 t su 15 2 10 4 t h MIN 0 1 tPLH 14 8.5 tPHL 14 10.5 tPHL CLR QM A X 1 7 9 . 5 tPZH 18 7 tPZL 18 10.5 tPHZ 10 6 tPLZ 12 7.5 UNIT fmax : MHz other : ns CLK OE MIN PRE or CLR low CLK "H" CLK "L" MAX MAX MAXOE Data PRE or CLR inactive Q Q Q MIN ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS 551 Logic Diagram PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 874 DUAL 4-BIT D-TYPE EDGE-TRIGGERD FLIP-FLOPS WITH 3-STATE OUTPUTS

• 3-State Buffer-Type Outputs Drive Bus Lines Directly
• Bus-Structured Pinout
• Asynchronous Clear R 1DD1 R 1DD2 R 1DD3 R 1DD4 OE CLK CLR FUNCTION TABLE INPUTS L L CLK H OUTPUTS H L L L XH CLR L Z OE D L L X H H H X X X LX

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS552 Logic Diagram S 1DD1 S 1DD2 S 1DD3 S 1DD4 OE CLK PRE 876 DUAL 4-BIT D-TYPE EDGE-TRIGGERD FLIP-FLOPS WITH 3-STATE OUTPUTS

• 3-State Buffer-Type Outputs Drive Bus Lines Directly
• Bus-Structured Pinout
• Asynchronous Clear

553PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ALS AS UNIT ICC MAX 31 160 mA IOH MAX -2.6 -15 mA IOL MAX 24 48 mA INPUT OUTPUT MAX or MIN ALS AS fmax MIN 30 80 PRE "L" 10 4.5 CLK "H" 16.5 6.2 CLK "L" 16.5 6.2 Data 15 4.5 PRE inactive 10 5 th MIN 0 2 tPLH 14 8.5 tPHL 14 10.5 tPHL PRE Q MAX 19 9.5 tPZH 18 7 tPZL 18 11 tPHZ 10 7 tPLZ 13 7 UNIT fmax : MHz, other : ns MAX MAX MINtsu CLK OE OE Q Q Q PARAMETER MAX tw MIN ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS L L CLK H L L L L XH PRE H Z OE QD L L X H H H X X X LX FUNCTION TABLE (each filip-flop) INPUTS OUTPUT

4MSB = P0 = Q0 P1 = Q1 P2 = Q2 P3 = Q3 P5 = Q5 P7 = Q7 P6 = Q6 PLE P > QIN P < QIN L/A P < QOUT P > QOUT : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 885 8-BIT MAGNITUDE COMPARATORS

• SN54AS885 Latchable P-Input Ports with Power-Up Clear
• Choice of Logical or Arithmetic (Two's Complement) Comparison
• Data and PLE Inputs Utilize pnp Input Transistors to Reduce dc Loading Effects
• Cascadable to n Bits While Maintaining High Performance

555PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN AS UNIT ICC MAX 210 mA IOH MAX -2 mA IOL MAX 20 mA PARAMETER INPUT OUTPUT MAX or MIN AS tsu 2 th 4 tPLH 13 tPHL 13 tPLH 8 tPHL 8 tPLH 17.5 tPHL 15 UNIT: ns Any P or Q data input P < QOUT, P > QOUT L / A MIN MAX Data before PLE ↓ Data after PLE ↓ P < QIN, P > QIN P < QOUT, P > QOUT P < QOUT, P > QOUT MAX MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS OUTPUTS COMPARISON L/A DATA P0–P7, Q0–Q7 P > QIN P < QIN P > QOUT P < QOUT Logical H P > Q X X H L Logical H P < Q X X H Logical† HP = Q H or L H or L H or L H or L Arithmetic L P AG Q X X L Arithmetic L Q AG P X X L H LH Arithmetic† LP = Q H or L H or L H or L H or L † In these cases, P > QOUT follows P > QIN and P < QOUT follows P < QIN. AG = arithmetically greater than

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 990 8-BIT D-TYPE TRANSPARENT READ-BACK LATCH

• 3-State I/O-Type Read-Back Inputs
• True Logic Outputs
• Bus-Structured Pinout MAX or MIN ALS UNIT ICC MAX 70 mA Q -2.6 mA D -0.4 mA Q2 4 m A D8 m AI OL IOH PARAMETER MAX MAX PARAMETER INPUT OUTPUT MAX or MIN ALS tw MIN 10 tsu 10 t h MIN 5 tPLH 17 tPHL 24 tPLH 26 tPHL 26 ten MAX 21 tdis MAX 19 UNIT: ns Data before OERB MIN LE high Data before LE ↓ Data after LE ↓ OERB LE DQ Q D MAX MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

557PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram To Eight Other Channels 2 23 OERB LE 1D 1Q OEQ CLR R MAX or MIN ALS UNIT ICC MAX 80 mA Q -2.6 mA D -0.4 mA Q2 4 m A D8 m A MAX MAX PARAMETER I OH IOL PARAMETER INPUT OUTPUT MAX or MIN ALS tw 10 tsu 10 t h MIN 5 tPLH 14 tPHL 16 tPLH 20 tPHL 25 tPHL Q2 0 D2 6 t en 21 tdis 14 ten 18 tdis 14 UNIT:ns Data affter LE ↓ OEQ D LE CLR OERB MIN MIN C "H" CLR "L" Data befor LE ↓ Data befor OERB ↓ MAX MAX MAX Q Q Q D MAX MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS 992 9-BIT D-TYPE TRANSPARENT READ-BACK LATCH WITH 3-STATE OUTPUTS

• 3-State I/O-Type Read-Back Inputs
• True Logic Outputs
• Bus-Structured Pinout
• Designed with Nine Bits for Parity Applications

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS558 Logic Diagram To Nine Other Channels 22 3 OERB LE 1D 1Q MAX or MIN ALS UNIT ICC MAX 82 mA Q -2.6 mA D -0.4 mA Q2 4 m A D8 m A MAX MAX PARAMETER I OH IOL PARAMETER INPUT OUTPUT MAX or MIN ALS tw MIN 10 tsu 10 t h MIN 5 tPLH 14 tPHL 18 tPLH 21 tPHL 27 ten 21 tdis 16 UNIT:ns LE OERB MIN D Q MAX MAX MAX D C "H" Data befor LE Data befor OERB ↓ Data affter LE ↓ Q ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS 994 10-BIT D-TYPE TRANSPARENT READ-BACK LATCH

• 3-State I/O-Type Read-Back Inputs
• True Logic Outputs
• Bus-Structured Pinout

559PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram To Seven Other Channels OE T/C CLR RD R EN CLK 996 8-BIT D-TYPE EDGE-TRIGGERED READ- BACK LATCHES

• 3-State I/O-Type Read-Back Inputs
• True Logic Outputs
• T/C Determines True or Complementary Data at Q Outputs MAX or MIN ALS ALS-1 UNIT ICC MAX 85 85 mA Q2 4 4 8 m A D8 8 m A Q -2.6 -2.6 mA D -0.4 -0.4 mA PARAMETER I OL MAX IOH MAX PARAMETER INPUT OUTPUT MAX or MIN ALS ALS-1 tw 10 10 14.5 14.5 14.5 14.5 t su 15 15 10 10 15 15 10 10 t h 00 t PLH 28 28 tPHL 28 28 tPLH CLR ( T/C = L ) 27 27 tPHL CLR ( T/C = H ) 23 23 tPLH 23 23 tPHL 23 23 tPHL CLR D MAX 30 30 ten*3 16 16 tdis*4 19 19 ten*3 16 16 tdis*4 19 19 ten*3 15 15 tdis*4 10 10 UNIT: ns Q EN DRD T / C D RD high after CLK ↑ *2 CLK ( T/C = H or L ) Data after CLK ↑ CLK high before EN ↑ *1 CLR high (inactive) before CLK ↑ EN low after CLK ↑ MIN MIN MIN CLR low CLK low CLK high Data before CLK EN low before CLK ↑ MAX MAXOE MAX MAX MAX MAX Q Q Q ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 1000 QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS/DRIVERS

• Buffer Version of SN74ALS00A
• Driver Version of SN74AS00
• High Capacitive-Drive Capability 1004 HEX INVERTING DRIVERS
• Driver Version of SN74ALS04B and SN74AS04
• High Capacitive-Drive Capability 6A 6Y 5A 5Y 4A 4Y 3A 3Y 2A 2Y 1Y1A PARAMETER MAX or MIN ALS AS UNIT ICC MAX 7.8 19 mA IOH MAX -2.6 -48 mA IOL MAX 24 48 mA PARAMETER INPUT OUTPUT MAX or MIN ALS AS tPLH 84 tPHL 74 UNIT: ns A or B Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS H L BA H X OUTPUT Y H X L L H PARAMETER MAX or MIN ALS AS UNIT ICC MAX 12 27 mA IOH MAX -15 -48 mA IOL MAX 24 48 mA PARAMETER INPUT OUTPUT MAX or MIN ALS AS tPLH 74 tPHL 64 UNIT: ns A or B Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE OUTPUT Y H L INPUT A H L

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 1005 HEX INVERTING BUFFERS WITH OPEN-COLLECTOR OUTPUTS

• Buffer Version of SN74ALS05A 1008 QUADRUPLE 2-INPUT POSITIVE-AND BUFFER/DRIVER
• Buffer Version of SN74ALS08
• Driver Version of SN74AS08 6A 6Y 5A 5Y 4A 4Y 3A 3Y 2A 2Y 1Y1A 1A 1 PARAMETER MAX or MIN ALS UNIT ICC MAX 12 mA VOH MAX 5.5 V IOL MAX 24 mA PARAMETER INPUT OUTPUT MAX or MIN ALS tPLH 30 tPHL 10 UNIT: ns AY M A X ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE OUTPUT Y H L INPUT A H L PARAMETER MAX or MIN ALS AS UNIT ICC MAX 9.3 22 mA IOH MAX -2.6 -48 mA IOL MAX 24 48 mA PARAMETER INPUT OUTPUT MAX or MIN ALS AS tPLH 96 tPHL 96 UNIT: ns A or B Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS H L BA H X OUTPUT Y H X L L L

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS562 Logic Diagram1034 HEX DRIVERS

• SN74AS1034A Offer High Capacitive-Drive Capability
• Noninverting Drivers PARAMETER MAX or MIN ALS AS UNIT ICC MAX 14 35 mA IOH MAX -15 -48 mA IOL MAX 24 48 mA PARAMETER INPUT OUTPUT MAX or MIN ALS AS tPLH 86 tPHL 86 UNIT: ns AY MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE OUTPUT Y H L INPUT A H L 6A 6Y 5A 5Y 4A 4Y 3A 3Y 2A 2Y 1Y1A 1032 QUADRUPLE 2-INPUT POSITIVE-OR BUFFERS/DRIVERS
• Y = A + B
• Driver Version of SN74AS32
• High Capacitive-Drive Capability Logic Diagram PARAMETER MAX or MIN ALS AS UNIT ICC MAX 10.6 24 mA IOH MAX -2.6 -48 mA IOL MAX 24 48 mA PARAMETER INPUT OUTPUT MAX or MIN ALS AS tPLH A or B Y MAX 9 6.3 tPHL A or B YM A X 1 2 6 . 3 UNIT:ns ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE (each gate) INPUTS OUTPUT H Y H A H X L X LL B H

HEX NONINVERTING BUFFERS WITH OPEN- COLLECTOR OUTPUTS

• Noninverting Buffers with Open-Collector Outputs 6A 6Y 5A 5Y 4A 4Y 3A 3Y 2A 2Y 1Y1A PARAMETER MAX or MIN ALS UNIT ICC MAX 14 mA VOH MAX 5.5 V IOL MAX 24 mA PARAMETER INPUT OUTPUT MAX or MIN ALS tPLH 30 tPHL 12 UNIT: ns AY M A X ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE OUTPUT Y H L INPUT A H L 1240 OCTAL BUFFER AND LINE DRIVER WITH 3-STATE OUTPUTS
• Low-Power Versions of SN74ALS240A
• 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
• 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers PARAMETER MAX or MIN ALS UNIT ICCZ MAX 13 mA ICCL MAX 14 mA IOH MAX -15 mA IOL MAX 16 mA PARAMETER INPUT OUTPUT MAX or MIN ALS tPLH MAX 13 tPHL 13 tPZH MAX 20 tPZL 22 tPHZ MAX 10 tPLZ 13 UNIT: ns OE Y A OE Y Y ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS Logic Diagram PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 17 3 1A1 1A2 1A3 1A4 1Y1 2A1 2A2 2A3 2A4 2Y1 1Y2 1Y3 1Y4 2Y2 2Y3 2Y4 1OE 2OE

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 1244 OCTAL BUFFERS AND DRIVERS WITH 3-STATE OUTPUTS

• 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
• pnp Inputs Reduce dc Loading
• Low-Power Versions of SN74ALS244 Series 17 3 1A1 1A2 1A3 1A4 1Y1 2A1 2A2 2A3 2A4 2Y1 1Y2 1Y3 1Y4 2Y2 2Y3 2Y4 2OE 1OE PARAMETER MAX or MIN ALS UNIT ICCZ MAX 20 mA ICCL MAX 17 mA IOH MAX -15 mA IOL MAX 16 mA PARAMETER INPUT OUTPUT MAX or MIN ALS tPLH 14 tPHL 14 tPZH 22 tPZL 22 tPHZ 13 tPLZ 16 UNIT: ns MAX Y Y A OE OE Y MAX MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS 1245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
• Low-Power Versions of 4ALS245 Series DIR A1 B1 21 8 To Seven Other Transceivers OE PARAMETER MAX or MIN ALS UNIT ICCZ MAX 36 mA ICCL MAX 33 mA IOH MAX -15 mA IOL MAX 16 mA PARAMETER INPUT OUTPUT MAX or MIN ALS tPLH 13 tPHL 13 tPZH 25 tPZL 25 tPHZ 12 tPLZ 18 UNIT: ns A or B B or A OE OE A or B A or B MAX MAX MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE CONTROL INPUTS H L DIR H X OPERATION A data to B bus L B data to A bus Isolation OE L

565PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 1404 OSCILLATOR DRIVER FOR CRYSTAL OSCILLATOR OR CERAMIC RESONATOR LVC 1.8V LVC 2.5V LVC LVC 5V UNIT 0.01 0.01 0.01 0.01 mA -4 -8 -24 -32 mA 48 2 4 32 mA 2- - - m AIOL (XOUT) MAX PARAMETER ICC IOH (OSCOUT, XOUT, Y outputs) IOH (OSCOUT, XOUT, Y outputs) MAX or MIN MAX MAX MAX PARAMETER INPUT OUTPUT MAX or MIN LVC 1.8V LVC 2.5V LVC LVC tPLH 17.3 7.4 6.4 5.3 tPHL 17.3 7.4 6.4 5.3 tPLH 15.8 5.8 5.4 4.6 tPHL 15.8 5.8 5.4 4.6 tPLH 25.7 7.1 7.8 6.7 tPHL 25.7 7.1 7.8 6.7 tPLH 24.5 12 12.7 11.2 tPHL 24.5 12 12.7 11.2 UNIT: ns OSCOUT CTRL XOUT MAX MAX MAX XIN A MAXY XIN XOUT ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLES INPUTS OUTPUTS CTRL XIN XOUT OSCOUT HL H L HH H LX L L H INPUT A OUTPUT Y LH HL Logic Diagram CTRL XOUT OSCOUT Y XIN 3 A

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS566 Logic Diagram 1640 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

• Lower-Power Versions of SN74ALS640B
• Inverting Logic
• 3-State Outputs A1 B1 OE DIR To Seven Other Transceivers 21 8 FUNCTION TABLE CONTROL INPUTS H L DIR H X OPERATION L Isolation OE L A data to B bus B data to A bus PARAMETER MAX or MIN ALS UNIT ICC MAX 32 mA IOH MAX -15 mA IOL MAX 16 mA PARAMETER INPUT OUTPUT MAX or MIN ALS tPLH 15 tPHL 10 tPZH 20 tPZL 22 tPHZ 10 tPLZ 13 UNIT: ns MAX MAX MAX B or A A or B A or B A or B OE OE ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

567PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram 1645 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

• Lower-Power Versions of SN74ALS645A
• 3-State Outputs A1 B1 OE DIR To Seven Other Transceivers 21 8 PARAMETER MAX or MIN ALS UNIT ICC MAX 38 mA IOH MAX -15 mA IOL MAX 16 mA PARAMETER INPUT OUTPUT MAX or MIN ALS tPLH 13 tPHL 13 tPZH 25 tPZL 25 tPHZ 12 tPLZ 18 UNIT: ns MAX MAX A or B B or A A or B A or B OE OE MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE CONTROL INPUTS H L DIR H X OPERATION A data to B bus L B data to A bus Isolation OE L

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 2240 OCTAL BUFFERS AND LINE/MOS DRIVERS WITH 3-STATE OUTPUTS

• I/O Ports Have 25-Ω Series Resistors, So No External Resistors Are Required (SN74ALS2240, SN74ABT2240A)
• Output Ports Have Equivalent 33-Ω Series Resistors, So No External Resistors Are Required (SN74BCT2240) PARAMETER MAX or MIN ALS SN74 BCT ABT UNIT ICCZ MAX 20 8 0.25 mA ICCL MAX 23 76 30 mA IOH MAX -15 -12 -32 mA IOL MAX 15 12 12 mA PARAMETER INPUT OUTPUT MAX or MIN ALS SN74 BCT ABT tPLH 10 5.7 4.8 tPHL 10 4.4 5.4 tPZH 17 9.3 5.2 tPZL 20 12 .4 6.8 tPHZ 10 8.7 6.4 tPLZ 15 10 .6 6.2 UNIT: ns AY MAX OE Y MAX Y MAXOE ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

569PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram 2241 OCTAL BUFFERS AND LINE/MOS DRIVERS WITH 3-STATE OUTPUTS

• Output Ports Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required (SN74ABT2241A)
• Output Ports Have Equivalent 33-Ω Series Resistors, So No External Resistors Are Required (SN74BCT2241) 21 8 1Y1 1OE 1A1 41 6 1Y21A2 61 4 1Y31A3 81 2 1Y41A4 11 9 2Y1 2OE 2A1 13 7 2Y22A2 15 5 2Y32A3 17 3 2Y42A4 PARAMETER MAX or MIN SN74 BCT ABT UNIT ICCZ MAX 9 0.25 mA ICCL MAX 76 30 mA IOH MAX -12 -32 mA IOL MAX 12 12 mA PARAMETER INPUT OUTPUT MAX or MIN SN74 BCT ABT tPLH 4.9 4.7 tPHL 6.9 5.6 tPZH 8.9 5.8 tPZL 10.3 8.4 tPHZ 8.7 6.6 tPLZ 11.3 6.4 tPZH 8.9 5.8 tPZL 10.3 8.4 tPHZ 8.7 6.6 tPLZ 11.3 6.4 UNIT: ns MAX Y Y Y Y Y MAX MAX MAX MAX 2OE A 1OE 1OE 2OE ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 2244 OCTAL BUFFERS AND LINE/MOS DRIVERS WITH 3-STATE OUTPUTS

• Output Ports Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required (SN74ABT2244A)
• Output Ports Have Equivalent 33-Ω Series Resistors, So No External Resistors Are Required (SN74BCT2244)
• Output Ports Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required (SN74LVC2244A) FUNCTION TABLE INPUTS H L A H X OUTPUT Y H LL OE L Z PARAMETER MAX or MIN ALS SN74 BCT ABT LVC 3V UNIT ICCZ MAX 23 10 0.25 0.01 mA ICCL MAX 22 77 30 0.01 mA IOH MAX -15 -12 -32 -12 mA IOL MAX 15 12 12 12 mA PARAMETER INPUT OUTPUT MAX or MIN ALS SN74 BCT ABT LVC tPLH 16 4.9 4.7 5.5 tPHL 17 6.7 5.6 5.5 tPZH 17 8.7 5.5 7.1 tPZL 14 10.4 8.3 7.1 tPHZ 9 7.8 6.6 6.8 tPLZ 9 9.8 5.8 6.8 UNIT: ns AY MAX OE Y MAX Y MAXOE ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 2245 OCTAL TRANSCEIVER AND LINE/MOS DRIVERS WITH 3-STATE OUTPUTS

• B Port Has Equivalent 33-Ω Series Resistors, So No External Resistors Are Required (SN74BCT2245)
• B-Port Outputs Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required (SN74ABT2245)
• Outputs Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required (SN74ABTR2245)
• All Outputs Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required (SN74LVCR2245)
• B-Port Outputs Have Equivalent 22-Ω Series Resistors, So No External Resistors Are Required (SN74LVTH2245) DIR OE To Seven Other Channels PARAMETER MAX or MIN SN74 BCT ABT ABTR LVTH LVCR 3V UNIT ICCZ MAX 15 0.25 0.25 0.19 0.01 mA ICCL MAX 100 32 32 5 0.01 mA IOH (A port) MAX -3 -32 -12 -32 -12 mA IOH (B port) MAX -12 -12 -12 -12 -12 mA IOL (A port) MAX 24 64 12 64 12 mA IOL (B port) MAX 12 12 12 12 12 mA PARAMETER INPUT OUTPUT MAX or MIN SN74 BCT ABT ABTR LVTH LVCR tPLH 7 3.6 3.8 3.5 6.3 tPHL 7.7 4 4.5 3.5 6.3 tPLZ 7.6 4.5 4.8 5 7.8 UNIT: ns AB MAX A MAXB B MAX B MAX A MAX A MAX OE OE OE OE ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS H L DIR H X OPERATION Isolation LB data to A bus A data to B bus L OE

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS572 Logic Diagram OE LE To Seven Other Channels PARAMETER MAX or MIN F UNIT ICC MAX 66 mA IOH MAX -3 mA IOL MAX 12 mA PARAMETER INPUT OUTPUT MAX or MIN F tw MIN 6 tsu MIN 2 th MIN 6 tPLH 9 tPHL 7 tPLH 13 tPHL 8 tPZH 12 tPZL 9.5 tPHZ 7.5 tPLZ 6 UNIT:ns OE MAX MAX MAX MAX Q Q Q Q LE OE LE high Data before LE Data after LE ↓ D ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE (each latch) INPUTS H L L L LE D X L H H OUTPUT Q X H L X Z H L OE 2373 25-Ω OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

• 3-State True Outputs with 25-Ω Sink Resistors
• Full Parallel Access for Loading
• Buffered Control Inputs

573PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. VS 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 VCC Vbat SD G VCOMP PARAMETER MAX or MIN SN74 BCT UNIT ICC MAX 3 mA IOH MAX -0.4 mA Ibat (Output low) MAX 3 mA IOL (Y Output) MAX 8 mA IOL (I/S Output) MAX 20 mA PARAMETER INPUT OUTPUT MAX or MIN SN74 BCT tPLH 12 tPHL 12 tPLH 10 tPHL 11 tPLH 12 tPHL 12 tPLH 250 tPHL 250 tPLH 250 tPHL 250 UNIT: ns A or B Any Y MAX Any Y MAXAny G VS MAX SD VCC VCC Any Y MAX Any Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS H H X OUTPUTS X L H X L SELECT H X L H X L H L CONTROL 1B 1A 1Y0 X L LL LL LL X H X H H HH L L XX XX 1GG SD H H H H H H L 1Y1 H H H H H L 1Y2 H H H H H L 1Y3 H H H H HHH INPUTS H H X OUTPUTS X H X L SELECT H X L H X L H L CONTROL 2B 2A 2Y0 X L L L L X H X H H HH L L XX XX 2GG SD H H H H H H L 2Y1 H H H H H L 2Y2 H H H H H L 2Y3 H H H H HHH H H H H 2414 MEMORY DECODER WITH ON-CHIP SUPPLY VOLTAGE MONITOR

• Built-In Supply-Voltage Monitor for VCC
• Separate Enable Inputs for Easy Cascading Logic Diagram

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 2541 OCTAL LINE DRIVER/MOS DRIVER WITH 3-STATE OUTPUTS

• Outputs Have 25-Ω Series Resistor So No External Resistors Are Required 2827 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
• Output Ports Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required (SN74ABT2827)
• Output Ports Have Equivalent 25-Ω Resistors; No External Resistors Are Required (SN74BCT2827C) A1 2 Y118 OE2 OE1 All output resistors are 25 Ω. OE1 OE2 A1 Y1 To Nine Other Channels PARAMETER MAX or MIN ALS UNIT ICCZ MAX 22 mA ICCL MAX 25 mA IOH MAX -0.4 mA IOL MAX 12 mA PARAMETER INPUT OUTPUT MAX or MIN ALS tPLH 15 tPHL 12 tPZH 15 tPZL 20 tPHZ 10 tPLZ 12 UNIT: ns AY MAX Y MAX OE OE Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS PARAMETER MAX or MIN SN74 BCT ABT UNIT ICCZ MAX 6 0.25 mA ICCL MAX 40 40 mA IOH MAX -1 -12 mA IOL MAX 12 12 mA PARAMETER INPUT OU TPUT MAX or MIN SN74 BCT ABT tPLH 6 5.5 tPHL 7.8 5.1 tPZH 10.7 6.7 tPZL 12.9 7.8 tPHZ 13 7.2 tPLZ 10 7.5 UNIT: ns A OE OE MAX MAX MAX Y Y Y ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 2828 10-BIT BUS/MOS MEMORY DRIVERS WITH 3-STATE INVERTING

• Output Ports Have Equivalent 33-Ω Series Resistors, So No External Resistors Are Required (SN74BCT2828) To Nine Other Channels OE1 OE2 22 3 PARAMETER MAX or MIN SN74 BCT UNIT ICCZ MAX 6 mA ICCL MAX 40 mA IOH MAX -1 mA IOL MAX 12 mA PARAMETER INPUT OUTPUT MAX or MIN SN74 BCT tPLH 6.6 tPHL 5 tPZH 9 tPZL 11.5 tPHZ 10.8 tPLZ 8.7 UNIT: ns OE Y MAX AY MAX OE Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 2952 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

• Two 8-Bit Back-to-Back Registers Store Data Flowing in Both Directions
• Noninverting Outputs
• 3-State Outputs

577PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. MAX or MIN SN74 BCT ABT LVTH LVC 3V UNIT ICC MAX 55 35 5 0.01 mA A -3 -32 -32 -24 mA B -15 -32 -32 -24 mA A 24 64 64 24 mA B 64 64 64 24 mA MAXIOH IOL MAX PARAMETER PARAMETER INPUT OUTPUT MAX or MIN SN74 BCT ABT LVTH LVC fmax MIN 125 150 150 150 tw 4 3.3 3.3 3.3 4 3.3 3.3 3.3 tsu 2.5 2.5 1.5 1.3 2.5 2.5 1.5 - 23 1.5 1.1 23 1.9 - th 1.5 1.5 1 1.1 2.5 2 1.2 1.1 tPLH CLKBA 9 5.9 4.6 8.2 tPHL CLKAB 10.5 6.3 4.6 8.2 tPZH OEBA 8.2 5.6 4.6 7.8 tPZL OEAB 12.9 6.6 4.6 7.8 tPHZ OEBA 8.4 6.4 5.4 7.8 tPLZ OEAB 7 6.2 5.1 7.8 UNIT fmax : MHz other : ns MAX MAX CLKENAB or CLKENBA Low A,B A,B MINCLK "H" CLK "L" MIN MAX CLKENAB or CLKENBA A or B after CLK A,B MIN A or B before CLK High A or B before CLK Low CLKENAB or CLKENBA High ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS X FUNCTION TABLE† INPUTS CLKAB OUTPUT B0H A L L X CLKENAB XX BOEAB L L L H H L H Z X XB 0X LH or L † A-to-B data flow is shown; B-to-A data flow is similar but uses CLKENBA, CLKBA, and OEBA. ‡ Level of B before the indicated steady-state input conditions were established

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 2953 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS

• Two 8-Bit, Back-to-Back Registers Store Data Flowing in Both Directions
• Inverting Outputs
• 3-State Outputs MAX or MIN SN74 BCT UNIT ICC MAX 55 mA A- 3 m A B -15 mA A2 4 m A B6 4 m AI OL MAX PARAMETER IOH MAX PARAMETER INPUT OUTPUT MAX or MIN SN74 BCT fmax MIN 110 tw 4.5 4.5 t su 2.5 2.5 t h 1.5 tPLH CLKBA 9.5 tPHL CLKAB 10.2 tPZH OEBA 8.8 tPZL OEAB 14 tPHZ OEBA 9.1 tPLZ OEAB 7.6 UNIT fmax : MHz other : ns A,B A,B MAX MAX MAX CLKENAB or CLKENBA A or B CLK "H" CLK "L" A or B High A,B MIN MIN MINA or B Low CLKENAB or CLKENBA High CLKENAB or CLKENBA Low ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS X FUNCTION TABLE† INPUTS CLKAB OUTPUT A0H A L L X OEAB XX BOEAB L L L H H L H L Z † A-to-B data flow is shown; B-to-A data flow is similar but uses CEBA, CLKBA, and OEBA. ‡ Level of B before the indicated steady-state input conditions were established

579PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 4002 DUAL 4-INPUT POSITIVE-NOR GATES

• Y = A + B + C + D Logic Diagram nA nB nY nC nD PARAMETER MAX or MIN SN74 HC CD74 HC UNIT ICC MAX 0.02 0.04 mA IOH MAX -4 -4 mA IOL MAX 4 4 mA PARAMETER INPUT OUTPUT MAX or MIN SN74 HC CD74 HC tPLH MAX 28 30 tPHL MAX 28 30 UNIT:ns YA, B, C, D ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS INPUTS L BA X X OUTPUT Y H X L L C X H L H L L L D X X L X XHX H X X X FUNCTION TABLE NOTES: H = High Voltage Level L = Low Voltage Level X = Irrelevant

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS580 Logic Diagram 5(13) D Q CP Q R D Q CP Q R 4(12) D Q CP Q R 3(11) D Q CP Q R 2(10) DATA MR 6(14) 7(15) CP 9(1) PARAMETER MAX or MIN CD74 HC UNIT ICC MAX 0.16 mA IOH MAX -4 mA IOL MAX 4 mA PARAMETER INPUT OUTPUT MAX or MIN CD74 HC fmax MIN 20 tW 24 t SUL MIN 18 tSUH MIN 18 tH MIN 0 tPLH 54 tPHL 54 tPLH 83 tPHL 83 tPLH 98 tPHL 98 UNIT fmax : MHz other : ns MIN Data-In to CP Clock Qn MAX Clock MR Data-In to CP MAX MAX MR MR Qn (Clock High) Qn (Clock Low) ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS CP X D X X l h R H L L L OUTPUT L L H q’0 L q’1 q’0 q’0 L q’2 q’1 q’1 L q’3 q’2 q’2 Q3Q0 NOTES: H= High Voltage Level h= High Voltage Level One Set-up Time Prior to the Low to High Clock Transition L= Low Voltage Level l= Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition X= Don’t Care. ↑ = Low to High Clock Transition ↓ = High to Low Clock Transition q’n = Lower case letters indicate the state of the referenced output one set-up time prior to the Low to High clock transition. 4015 DUAL 4-STAGE STATIC SHIFT REGISTER

581PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram VCC GND nZ nY nE PARAMETER MAX or MIN CD74 HC UNIT ICC MAX 0. 04 mA RON MAX 480 Ω PARAMETER INPUT OUTPUT MAX or MIN CD74 HC tPLH 18 tPHL 18 tPZH 57 tPZL 57 tPHZ 44 tPLZ 44 UNIT:ns MAX En Z En Z Switch In Switch Out MAX MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS NOTES: H= High Level Voltage L= Low Level Voltage FUNCTION TABLE INPUT nE H L SWITCH ON OFF 4016 QUAD BILATERAL SWITCH

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS582 Logic Diagram MR (15) (3) (2) (4) (7) (10) (1) (5) (6) (9) (11) TC (12) CP (14) CE (13) R R R R R INPUTS H L CP OUTPUT STATE† X No Change CE X X H L X X X H L MR No Change Increments Counter Increments Counter No Change No Change L L L L L FUNCTION TABLE NOTES: H = High Level L = Low Level ↑ = High to Low Transition ↓ = Low to High Transition X = Don’t Care † If n < 5 TC = H, Otherwise = L PARAMETER MAX or MIN SN74 HC CD74 HC UNIT ICC MAX 0.08 0.16 mA IOH MAX -4 -4 mA IOL MAX 4 4 mA PARAMETER INPUT OUTPUT MAX or MIN SN74 HC CD74 HC fmax MIN 25 20 20 24 20 24 13 22 13 - t h MIN 5 0 tPLH 58 69 tPHL 58 69 tPLH 63 75 tPHL 63 75 tPLH 58 69 tPHL 58 69 tPLH -6 9 tPHL 58 69 UNIT fmax : MHz, other : ns CE to CP MIN MIN MAX MAX MAX MAX 0 to 9 0 to 9 0 to 9 TCMR CE to CP CLK Inactive t w tsu MR CE CP CP MR ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS 4017 DECADE COUNTERS/DIVIDER

583PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram (SN74HC) R T R T R T R T R T R T R T R T R T R T R T R T R T R T 9 7 5 4 61 31 21 41 5 1 2 3 CLR CLK QA QD QE QF QI QL QM QNQG QH QJ QK 4020 14-STAGE BINARY COUNTERS

• Same Pinouts as CMOS4020
• VCC: 2V to 6V PARAMETER MAX or MIN SN74 HC CD74 HC CD74 HCT UNIT ICC MAX 0.08 0.16 0.16 mA IOH MAX -4 -4 -4 mA IOL MAX 4 4 4 mA INPUT OUTPUT MAX or MIN SN74 HC CD74 HC CD74 HCT fmax MIN 22 20 16 CLK (CD74: CP) 23 24 30 CLR high 18 24 30 tsu CLK (CD74: CP) CLR inactive before CLK ↓ MIN 15 - - tPLH 38 42 60 tPHL 38 42 60 tPHL CLR (CD74: CP) Any MAX 35 51 60 UNIT fmax : MHz other : ns MAX MINtw PARAMETER CLK (CD74: CP) QA (CD74: Q 1) ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE (SN74) CLR OUTPUTCLK No Change Advance to Next State All Outputs Are Low L H L X NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, = ↑ Transition from Low to High Level, ↓ = Transition from High to Low.

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS584 4024 7-STAGE BINARY COUNTERS Logic Diagram Q1’ CP Q CP Q R CP Q CP Q R CP Q CP Q R CP Q CP Q R CP Q CP Q R CP Q CP Q R CP Q CP Q R CP MR GND VCC PARAMETER MAX or MIN SN74 HC CD74 HC CD74 HCT UNIT ICC MAX 0.08 0.16 0.16 mA IOH MAX -4 -4 -4 mA IOL MAX 4 4 4 mA PARAMETER INPUT OUTPUT MAX or MIN SN74 HC CD74 HC CD74 HCT fmax MIN 22 20 16 tw 23 24 30 20 24 30 t su MIN 20 - - tPLH 30 42 60 tPHL 30 42 60 tPLH -5 1 6 0 tPHL 33 51 60 UNIT fmax : MHz, other : ns MR (CLR) any Q MAX MAX CP (CLK) (QA) MINCP (CLK) MR (CLR H) CLR iow before CLK ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE (SN74) CLR OUTPUTCLK No Change Advance to Next State All Outputs Are Low L H L X NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, = ↑ Transition from Low to High Level, ↓ = Transition from High to Low.

585PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram (SN74HC) R T R T R T R T R T R T R T R T R T R T R T R T 95 3 24 1 3 12 14 15 1 CLR CLK QA QD QE QH QK QLQF QG QI QJ QB QC 4040 12-STAGE BINARY COUNTERS

• Same Pinouts as CMOS4040
• VCC: 2V to 6V PARAMETER MAX or MIN SN74 HC CD74 HC CD74 HCT LV LV 5V UNIT ICC MAX 0.08 0.16 0.16 - 0.02 mA IOH MAX -4 -4 -4 -6 -12 mA IOL MAX 4 4 4 6 12 mA INPUT OUTPUT MAX or MIN SN74 HC CD74 HC CD74 HCT LV LV fmax MIN 22 20 1 65 08 0 CLK (CP) 23 24 30 5 5 CLR (MR) high 18 24 30 5 5 tsu CLK (CP) CLR(MR) inactive before CLK(CP) ↓ MIN 15 - - 5 5 tPLH 38 42 60 17.5 10.5 tPHL 38 42 60 17.5 10.5 tPHL CLR (MR) Any MAX 35 51 60 18.5 12 UNIT fmax : MHz other : ns tw PARAMETER MIN CLK (CP) Q A (Q1) MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE CLR OUTPUTCLK No Change Advance to Next State All Outputs Are Low L H L X NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition from Low to High Level, ↓ = Transition from High to Low.

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS586 Logic Diagram 4046 PHASE-LOCKED-LOOP WITH VCO DEMOUT PC2OUT p n GND VCC PCPOUT PC3OUT PC1OUT DOWN RD Q Q D CP RD Q Q D CP UP VCC VCC RD Q Q SD INH VCOIN VCO - + VCOOUT COMPIN - + SIGINC1BC1A VREF 67 4 3 1 4 - + Pin Descriptions PIN NUMBER SYMBOL NAME AND FUNCTION 1P C P OUT Phase Comparator Pulse Output 2P C 1 OUT Phase Comparator 1 Output

3 COMPIN Comparator Input

61 A Capacitor C1 Connection A

C C1B Capacitor C1 Connection B

8 GND Ground (0V)

10 DEM OUT Demodulator Output

11 R 1 Resistor R1 Connection

12 R 2 Resistor R2 Connection

13 PC2 OUT Phase Comparator 2 Output

14 SIG IN Signal Input

15 PC3 OUT Phase Comparator 3 Output

16 V CC Positive Supply Voltage

587PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN CD74 HC CD74 HCT UNIT ICC MAX 0.16 0.16 mA IOH MAX -4 -4 mA IOL MAX 4 4 mA PARAMETER INPUT OUTPUT MAX or MIN CD74 HC CD74 HCT tPLH SIGIN 60 68 tPHL COMPIN 60 68 tPLH SIGIN 90 102 tPHL COMPIN 90 102 tPLH SIGIN 74 87 tPHL COMPIN 74 87 tTLH 22 22 tTHL 22 22 tPZH SIGIN 80 90 tPZL COMPIN 80 90 tPLZ SIGIN 95 102 tPHZ COMPIN 95 102 UNIT:ns AY MAX MAX MAXPCIOUT MAX PC2OUT PC2OUT MAX MAX PCPOUT PC3OUT ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS YA PARAMETER MAX or MIN CD74 HC UNIT ICC MAX 0.04 mA IOH MAX -4 mA IOL MAX 4 mA PARAMETER INPUT OUTPUT MAX or MIN CD74 HC tPLH 26 tPHL 26 UNIT:ns MAXnYnA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS A Y PARAMETER MAX or MIN CD74 HC UNIT ICC MAX 0.04 mA IOH MAX -4 mA IOL MAX 4 mA PARAMETER INPUT OUTPUT MAX or MIN CD74 HC tPLH 26 tPHL 26 UNIT:ns nA nY MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS 4049 HEX INVERTING BUFFERS 4050 HEX NON-INVERTING BUFFERS

Logic Diagram (SN74LV) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. COM INH C B A 11 PARAMETER MAX or MIN CD74 HC CD74 HCT LV LV 5V UNIT ICC MAX 0.16 0.16 - 0.02 mA RON MAX 180 180 190 100 Ω PARAMETER INPUT OUTPUT MAX or MIN CD74 HC CD74 HCT LV LV tPLH 18 18 12 8 tPHL 18 18 12 8 tPZH 68 83 25 18 tPZL 68 83 25 18 tPHZ 68 68 25 18 tPLZ 68 68 25 18 UNIT: ns INH COM or Yn (An) MAX MAX MAX COM or Yn (An) Yn (An) or COM INH COM or Yn (An) ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE (SN74) INPUTS AB L L ON CHANNEL H INH H L L X L C X L H L H L H L L X L L L L None L L H H L L L L H H H H H H 4051 8-CHANNEL ANALOG MULTIPLEXERS / DEMULTIPLEXERS

Logic Diagram (SN74LV) 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 1-COM INH B A 2-COM : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 4052 DUAL 4-CHANNEL ANALOG MULTIPLEXERS / DEMULTIPLEXERS PARAMETER MAX or MIN CD74 HC CD74 HCT LV LV 5V UNIT ICC MAX 0.16 0.16 - 0.02 mA RON MAX 180 180 190 100 Ω PARAMETER INPUT OUTPUT MAX or MIN CD74 HC CD74 HCT LV LV tPLH 18 18 12 8 tPHL 18 18 12 8 tPZH 98 105 25 18 tPZL 98 105 25 18 tPHZ 75 75 25 18 tPLZ 75 75 25 18 UNIT: ns MAX INH COM or Yn (An) MAX COM or Yn (An) Yn (An) or COM MAXINH COM or Yn (An) ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE (SN74) INPUTS AB L L ON CHANNEL 1Y0, 2Y0 1Y2, 2Y2 H INH H L L X 1Y3, 2Y3 L HL X None L L H H 1Y1, 2Y1

591PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram (SN74LV) 1Y0 1Y1 2Y0 2Y1 3Y0 1-COM INH B A 3-COM 3Y1 2-COM C 4053 TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS PARAMETER MAX or MIN CD74 HC CD74 HCT LV LV 5V UNIT ICC MAX 0.16 0.16 - 0.02 mA RON MAX 180 180 190 100 Ω PARAMETER INPUT OUTPUT MAX or MIN CD74 HC CD74 HCT LV LV tPLH 18 18 12 8 tPHL 18 18 12 8 tPZH 66 72 25 18 tPZL 66 72 25 18 tPHZ 63 66 25 18 tPLZ 63 66 25 18 UNIT: ns COM or Yn (An, Bn, Cn) Yn (An, Bn, Cn) or COM MAX MAX INH COM or Yn (An, Bn, Cn) MAX INH COM or Yn (An, Bn, Cn) ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE (SN74) INPUTS AC L L ON CHANNEL 1Y0, 2Y0, 3Y0 1Y0, 2Y1, 3Y0 H INH H L L X 1Y1, 2Y1, 3Y0 L HL L L L L X None L L H L H L H H B X L L H H L L H H L L H H 1Y1, 2Y0, 3Y0 1Y0, 2Y0, 3Y1 1Y0, 2Y1, 3Y1 1Y1, 2Y1, 3Y1 1Y1, 2Y0, 3Y1

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS592 Function Diagram GND CLOCK INPUT VCC Ka MODE SELECT INPUTS LATCH ENABLE Kb Kc J10 J11 J12 J13 J14 J15 J16 PRESETTABLE LOGIC PROGRAM JAM INPUTS (BCD) FIRST COUNTING SECTION LAST COUNTING SECTION +1, 2, 2, 4, 8 RECOGNITION GATING PRESET ENABLE DIVIDE-BY-N OUTPUT OUTPUT STAGE Function 4059 MODE CONTROL INTERMEDIATE COUNTING SECTION PARAMETER MAX or MIN CD74 HC UNIT ICC MAX 0.16 mA IOH MAX -4 mA IOL MAX 4 mA PARAMETER INPUT OUTPUT MAX or MIN CD74 HC fmax MIN 18 tw MIN 27 tsu MIN 22 tPLH 60 tPHL 60 tPLH 53 tPHL 53 UNIT fmax : MHz other : ns CP CP Kb, Kc to CP MAX MAX Q Q CP LE ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUTSELECTMODE KbKa L H X H L H L H L H H L H L L H H H Kc FUNCTION TABLE 4059 CMOS PROGRAMMABLE DIVIDE-BY-N COUNTER

593PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram (SN74HC) 4060 ASYNCHRONOUS 14-STAGE BINARY COUNTERS AND OSCILLATORS

• Same Pinouts as CMOS4060
• Allow Design of Either RC or Crystal Oscillator Circuits
• VCC: 2V to 6V R T R T R T R T R T R T R T R T 61 41 31 5 1 2 3 11CLKI QI QL QM QNQG QH QJ R T QF R T R T R T R T R T QD QE 12CLR CLKO CLKO PARAMETER MAX or MIN SN74 HC CD74 HC CD74 HCT UNIT ICC MAX 0.08 0.16 0.16 mA IOH MAX -4 -4 -4 mA IOL MAX 4 4 4 mA PARAMETER INPUT OUTPUT MAX or MIN SN74 HC CD74 HC CD74 HCT fmax MIN 22 20 20 tw 23 24 24 23 24 38 t su CLR inactive before CLK ↓ MIN 40 - - tPLH 123 90 100 tPHL 123 90 100 tPHL CLR (MR) Any MAX 35 53 66 UNIT fmax : MHz other : ns MIN CLKI (φI) Q D (Q4) MAX CLKI (φI) CLR high (MR) ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE (SN74) INPUTS CLR OUTPUTS CLKI Q D to QN CLKO No Change Advance to Next State All Outputs are Low L HH L LX CLKO

Logic Diagram (SN74) A VCC VCC B One of Four Switches C : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 4066 QUADRUPLE BILATERAL SWITCHES

• Same Pinouts as CMOS4016, 4066
• Low On-State Impedance: 50-Ω TYP at VCC = 6V
• Individual Switch Controls
• Extremely Low Input Current
• High On-Off Output Voltage Ratio
• Low Crosstalk Between Switches PARAMETER MAX or MIN SN74 HC CD74 HC CD74 HCT AHC LV LV 5V UNIT RON MAX 106 128 128 100 190 100 Ω PARAMETER INPUT OUTPUT MAX or MIN SN74 HC CD74 HC CD74 HCT AHC LV LV tPLH 15 18 18 8 12 8 tPHL 15 18 18 8 12 8 tPZH 45 30 36 16 22 16 tPZL 45 30 36 16 22 16 tPHZ 50 45 53 16 22 16 tPLZ 50 45 53 16 22 16 UNIT: ns MAX MAX MAX A or B (Y or Z) A or B (Y or Z) A or B (Y or Z) B or A (Z or Y) C (E) C (E) ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE (SN74) INPUT (C) SWITCH OFF H L ON NOTE: H = High Level L = Low Level

595PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Function Diagram E PN PN I15 14 - OUTPUT CIRCUITS SAME AS ABO VE (WITH ANALOG INPUTS) I1 TO I14 BINARY

1 OF 16

SN = 5 STAGES E = 4 STAGES 13S3

1 COMMON

ICC MAX 0.16 0.16 mA RON MAX 240 240 Ω PARAMETER INPUT OUTPUT MAX or MIN CD74 HC CD74 HCT tPLH 22 22 tPHL 22 22 tPZH 83 90 tPZL 83 90 tPHZ 83 83 tPLZ 83 83 tPZH 90 90 tPZL 90 90 tPHZ 87 87 tPLZ 87 87 UNIT:ns MAX MAX MAX COMON I/O MAX MAX Switch In COMON I/O E Sn CO MON I/O EC O M ON I/O Sn CO MON I/O ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE X X SELECTED CHANNEL X X X E None 000 00 0 NOTES: H= High Level L= Low Level X= Don’t Care 4067 16-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS596 Logic Diagram nA nB nY nC PARAMETER MAX or MIN SN74 HC CD74 HC CD74 HCT UNIT ICC MAX 0.02 0.04 0.04 mA IOH MAX -4 -4 -4 mA IOL MAX 4 4 4 mA PARAMETER INPUT OUTPUT MAX or MIN SN74 HC CD74 HC CD74 HCT tPLH A, B or C Y MAX 25 30 36 tPHL A, B or C Y MAX 25 30 36 UNIT:ns ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS INPUTS H L BA H X OUTPUT Y H HX L L C H X L X XX H FUNCTION TABLE NOTES: H = High Voltage Level L = Low Voltage Level X = Don’t Care 4075 TRIPLE 3-INPUT OR GATES

• Y = A + B + C

597PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram FFO DQ CPCP FF1 FF2 FF3 FF4 FF5 FF6 FF7 CP CP Q D QS1 QS2 L7L6L5L4L3L2L1LO STR STR Q DATA CP STR OE OE OE PARAMETER MAX or MIN CD74 HC CD74 HCT UNIT ICC MAX 0.16 0.16 mA IOL MAX 4 4 mA IOH MAX -4 -4 mA PARAMETER INPUT OUTPUT MAX or MIN CD74 HC CD74 HCT tW MIN 24 24 tWH MIN 24 24 tSU 15 15 30 30 t H 34 t PLH 45 - tPHL 45 - tPLH 41 - tPHL 41 - tPLH 59 - tPHL 59 - tPLH 54 - tPHL 54 - tPZH 53 - tPZL 53 - tPLZ 38 - tPHZ 38 - UNIT:ns Data STR Qn Qn Qn CP CP CP STR OE OE QS1 QS2 Qn MAX MAX MAX MAX MIN MIN MAX MAX CP STR Data STR ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS CP OE H L L H H H STR H L H H X X D H L X X X H PALALLEL OUTPUT Z L H Qn-1 Qn-1 NC NC Z NC NC Z Z QnQ0 SERIAL OUTPUT NC Q’6 NC Q’6 Q’7 NC Q’6 NC Q’6 NC NC Q’7 QS2QS1‡ NOTES: †. H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, NC = No charge, Z = High Impedance Off-state, ↑ = Transition from Low to High Level, ↓ = Transition from High Low. ‡. At the positive clock edge the information in the seventh resister stage is transferred to the 8th register stage and QS1 output. 4094 8-STAGE SHIFT AND STORE BUS REGISTER, THREE-STATE

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS598 Logic Diagram VCC VEE nZ nY E LOGIC LEVEL CONV. VCC VEE TO 3 OTHER SWITCHES nS PARAMETER MAX or MIN CD74 HC CD74 HCT UNIT ICC MAX 0.32 0.32 mA RON MAX 270 270 Ω PARAMETER INPUT OUTPUT MAX or MIN CD74 HC CD74 HCT tPLH 18 18 tPHL 18 18 tPZH 62 66 tPZL 62 85 tPLZ 62 75 tPHZ 62 - tPZH 53 60 tPZL 53 75 tPLZ 53 - tPHZ 53 66 UNIT:ns nS MAX Switch outSwitch in Z Z E MAX MAX EZ MAX nS Z MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS INPUTS SWITCH OFF E H L LO N OFF S X L H FUNCTION TABLE 4316 QUAD ANALOG SWITCH WITH LEVEL TRANSLATION

599PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram A COMMON 15S0 11LE 7E1 8E2 MULTIPLEXER/ DEMULTIPLEXER CHANNEL ADDRESS LATCH PARAMETER MAX or MIN CD74 HC CD74 HCT UNIT ICC MAX 0.32 0.32 mA RON MAX 240 240 Ω PARAMETER INPUT OUTPUT MAX or MIN CD74 HC CD74 HCT tW MIN 30 28 tsu MAX 18 18 tH MIN 5 5 tPLH 11 11 tPHL 11 11 tPZH 90 113 tPZL 90 113 tPZH 90 113 tPZL 90 113 tPLZ 75 83 tPHZ 75 83 tPLZ 75 90 tPHZ 75 90 tPLZ 83 90 tPHZ 83 90 tPHZ 83 98 tPLZ 83 98 UNIT:ns VOS VOS LE Sn MAX MAX MAX MAX MAX MAX MAX V OS VOS VOS VOS LE Sn to LE Sn to LE Switch In Switch Out E1, E2, LE Sn ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS H L L L L L L L L H L H “ON”† SWITCCHES LE = H None NOTES: †W hen LE is low S0-S2 data are latched and switches cannot change state. H = High Voltage Level, L = Low Voltage Level, X = Don’t Care XXX L L H H L L H H H H H H H H H L L H H L L H H L H L H L L H 4351 ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LATCH

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS600 Function Diagram TG A COMMON OUT/IN 16181915 A3 A2 A1 A0 BINARY TO

1 OF 4

ICC MAX 0.32 mA RON MAX 240 Ω PARAMETER INPUT OUTPUT MAX or MIN CD74 HC tW MIN 30 tsu MIN - tH MIN 5 tPLH 11 tPHL 11 tPZH 105 tPZL 105 tPZH 113 tPZL 113 tPLZ 83 tPHZ 83 UNIT:ns MAX MAX MAX MAX Switch In LE Sn to LE Sn to LE Switch Out E1, E2, LE V OS VOS VOS Sn E1, E2, LE ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS H L L L L H L H “ON”† SWITCCHES LE = H A3, B3 None A0, B0 A1, B1 A2, B2NOTES: †W hen LE is low S0-S2 data are latched and switches cannot change state. H = High Voltage Level, L = Low Voltage Level, X = Don’t Care XX H H H L L H H L L H 4352 ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LATCH

601PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram4374 OCTAL EDGE-TRIGGERED D-TYPE DUAL-RANK FLIP-FLOP WITH 3-STAE OUTPUTS

• 3-State Outputs Drive Bus Lines Directly CLK 1Q1 OE To Seven Other Channels PARAMETER MAX or MIN AS UNIT ICC MAX 150 mA IOH MAX -15 mA IOL MAX 48 mA PARAMETER INPUT OUTPUT MAX or MIN AS fmax MIN 125 tw MIN 4 tsu MIN 4 th MIN 1 tPLH 8 tPHL 8 tPZH 6 tPZL 8 tPHZ 6.5 tPLZ 7 UNIT fmax : MHz other : ns MAX MAX MAX CLK OE OE Q Q Q ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS H L D H X OUTPUT Q Z LL L CLK XX QO H OE L L

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS602 Logic Diagram a b c d e f g LATCH DQ Q LELE BL LELE LATCH D Q Q Q Q LELE LELE LATCH DQ LELE LELE D Q LELE LE LE LT LELE LE 4511 BCD-TO-7 SEGMENT LATCH/DECODER/DRIVERS

603PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN CD74 HC CD74 HCT UNIT ICC MAX 0.16 0.16 mA IOH MAX -7.4 -4 mA IOL MAX 4 4 mA PARAMETER INPUT OUTPUT MAX or MIN CD74 HC CD74 HCT tW MIN 24 24 tsu MIN 18 24 tH MIN 3 5 tPLH 90 90 tPHL 90 90 tPLH 81 81 tPHL 81 81 tPLH 66 66 tPHL 66 66 tPLH 48 50 tPHL 48 50 UNIT:ns MAX MAX MAX MAX Latch Enable Dn to LE Dn to LE a to g a to g a to g a to g Dn LE BL LT ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE LE H X X L BL LT H H XL X D2 D1 D0 X X X X X X XXXX X LLL LL LL LL L L H H H L H L L L H H H L H L L L H H H L H L L L H H H L H a H b H c H d H e H f H g H LLLLL L L L LL LLL LLLLLLL LLLLLLL LLLLLLL LLLLLLL LLLLLLL L HH H H HH H H H HH H H H HHH L H H H H H H H H HHHHH HHH L HH HH H HH H L H LL L LL L LLLL L HHH L H H L LL L L L L L LH LH H LH H LH H LH H LH H H H H H L L L L L L L H H H H H H H H L H H H H LH H LH H LH H LH H LH H LH H LH H LH H LH H LH H H H Blank Blank Blank Blank Blank Blank Blank Display X = Don’t care † Depends on BCD code previously appied when LE = L NOTES: Display is blank for all illegal input codes (BCD > HLLH).

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS604 Logic Diagram A0 S Q Q Q Q Q S S S R R R R LE E Q Q Q Y10 Y11 Y12 Y13 Y14 Y15 PARAMETER MAX or MIN SN74 HC CD74 HC CD74 HCT UNIT ICC MAX 0.08 0.16 0.16 mA IOH MAX -4 -4 -4 mA IOL MAX 4 4 4 mA PARAMETER INPUT OUTPUT MAX or MIN SN74 HC CD74 HC CD74 HCT tw MIN 20 22 45 tsu MIN 25 30 30 th MIN 505 tPLH MAX 58 83 83 tPHL 58 83 83 tPLH MAX 58 68 75 tPHL 58 68 75 tPLH MAX 44 53 60 tPHL 44 53 60 UNIT:ns LE (LE) LE (LE) LE (LE) YA0, 1, 2, 3 (A, B, C, D) Y YE (G) LE (LE) ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS (LE = H) DECODER INPUTS ADDRESSED OUTPUT HA3 A2 A1 A0 LL L L L Y 0 LL L H Y 1 LL L L Y 2 LL L H Y 3 LL H L Y 4 LL H H Y 5 LL H L Y 6 LL H H Y 7 LH L L Y 8 LH L L H H L L H H L LH Y 9 LH L H L Y10 LH L H H Y11 LH H L L Y12 LH H L H Y13 LH H H L Y14 LH H H H Y15 HX X X X All outputs = L FUNCTION TABLE E H = high, L = low, X = don’t care 4514 4-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES

605PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram A0 S Q Q Q Q Q S S S R R R R LE E Q Q Q Y10 Y11 Y12 Y13 Y14 Y15 4515 4-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES (LE = H) DECODER INPUTS ADDRESSED OUTPUT LA3 A2 A1 A0 LL L L L Y 0 LL L H Y 1 LL L L Y 2 LL L H Y 3 LL H L Y 4 LL H Y 5 LL H L Y 6 LL H H Y 7 LH L L Y 8 LH L L H H L LH H H L LH Y 9 LH L H L Y10 LH L H H Y11 LH H L L Y12 LH H L H Y13 LH H H L Y14 LH H H H Y15 HX X X X All outputs = H FUNCTION TABLE E H = high, L = low, X = don’t care PARAMETER MAX or MIN SN74 HC CD74 HC CD74 HCT UNIT ICC MAX 0.08 0.16 0.16 mA IOH MAX -4 -4 -4 mA IOL MAX 4 4 4 mA PARAMETER INPUT OUTPUT MAX or MIN SN74 HC CD74 HC CD74 HCT tw MIN 20 2 24 5 tsu MIN 25 3 03 0 th MIN 505 tPLH A0,1 ,2 ,3 CD74HCT:Y 58 83 83 tPHL (A, B, C, D) (Y) 58 83 83 tPLH LE CD74HCT:Y 58 68 75 tPHL (LE) (Y) 58 68 75 tPLH E CD74HCT:Y 44 53 60 tPHL (G) (Y) 44 53 60 UNIT:ns MAX MAX LE (LE) LE (LE) LE (LE) MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS606 Logic Diagram D Q0 Q1 Q2 3(11) 4(12) 5(13) 6(14) MR CP E VCC GND 7(15) 1(9) 2(10) FF R Q CL Q D FF R Q CL Q D FF R Q CL Q D FF R Q CL Q PARAMETER MAX or MIN CD74 HC UNIT ICC MAX 0.16 mA IOH MAX -4 mA IOL MAX 4 mA PARAMETER INPUT OUTPUT MAX or MIN CD74 HC fmax MIN 20 tw 24 tsu 24 tPLH 72 tPHL 72 tPLH 72 tPHL 72 tPLH 45 tPHL 45 UNIT fmax : MHz other : ns CP MR Enable to CP CP to Enable Enable Qn Qn QnMR CP MAX MIN MIN MAX MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUTS X E OUTPUT STATE No Change No Change No Change Q0 thru Q3 = L CP H L L MR L L Increment CounterH Increment Counter No Change L L L H XH L L FUNCTION TABLE 4518 DUAL SYNCHRONOUS COUNTERS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 607 Logic Diagram 6(14) D Q0 Q1 Q2 3(11) 4(12) 5(13) MR CP E VCC VCC GND 7(15) 1(9) 2(10) FF R Q CL Q D FF R Q CL Q D FF R Q CL Q D FF R Q CL Q PARAMETER MAX or MIN CD74 HC CD74 HCT UNIT ICC MAX 0.16 0.16 mA IOH MAX -4 -4 mA IOL MAX 4 4 mA PARAMETER INPUT OUTPUT MAX or MIN CD74 HC CD74 HCT fmax MIN 20 17 tw 24 30 30 30 tsu 24 24 24 - tPLH 72 80 tPHL 72 80 tPLH 72 83 tPHL 72 83 tPLH 45 53 tPHL 45 53 UNIT fmax : MHz other : ns CP MR Enable to CP CP to Enable Qn Qn CP Enable MR Qn MAX MIN MIN MAX MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUTS X E OUTPUT STATE No Change No Change No Change Q0 thru Q3 = L CP X L L MR L L Increment CounterH Increment Counter No Change L L X H XH L L FUNCTION TABLE 4520 DUAL SYNCHRONOUS COUNTERS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS608 Logic Diagram D CL CL Q QR2R1 FF VCC VCC RX CX 2(14) 1(15) R A B 3(13) 4(12) 5(11) VCC VCC HIGH Z VCC VCC COMP II + 6(10) 7(9) Q Q VCC 4538 DUAL RETRIGGERABLE PRECISION MONO STABLE MULTIVIBRATOR

609PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN CD74 HC CD74 HCT UNIT ICC MAX 0.16 0.16 mA IOH MAX -4 -4 mA IOL MAX 4 4 mA PARAMETER INPUT OUTPUT MAX or MIN CD74 HC CD74 HCT tWH 24 24 tWL 24 24 tWL 24 30 tPLH Q7 5 8 3 tPHL Q 75 83 tPLH Q 75 75 tPHL Q7 5 6 0 UNIT:ns R MAX MIN MAX A, B A, B R A, B ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS XX A OUTPUTS R XH B L XL X X H HL H Q H H H L E L L H = High Level, L = Low Level, = Transition from Low to High, = Transition from High to Low, One High Level Pulse, One Low Level Pulse, X = Irrelevant.

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS610 Logic Diagram Dn Dn Qn Qn p p n n Qn Qn LD LD LD LD LD LD LATCH D0D0 LDLD LDLD LATCH D1D1 3 Q1 LDLD LDLD LATCH D2D2 Q2LDLD LDLD LATCH D3D3 Q3LDLD LD LDLD LD LD a c b d PH e f g CD54/74HC4543 CD54/74HCT4543 4543 BCD-TO-7 SEGMENT LATCH/DECODER/DRIVERS

611PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN CD74 HC CD74 HCT UNIT ICC MAX 0.16 0.16 mA IOH MAX -1 -4 mA IOL MAX 1 4 mA PARAMETER INPUT OUTPUT MAX or MIN CD74 HC CD74 HCT tW MIN 15 15 tsu MIN 18 18 tH MIN 9 12 tPLH 102 120 tPHL 102 120 tPLH 111 116 tPHL 111 116 tPLH 80 99 tPHL 80 99 tPLH 60 99 tPHL 60 99 UNIT:ns LD MAX MAX MAX MAX BI PH a - g a - g a - g Latch Disable Dn to LD Dn to LD Dn a - g ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE LD H X L L B1 PH L H H L L L L L L L L L L L L L L L L L N L X D2 D1 D0 XXX XX as above XX LLL LL LL LL L L H H H L H L L L H H H L H L L L H H H L H L L L H H H L H abcde fg LLLLL L L LL LLL LLLLLLL LLLLLLL LLLLLLL LLLLLLL LLLL NOTE NOTE inverse above LLL L HH H H HH H H H HH H H H H HHH L H H H H H H H H HH H HHH HHH L HH HH H HH H L H HL L LL L LLLL L HH L H H L LL L L L L L L L H L H L H L H L H H H H H L L L L L L L H H H H H H H H L H H H H L H L H L H L H L H L H L H L H H L as above Blank as above Blank Blank Blank Blank Blank Blank Display NOTE: Depends open the BCD code previously appied when LE = High

C B A Injection- Current Control Injection- Current Control Injection- Current Control Injection- Current Control Injection- Current Control Injection- Current Control Injection- Current Control Injection- Current Control Injection- Current Control : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 4851 8-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER WITH INJECTION-CURRENT EFFECT CONTROL PARAMETER MAX or MIN SN74 HC UNIT ICC MAX 0.01 mA RON MAX 250 Ω PARAMETER INPUT OUTPUT MAX or MIN SN74 HC tPLH 12.5 tPHL 12.5 tPLH 15 tPHL 15 tPLH 90 tPHL 90 tPLH 90 tPHL 90 UNIT: ns COM or Yn MAX Yn or COM INH COM or Yn COM or Yn INH COM or Yn MAX MAX MAX INH ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS ON INH C B A ON CHANNEL LLL L L L L LY 0 LL H Y 1 LL Y2 LL H H H H H LH L Y 4 LH H Y 5 LH L Y 6 LH H Y 7 HX XX None

613PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 1-COM INH B A 2-COM PARAMETER MAX or MIN SN74 HC UNIT ICC MAX 0.01 mA RON MAX 270 Ω PARAMETER INPUT OUTPUT MAX or MIN SN74 HC tPLH 12.5 tPHL 12.5 tPLH 15 tPHL 15 tPLH 45 tPHL 45 tPLH 90 tPHL 90 UNIT: ns COM or Yn MAX Yn or COM Channel Select COM or Yn COM or Yn INH COM or Yn MAX MAX MAX INH ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS ON INH B A ON CHANNEL LL L L L 1Y0, 2Y0 LH 1Y1, 2Y1 L 1Y2, 2Y2 LH H H 1Y3, 2Y3 HX X N one 4852 DUAL 4-TO-1 CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER WITH INJECTION-CURRENT EFFECT CONTROL

• Low Crosstalk Between Switches
• Pin Compatible with SN74HC4052

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 5400 11-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS

• Output Ports Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required (SN74ABT5400A) 5401 11-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS
• Output Ports Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required (SN74ABT5401) To Ten Other Channels OE1 OE2 28 1 To Ten Other Channels OE1 OE2 D1 28 1 FUNCTION TABLE INPUTS H L D H X INPUT Y L L H L X XX Z H OE1 L L OE2 Z PARAMETER MAX or MIN ABT UNIT ICC MAX 45 mA IOH MAX -12 mA IOL MAX 12 mA PARAMETER INPUT OU TPUT MAX or MIN ABT tPLH 6.2 tPHL 5.6 tPZH 8.7 tPZL 7.5 tPHZ 5.2 tPLZ 6.9 UNIT: ns OE D OE Y MAX MAX MAX Y Y ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS H L D H X OUTPUT Y H ZX L L OE1 H L X OE2 L X L Z PARAMETER MAX or MIN ABT UNIT ICC MAX 45 mA IOH MAX -12 mA IOL MAX 12 mA PARAMETER INPUT OUTPUT MAX or MIN ABT tPLH 6.9 tPHL 5.7 tPZH 8.5 tPZL 6.8 tPHZ 5.2 tPLZ 6.9 UNIT: ns OE Y MAX DY MAX OE Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 615 Logic Diagram 5402 12-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS

• Output Ports Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required (SN74ABT5402A) 5403 12-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS
• Output Ports Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required (SN74ABT5403) To Eleven Other Channels OE1 OE2 28 1 To 11 Other Channels OE1 OE2 D1 28 1 FUNCTION TABLE INPUTS H L D H X OUTPUT Y H ZX L L OE1 H L X OE2 L X L Z PARAMETER MAX or MIN ABT UNIT ICC MAX 48 mA IOH MAX -12 mA IOL MAX 12 mA PARAMETER INPUT O UTPUT MAX or MIN ABT tPLH 6.2 tPHL 5.6 tPZH 8.7 tPZL 7.5 tPHZ 5.2 tPLZ 6.9 UNIT: ns OE Y MAX OE Y MAX DY MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS H L D H X OUTPUT Y H ZX L L OE1 H L X OE2 L X L Z PARAMETER MAX or MIN ABT UNIT ICC MAX 45 mA IOH MAX -12 mA IOL MAX 12 mA PARAMETER INPUT O UTPUT MAX or MIN ABT tPLH 6.9 tPHL 5.7 tPZH 8.5 tPZL 6.8 tPHZ 5.2 tPLZ 6.9 UNIT: ns OE Y MAX DY MAX OE Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS Logic Diagram

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 7001 QUADRUPLE POSITIVE-AND GATES WITH SCHMITT-TRIGGER INPUTS

• Same Pinouts as SN74HC08
• VCC: 2V to 6V
• Schmitt-Triggered Inputs
• Y = A•B 7002 QUADRUPLE POSITIVE-NOR GATES WITH SCHMITT-TRIGGER INPUTS
• Same Pinouts as SN74HC36
• VCC: 2V to 6V
• Schmitt-Triggered Inputs
• Y = A + B A B Y A B Y PARAMETER MAX or MIN SN74 HC UNIT ICC MAX 0.02 mA IOH MAX -4 mA IOL MAX 4 mA PARAMETER INPUT OUTPUT MAX or MIN SN74 HC tPLH 33 tPHL 33 UNIT: ns A or B Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS PARAMETER MAX or MIN SN74 HC UNIT ICC MAX 0.02 mA IOH MAX -4 mA IOL MAX 4 mA PARAMETER INPUT OUTPUT MAX or MIN SN74 HC tPLH 33 tPHL 33 UNIT: ns A or B Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 7032 QUADRUPLE POSITIVE-OR GATES WITH SCHMITT-TRIGGER INPUTS

• Same Pinouts as SN74HC32
• VCC: 2V to 6V
• Schmitt-Triggered Inputs
• Y = A + B A B Y PARAMETER MAX or MIN SN74 HC UNIT ICC MAX 0.02 mA IOH MAX -4 mA IOL MAX 4 mA PARAMETER INPUT OUTPUT MAX or MIN SN74 HC tPLH 33 tPHL 33 UNIT: ns A or B Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS618 7046 PHASE-LOCKED LOOP WITH VCO AND LOCK DETECTOR Logic Diagram DEMOUT PC2OUT 13 p n GND VCC 2PC1OUT DOWN RD Q Q D CP RD Q Q D CP UP VCC VCC INH VCOIN VCO - + VCOOUT COMPIN - + SIGINC1BC1A VREF 67 4 3 1 4 - + 150Ω 1.5K LOCK DETECTOR OUTPUT LOCK DETECTOR CAPACITOR C LD LOCK DETECTOR PARAMETER MAX or MIN CD74 HC CD74 HCT UNIT ICC MAX 0.16 0.16 mA IOH MAX -4 -4 mA IOL MAX 4 4 mA PARAMETER INPUT OUTPUT MAX or MIN CD74 HC CD74 HCT tPLH 60 68 tPHL 60 68 tPZH 84 90 tPZL 84 90 tPHZ 98 105 tPLZ 98 105 UNIT:ns MAX MAX MAX SIG IN, COMP IN SIGIN, COMP IN SIGIN, COMP IN PC1OUT PC2OUT PC2OUT ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 619 Logic Diagram Logic Diagram 8003 DUAL 2-INPUT POSITIVE-NAND GATES 1Y PARAMETER MAX or MIN ALS AS UNIT ICC MAX 1.5 8.7 mA IOH MAX -0.4 -2 mA IOL MAX 8 20 mA PARAMETER INPUT OUTPUT MAX or MIN ALS AS tPLH 11 4.5 tPHL 84 UNIT: ns A or B Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS 7266 QUAD 2-INPUT EXCLUSIVE-NOR GATES

• Y = A ⊕ B nA nB nY INPUTS H L BA L OUTPUT Y L H H H L L H L H FUNCTION TABLE NOTES: H = High Voltage Level L = Low Voltage Level PARAMETER MAX or MIN SN74 HC CD74 HC UNIT ICC MAX 0.02 0.04 mA IOH MAX -4 -4 V IOL MAX 4 4 V PARAMETER INPUT OUTPUT MAX or MIN SN74 HC CD74 HC tPLH Y MAX 25 35 tPHL Y MAX 25 35 UNIT:ns A or B ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16240 16-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

621PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ABT LVT LVTH ALVTH 3V AC ACT AHC AHCT LVCH LVCZ ALVCH 3V UNIT IOH MAX -32 -32 -32 -32 -24 -24 -8 -8 -24 -24 -24 mA IOL MAX 64 64 64 64 24 24 8 8 24 24 24 mA PARAMETER MAX or MIN AUC 1.8V AUC 2.3V UNIT ICC MAX 0.02 0.02 mA IOH MAX -8 -9 mA IOL MAX 8 9 mA PARAMETER INPUT OUTPUT MAX or MIN ABT LVT LVTH ALVTH 3V AC ACT AHC AHCT PARAMETER INPUT OUTPUT MAX or MIN LVCH LVCZ ALVCH AUC 1.8V AUC 2.3V tPZH 4.7 4.7 5 2.5 2 tPZL 4.7 4.7 5 2.5 2 UNIT: ns MAX Y MAX Y MAX A OE OE Y OE Y MAX AY MAX OE Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE (each 4-bit buffer) INPUTS H L A H OUTPUT Y HL L OE L X Z

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16241 16-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

623PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ABT LVTH 3V ACT UNIT ICC MAX 34 5 0.08 mA IOH MAX -32 -32 -24 mA IOL MAX 64 64 24 mA PARAMETER INPUT OUTPUT MAX or MIN ABT LVTH 3V ACT tPLH 3.7 3.5 9.5 tPHL 4.5 3.5 9.1 tPZH 5 4.5 9.4 tPZL 6.9 4.5 10.5 tPHZ 6.2 5.3 11.6 tPLZ 5.6 4.9 10.7 UNIT: ns OE or OE Y MAX AY MAX OE or OE Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS H L 1A, 4A H OUTPUTS 1Y, 4Y HL L 1OE, 4OE L X Z INPUTS H L 2A, 3A H OUTPUTS 2Y, 3Y H L L 2OE, 3OE X Z H

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16244 16-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

625PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ABT ABTH LVT LVTH ALB ALVTH 3V AC ACT AHC AHCT LVC 3V UNIT IOH MAX -32 -32 -32 -32 -25 -32 -24 -24 -8 -8 -24 mA IOL MAX 64 64 64 64 25 64 24 24 8 8 24 mA PARAMETER MAX or MIN LVCH LVCZ ALVC ALVCH AVC AUC 1.8V AUC 2.3V AUCH 1.8V AUCH 2.3V UNIT IOH MAX -24 -24 -24 -24 -12 -8 -9 -8 -9 mA IOL MAX 24 24 24 24 12 8989 m A PARAMETER INPUT OUTPUT MAX or MIN ABT ABTH LVT LVTH ALB ALVTH 3V AC ACT PARAMETER INPUT OUTPUT MAX or MIN AHC AHCT LVC LVCH LVCZ ALVC ALVCH AVC PARAMETER INPUT OUTPUT MAX or MIN AUC 1.8V AUC 2.3V AUCH 1.8V AUCH 2.3V tPLH 1.8 1.8 1.8 1.8 tPHL 1.8 1.8 1.8 1.8 tPZH 2.5 1.9 2.5 1.9 tPZL 2.5 1.9 2.5 1.9 tPHZ 4.0 2 4.0 2 tPLZ 4.0 2 4.0 2 UNIT: ns OE Y MAX AY MAX OE Y MAX OE Y MAX AY MAX OE Y MAX OE Y MAX AY MAX OE Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE (each buffer) INPUTS H L A H OUTPUT Y H L L OE L X Z

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS

627PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ABT ABTH LVT LVTH ALB ALVTH ALVT HR AC ACT AHCT UNIT ICC MAX 32 32 55 5.6 5 5 0.08 0.08 0.04 mA IOH MAX -32 -32 -32 -32 -25 -32 -12 -24 -24 -8 mA IOL MAX 64 64 64 64 25 64 12 24 24 8 mA PARAMETER MAX or MIN LVC LVCH LVCHR LVCR LVCZ ALVCH ALVC HR AVC AUC 1.8V AUC 2.3V UNIT IOH MAX -24 -24 -12 -12 -24 -24 -12 -12 -8 -9 mA IOL MAX 24 24 12 12 24 24 12 12 8 9 mA PARAMETER INPUT OUTPUT MAX or MIN ABT ABTH LVT LVTH ALB ALVTH ALVT HR AC PARAMETER INPUT OUTPUT MAX or MIN ACT AHCT LVC LVCH LVCHR LVCR LVCZ ALVCH tPLH 10.5 10.5 4 4 4.8 4.8 4 3 tPHL 10.2 10.5 4 4 4.8 4.8 4 3 PARAMETER INPUT OUTPUT MAX or MIN ALVC HR AVC AUC 1.8V AUC 2.3V tPLH 4.2 1.7 2 1.9 tPHL 4.2 1.7 2 1.9 tPZH 5.6 3.7 3.1 2.6 tPZL 5.6 3.7 3.1 2.6 tPHZ 5.5 3.9 4.8 2.9 tPLZ 5.5 3.9 4.8 2.9 UNIT: ns OE B or A MAX A or B B or A MAX OE B or A MAX OE B or A MAX A or B B or A MAX OE B or A MAX OE B or A MAX A or B B or A MAX OE B or A MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE (each 8-bit section) INPUTS H L DIR H OPERATION B data to A busL OE L X Isolation A data to B bus

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16260 12-BIT TO 24-BIT MULTIPLEXES D-TYPE LATCH WITH 3-STATE OUTPUTS

629PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ABTH ALVCH 3V UNIT ICC MAX 63 0.04 mA IOH MAX -32 -24 mA IOL MAX 64 24 mA PARAMETER INPUT OUTPUT MAX or MIN ABTH ALVCH tw Pulse duration, LE1B, LE2B, LEA1B, or LEA2B high MIN 3.3 3.3 tsu Setup time, data before LE1B, LE2B, LEA1B, or LEA2B ↓ MIN 1.5 1.1 th Hold time, data after LE1B, LE2B, LEA1B, or LEA2B ↓ MIN 11 . 5 tPLH 5.6 4.3 tPHL 5.9 4.3 tPLH 5.8 4.4 tPHL 5.3 4.4 SEL (B1) 5.3 5.6 SEL (B2) 6 5.6 SEL (B1) 4.4 5.6 SEL (B2) 5.9 5.6 t PZH 5.7 5.4 tPZL 5.8 5.4 tPHZ 6.4 4.6 tPLZ 4.8 4.6 UNIT: ns MAX MAX tPLH tPHL A MAX MAX A or B B or A A or BLE OE A or B MAX OE A or B MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS H L OUTPUT A1B H L X X H X L X A0 X H L X X X X X H L H L H L SEL X H H L LE1B X X X X H H L LE2B X X X X H L L L L L L OEA Z B TO A (OEB = H) INPUTS H H L H L L OUTPUTS H L X X H X L X 2B0 2B0 2B0 X H L 1B 2B Active Active Active Active H H H H L L L LEA1B X X X X H H L H H L L LEA2B X X X X H L L L L L L OE1B Z ZZ Z 1B0 H L 1B0 1B0 H H H L L L LL LL LL L L L OE2B A TO B (OEA = H)

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16269 12-BIT TO 24-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS

631PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ALVCH ALVCHR AVC 3V UNIT ICC MAX 0.04 0.04 0.04 mA IOH MAX -24 -12 -12 mA IOL MAX 24 12 12 mA PARAMETER INPUT OUTPUT MAX or MIN ALVCH ALVCHR AVC fmax MIN 135 135 175 tw Pulse duration, CLK high or low MIN 3.3 3.3 3.5 A data before CLK ↑ MIN 1.7 1 1.9 B data before CLK ↑ MIN 1.8 1.1 1.9 SEL before CLK ↑ MIN 1.3 1.3 1.3 CLKENA1 or CLKENA2 before CLK ↑ MIN 0.9 0.8 1.1 OE before CLK ↑ MIN 1.3 1.2 1.1 A data after CLK ↑ MIN 0.6 1.2 1 B data after CLK ↑ MIN 0.6 1 0.7 SEL after CLK ↑ MIN 0.7 1.7 0.4 CLKENA1 or CLKENA2 after CLK ↑ MIN 1.1 1.6 1 OE after CLK ↑ MIN 0.8 1.2 0.3 B6 . 2 5.8 3 A5 5.2 2.7 B6 . 1 5.8 3.8 A5 . 9 5.3 3.4 B6 . 1 6 3 . 7 A5 . 6 6 3 . 4 UNIT fmax : MHz other : ns t su Setup time th Hold time CLK CLK MAX CLK tpd ten MAX MAX tdis ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS OUTPUTS CLK Z H L H LH L OEA A 1B,2B H L OEB OUTPUT ENABLE Active Z ActiveZ Active Z Active 1B0†2 B 0† INPUTS OUTPUTS CLK H X L LH L CLKENA1 1B 2B L H L H L A A-TO-B STORAGE (OEB = L) X X X X X X X XXH L CLKENA2 L H † Output level before the indicated steady-state input conditions were established A0† INPUTS OUTPUT ACLK X L X H L 2B1BSEL B-TO-A STORAGE (OEA = L) XX A0† H L XX H H L X X X X H L L H L H † Output level before the indicated steady-state input conditions were established

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16270 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

633PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ALVCH 3V UNIT ICC MAX 0.04 mA IOH MAX -24 mA IOL MAX 24 mA PARAMETER INPUT OUTPUT MAX or MIN ALVCH fmax MIN 150 tw Pulse duration, CLK high or low MIN 3.3 A data before CLK ↑ MIN 3.1 B data before CLK ↑ MIN 0.9 CLKENA1 or CLKENA2 before CLK ↑ MIN 2.7 CLKEN1B or CLKEN2B before CLK ↑ MIN 2.6 OE before CLK ↑ MIN 3.2 A data after CLK ↑ MIN 0.2 B data after CLK ↑ MIN 1.7 CLKENA1 or CLKENA2 after CLK ↑ MIN 0.3 CLKEN1B or CLKEN2B after CLK ↑ MIN 0.6 OE after CLK ↑ MIN 0.1 5.1 4.7 SEL A MAX 5.5 5.8 5.8 UNIT fmax : MHz other : ns MAX CLKt en MAX MAX tpd tdis A or B A or B A or B tsu Setup time th Hold time CLK CLK ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS OUTPUTS CLK Z H L H LH L OEA A 1B,2B H L OEB 1B0‡ 1B0‡ 1B0‡ 2B0‡ 2B0‡ 2B0‡ OUTPUT ENABLE Active Z ActiveZ Active Z Active INPUTS OUTPUTS CLK H L H L H L L H L CLKENA1 1B 2B L H L H H L L A A-TO-B STORAGE (OEB = L) XX H L CLKENA2 L H L H L CLK L X X X H L CLKEN1B L CLKEN2B H X X X L H † Two CLK edges are needed to propagate data. ‡ Output level before the indicated steady-state input conditions were established A0‡ INPUTS OUTPUT A L H L 2B1BSEL B-TO-A STORAGE (OEA = L) XX A0‡ H L XX X X H H L X X X X H L L H L H ‡ Output level before the indicated steady-state input conditions were established

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16271 12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS

635PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ALVCH 3V UNIT ICC MAX 0.04 mA IOH MAX -24 mA IOL MAX 24 mA PARAMETER INPUT OUTPUT MAX or MIN ALVCH fmax MIN 130 tw Pulse duration, CLK high or low MIN 3.3 A before CLK ↑ MIN 1.7 B before LE MIN 1.3 CLKEN before CLK ↑ MIN 1 A after CLK ↑ MIN 0.7 B after LE MIN 1.1 CLKEN after CLK ↑ MIN 0.9 CLK B MAX 4.3 LE 4.8 SEL 5.2 ten OEB or OEA B or A MAX 5.1 tdis OEB or OEA B or A MAX 4.2 UNIT fmax : MHz other : ns MAX tsu Setup time th Hold time tpd A ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUTS X OEB L Z ActiveH OEA OUTPUTS 1B, 2BA H L L L Active L Z Z Z Active Active OUTPUT ENABLE INPUTS X ACLKENA2 H L OUTPUTS 1B0† H L CLKENA1 CLK 2B 1B H X X L X L HX H X L L X L 2B0† X L H X A-TO-B STORAGE (OEB = L) INPUTS X 1BSEL H X OUTPUTA A0† H L LE H L H L X X X H X X X L X L L X H H L L H L † Output level before the indicated steady-state input conditions were established L A0† FUNCTION TABLE B-TO-A STORAGE (OEA = L)

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

637PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ALVCH 3V UNIT ICC MAX 0.04 mA IOH MAX -24 mA IOL MAX 24 mA PARAMETER INPUT OUTPUT MAX or MIN ALVCH fmax MIN 150 tw Pulse duration, CLK high or low MIN 3.3 A data before CLK ↑ MIN 2 B data before CLK ↑ MIN 1.8 DIR before CLK ↑ MIN 1.7 SEL before CLK ↑ MIN 1.8 A data after CLK ↑ MIN 0.7 B data after CLK ↑ MIN 0.6 DIR after CLK ↑ MIN 0.5 SEL after CLK ↑ MIN 0.8 B5 . 3 A5 . 7 B7 . 4 A5 . 7 B6 . 4 UNIT fmax : MHz other : ns t dis OE MAX MAX MAX t pd tsu Setup time th Hold time CLK OEten ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUTS X DIR H Z Active OE OUTPUTS 1B, 2BA H L LLZ Z Z Active OUTPUT ENABLE INPUTS X A H L OUTPUTS 1B0† CLK 2B 1B H X L L L‡ 2B0† X X A-TO-B STORAGE (OE = L, DIR = H) INPUTS 1BSEL SEL H OUTPUT A H L CLK CLK X X H X X L L H H L L § Two CLK edges are needed to propagate the data. The data is loaded in the first register when SEL is low and propagates to the second register when SEL is high. FUNCTION TABLE † Output level before the indicated steady-state input conditions were established ‡ Two CLK edges are needed to propagate the data. B-TO-A STORAGE (OE = L, DIR = L)

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

639PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ALVC ALVCH AVC 3V UNIT ICC MAX 0.04 0.04 0.04 mA IOH MAX -24 -24 -12 mA IOL MAX 24 24 12 mA PARAMETER INPUT OUTPUT MAX or MIN ALVC ALVCH AVC fmax MIN 150 150 150 LE low 3.3 3.3 3.3 CLK high or low MIN 3.3 3.3 3.3 Data before CLK ↑ MIN 1.5 1.5 0.7 Data before LE ↑ CLK high MIN 1.3 1.3 0.9 Data before LE ↑ CL K low MIN 1.2 1.2 1 Data after CLK ↑ MIN 0.9 0.9 0.7 Data after LE ↑ CLK high MIN 1.1 1.1 1.5 Data after LE ↑ CL K low MIN 1.1 1.1 1.3 A MAX 3.3 3.3 2.5 LE 4.4 4.4 4 CLK MAX 4.1 4.1 3.1 ten OE Y 4.6 4.6 6.2 tdis OE Y MAX 4.4 4.4 5.3 UNIT fmax : MHz other : ns tpd Y tw Pulse duration tsu Setup time th Hold time ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS X L ACLK L L OUTPUT Y Z HH OE H L X L X X L or H L † Output level before the indicated steady-state input conditions were established LE X H HL HH XL Y0†H L L L

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS

641PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ALVCH 3V UNIT ICC MAX 0.04 mA IOH MAX -24 mA IOL MAX 24 mA PARAMETER INPUT OUTPUT MAX or MIN ALVCH tPLH 4 tPHL 4 tPZH 5.1 tPZL 5.1 tPHZ 4 tPLZ 4 UNIT: ns AB MAX MAX MAX OE OE B B ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS OE H L L A H L H OUTPUT Bn Z H L

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS642 16373 16-BIT TRANSPARENT LATCHES WITH 3-STATE OUTPUTS Logic Diagram 1OE 1LE 1D1 To Seven Other Channels 1Q1 2OE 2LE 2D1 2Q1 To Seven Other Channels 132C1

643PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ABT LVTH ALVTH 3V AC ACT AHC AHCT LVC LVC ver.A 3V3V LVCH ALVCH AVC UNIT 0.04 mA IOH MAX -32 -32 -32 -24 -24 -8 -8 -24 -24 -24 -12 mA IOL MAX 64 64 64 24 24 8 8 24 0.02 -24 24 24 24 mA PARAMETER MAX or MIN AUC 1.8V AUC 2.3V UNIT ICC MAX 0.02 0.02 mA IOH MAX -8 -9 mA IOL MAX 8 9 mA PARAMETER INPUT OUTPUT MAX or MIN ABT LVTH ALVTH 3V AC ACT AHC AHCT tw Pulse duration, LE high or low MIN 3.3 3 1.5 4 1 5 6.5 Data before LE ↓ , data high MIN 1.5 1 1.4 1.5 1 4 1.5 Data before LE ↓ , data low MIN 1.5 1 0.9 1.5 1 41 . 5 Data after LE ↓ , data high MIN 11 0 . 9 2 . 4 51 3 . 5 Data after LE ↓ , data low MIN 11 1 . 4 2 . 4 51 3 . 5 PARAMETER INPUT OUTPUT MAX or MIN LVC LVCH ALVCH AVC AUC 1.8V AUC 2.3V Data after LE ↓ , data high MIN 1.2 1. 410 . 7 0 . 6 Data after LE ↓ , data low MIN 1.2 1. 410 . 7 0 . 6 tPLZ 3.3 1.7 1.7 1.2 1.2 4.2 4.2 4.6 4.6 4.7 4.7 5.9 5.9 UNIT: ns AUC:Preview OE Q MAX OE Q MAX t h Hold time tsu Setup time MAX MAX DQ QLE tsu Setup time th Hold time DQ MAX LE Q MAX OE Q MAX OE Q MAX LVC ver.A ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE (each latch) INPUTS H L D H X OUTPUT Q H Z L L OE H X LE L XL QOL H

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

645PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ABT LVTH ALVTH 3V AC ACT AHC AHCT LVCH ALVCH AVC UNIT 0.04 mA IOH MAX -32 -32 -32 -24 -24 -8 -8 -24 -24 -24 -12 mA IOL MAX 64 64 64 24 24 8 8 24 LVC 0.04 -24 24 24 24 mA PARAMETER MAX or MIN AUC 1.8V AUC 2.3V AUCH 1.8V AUCH 2.3V UNIT ICC MAX 0.02 0.02 0.02 0.02 mA IOH MAX -8 -9 -8 -9 mA IOL MAX 8989 m A PARAMETER INPUT OUTPUT MAX or MIN ABT LVTH ALVTH 3V AC ACT AHC AHCT LVC fmax MIN 150 160 250 100 65 110 110 100 CLK high 3.3 3 1.5 5 7.5 5 6.5 4 CLK low 3.3 3 1.5 5 4.5 5 6.5 4 Data before CLK ↑ , data high 1.1 1.8 1 5 4.5 3 2.5 2 PARAMETER INPUT OUTPUT MAX or MIN LVCH ALVCH AVC AUC 1.8V AUC 2.3V AUCH 1.8V AUCH 2.3V fmax MIN 150 150 200 250 250 250 250 UNIT fmax : MHz other : ns OE Q MAX MIN Q MAX tw Pulse duration MIN OE tw Pulse duration MIN tsu Setup time MIN th Hold time OE Q MAX MIN CLK Q MAX tsu Setup time OE Q MAX th Hold time MIN CLK Q MAX 150 3.3 3.3 1.9 1.9 1.9 1.9 4.5 4.5 4.6 4.6 5.5 5.5 LVC ver.A LVC ver.A ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE (each fllp-flop) INPUTS H L D H X OUTPUT Q H Z L L OE X CLK L XH or L QOL

D D CLK CLK D D 1Ax 2Ax 1Bx 2Bx 1Ax 1Bx 2Bx 2Ax 1Bx 2Bx 1Ax 2Ax 1Bx 1Ax 2Ax 2Bx SEL2 SEL3 SEL4 CLK SELEN SEL0 SEL1 PRE : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 647 PARAMETER MAX or MIN ALVCH ALVC HR UNIT ICC MAX 0.04 0.04 mA IOH MAX -24 -12 mA IOL MAX 24 12 mA PARAMETER INPUT OUTPUT MAX or MIN ALVCH ALVC HR fmax MIN 120 120 tw Pulse duration, CLK high or low MIN 33 A or B data before CLK ↑ MIN 1.4 1.4 SEL before CLK ↑ MIN 3.5 3.5 SELEN before CLK ↑ MIN 1.8 1.8 PRE before CLK ↑ MIN 0.7 0.7 A or B data after CLK ↑ MIN 11 SEL after CLK ↑ MIN 00 SELEN after CLK ↑ MIN 0.8 0.8 tpd CLK A or B MAX 5. 1 6.2 ten CLK CLK A or B MAX 5. 7 6.8 5.7 6.1 6.1 6.4 UNIT fmax : MHz other : ns MAXA or B t su Setup time th Hold time tdis PRE ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS OUTPUT CLK SEND PORT RECEIVE PORT XX B 0† XL XH ↑ L ↑ H L H L H HX † LX B 0 † Output level before the indicated steady-state input conditions were established DATA-FLOW CONTROL INPUTS PRE SELEN CLK SEL0 SEL1 SEL2 SEL3 SEL4 HX XX XX XX All outputs disabled LH ↑ XX XX XN o change LL ↑ 00 00 0N one, all I/Os off LL ↑ 00 00 1N ot used LL ↑ 00 01 0N ot used LL ↑ 00 01 1N ot used LL ↑ 00 10 0N ot used LL ↑ 00 10 1N ot used LL ↑ 00 11 0N ot used LL ↑ 00 11 1N ot used LL ↑ 01 00 0 2A to 1A and 1B to 2B LL ↑ 01001 2A to 1A LL ↑ 01010 2B to 1B LL ↑ 01 01 1 2A to 1A and 2B to 1B LL ↑ 01 10 0 1A to 2A and 1B to 2B LL ↑ 01101 1A to 2A LL ↑ 01110 1B to 2B LL ↑ 01 11 1 1A to 2A and 2B to 1B LL ↑ 10 00 0 1A to 1B and 2B to 2A LL ↑ 10001 1A to 1B LL ↑ 10010 2A to 2B LL ↑ 10 01 1 1A to 1B and 2A to 2B LL ↑ 10 10 0 1B to 1A and 2A to 2B LL ↑ 10101 1B to 1A LL ↑ 10110 2B to 2A LL ↑ 10 11 1 1B to 1A and 2B to 2A LL ↑ 11 00 0 2B to 1A and 2A to 1B LL ↑ 11001 1B to 2A LL ↑ 11010 2B to 1A LL ↑ 11 01 1 2B to 1A and 1B to 2A LL ↑ 11 10 0 1A to 2B and 1B to 2A LL ↑ 11101 1A to 2B LL ↑ 11110 2A to 1B LL ↑ 11 11 1 1A to 2B and 2A to 1B DATA FLOW

D CLK CE LE D CLK CE CLK CE D LE CLK CE D LE LE CLK CE D LE CLK CE D LE CLK CE D LE CLK CE D M U X CE CLK D LE P CE_SEL0 CE_SEL1 CLKENAB 1B1 1B2 1B3 1B4 CLKENAB Selector One of Four Channels CLKAB OEA OEB OEB4 OEB3 OEB2 OEB1 CLKENBA CLKBA LEBA SEL0 SEL1 CLKENB LEB1 LEB2 LEB3 LEB4 LEAB4 LEAB3 LEAB2 LEAB1 : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16460 4-TO-1 MULTIPLEXED/DEMULTIPLEXED TRANSCEIVERS WITH 3-STATE OUTPUTS

649PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. MAX or MIN ABTH fmax MIN 160 CLKAB high or low MIN 3.8 CLKBA high or low MIN 4.5 LEAB1, 2, 3 or 4 high MIN 2.2 LEBA high MIN 2.1 LEB1, 2, 3 or 4 high MIN 2.4 A bus MIN 2.5 CE_SEL0/1 MIN 3.2 CLKENAB MIN 3.2 Before LEAB1, 2, 3, or 4 ↓ A bus MIN 3.6 B bus MIN 3.8 CLKENB MIN 2.3 CLKENBA MIN 2.5 LEB1, 2, 3 or 4 MIN 4.3 SEL0/1 MIN 4.5 Before LEB1, 2, 3, or 4 ↓ B bus MIN 3.2 B bus MIN 4 LEB1, 2, 3 or 4 MIN 4.4 SEL0/1 MIN 4.3 A bus MIN 0.5 CE_SEL0/1 MIN 1.1 CLKENAB MIN 0.5 after LEAB1, 2, 3, or 4 ↓ A bus MIN 1.2 B bus MIN 1.3 CLKENB MIN 1 CLKENBA MIN 1 SEL0/1 MIN 0 after LEB1, 2, 3, or 4 ↓ B bus MIN 1.5 B bus MIN 0.4 SEL0/1 MIN 0.1 Before CLKBA th Hold time after CLKAB ↑ after CLKBA ↑ after CLKBA ↑ tsu Setup time PARAMETER tw Pulse duration Before CLKAB ↑ Before CLKBA ↑ PARAMETER INPUT OUTPUT MAX or MIN ABTH tPLH 6.5 tPHL 6.5 tPZH 5.6 tPZL 5.2 tPHZ 5.9 tPLZ 6.5 tPLH 5.7 tPHL 5.7 tPZH 6.4 tPZL 6.3 tPHZ 7 tPLZ 6.1 tPZH 5.8 tPZL 5.6 tPHZ 6.1 tPLZ 5.3 tPLH 7.4 tPHL 7.7 tPLH 6.2 tPHL 5.9 tPLH 5.6 tPHL 5.3 tPLH 5.8 tPHL 5.6 tPLH 7.2 tPHL 6.8 tPLH 7.5 tPHL 6.9 UNIT fmax : MHz other : ns LEBA1, 2, 3, 4 A MAX SEL A MAX LEBA A MAX LEAB1, 2, 3, 4 B MAX CLKBA A MAX CLKAB B MAX OEB1, 2, 3, 4 B MAX OEB1, 2, 3, 4 B MAX OEB B MAX OEB B MAX OEA A MAX AB MAX BA MAX OEA A MAX PARAMETER MAX or MIN ABTH UNIT ICC MAX 32 mA IOH MAX -32 mA IOL MAX 64 mA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS H L H L OUTPUT BnOEB H H L L OEBn Z Z ZA-TO-B OUTPUT ENABLE INPUTS H L L L L L OUTPUTS CLKENAB X X H or L H or L L CLKAB H L H L CE_SEL0 X X X X H L H L CE_SEL1 X X X X H L H L L LEAB1 H L LEAB2 H L LL LEAB3 L L L L L L LEAB4 B1 A A A A A A A A0 A0 A0 A0 A0 A0 A A-TO-B OUTPUT ENABLE (assuming OEB = L, OEBn = L) ‡ Active ‡ Output level before the indicated steady-state input conditions were established †n = 1, 2, 3, 4 L LL LL L L LL LL LL LL INPUTS X L L L H OUTPUT ACLKENBA X X X X X X L CLKBA XX H H L L LEBA H L OEA H L X X H L L B H L A0† H L A0† Z B-TO-A STORAGE (after point P) L L L L L L INPUTS L L PCLKENB X X X X X X L CLKBA H L LEB1 B40† B30† B20† B10† B-TO-A STORAGE (after point P) L L H L LEB2 L L H L LL LL LL LEB3 L L H L X L X L LEB4 L L H H H L SEL1 L L H H H H H L H L H HH L SEL0 L L L L L L

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16470 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

651PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE INPUTS H L OUTPUT B H B0‡ X L CLKENAB † A-to-B data flow is shown: B-to-A flow is similar but uses CLKENBA, CLKBA, and OEBA. ‡O utput level before the indicated steady-state input conditions were established. L CLKAB X H L X H L A X OEAB L L X ↑ L L X X Z Z PARAMETER MAX or MIN ABT ACT UNIT ICC MAX 35 0.08 mA IOH MAX -32 -24 mA IOL MAX 64 24 mA PARAMETER INPUT OUTPUT MAX or MIN ABT ACT fmax MIN 150 55 tw Pulse duration, CLKAB or CLKBA high MIN 3.3 4 tw Pulse duration, CLKAB or CLKBA low 3.3 8.5 tsu Setup time, data before CLKAB ↑ or CLKBA ↑ MIN 4 6 th Hold time, data after CLKAB ↑ or CLKBA ↑ MIN 1 1 tPLH 4.9 11.8 tPHL 4.9 11.7 tPZH 4.9 11.9 tPZL 6.8 13.4 tPHZ 5.5 9.9 tPLZ 5.3 9.5 tPZH 5.7 12.5 tPZL 7.2 14.3 tPHZ 5.8 11.2 tPLZ 5.4 10.9 UNIT fmax : MHz other : ns CLKEN A or B MAX OE A or B MAX CLKEN A or B MAX CLK A or B MAX OE A or B MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16500 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

653PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE INPUTS H OUTPUT B H B0‡ X L LEAB † A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. ‡ Output level befor the indicated steady-state input conditions were established. §O utput level before the indicated steady-state input conditions were established, provided that CLKAB was low before LEAB went low. L OEAB H X H L A X CLKAB L LL X XZ L L H H H H H H H H LX X B0§ H PARAMETER MAX or MIN ABT LVTH ALVCH 3V UNIT ICC MAX 36 5 0.04 mA IOH MAX -32 -32 -24 mA IOL MAX 64 64 24 mA PARAMETER INPUT OUTPUT MAX or MIN ABT LVTH ALVCH fmax MIN 150 150 150 LEAB or LEBA high 2.5 3.3 3.3 CLKAB or CLKBA high or low 33 . 3 3 . 3 A before CLKAB ↓ 32 . 9 1 . 3 B before CLKBA ↓ 32 . 9 1 . 3 A before LEAB ↓ or LEBA ↓ CLK high 11 . 41 A before LEAB ↓ or LEBA ↓ CLK low 2.5 2.9 1.4 A after CLKAB ↓ or B after CLKBA ↓ 00 . 4 1 . 3 A after LEAB ↓ or B after LEBA ↓ high 21 . 6 1 . 5 A after LEAB ↓ or B after LEBA ↓ low 21 . 6 1 . 2 tPLH 4 3.7 3.9 tPHL 4.9 3.7 3.9 tPZH 5 5.1 4.7 tPZL 5 5.1 4.7 tPHZ 5.3 5 5.5 tPLZ 5.3 5 5.5 tPZH 5.1 4.8 4.6 tPZL 5.4 4.8 4.6 tPHZ 6.5 5.8 5 tPLZ 5.4 5.8 5 tPZH 5.1 4.8 5.2 tPZL 5.4 4.8 5.2 tPHZ 6.5 5.8 4.3 tPLZ 5.4 5.8 4.3 UNIT fmax : MHz other : ns OEBA A MAX OEAB B MAX OEBA A MAX CLKAB or CLKBA B or A MAX OEAB B MAX A or B B or A MAX LEAB or LEBA B or A MAX th Hold time MIN tw Pulse duration tsu Setup time MIN MIN ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

655PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE INPUTS H OUTPUT B H B0‡ X L LEAB † A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. ‡O utput level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low. §O utput level before the indicated steady-state input conditions were established. L OEAB H X H L A X CLKAB L LL X XZ L L H H H H H H H H LX X B0§ H L PARAMETER MAX or MIN ABT LVTH ALVCH AUC 1.8V AUC 2.3V UNIT ICC MAX 76 5 0.04 0.02 0.02 mA IOH MAX -32 -32 -24 -8 -9 mA IOL MAX 64 64 24 8 9 mA PARAMETER INPUT OUTPUT MAX or MIN ABT LVTH ALVCH AUC 1.8V AUC 2.3V fmax MIN 105 150 150 300 350 A before LEAB ↓ or LEBA ↓ CLK high MIN 42 . 4 1 . 5 0.3 0.3 A before LEAB ↓ or LEBA ↓ CLK low MIN 1.5 1.4 1 0.3 0.3 A after CLKAB ↑ or B after CLKBA ↑ MIN 11 0 . 7 0.9 0.9 tPHL 4 3.7 3.9 2.8 2.3 tPZH 5.1 5.1 4.6 3.8 3 tPZL 4.4 5.1 4.6 3.8 3 tPHZ 5 5.1 4.9 3.3 2.7 tPHZ 5.8 5.8 5 3.2 3.1 tPLZ 4.9 5.8 5 3.2 3.1 tPZH 4.7 4.8 5 3.7 3 tPZL 6.5 4.8 5 3.7 3 tPHZ 5.8 5.8 4.2 5.2 3 tPLZ 4.9 5.8 4.2 5.2 3 UNIT fmax : MHz other : ns AUC:Preview tw Pulse duration MAX LEAB or LEBA MAX tsu Setup time th Hold time CLKAB or CLKBA MAX OEBA B MAX B MAX MAX OEBA A MAX A or B B or A B or A B or A A OEAB OEAB ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16524 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS

657PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE † Output level before the indicated steady-state input conditions were established ‡ Four positive CLK edges are needed to propagate data from B to A when SEL is low. INPUTS H L L L L OUTPUT ACLKENBA XX CLK X H H SEL H L H L B H L A0† B-TO-A STORAGE (OEBA = L) L L PARAMETER INPUT OUTPUT MAX or MIN ALVCH fmax MIN 150 tw Pulse duration, CLK high or low MIN 3 B data before CLK ↑ MIN 1.1 SEL before CLK ↑ MIN 2.1 CLKENBA before CLK ↑ MIN 2 B data after CLK ↑ MIN 1.2 SEL after CLK ↑ MIN 0.8 CLKENBA after CLK ↑ MIN 0.3 AB 3.2 CLK A 5.2 ten OEAB or OEBA A or B 5.1 tdis OEAB or OEBA A or B 4.9 UNIT fmax : MHz other : ns tsu Setup time th Hold time MAX MAX tpd PARAMETER MAX or MIN ALVCH 3V UNIT ICC MAX 0.04 mA IOH MAX -24 mA IOL MAX 24 mA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16525 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS

659PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. INPUTS X A H L B0† H CLKENAB CLKAB H X L L L A-TO-B STORAGE (OEAB = L) † Output level before the indicated steady-state input conditions were established FUNCTION TABLE INPUTS X BCLK2BA CLK1BA H L A0† H L CLKENA SEL H X H L H L X L L L LX X H X L B-TO-A STORAGE (OEBA = L) OUTPUT B OUTPUT A † Output level before the indicated steady-state input conditions were established ‡ Three CLK1BA edges and one CLK2BA edge are needed to propagate data from B to A when SEL is low. PARAMETER MAX or MIN ALVCH 3V UNIT ICC MAX 0.04 mA IOH MAX -24 mA IOL MAX 24 mA PARAMETER INPUT OUTPUT MAX or MIN ALVCH fmax MIN 150 tw Pulse duration, CLK high or low MIN 3 A data before CLKAB ↑ MIN 1.3 B data before CLK2BA ↑ MIN 1.7 B data before CLK1BA ↑ MIN 1.1 SEL before CLK2BA ↑ MIN 3.3 CLKENAB before CLKAB ↑ MIN 1.6 CLKENBA before CLK1BA ↑ MIN 2.1 CLKENBA before CLK2BA ↑ MIN 2.2 A data after CLKAB ↑ MIN 0.9 B data after CLK2BA ↑ MIN 0.6 B data after CLK1BA ↑ MIN 1 SEL after CLK2BA ↑ MIN 0.1 CLKENAB after CLKAB ↑ MIN 0.3 CLKENBA after CLK1BA ↑ MIN 0.1 CLKENBA after CLK2BA ↑ MIN 0 tpd CLKAB or CLK2BA A or B 4.2 ten OEAB or OEBA A or B 5.1 tdis OEAB or OEBA A or B 4.9 UNIT fmax : MHz other : ns MAX tsu Setup time th Hold time ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

To Seven Other Channels To Seven Other Channels 362 13 : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16540 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS FUNCTION TABLE (each 8-bit section) INPUTS H L A H X OUTPUT Y H Z X L OE2 H L X OE1 L LL X Z PARAMETER MAX or MIN ABT ACT AHC AHCT LVCH 3V UNIT ICC MAX 34 0.08 0.04 0.04 0.02 mA IOH MAX -32 -24 -8 -8 -24 mA IOL MAX 64 24 8 8 24 mA PARAMETER INPUT OUTPUT MAX or MIN ABT ACT AHC AHCT LVCH tPZH 5.1 8.9 10.5 13 4.8 tPZL 5.9 10.5 10.5 13 4.8 tPHZ 5.7 11.9 10.5 13 5.9 tPLZ 4.7 11.1 10.5 13 5.9 UNIT: ns OE Y MAX AY MAX OE Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

661PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram 16541 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 1OE1 1OE2 2OE1 2OE2 1A1 1Y1 2Y12A1 To Seven Other Channels To Seven Other Channels 362 13 FUNCTION TABLE (each 8-bit section) INPUTS H L A H X OUTPUT Y H Z X L OE2 H L X OE1 L LL X Z PARAMETER MAX or MIN ABT LVTH 3V ACT AHC AHCT LVCH 3V UNIT ICC MAX 34 5 0.08 0.04 0.04 0.02 mA IOH MAX -32 -32 -24 -8 -8 -24 mA IOL MAX 64 64 24 8 8 24 mA PARAMETER INPUT OUTPUT MAX or MIN ABT LVTH 3V ACT AHC AHCT LVCH tPZL 6 4.6 11 10.5 13 5.6 UNIT: ns OE Y MAX AY MAX OE Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16543 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

663PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE (each 8-bit section) INPUTS OUTPUT B B0‡ X † A-to-B data flow is shown: B-to-A flow control is the same except that it uses CEBA, LEBA, and OEBA. ‡O utput level before the indicated steady-state input conditions were established. L H X H L AOEAB L L XZ L H H H L CEAB LEAB XX LL XZ LL X PARAMETER MAX or MIN ABT LVTH 33V V AC ACT LVCH ALVCH 3V UNIT ICC MAX 35 5 0.08 0.08 0.02 0.04 mA IOH MAX -32 -32 -24 -24 -24 -24 mA IOL MAX 64 LVT -32 64 64 24 24 24 24 mA PARAMETER INPUT OUTPUT MAX or MIN ABT LVTH 3V AC ACT LVCH ALVCH tw Pulse duration, LEAB or LEBA low MIN 43 . 3 4 7.5 3.3 3.3 Data before CEAB ↑ or CEBA ↑ , high MIN -0 -- 1.1 1.2 Data before CEAB ↑ or CEBA ↑ , low MIN -0 . 6 -- 1 . 1 1.2 Data after LEAB ↑ or LEBA ↑ , high MIN 1.5 1.5 3 4 1.9 1.3 Data after LEAB ↑ or LEBA ↑ , low MIN 21 . 2 3 4 1.9 1.3 Data after CEAB ↑ or CEBA ↑ , high MIN -1 . 7 - - 1.9 1.3 Data after CEAB ↑ or CEBA ↑ , low MIN -1 . 6 - - 1.9 1.3 tPLZ 5.4 4 LVT 3.3 0.8 1.5 0.7 1.6 0.8 1.2 0.8 1.3 4.6 4.6 6.3 5.8 6.2 6.5 5.8 6.4 6.4 UNIT: ns MAX MAXA or B B or A OE A or B MAX LE A or B MAX CE A or B MAX t su Setup time th Hold time OE A or B MAX CE A or B ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16600 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

665PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE INPUTS H OUTPUT B H B0‡ X L † A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CLKBA and CLKENBA. ‡O utput level before the indicated steady-state input conditions were established. §O utput level before the indicated steady-state input conditions were established, provided that CLKAB was low before LEAB went low. H X H L A X L L L X XZ L L H H H H LX X B0§ H L L H CLKENAB OEAB LEAB CLKAB X L X X B0‡ B0‡ L X L X L L X L X L L L L L L L PARAMETER MAX or MIN ABT ALVCH 3V UNIT ICC MAX 36 0.04 mA IOH MAX -32 -24 mA IOL MAX 64 24 mA PARAMETER INPUT OUTPUT MAX or MIN ABT ALVCH fmax MIN 150 150 tw Pulse duration LEAB or LEBA high MIN 2.5 3.3 CLKAB or CLKBA high or low MIN 3 3.3 tsu Setup time A before CLKAB ↓ or B before CLKBA ↓ MIN 3 - Data before CLK ↑ -1 . 2 A before LEAB ↓ or B before LEBA ↓ , CLK high MIN 2.5 1.1 A before LEAB ↓ or B before LEBA ↓ , CLK low MIN 2.5 1.5 CLKEN after CLK ↓ 2.5 - CLKEN after CLK ↑ MIN 2.5 0.8 th Hold time A after CLKAB ↓ or B after CLKBA ↓ MIN 0 - Data after CLK ↑ -1 . 5 A after LEAB ↓ or B after LEBA ↓ , CLK high MIN 2 1.6 A after LEAB ↓ or B after LEBA ↓ , CLK low MIN 2 1.3 CLKEN after CLK ↓ 1- CLKEN after CLK ↑ MIN - 1.4 tPLH 44 tPHL 4.9 4 tPLH 5 4.8 tPHL 5 4.8 tPLH 5.3 5.7 tPHL 5 5.7 tPZH 5.1 5.2 tPZL 5.4 5.2 tPHZ 6.2 4.4 tPLZ 5.4 4.4 tPZH 5.1 5.2 tPZL 5.4 5.2 tPHZ 6.2 4.4 tPLZ 5.4 4.4 UNIT fmax : MHz other : ns OEBA A MAX OEBA A MAX A or B MAX OEAB B or A MAX B or A MAX MAX B or A LEAB or LEBA CLKAB or CLKBA OEAB B MAX B ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16601 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

667PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE INPUTS H OUTPUT B H B0‡ X L † A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CLKBA and CLKENBA. ‡O utput level before the indicated steady-state input conditions were established. §O utput level before the indicated steady-state input conditions were established, provided that CLKAB was low before LEAB went low. L X H L A X L L H X XZ L L H H H H LX X B0§ H L L H CLKENAB OEAB LEAB CLKAB X L X X B0‡ B0‡ L X L X L L X L X L L L L L L L PARAMETER MAX or MIN ABT ALVTH ALVCH ALVCHR ICC MAX 36 5 0.04 0.04 IOH MAX -32 -32 -24 -12 IOL MAX 64 64 24 12 PARAMETER INPUT OUTPUT MAX or MIN ABT ALVTH ALVCH fmax MIN 150 150 150 LEAB or LEBA high MIN 2.5 1.8 3.3 CLKAB or CLKBA high or low MIN 3 2.3 3.3 Data before CLK ↑ high 4 2.4 2.1 Data before CLK ↑ low 4 3.8 2.1 A before LEAB ↓ or B before LEBA ↓ , CLK high MIN 2.5 11 . 6 A before LEAB ↓ or B before LEBA ↓ , CLK low MIN 1 0. 6 1.1 CLKEN before ↑ high 2.5 1.4 1.7 CLKEN before ↑ low 2.5 1.9 1.7 Data after CLK ↑ high 0 0.5 0.8 Data after CLK ↑ low 0 0.5 0.8 A after LEAB ↓ or B after LEBA ↓ , CLK high MIN 2 2 1.4 A after LEAB ↓ or B after LEBA ↓ , CLK low MIN 2 2. 3 1.7 CLKEN after ↑ high 0 0.6 0.6 CLKEN after ↑ low 0 0.5 0.6 tPLH 4 3.9 4.1 tPHL 4.9 3.9 4.1 tPLH 5 4.6 4.7 tPHL 5.2 4.6 4.7 tPLH 4.7 4.5 5 tPHL 4.6 4.6 5 tPZH 5.5 4.2 5.2 tPZL 5.8 4.4 5.2 tPHZ 6.2 5.3 4.4 tPLZ 5.4 4.6 4.4 tPZH 5.5 4.2 5.2 tPZL 5.8 4.4 5.2 tPHZ 6.2 5.3 4.4 tPLZ 5.4 4.6 4.4 UNIT fmax : MHz other : ns OEBA A MAX A or B B or A B or A B or A A OEAB OEAB CLKAB or CLKBA MAX OEBA B MAX B MAX MAX t w Pulse duration MAX LEAB or LEBA MAX tsu Setup time th Hold time MIN MIN MIN MIN ALVCHR 150 3.3 3.3 2.1 2.1 1.6 1.1 1.7 1.7 0.8 0.8 1.4 1.7 0.6 0.6 4.4 4.4 5.1 5.1 5.4 5.4 5.6 5.6 4.7 4.7 5.6 5.6 4.7 4.7 ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

To Seven Other ChannelsTo Seven Other Channels : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16620 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

669PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE INPUTS L L OEAB H OPERATION L OEBA B data to A bus A data to B bus H Isolation B data to A bus, A data to B bus HH L PARAMETER MAX or MIN AC ACT UNIT ICC MAX 0.08 0.08 mA IOH MAX -24 -24 mA IOL MAX 24 24 mA PARAMETER INPUT OUTPUT MAX or MIN AC ACT tPLH 6.8 8.5 tPHL 8.2 10.5 tPLH 6.8 8.5 tPHL 8.2 10.5 tPZH 7.9 9.1 tPZL 9.4 10.9 tPHZ 9.2 11.9 tPLZ 8.3 10.6 tPZH 7.3 8.9 tPZL 9.1 10.5 tPHZ 9 10.8 tPLZ 8 9.6 UNIT: ns OEAB B MAX A A OEAB B MAX OEBA MAX AB MAX OEBA MAX BA MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16623 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS FUNCTION TABLE (each 8-bit section) INPUTS H L OEAB H OPERATION L OEBA B data to A bus A data to B bus H Isolation LH L B data to A bus, A data to B bus PARAMETER MAX or MIN ABT ACT UNIT ICC MAX 35 0.08 mA IOH MAX -32 -24 mA IOL MAX 64 24 mA PARAMETER INPUT OUTPUT MAX or MIN ABT ACT tPLH 3.6 7.7 tPHL 4.3 8.6 tPZH 4.9 9.5 tPZL 6 11.1 tPHZ 61 2 tPLZ 5.4 10.7 tPZH 4.9 9.3 tPZL 6 10.6 tPHZ 6 10.4 tPLZ 5.4 9.5 UNIT: ns OEAB B MAX OEAB B MAX OEBA A MAX A or B B or A MAX OEBA A MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

671PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram 1OE 1DIR 1A1 1B1247 To Seven Other Channels 2OE 2DIR 2A1 2B11336 To Seven Other Channels 16640 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS FUNCTION TABLE (each 8-bit section) INPUTS L DIR OPERATION L OE H Isolation LH X B data to A bus A data to B bus PARAMETER MAX or MIN ABT AC ACT UNIT ICC MAX 32 0.08 0.08 mA IOH MAX -32 -24 -24 mA IOL MAX 64 24 24 mA PARAMETER INPUT OUTPUT MAX or MIN ABT AC ACT tPLH 4.3 7.3 9.1 tPHL 3.9 8.6 10.5 tPZH 5.5 8 9.8 tPZL 6.3 9.9 11.5 tPHZ 6.3 9.9 12.5 tPLZ 4.2 9 11 UNIT: ns OE A or B MAX A or B B or A MAX OE A or B MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16646 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS FUNCTION TABLE INPUTS SBASAB OPERATION OR FUNCTION Store B, A unspecitied † X Store A, B unspecitied † † The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every low-to-high transition of the clock inputs. X L DATA I/O Isolation, hold storage Store A and B data Stored B data to A bus Real-time B data to A bus Stored A data to B bus Real-time A data to B bus A1 THRU A8 Input Unspecified † Output Output Input Input Input Input disabled B1 THRU B8 Input Unspecified † Output Output Input Input Input Input disabled CLKBA X CLKAB X H or L L H DIR X X H L H L X X L L L H OE X X H or L H or L H or L X X X X X XH X X X X X X L H X X X

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 673 PARAMETER MAX or MIN ABT LVTH 3V AC ACT LVC LVCH ALVCH AVC 3V UNIT IOH MAX -32 -32 -24 -24 -24 -24 -24 -12 mA IOL MAX 64 64 24 24 24 24 24 12 mA PARAMETER INPUT OUTPUT MAX or MIN ABT LVTH 3V AC ACT LVC LVCH ALVCH fmax MIN 125 150 75 90 150 150 150 3.3 A or B before CLKAB ↑ or CLKBA ↑ , data high MIN 3 1.2 5 42 . 7 2 . 9 1.4 A or B before CLKAB ↑ or CLKBA ↑ , data low MIN 3 256 2 . 72 . 9 1.4 A or B after CLKAB ↑ or CLKBA ↑ , data high MIN 0 0. 511 . 5 0 .3 0.3 0.7 A or B after CLKAB ↑ or CLKBA ↑ , data low MIN 0 0. 511 . 5 0 .3 0.3 0.7 4.5 4.5 3.9 3.9 5.3 5.3 5.1 5.1 4.7 4.7 5.1 5.1 tPHZ 6.7 5.7 9.4 10.8 7 7 5.3 tPLZ 5.9 5.2 8.8 10.4 7 7 5.3 DIR A or B MAX A or B B or A MAX MAX MAX MAX MAX B or A A or B OE OE SAB or SBA DIR A or B A or B MAX tsu Setup time th Hold time B or ACLKAB or CLKBA LVT 150 3.3 1.3 2.4 0.5 0.5 5.7 5.7 4.7 4.7 6.2 6.2 5.4 5.6 6.5 5.8 5.7 5.8 7.2 6.6 PARAMETER INPUT OUTPUT MAX or MIN AVC f max MIN 350 tw Pulse duration CLKAB or CLKBA high or low MIN 1.4 A or B before CLKAB ↑ or CLKBA ↑ , data high MIN 0.8 A or B before CLKAB ↑ or CLKBA ↑ , data low MIN 0.8 A or B after CLKAB ↑ or CLKBA ↑ , data high MIN 0.6 A or B after CLKAB ↑ or CLKBA ↑ , data low MIN 0.6 tPLH 3.3 tPHL 3.3 tPLH 2.6 tPHL 2.6 tPLH 4 tPHL 4 tPZH 4 tPZL 4 tPHZ 4.2 tPLZ 4.2 tPZH 4.3 tPZL 4.3 tPHZ 4.3 tPLZ 4.3 UNIT fmax : MHz other : ns DIR A or B MAX A or B B or A MAX MAX MAX MAX MAX B or A A or B OE OE SAB or SBA DIR A or B A or B MAX tsu Setup time th Hold time B or ACLKAB or CLKBA LVT -32 ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16651 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

675PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE INPUTS X X CLKABOEAB X X X OPERATION OR FUNCTION Isolation Store A and B data Store A data to B bus and Store A, hold B Store B data to A bus Store A data to B bus Store A in both registers Hold A, store B Store B in both registers Real-time B data to A bus Real-time A data to B bus L L L L CLKBA X X X L L SAB H HH X L SBA H X XX XX X X X X X X X X L OEBA H H H H H H L L L L DATA I/O † B1-B8A1-A8 Input Output Unspecified‡ Output Output Output Output Output Input Input Output Input Output Input Unspecified‡ Input Input Input Input Input Input Input † The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions are always enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs. ‡ Select control = L; clocks can occur simultaneously. Select control = H; clocks must be staggered to load both registers. L H H H H L L L L L L L Store B data to A bus PARAMETER MAX or MIN ACT UNIT ICC MAX 0.08 mA IOH MAX -24 mA IOL MAX 24 mA PARAMETER INPUT OUTPUT MAX or MIN ACT fmax MIN 90 tw Pulse duration CLKAB or CLKBA high or low MIN 5.5 tsu Setup time A before CLKAB ↑ or B before CLKBA ↑ MIN 5.3 th Hold time A after CLKAB ↑ or B after CLKBA ↑ MIN 1 tPLH 11.3 tPHL 11.9 tPLH 13.7 tPHL 13.6 tPLH 17.3 tPHL 17.8 tPZH 12.3 tPZL 13.9 tPHZ 10.6 tPLZ 10.8 tPZH 11.9 tPZL 13.5 tPHZ 11.4 tPLZ 11.6 UNIT fmax : MHz other : ns MAX OEBA A or B A or B A A CLKAB or CLKBA B OEBA SAB or SBA OEAB OEAB B MAX A or B B or A MAX MAX MAX MAX MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16652 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

677PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE INPUTS SBASAB OPERATION OR FUNCTION Store B in both registers X † The data output functions may be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs. Data input functions are always enabled; i.e., data at the bus pins is stored on every low-to-high transition of the clock inputs. ‡ Select control = L; clocks can occur simultaneously. Select control = H; clocks must be staggered in order to load both registers. X DATA I/O† Isolation Store A and B data Store A data to B bus Real-time B data to A bus Stored A data to B bus and stored B data A bus Real-time A data to B bus A1 THRU A8 Input Output Output Input Input Input Unspecified ‡ B1 THRU B8 Input Output Output Input Input Input Unspecified ‡ CLKBACLKAB H or L H L OEAB L H H L X L L L H OEBA X H or L H or L H or L X X X X X X X X X X X L H X X X X L L H H H H H H L L H or L H or L H or L H or L L H H X X H X Output Output Output Input Input Output Input Input Stored B data to A bus Store A, hold B Store A in both registers Hold A, store B PARAMETER MAX or MIN ABT LVTH 3V AC ACT LVCH 3V UNIT ICC MAX 32 5 0.08 0.08 0.02 mA IOH MAX -32 -32 -24 -24 -24 mA IOL MAX 64 64 24 24 24 mA PARAMETER INPUT OUTPUT MAX or MIN ABT LVTH 3V AC ACT LVCH fmax MIN 125 150 95 90 150 tw Pulse duration CLKAB or CLKBA high or low MIN 4.3 3. 35 5.5 3.3 A before CLKAB ↑ or B before CLKBA ↑ , high MIN 3 1.2 4 .5 4.5 3 A before CLKAB ↑ or B before CLKBA ↑ , low MIN 3 2 4.5 4.5 3 A after CLKAB ↑ or B after CLKBA ↑ , high MIN 0 0.5 0 1 0.2 A after CLKAB ↑ or B after CLKBA ↑ , low MIN 0 0.5 0 1 0.2 tPLH 5 4.5 13.8 16 7.4 tPHL 5 4.5 13.8 16.9 7.4 tPZH 5 4.3 10.7 11.7 6.3 tPLZ 4 5.4 8.7 9.2 6.2 tPZL 4.6 4.2 13 12.4 6.3 tPHZ 5.9 5.5 8 10.5 6.2 UNIT fmax : MHz other : ns tsu Setup time th Hold time OEAB B CLKAB or CLKBA MAX A or B B or A MAX MAX MAX MAXA MAX B OEBA SAB or SBA OEAB MAX OEBA A or B A or B A ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16657 16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS

679PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ABT ACT UNIT ICC MAX 36 0.08 mA IOH MAX -32 -24 mA IOL MAX 64 24 mA PARAMETER INPUT OUTPUT MAX or MIN ABT ACT tPLH 4.1 10.7 tPHL 4.3 10.6 tPLH 6.7 14.3 tPHL 6.1 14.3 tPLH 6.7 13.7 tPHL 6.1 14.1 tPLH 6.7 14.6 tPHL 6.1 14.7 tPLH 6.7 13.8 tPHL 6.1 14.2 tPZH 5.6 11.3 tPZL 61 3 tPHZ 5.4 11.2 tPLZ 4.3 10.5 tPZH 5.6 11.3 tPZL 61 3 tPHZ 5.4 11.2 tPLZ 4.3 10.5 UNIT: ns MAX MAX A or B B or A MAX PARITY ERR OE MAX A or B ODD / EVEN PARITY, ERR MAX ERR PARITY MAX B OE PARI TY, ERR MAX A or B A or B OE PARI TY, ERR MAX OE MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE (each 8-bit section) INPUTS L INPUT/OUTPUT PARITYOE NUMBER OF A OR B INPUTS THAT ARE HIGH L L L L L L L L L L L H T/R L L L L L L L L X ODD/EVEN L L L L L L H H H H 0, 2, 4, 6, 8 1, 3, 5, 7 Don't care X H H H H H H L L Z H H L L H H L L H H ERR Z L L L L H H H H Z Z Z Z OUTPUTS OUTPUT MODE Z Receive Transmit Receive Transmit Receive Receive Receive Transmit Receive Transmit Receive Receive

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS680 Logic Diagram16721 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS CLK CLKEN To 19 Other Channels OE CE 55 2 FUNCTION TABLE (each filp-flop) INPUTS OUTPUT Q L X H L DCLK L X Z L H H L OE CLKEN X L L X QO L X HL LH QO PARAMETER MAX or MIN ALVCH 3V UNIT ICC MAX 0.04 mA IOH MAX -24 mA IOL MAX 24 mA PARAMETER INPUT OUTPUT MAX or MIN ALVCH fmax MIN 150 tw Pulse duration CLK high or low MIN 3.3 Data before CLK ↑ MIN 3.1 CLKEN before CLK ↑ MIN 2.7 Data after CLK ↑ MIN 0 CLKEN after CLK ↑ MIN 0 tPLH 4.3 tPHL 4.3 tPZH 4.8 tPZL 4.8 tPHZ 4.4 tPLZ 4.4 UNIT fmax : MHz other : ns MAX MAXQ Q MAX tsu Setup time th Hold time CLK Q OE OE ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 16722 22-BIT FLIP-FLOP WITH 3-STATE OUTPUTS CLK CLKEN To 21 Other Channels OE CE 63 2 FUNCTION TABLE (each filp-flop) INPUTS OUTPUT Q L X X L DCLK L X Z L H H L OE CLKEN X L L or H X QO L X HL LH QO PARAMETER MAX or MIN AVC 3V UNIT ICC MAX 0.04 mA IOH MAX -12 mA IOL MAX 12 mA PARAMETER INPUT OUTPUT MAX or MIN AVC fmax MIN 150 tw Pulse duration CLK high or low MIN 2.8 Data before CLK ↑ MIN 2.5 CLKEN before CLK ↑ MIN 1.4 Data after CLK ↑ MIN 0 CLKEN after CLK ↑ MIN 1.2 tPLH 2.6 tPHL 2.6 tPZH 4.3 tPZL 4.3 tPHZ 3.4 tPLZ 3.4 UNIT fmax : MHz other : ns MAX MAXQ Q MAX tsu Setup time th Hold time CLK Q OE OE ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16820 10-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH DUAL OUTPUTS 2OE 1Q1CLK To Nine Other Channels 1OE 1Q2 FUNCTION TABLE (each fllp-flop) INPUTS H L D H X OUTPUT Qn† H Z L L OEn† X CLK L X Q0LL † n = 1, 2 PARAMETER MAX or MIN ALVCH 3V UNIT ICC MAX 0.04 mA IOH MAX -24 mA IOL MAX 24 mA PARAMETER INPUT OUTPUT MAX or MIN ALVCH fmax MIN 150 tw Pulse duration CLK high or low MIN 3.3 tsu Setup time Data before CLK ↑ MIN 1.4 th Hold time Data after CLK ↑ MIN 1 tPLH 4.8 tPHL 4.8 tPZH 5 tPZL 5 tPHZ 4.5 tPLZ 4.5 UNIT fmax : MHz other : ns MAX MAXQ Q MAXCLK Q OE OE ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 16821 20-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS 1D1 1OE 1Q1 1CLK To Nine Other Channels 2D1 2OE 2Q1 2CLK To Nine Other Channels One of Ten Channels One of Ten Channels FUNCTION TABLE (each fllp-flop) INPUTS H L D H X OUTPUT Q H Z L L OE X CLK L X Q0LL PARAMETER MAX or MIN ABT ALVTH 3V ACT ALVCH 3V UNIT ICC MAX 89 5 0.08 0.04 mA IOH MAX -32 -32 -24 -24 mA IOL MAX 64 64 24 24 mA PARAMETER INPUT OUTPUT MAX or MIN ABT ALVTH 3V ACT ALVCH fmax MIN 150 150 70 150 tw Pulse duration CLK high or low MIN 3.3 1.5 7 3.3 Data before CLK ↑ , low MIN 1.8 1.5 7.5 3.4 Data before CLK ↑ , high MIN 1.8 1.5 7.5 3.4 Data after CLK ↑ , high MIN 1.3 1 0.5 0 Data after CLK ↑ , low MIN 1.3 1 0.5 0 tPLH 6.1 3.5 13.4 4.5 tPHL 5.4 3.5 14 4.5 tPZH 5.7 4.1 11.9 5.1 tPZL 5.6 3.6 14.7 5.1 tPHZ 6.5 4.8 10.7 4.6 tPLZ 7.1 4.8 10 4.6 UNIT fmax : MHz other : ns tsu Setup time th Hold time CLK Q OE OE MAX MAXQ Q MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS684 16823 18-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH DUAL OUTPUTS To Eight Other Channels 1D1 1Q1 1CLKEN 1OE 1CLR R C1 3 CE 1CLK To Eight Other Channels 2D1 2Q1 2CLKEN 2OE 2CLR R C1 15 CE 2CLK FUNCTION TABLE (each 9-bit filp-flop) INPUTS OUTPUT Q L X L DCLK L X Z L H H L OE CLKEN X L L X L X H L LH CLR X H L H H XLH X X XL PARAMETER MAX or MIN ABT ABTH AC ACT ALVCH 3V UNIT ICC MAX 80 80 0.08 0.08 0.04 mA IOH MAX -32 -32 -24 -24 -24 mA IOL MAX 64 64 24 24 24 mA PARAMETER INPUT OUTPUT MAX or MIN ABT ABTH AC ACT ALVCH fmax MIN 150 150 115 90 150 Data high before CLK ↑ MIN 1.7 1.7 5 7 1 Data low before CLK ↑ MIN 1.7 1.7 5 7 1.3 tPLH 6.8 6.8 12 12.1 4.5 tPHL 66 12.7 12.9 4.5 tPLH ---- 4 . 6 tPHL 6.1 6.7 11 12.5 4.6 UNIT fmax : MHz other : ns Q MAX Q MAX Q OE OE MAX MAXQ tsu Setup time th Hold time tw Pulse duration CLR CLK ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS Logic Diagram

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 685 Logic Diagram16825 18-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 1OE1 1Y1 1OE2 56 1A1 55 To Eight Other Channels 2OE1 2Y1 2OE2 29 2A1 41 To Eight Other Channels FUNCTION TABLE (each 9-bit section) INPUTS H L A H X OUTPUT Y H Z X L OE2 H L X OE1 L LL X Z PARAMETER MAX or MIN ABT ACT ALVCH 3V UNIT ICC MAX 32 0.08 0.04 mA IOH MAX -32 -24 -24 mA IOL MAX 64 24 24 mA PARAMETER INPUT OUTPUT MAX or MIN ABT ACT ALVCH tPLH 3.9 10.5 3.4 tPHL 4.4 10.3 3.4 tPZH 6.1 11 4.7 tPZL 6 13.2 4.7 tPHZ 6.9 11.5 4.5 tPLZ 6.6 10.6 4.5 UNIT: ns OE Y MAX AY MAX OE Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS686 16827 20-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 1Y12 1OE1 1OE2 56 2Y115 292OE1 2OE2 To Nine Other Channels To Nine Other Channels 1A1 2A1 Logic Diagram

687PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE (each 10-bit section) INPUTS H L A H X OUTPUT Y H Z X L OE2 H L X OE1 L LL X Z PARAMETER MAX or MIN ABT ALVTH 3V ACT ALVCH AVC 3V UNIT ICC MAX 32 6 0.08 0.04 0.04 mA IOH MAX -32 -32 -24 -24 -12 mA IOL MAX 64 64 24 24 12 mA PARAMETER INPUT OUTPUT MAX or MIN ABT ALVTH 3V ACT ALVCH AVC tPLH 3.4 3 11 3.4 1.7 tPZL 5.5 3.4 14 4.7 5.1 UNIT: ns OE Y MAX AY MAX OE Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS688 16831 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS Logic Diagram CLK D Q To Eight Other Channels OE1 OE2 CLK SEL 1Y1 2Y1 3Y1 4Y1 FUNCTION TABLE INPUTS X H H CLKSEL OUTPUT Y Z OE H L L L L X X X A X L L L H L H L H L H PARAMETER MAX or MIN ALVCH 3V UNIT ICC MAX 0.04 mA IOH MAX -24 mA IOL MAX 24 mA PARAMETER INPUT OUTPUT MAX or MIN ALVCH fmax MIN 150 tw Pulse duration CLK high or low MIN 3.3 tsu Setup time A data before CLK ↑ MIN 1.6 th Hold time A data after CLK ↑ MIN 1.1 tPLH 3.6 tPHL 3.6 tPLH 3.9 tPHL 3.9 tPLH 4.4 tPHL 4.4 tPZH 4.3 tPZL 4.3 tPHZ 4.5 tPLZ 4.5 UNIT fmax : MHz other : ns MAX SEL Y MAX YCLK OE OE Y AY MAX MAX MAX Y ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

689PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram CLK D Q To Six Other Channels OE1 OE2 CLK SEL 1Y1 2Y1 3Y1 4Y1 16832 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS FUNCTION TABLE INPUTS X H H CLKSEL OUTPUT Y Z OE H L L L L X X X A X L L L H L H L H L H PARAMETER MAX or MIN ALVCH 3V UNIT ICC MAX 0.04 mA IOH MAX -24 mA IOL MAX 24 mA PARAMETER INPUT OUTPUT MAX or MIN ALVCH fmax MIN 150 tw Pulse duration CLK high or low MIN 3.3 tsu Setup time A data before CLK ↑ MIN 1.6 th Hold time A data after CLK ↑ MIN 1.1 tPLH 3.6 tPHL 3.6 tPLH 3.9 tPHL 3.9 tPLH 4.4 tPHL 4.4 tPZH 4.3 tPZL 4.3 tPHZ 4.5 tPLZ 4.5 UNIT fmax : MHz other : ns MAX MAX MAX Y OE OE Y AY MAX SEL Y MAX YCLK ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

R EN EN 1A1–1A8 1CLK 1PARITY 1B1–1B8 2ERR 2CLR 2OEA 2OEB MUX R EN EN 2A1–2A8 2CLK 2PARITY 2B1–2B8 : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16833 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

691PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. CLR A data to B bus and generate parity A data to B bus and generate inverted parity INPUTS OUTPUT AND I/O FUNCTIONCLK Ai Σ OF H Bi† Σ OF H B PARITY ERR ‡OEA X Odd Even Odd Even Odd Even X X X X XX X X X XX X L H NAAH H HH H H ↑ OEB L NALL H LA NC L L H H L H No No Isolation§ Check error flag register B data to A bus and check parity L H A NA NA NA HNA NA NA ZZZ B NA Odd Even NA NAL FUNCTION TABLE † State of ERR before any changes at CLR, CLK, or point P CLR Clear INPUTS INTERNAL TO DEVICE OUTPUT PRE-STATE OUTPUT ERR FUNCTION CLK POINT P ERRn-1† XX X X H H H L H L HH L L X L H Sample ERROR-FLAG FUNCTION TABLE NA = not applicable, NC = no change, X = don’t care † Summation of high-level inputs includes PARITY along with Bi inputs. ‡ Output states shown assume ERR was previousiy high. § In this mode, ERR (when clocked) shows inverted panrity of the A bus. PARAMETER MAX or MIN ABT ACT UNIT ICC MAX 36 0.08 mA IOH MAX -32 -24 mA IOL MAX 64 24 mA PARAMETER INPUT OUTPUT MAX or MIN ABT ACT CLK high or low 34 CLR low -4 A data before CLK ↑ , A port 4..5 - A data before CLK ↑ , CLR 11 . 5 A data before CLK ↑ , OEA 5- th Hold time A data after CLK ↑ , A port or OEA MIN 0 0 tPLH 4.1 10.4 tPHL 4.3 10.7 tPLH 6.7 13.5 tPHL 6.1 13.8 tPZH 5.6 11.2 tPZL 61 3 tPHZ 5.4 10.8 tPLZ 4.3 10.1 tPLH CLK, CLR 4.6 15.8 tPHL CLK 3.9 11.6 tPLH 6.7 - tPHL 6.1 - tPLH 6.7 13.2 tPHL 6.1 13.6 tPZH 5.7 9.5 tPZL 6.5 10.7 tPHZ 4.7 10.2 tPLZ 4.1 9.7 tPZH 5.7 - tPZL 6.5 - tPHZ 4.7 - tPLZ 4.1 - UNIT: ns OEA PARITY MAX OEA PARITY OEB PARITY MAX MAX MAX MAX MAX MIN MIN MAX MAX MAX MAX MAX A PARITY OEA PARITY ERR OEB PARITY tw Pulse duration OEB PARITY OEB or OEA tsu Setup time B or A A or B A or B OEB or OEA A or B ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16834 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS OE CLK CLK To 17 Other Channels LE FUNCTION TABLE INPUTS X L ACLK L L OUTPUT Y Z HH OE H L X L X X H L LE X H HL L HH X L Y0†H L X Y0‡H L L L † Output level before the indicated steady-state input conditions were established, provided that CLK is high before LE goes high ‡ Output level before the indicated steady-state input conditions were established PARAMETER MAX or MIN ALVC AVC 3V UNIT ICC MAX 0.04 0.04 mA IOH MAX -24 -12 mA IOL MAX 24 12 mA PARAMETER INPUT OUTPUT MAX or MIN ALVC AVC fmax MIN 150 150 LE low MIN 3.3 3.3 CLK high or low MIN 3.3 3.3 Data before CLK ↑ MIN 1.7 0.7 Data before LE ↑ , CLK high 1.9 1 Data before LE ↑ , CLK low 1.5 1 A data after CLK ↑ MIN 0.7 0.9 Data after LE ↑ , CLK high 0.9 1.4 Data after LE ↑ , CLK low 0.9 1.3 tPLH 3.6 2.5 tPHL 3.6 2.5 tPLH 4.9 4 tPHL 4.9 4 tPLH 4.6 3.1 tPHL 4.6 3.1 tPZH 5 6.2 tPZL 5 6.2 tPHZ 4.5 5.3 tPLZ 4.5 5.3 UNIT fmax : MHz other : ns MIN MIN MAX MAX MAX t h Hold time Y tsu Setup time tw Pulse duration OE Y AY LE Y OE CLK MAX MAX Y ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 16835 3.3-V ABT 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS OE CLK CLK To 17 Other Channels LE FUNCTION TABLE † Output level before the indicated steady-state input conditions were established, provided that CLK was high before LE went low. ‡ Output level before the indicated steady-state input conditions were established INPUTS H L L L L OUTPUT YOE XX LE X X X H CLK H L A H L H L Y0† Y0‡ Z L H H L XL X H LLL L L PARAMETER MAX or MIN LVTH ALVC ALVCH AVC 3V UNIT ICC MAX 5 0.04 0.04 0.04 mA IOH MAX -32 -24 -24 -12 mA IOL MAX 64 24 24 12 mA PARAMETER INPUT OUTPUT MAX or MIN LVTH ALVC ALVCH AVC fmax MIN 150 150 150 150 LE low MIN 3.3 3. 33 . 33 . 3 CLK high or low MIN 3.3 3. 33 . 33 . 3 Data before CLK ↑ MIN 2.1 1. 71 . 70 . 7 Data before LE ↓ , CLK high MIN 2.3 1. 51 . 50 . 8 Data before LE ↓ , CLK low MIN 1.5 1 1 0.5 A data after CLK ↑ MIN 1 0.7 0 .7 1.3 Data after LE ↓ , CLK high MIN 0.8 1. 41 . 41 . 6 Data after LE ↓ , CLK low MIN 0.8 1. 41 . 41 . 4 tPLH 3.7 3.6 3.6 2.5 tPHL 3.7 3.6 3.6 2.5 tPLH 5.1 4.2 4.2 3.8 tPHL 5.1 4.2 4.2 3.8 tPLH 5.1 4.5 4.5 3.1 tPHL 5.1 4.5 4.5 3.1 tPZH 4.6 4.6 4.6 6.2 tPZL 4.6 4.6 4.6 6.2 tPHZ 5.8 3.9 3.9 5.3 tPLZ 5.8 3.9 3.9 5.3 UNIT fmax : MHz other : ns YCLK th Hold time MAXY LE Y MAX tsu Setup time tw Pulse duration MAX MAX MAX Y OE OE Y A ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16841 20-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS FUNCTION TABLE (each 10-bit latch) INPUTS H L D H X OUTPUT Q H Z L L OE X LE L X Q0LL H H PARAMETER MAX or MIN ABT ACT ALVCH 3V UNIT ICC MAX 89 0.08 0.04 mA IOH MAX -32 -24 -24 mA IOL MAX 64 24 24 mA TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS MAX or MIN ABT ACT ALVCH 44 3 . 3 4- 3 . 3 11 . 5 - -- 1 . 1 23- 24 . 5 - MIN -- 1 . 1 5 11.8 3.9 5.1 12.2 3.9 5 12.7 4.3 5 12.7 4.3 5.7 11.3 4.9 5.6 13.7 4.9 6.5 10.2 4.1 7.1 9.6 4.1 UNIT : ns LE MIN MIN high low Data after LE high low MIN tPLH tPHL tPLH Pulse duration Setup time Hold timeth tsu tPZL tPHZ tPLZ Data before LE ↓ Data before LE ↑ Q Q OE OE Data after LE ↑ LE Q Q tPZH MAX MAX PARAMETER INPUT OUTPUT tw tPHL MAX MAX D ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS

695PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 16843 18-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS Logic Diagram 1Q1 R 1OE 2 To Eight Other Channels 1PRE 55 1CLR 1 1LE 56 1D1 54 2Q1 R 2OE 27 To Eight Other Channels 2PRE 30 2CLR 28 2LE 29 2D1 42 INPUTS OUTPUT Q X L DLE L Z L H H L L X H L L H CLR X H L H HX X X L OEPRE X X H H X H X HH H L L FUNCTION TABLE (each 9-bit latch) PARAMETER MAX or MIN ABT UNIT ICC MAX 85 mA IOH MAX -32 mA IOL MAX 64 mA PARAMETER INPUT OUTPUT MAX or MIN ABT tw Pulse duration 3.3 3.3 3.3 t su Setup time 0.9 0.6 th Hold time 1.7 1.8 tPLH 4.8 tPHL 4.8 tPLH 5.9 tPHL 5.3 tPLH 6.1 tPHL 5 tPLH 5.4 tPHL 6 tPZH 5.4 tPZL 5.8 tPHZ 6.3 tPLZ 5.2 UNIT: ns OE OE CLR low PRE low LE high Data before LE ↓ , high Data before LE ↓ , low Data after LE ↓ , high Data after LE ↓ , low D LE PRE CLR MIN Q Q Q Q Q MIN MIN MAX MAX MAX MAX MAX MAX Q ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITION TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

B1–B8 A1–A8 LE OEA OEB EN EN MUX1 P : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16853 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS CLR A data to B bus and generate parity A data to B bus and generate inverted parity INPUTS OUTPUT AND I/Os FUNCTIONLE Ai Σ OF H Bi† Σ OF H B PARITY ERR ‡OEA X Odd Even L Odd H Even Odd Even X XX X X XX X L H NAAH H HH H X X OEB L NALL H LA NC NC L L HL H H L L H Isolation§ (parity check) Store error flag B data to A bus and check parity H HH H A NA NA NA XX XX XH Clear error flag registerL NA NA HNA NA NA ZZZ B NA Odd Even NA NA NALL HL CLR Clear INPUTS INTERNAL TO DEVICE OUTPUT OUTPUT ERR FUNCTION LE POINT P ERR n-1† X X X H HH H H L L L L H HHH L LL L H L X L H L Sample Pass StoreX H L X FUNCTION TABLE ERROR-FLAG FUNCTION TABLE NA = not applicable, NC = no change, X = don’t care † Summation of high-level inputs includes PARITY along with Bi inputs. ‡ Output states shown assume ERR was previousiy high. § In this mode, ERR (when clocked) shows inverted panrity of the A bus. † State of ERR before changes at CLR, LE, or point P

697PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ABT UNIT ICC MAX 40 mA IOH MAX -32 mA IOL MAX 64 mA PARAMETER INPUT OUTPUT MAX or MIN ABT LE high or low MIN 8.5 CLR low 4 A, B and PARITY before LE ↓ MIN 10 CLR before LE ↓ 0 A, B and PARITY after LE ↓ MIN 0 CLR after LE ↓ 0 tPLH 4.1 tPHL 4.3 tPLH 7.1 tPHL 7.2 tPLH CLR ERR MAX 5.7 tPZH 5.6 tPZL 6 tPHZ 5.4 tPLZ 4.3 tPZH 5.7 tPZL 6.5 tPHZ 4.7 tPLZ 4.1 tPLH 4.8 tPHL 4.9 tPLH 7.2 tPHL 7.4 UNIT: ns MAX MAX MAX MAX LE ERR MAX MAX tw Pulse duration OE A or B B or A A or OE PARITY tsu Setup time th Hold time A or B A, B or PARITY ERR MAX OE A or B OE PARITY MAX OE PARITY ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16861 20-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS PARAMETER MAX or MIN ACT UNIT ICC MAX 0.08 mA IOH MAX -24 mA IOL MAX 24 mA PARAMETER INPUT OUTPUT MAX or MIN ACT tPLH 10.4 tPHL 11.1 tPZH 10 tPZL 12.7 tPHZ 10.7 tPLZ 10 UNIT: ns OEBA or OEAB A or B MAX A or B B or A MAX OEBA or OEAB A or B MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS A to B B to A Isolation INPUTS OPERATION H OEBAOEAB L HH HL LL Latch A and B (A = B) FUNCTION TABLE (each 10-bit section)

699PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram 1OEBA 1OEAB 1A1 1B1255 To Nine Other Channels 2OEBA 2OEAB 2A1 2B11542 To Nine Other Channels 16863 18-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS PARAMETER MAX or MIN ABT ACT ALVCH 3V UNIT ICC MAX 32 0.08 0.04 mA IOH MAX -32 -24 -24 mA IOL MAX 64 24 24 mA PARAMETER INPUT OUTPUT MAX or MIN ABT ACT ALVCH tPLH 3.5 11.1 3.4 tPHL 3.9 11.8 3.4 tPZH 5.4 10.6 4.7 tPZL 4.8 13.6 4.7 tPHZ 6 11.6 4.2 tPLZ 51 1 4.2 UNIT: ns OEBA or OEAB A or B MAX A or B B or A MAX OEBA or OEAB A or B MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE (each 9-bit section) INPUTS H L H OPERATION L OEAB B data to A bus A data to B bus H Isolation OEBA H

1A1–1A8 1APAR 1ERRB 2A1–2A8 2APAR 2ERRB ODD/EVEN SEL OEBA 1B1–1B8 1BPAR 1ERRA 2B1–2B8 2BPAR 2ERRA 1CLKENBA 2CLKENBA CLKBA LEBA QA QB 64, 33 1, 32 : OBSOLETED or NOT RECOMMENDED NEW DESIGNS INPUTS H H H H H H L L L L OPERATION OR FUNCTION SEL H H L L OEBA L L Parity is checked on port A and is generated on port B. Parity is checked on port B and is generated on port A. Parity is checked on port B and port A. Parity is generated on port A and B if device is in FF mode. Parity funcions are disabled; device acts as a standard 18-bit registered transceiver. QA data to B, QB data to A QB data to A QA data to B Isolation OEAB H H H H L L L L PARITY-ENABLE FUNCTION TABLEFUNCTION TABLE INPUTS H L L L L OUTPUT BCLKENAB H L L L L OEAB X X L X L L X X LEAB X X X XH CLKAB H L H L A H L H L Z B0‡ B0§ B0‡ L H H L X L X L X L L ‡ Output level before the indicated steady-state input conditions were established § Output level before the indicated steady-state input conditions were established, provided that CLKAB was low before LEAB went low INPUTS OUTPUTS H 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 N/A N/A N/A N/A 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 N/A N/A N/A N/AN/A N/A N/A N/A N/A N/AN/A N/A N/A N/A N/A BPAR ERRA BPAR ERRB H L H L N/A N/A N/A N/A H L H L H L H L H L H L H L H L H L H L H L H L H L H H H L L H L H L H L H L H L L H H L L H H L L H L H L H L L H L H H L H L APAR APAR Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z L H L H H L H L L H L PO‡ PE† Z ZPO‡ PE† ODD/EVEN Σ OF INPUTS A1-A8 = H Σ OF INPUTS B1-B8 = H H L H L H L H L H L H L H L H H L H L H H L L L L L H L H L H L H L H H H H H L H L H H H H H H L L L L H L H H H H H H H H L L L L L L L L H H H H H H H H L L L L L L L L L L L L L L L L L L L L L L L L L L SEL OEBA OEAB PARITY FUNCTION TABLE † Parity output is set to the level so that the specific bus side is set to even parity. ‡ Parity output is set to the level so that the specific bus side is set to odd parity. 16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS

701PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN LVCH ALVCH 3V UNIT ICC MAX 0.02 0.04 mA IOH MAX -24 -24 mA IOL MAX 24 24 mA PARAMETER INPUT OUTPUT MAX or MIN LVCH ALVCH fmax MIN 125 125 CLK ↑ MIN 3 3 LE high MIN 3 3 A, APAR or B, BPAR before CLK ↑ MIN 2.5 1.7 CLKEN before CLK ↑ MIN 2.5 1.7 A, APAR or B, BPAR before LE ↓ MIN 2 1.2 A, APAR or B, BPAR after CLK ↑ MIN 1.3 0.5 CLKEN after CLK ↑ MIN 1.5 0.7 A, APAR or B, BPAR after LE ↓ MIN 1.7 0.9 tPLH 5.4 4.4 tPHL 5.4 4.4 tPLH 7.7 6.7 tPHL 7.7 6.7 tPLH 5.7 4.7 tPHL 5.7 4.7 tPLH 8.5 7.5 tPHL 8.5 7.5 tPLH 7.8 6.8 tPHL 7.8 6.8 tPLH 7.5 6.5 tPHL 7.5 6.5 tPLH 6.1 5.1 tPHL 6.1 5.1 tPLH 6.1 5.1 tPHL 6.1 5.1 tPLH 6.6 5.6 tPHL 6.6 5.6 tPLH 8.7 7.7 tPHL 8.7 7.7 tPLH 8.9 7.9 tPHL 8.9 7.9 tPLH 5.8 4.8 tPHL 5.8 4.8 tPLH 6.3 5.3 tPHL 6.3 5.3 tPLH 8.4 7.4 tPHL 8.4 7.4 tPLH 8.5 7.5 tPHL 8.5 7.5 tPZH 6.3 5.3 tPZL 6.3 5.3 tPHZ 5.9 4.9 tPLZ 5.9 4.9 tPZH 5.9 4.9 tPZL 5.9 4.9 tPHZ 6.7 5.7 tPLZ 6.7 5.7 tPZH 6.5 5.5 tPZL 6.5 5.5 tPHZ 5.9 4.9 tPLZ 5.9 4.9 UNIT fmax : MHz other : ns MAX BPAR or APAR th Hold time tw Pulse duration A or B A or B MAX B or A tsu Setup time MAX BPAR or APAR ERRA or ERRB MAX MAX BPAR or APAR MAX APAR or BPAR APAR or BPAR MAXODD / EVEN BPAR or APAR ODD / EVEN SEL ERRA or ERRB CLKAB or CLKBA CLKAB or CLKBA CLKAB or CLKBA CLKAB or CLKBA A or B MAX MAX MAX MAX BPAR or APAR parity feedthrough BPAR or APAR parity generated ERRA or ERRB LEAB or LEBA LEAB or LEBA LEAB or LEBA LEAB or LEBA A or B BPAR or APAR parity feedthrough BPAR or APAR parity generated ERRA or ERRB MAX MAX MAX MAX B, BPAR or A, APAR B, BPAR or A, APAR OEAB or OEBA OEAB or OEBA MAX SEL SEL ERRA or ERRB ERRA or ERRB MAX OEAB or OEBA OEAB or OEBA ERRA or ERRB ERRA or ERRB MAX MAX MAX MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

(1A–8A)13 (9A–12A, APAR) Flip-Flop Flip-Flop DQ Parity Check DQ DQ XOR DQ APAR APAR (1A–10A) (1A–11A/YERREN, APAR) (1A–12A) 11A/YERREN OE MODE CLK CLKEN 1A–12A, APAR PAROE PARI/O YERR 1Y2–12Y2 1Y1–12Y1 : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16903 3.3-V 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS 11A/YERREN§ FUNCTION TABLE INPUTS X L L A 1Yn† – 8Yn†CLK L L L Z H H H OE H L X L X XL MODE X HL L HH H L L L L CLKEN X X X H H L L L 9Yn † – 12Yn† Z H L H L H L OE OUTPUTS INPUTS PARITY FUNCTION H PAROE‡ OUTPUT YERR H L L L H H HH ‡ When used as a single device, PAROE must be tied high. § Valid after appropriate number of clock pulses have set internal register. L L L L L L PARI/O L L L L APAR H H L L Σ OF INPUTS 1A – 10A = H 1, 3, 5, 7, 9 H X XX X X L X HX X X 0, 2, 4, 6, 8, 10 1, 3, 5, 7, 9 0, 2, 4, 6, 8, 10 L H H LL L H H H H H H H H H H L L L L L L H H L L 1, 3, 5, 7, 9 0, 2, 4, 6, 8, 10 1, 3, 5, 7, 9 INPUTS PARI/O FUNCTION† PAROE OUTPUT PARI/O L HL LL † This table applies to the first device of a cascaded pair of ALVCH16903 devices. L L APAR H H L L Σ OF INPUTS 1A – 10A = H 1, 3, 5, 7, 9 HZ XX 0, 2, 4, 6, 8, 10 1, 3, 5, 7, 9 0, 2, 4, 6, 8, 10 H † n =1, 2

703PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ALVCH 3V UNIT ICC MAX 0.04 mA IOH MAX -24 mA IOL MAX 24 mA INPUT OUTPUT MAX or MIN ALVCH MIN 125 tw Pulse duration CLK ↑ MIN 3 1A-12A before CLK ↑ , resister mode MIN 1.45 1A-10A before CLK ↑ , buffer mode MIN 4.4 APAR before CLK ↑ , resister mode MIN 1.3 APAR before CLK ↑ , buffer mode MIN 3.1 PA RI/O before CLK ↑ , both mode MIN 1.7 11A/YERREN before CLK ↑ , buffer mode MIN 1.6 CLKEN before CLK ↑ , resister mode MIN 2.2 1A-12A after CLK ↑ , resister mode MIN 0.55 1A-10A after CLK ↑ , buffer mode MIN 0.25 APAR after CLK ↑ , resister mode MIN 0.7 APAR after CLK ↑ , buffer mode MIN 0.25 PA RI/O before CLK ↑ , resister mode MIN 0.4 PA RI/O before CLK ↑ , buffer mode MIN 0.5 11A/YERREN after CLK ↑ , buffer mode MIN 0.4 CLKEN after CLK ↑ , resister mode MIN 0.4 tPLH 3.8 tPHL 3.8 tPLH 4.4 tPHL 4.4 tPLH 6.6 tPHL 6.6 tPLH 4.9 tPHL 4.9 tPLH 4.8 tPHL 4.6 tPZH 5.4 tPZL 5.4 tPZH 4.8 tPZL 4.8 tPHZ 5 tPLZ 5 tPHZ 3.8 tPLZ 3.8 tPLH 4 tPHL 4.2 UNIT fmax : MHz other : ns MAX MAX MAX CLK MODE OE PAROE CLK PARAMETER AY CLK PARI / O t su Setup time th Hold time fmax YERR MAXBuffer mode Both mode Both mode MAX MAX Both mode Both mode Y PA RI / O Both mode OE Y Both mode PAROE PARI / O MAX OEBoth mode YERR MAX Both mode Y MAX Y MAX Resister mode ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16952 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

705PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ABT ACT LVTH LVCH ALVCH 3V UNIT ICC MAX 35 0.08 5 0.02 0.04 mA IOH MAX -32 -24 -32 -24 -24 mA IOL MAX 64 24 64 24 24 mA PARAMETER INPUT OUTPUT MAX or MIN ABT ACT LVTH LVCH ALVCH fmax MIN 150 75 150 150 150 CLKEN high (SN74LVT: CLKEN high) -- -- 3 . 3 Data before CLK 3.5 5 1.7 2.8 1.5 CLKEN before CLK 36 . 5 21 .4 1 Data after CLK 11 0 . 8 0 .5 0.8 CLKEN after CLK 10 0 . 4 1.9 1.1 tPZL 61 3 4.9 6.6 4.4 tPHZ 5.5 9.4 6.2 6.7 4 tPLZ 4.2 8.7 5.3 6.7 4 UNIT fmax : MHz other : ns CLK A or B MAX OEBA or OEAB A or B A or B MAX OEBA or OEAB MAX tw Pulse duration tsu Setup time th Hold time MIN MIN MIN LVT 150 3.3 3.3 2.1 1.2 0.7 1.4 5.8 5.8 5.6 6.5 6.3 5.1 LVT -32 ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS OUTPUT B † A-to-B data flow is shown; B-to-A data flow is similar but uses CLKENBA, CLKBA, and OEBA. ‡ Level of B before the indicated steady-state input conditions were established. X H L A L XZ H H L L H CLKENAB OEABCLKAB L X X B0‡ B0‡ LX L L L H X

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 16973 8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH WITH FOUR INDEPENDENT BUFFERS

707PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ALVCH 3V UNIT ICC MAX 0.03 mA IOH MAX -24 mA IOL MAX 24 mA PARAMETER INPUT OUTPUT MAX or MIN ALVCH tw Pulse duration LE high MIN 2 tsu Setup time data before LE ↓ MIN 0.9 th Hold time data after LE ↓ MIN 0.9 tPLH 3 tPHL 3 tPLH 3 tPHL 3 tPLH 3 tPHL 3 tPLH 3 tPHL 3 tPZH 4.7 tPZL 4.7 tPZH 4.4 tPZL 4.4 tPZH 4.7 tPZL 4.7 tPHZ 4.1 tPLZ 4.1 tPHZ 4.1 tPLZ 4.1 tPHZ 4.7 tPLZ 4.7 UNIT: ns D MAXY AQ MAX MAX A or B LOE DIR Q TOE A or B A or BDIR Q A or B B or A MAX MAX MAX LE MAX MAX LOE TOE Q MAX A or B MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUTS TOE DIR OPERATION LL B data to A bus LH A data to B bus HX A bus and B bus Isolation INPUTS OUTPUT LOE LE A Q LHH H LH L LL L XQ o HXX Z INPUT D OUTPUT Y LL HH FUNCTION TABLE

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 1OE 1A1 1Y1 23 1 1A2 1Y222 3 1A3 1Y320 4 1A4 1Y419 6 2OE 2A1 2Y1 18 7 2A2 2Y217 9 2A3 2Y315 10 2A4 2Y414 12 25244 25-Ω OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS

• High Output Drive Current
• Distributed VCC and GND Pins Minimize Noise Generated by the Simultaneous Switching of Outputs PARAMETER MAX or MIN SN74 BCT SN64 BCT UNIT ICC MAX 119 119 mA IOH MAX -80 -80 mA IOL MAX 188 188 mA PARAMETER INPUT OUTPUT MAX or MIN SN74 BCT SN64 BCT tPLH 5.5 5.5 tPHL 6 6.3 tPZH 9.3 9.7 tPZL 10.2 10.4 tPHZ 6.3 6.5 tPLZ 8.4 9.5 UNIT: ns OE Y MAX AY MAX OE Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS FUNCTION TABLE (each buffer/driver) INPUTS H L A H X OUTPUT Y H Z LL OE L

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 25245 25-Ω OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

• High Output Drive Current
• Distributed VCC and GND Pins Minimize Noise Generated by the Simultaneous Switching of Outputs DIR OE To Seven Other Channels FUNCTION TABLE INPUTS L DIR OPERATION L OE H Isolation LH X B data to A bus A data to B bus PARAMETER MAX or MIN SN74 BCT SN64 BCT ABTH UNIT ICC MAX 125 125 20 mA IOH (A port) MAX -80 -80 -80 mA IOH (B port) MAX -3 -3 -32 mA IOL (A port) MAX 188 188 188 mA IOL (B port) MAX 24 24 64 mA PARAMETER INPUT OUTPUT MAX or MIN SN74 BCT SN64 BCT ABTH tPLH 5.7 5.7 3.9 tPHL 7.2 7.3 4.3 tPLH 5.5 5.5 3.9 tPHL 6.2 6.3 4.3 tPZH 9.6 9.7 6.5 tPZL 10.3 10.6 6.8 tPHZ 6.2 6.2 7.2 tPLZ 8.3 8.8 6.4 tPZH 8.9 8.9 6.5 tPZL 9.7 9.9 6.8 tPHZ 6.9 6.9 7.2 tPLZ 7.5 7.7 6.4 UNIT: ns OE B MAX B A OE MAX OE MAX AB MAX OE A MAX BA MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS710 25642 25-Ω OCTAL BUS TRANSCEIVER

• High Output Drive Current
• Distributed VCC and GND Pins Minimize Noise Generated by the Simultaneous Switching of Outputs Logic Diagram A1 B1 231 OE DIR To Seven Other Channels FUNCTION TABLE INPUTS OE L L H DIR X L H OPERATION B data to A bus A data to B bus Isolation PARAMETER MAX or MIN SN74 BCT UNIT ICC MAX 125 mA IOH (B port) MAX -3 mA IOL (A port) MAX 188 mA IOL (B port) MAX 24 mA VOH (A port) MAX 5.5 V PARAMETER INPUT OUTPUT MAX or MIN SN74 BCT tPLH 6.2 tPHL 4 tPLH 6.3 tPHL 5.9 tPLH 11.6 tPHL 11.3 tPZH 9.1 tPZL 9.8 tPHZ 7.3 tPLZ 7.3 UNIT: ns OE B MAX B A OE MAX OE MAX AB MAX BA MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 29821 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

• 3-State Outputs
• Data Flow-Through Pinout OE CLK To Nine Other Channels FUNCTION TABLE (each fllp-flop) INPUTS H L D H X OUTPUT Q H Z L L OE X CLK L XH or L Q0L PARAMETER MAX or MIN ALS SN74 BCT UNIT ICC MAX 115 35 mA IOH MAX -24 -24 mA IOL MAX 48 48 mA PARAMETER INPUT OUTPUT MAX or MIN ALS SN74 BCT fmax - 125 tw Pulse duration CLK high or low MIN 7 7 tsu Setup time Data before CLK ↑ MIN 4 7 th Hold time Data after CLK ↑ MIN 2 1 tPLH 10 12 tPHL 10 10 tPZH 14 12 tPZL 14 13 tPHZ 14 8 tPLZ 12 8 UNIT fmax : MHz other : ns MAX MAX MAX Q QOE OE QCLK ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS712 Logic Diagram 29825 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

• 3-State Outputs
• Data Flow-Through Pinout CLR CLK To Seven Other Channels OE1 OE2 OE3 CLKEN R FUNCTION TABLE INPUTS OUTPUT Q L X L DCLK L ZH H L OE† CLKEN X L X Q0L X H L LH CLR X H L H HX X H or L X L †O E = H if any of the output-enable inputs is high. OE = L if all of the output-enable inputs are low. PARAMETER MAX or MIN SN74 BCT UNIT ICC MAX 40 mA IOH MAX -24 mA IOL MAX 48 mA PARAMETER INPUT OUTPUT MAX or MIN SN74 BCT fmax MIN 125 CLK low MIN 4 CLK high or low MIN 4 Before CLK ↑ , data high MIN 6 Before CLK ↑ , data low MIN 3.5 CLR MIN 1 CLKEN before CLK ↑ MIN 8 After CLK ↑ , data high MIN 1.5 After CLK ↑ , data low MIN 0 CLKEN after CLK ↑ MIN 0.5 tPLH 9 tPHL 8.4 tPHL CLR Q MAX 9.5 tPZH 10.3 tPZL 10.2 tPHZ 9 tPLZ 8.2 UNIT fmax : MHz other : ns tsu Setup time th Hold time tw Pulse duration CLK Q MAX Q OE OE MAX MAXQ ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 29827 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

• pnp Inputs Reduce dc Loading
• 3-State Outputs
• Data Flow-Through Pinout To Nine Other Channels OE1 OE2 A1 22 3 FUNCTION TABLE INPUTS H L A L X OUTPUT L Z HH OE1 X OE2 H Z X L L L L Y PARAMETER MAX or MIN ALS SN74 BCT UNIT ICC MAX 40 40 mA IOH MAX -24 -24 mA IOL MAX 48 48 mA PARAMETER INPUT OUTPUT MAX or MIN ALS SN74 BCT tPLH 7 5.5 tPHL 7.5 7.5 tPZH 15 9.1 tPZL 15 12.8 tPHZ 17 8.8 tPLZ 12 8.4 UNIT: ns OE Y MAX AY MAX OE Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS714 29828 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

• pnp Inputs Reduce dc Loading
• 3-State Outputs
• Data Flow-Through Pinout Logic Diagram To Nine Other Channels OE2 OE1 2 23 PARAMETER MAX or MIN ALS UNIT ICC MAX 40 mA IOH MAX -24 mA IOL MAX 48 mA PARAMETER INPUT OUTPUT MAX or MIN ALS tPLH 7 tPHL 7.5 tPZH 15 tPZL 15 tPHZ 17 tPLZ 12 UNIT: ns MAX MAX MAXOE A OE Y Y Y ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS NOTICE : ALS IS NOT RECOMMENDED FOR NEW DESIGNS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 29841 10-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

• 3-State Outputs
• Data Flow-Through Pinout OE 1Q23 LE To Nine Other Channels FUNCTION TABLE INPUTS H L D H X OUTPUT H Z LL OE H L LE X X L HL Q PARAMETER MAX or MIN ALS SN74 BCT UNIT ICC MAX 85 35 mA IOH MAX -24 -24 mA IOL MAX 48 48 mA PARAMETER INPUT OUTPUT MAX or MIN ALS SN74 BCT tw Pulse duration LE high or low MIN 6 4 tsu Setup time Data beforeLE ↓ MIN 2.5 2 Data after LE ↓ , high MIN 4.5 1.5 Data after LE ↓ , low MIN 4.5 3.5 tPLH 9.5 7.5 tPHL 9.5 8.6 tPLH 12 8.6 tPHL 12 8.1 tPZH 14 9.2 tPZL 14 12.8 tPHZ 15 6.9 tPLZ 12 6.9 UNIT: ns OE OE QLE MAX MAX MAX Q Q t h Hold time DQ MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

S R : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 29843 9-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

• 3-State Outputs
• Data Flow-Through Pinout

717PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE INPUTS OUTPUT Q X L DLE L Z L H H L L X H L L H CLR X H L H HX X X L OEPRE X X H H X H X HH H L L PARAMETER MAX or MIN SN74 BCT UNIT ICC MAX 35 mA IOH MAX -24 mA IOL MAX 48 mA PARAMETER INPUT OUTPUT MAX or MIN SN74 BCT PRE low 7 CLR low 5 LE high 4 Data before LE ↓ , high or low 1.5 PRE or CLR inactive 2 th Hold time Data after LE ↓ , high or low MIN 3.5 tPLH 8 tPHL 9 tPLH 10 tPHL 10 tPLH 12 tPHL 12 tPLH 12 tPHL 12 tPZH 15 tPZL 15 tPHZ 8 tPLZ 8 UNIT: ns Q MAX Q OE OE MAX MAXQ CLR tsu Setup time tw Pulse duration D LE MIN MIN PRE Q MAX MAX MAX Q Q ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS718 29854 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER Logic Diagram EN A1–A8 OEA OEB LE CLR MUX EN B1–B8 PARITY ERR P

719PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ALS SN74 BCT UNIT ICC MAX 100 80 mA IOH MAX -24 -24 mA IOL MAX 48 48 mA PARAMETER INPUT OUTPUT MAX or MIN ALS SN74 BCT LE high MIN 10 - LE low MIN 10 10 CLR low MIN 10 10 Before LE ↓ , Bi and PARITY MIN 10 18 Before LE ↓ , CLR high MIN 15 - th Hold time Bi and PARITY after LE ↓ MIN 3 8 tPLH 88 tPHL 88 tPLH 15 15 tPHL 18 15 tPZH 17 17 tPZL 17 19 tPHZ 15 15 tPLZ 81 7 tPHL LE ERR MAX 12 9 tPLH CLR ERR MAX 12 15 tPLH 17 15 tPHL 19 16 tPLH 20 20 tPHL 20 15 UNIT: ns A or B MAX OEA PARITY MAX OEA or OEB B or A MAX PARITY MAX tw Pulse duration A or B A OEA or OEB tsu Setup time Bi / PARITY ERR MAX A or B MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS OUTPUT AND I/O OEA Even Even OPERATION A data to B bus and generate parity OEB L H HH Isolation§ B data to A bus and check parityH L Store error flagH L parity A data to B bus and generate invertedL L Clear error-flag registerX X CLR X L X X H X H X L LE X L H H L L H X H Ai Σ of Hs Odd X L Odd H Even X NA NA X Bi† Σ of Ls NA Even Odd NA X Odd X X A NA NA Z B X X B A A Z NA NA NA PARITY L H H L Z NA NA NA L ERR‡ NA NA H NC L H H N-1 H NA = not applicable, NC = no change, X = don’t care † Summation of high-level inputs includes PARITY along with Bi inputs. ‡ Output states Shown assume ERR was previously high. § In this mode, ERR, when enabled, shows inverted parity of the A bus.

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS A1 B1 OEBA11 OEBA2 OEAB1 OEAB2 To Eight Other Channels 29863 9-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

• True Outputs FUNCTION TABLE INPUTS OPERATION L H OEBA2OEBA1 X H B to AL XX L L OEAB1 H L L H XL H IsolationHXHX HHXX XHXH L A to B OEAB2 L X Latch A and B HX L L L PARAMETER MAX or MIN ALS SN74 BCT UNIT ICC MAX 65 45 mA IOH MAX -24 -24 mA IOL MAX 48 48 mA PARAMETER INPUT OUTPUT MAX or MIN ALS SN74 BCT tPLH 85 tPHL 8 7.5 tPZH 15 8.4 tPZL 15 12.6 tPHZ 17 8.8 tPLZ 12 8.1 UNIT: ns OEAB or OEBA A or B MAX A or B B or A MAX OEAB or OEBA A or B MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 29864 9-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS

• Inverted Outputs A1 B1 OEBA11 OEBA2 OEAB1 OEAB2 To Eight Other Channels FUNCTION TABLE INPUTS OPERATION L H OEBA2OEBA1 X H B to AL XX L L OEAB1 H L L H XL H IsolationHXHX HHXX XHXH L A to B OEAB2 L X Latch A and B HX L L L PARAMETER MAX or MIN SN74 BCT UNIT ICC MAX 45 mA IOH MAX -24 mA IOL MAX 48 mA PARAMETER INPUT OUTPUT MAX or MIN SN74 BCT tPLH 6.1 tPHL 4.8 tPZH 8.4 tPZL 12.5 tPHZ 8.4 tPLZ 8.2 UNIT: ns OEAB or OEBA A or B MAX A or B B or A MAX OEAB or OEBA A or B MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS722 32240 32-BIT BUFFER/DRIVER Logic Diagram 1OE 1A1 1A2 1A3 1A4 1Y1 1Y2 1Y3 1Y4 2OE 2A1 2A2 2A3 2A4 2Y1 2Y2 2Y3 2Y4 3OE 3A1 3A2 3A3 3A4 3Y1 3Y2 3Y3 3Y4 4OE 4A1 4A2 4A3 4A4 4Y1 4Y2 4Y3 4Y4 5OE 5A1 5A2 5A3 5A4 5Y1 5Y2 5Y3 5Y4 6OE 6A1 6A2 6A3 6A4 6Y1 6Y2 6Y3 6Y4 7OE 7A1 7A2 7A3 7A4 7Y1 7Y2 7Y3 7Y4 8OE 8A1 8A2 8A3 8A4 8Y1 8Y2 8Y3 8Y4

723PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. INPUTS OUTPUT Y Z OE H L LH L A X H L FUNCTION TABLE (each 4bit buffer/drirer) PARAMETER MAX or MIN LVCZ 3V LVT UNIT ICC MAX 0.2 10 mA IOH MAX -24 -32 mA IOL MAX 24 64 mA PARAMETER INPUT OUTPUT MAX or MIN LVCZ 3V LVT tPLH MAX 4. 23 . 5 tPHL MAX 4. 23 . 5 tPZH MAX 4.7 4 tPZL MAX 4. 74 . 4 tPHZ MAX 5. 94 . 5 tPLZ MAX 5. 94 . 2 UNIT:ns Y Y Y A OE OE ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS

725PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. INPUTS OUTPUT YOE L L H A X HH L Z L FUNCTION TABLE PARAMETER MAX or MIN LVT LVTH ALVTH LVC LVCH LVCZ ALVCH AUC 1.8V AUC 2.3V AUCH 1.8V AUCH 2.3V UNIT IOH MAX -32 -32 -32 -24 -24 -24 -24 -8 -9 -8 -9 mA IOL MAX 64 64 64 24 24 24 24 8989 mA PARAMETER INPUT OUTPUT MAX or MIN LVT LVTH ALVTH LVC LVCH LVCZ ALVCH AUC 1.8V PARAMETER INPUT OUTPUT MAX or MIN AUC 2.3V AUCH 1.8V AUCH 2.3V tPLH 1.8 1.8 1.8 tPHL 1.8 1.8 1.8 tPZH 1.9 2.5 1.9 tPZL 1.9 2.5 1.9 tPHZ 2 4.0 2 tPLZ 2 4.0 2 UNIT: ns OE Y MAX AY MAX OE Y MAX OE Y MAX AY MAX OE Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS726 Logic Diagram 32245 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS To Seven Other Channels 1DIR 1A1 1B1 1OE To Seven Other Channels 2DIR 2A1 2B1 2OE To Seven Other Channels 3DIR 3A1 3B1 3OE To Seven Other Channels 4DIR 4A1 4B1 4OE FUNCTION TABLE (each 9-bit section) INPUTS L DIR OPERATION L OE H Isolation LH X B data to A bus A data to B bus

727PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ABT ABTH LVTH LVC LVCH LVCR LVCZ ALVCH AUC 1.8V AUC 2.3V UNIT IOH MAX -32 -32 -32 -24 -24 -12 -24 -24 -8 -9 mA IOL MAX 64 64 64 24 24 12 24 24 8 9 mA PARAMETER INPUT OUTPUT MAX or MIN ABT ABTH LVTH LVC LVCH LVCR LVCZ ALVCH tPLH 55 3 . 3 44 4.8 4.0 4.4 4.4 4.1 4.1 PARAMETER INPUT OUTPUT MAX or MIN AUC 1.8V AUC 2.3V tPLH 2.0 1.9 tPHL 2.0 1.9 tPZH 3.1 2.6 tPZL 3.1 2.6 tPHZ 4.8 2.9 tPLZ 4.8 2.9 UNIT: ns OE B or A MAX A or B B or A MAX OE B or A MAX OE B or A MAX A or B B or A MAX OE B or A MAX LVCHR 4.8 4.8 6.3 6.3 7.4 7.4 LVCHR 0.04 -12 ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS728 Logic Diagram CLK 1 of 16 Channels CE C OEA SELA CLKA CLKENA LEA CLK CE C OEB SELB CLKB CLKENB LEB CLK CE C OEC SELC CLKC CLKENC LEC 32316 16-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS

729PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ABTH UNIT ICC MAX 40 mA IOH MAX -32 mA IOL MAX 64 mA PARAMETER INPUT OUTPUT MAX or MIN ABTH fmax MIN 150 LE high MIN 3.3 CLK high or low MIN 3.3 A, B, or C before CLK ↑ MIN 2.4 A or B before LE ↓ MIN 2.1 CLKEN before CLK ↑ MIN 3.2 A, B, or C after CLK ↑ MIN 1.4 A or B after LE ↓ MIN 2.1 CLKEN after CLK ↑ MIN 1.1 tPLH 6.1 tPHL 6.6 tPLH 6.5 tPHL 6.5 tPLH 7.5 tPHL 6.9 tPLH 7.5 tPHL 6.7 tPZH 6.4 tPZL 6.8 tPHZ 6 tPLZ 6.1 UNIT fmax : MHz other : ns MAX MAX MAX OE A, B, or C MAX OE A, B, or C MAX MAXCLK A, B, or C LE A, B, or C t w Pulse duration A, B, or C C, B, or A SEL A, B, or C tsu Setup time th Hold time ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE STORAGE† INPUTS OUTPUT † A-port register shown, B and C ports are similar but use CLKENB, CLKENC, CLKB, CLKC, LEB, and LEC. ‡O utput level before the indicated steady-state input conditions were established. X H L A L XH H L L H CLKENA LEACLKA L X X Q0‡ L X L L L X X X X X H L H H L H L Q0‡ Q0‡ A-PORT OUTPUT INPUTS L SELA H OUTPUT AOEA ZH Output of C register LL X Output of B register B-PORT OUTPUT INPUTS L SELB H OUTPUT BOEB ZH Output of A register LL X Output of C register C-PORT OUTPUT INPUTS L SELC H OUTPUT COEC ZH Output of B register LL X Output of A register

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS730 32318 18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS Logic Diagram CLK 1 of 18 Channels LE OEA SELA CLKA LEA CLK LE OEB SELB CLKB LEB CLK LE OEC SELC CLKC LEC D Q D Q D Q

731PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ABTH UNIT ICC MAX 45 mA IOH MAX -32 mA IOL MAX 64 mA PARAMETER INPUT OUTPUT MAX or MIN ABTH fmax MIN 150 LE high MIN 3.3 CLK high or low MIN 3.3 A, B, or C before CLK ↑ MIN 2.4 A, B, or C before LE ↓ MIN 2.1 A, B, or C after CLK ↑ MIN 1.4 A, B, or C after LE ↓ MIN 2.1 tPLH 6.1 tPHL 6.6 tPLH 6.5 tPHL 6.5 tPLH 7.5 tPHL 6.9 tPLH 7.4 tPHL 6.7 tPZH 6.8 tPZL 7.1 tPHZ 6.2 tPLZ 6 UNIT fmax : MHz other : ns tw Pulse duration A, B, or C C, B, or A SEL A, B, or C tsu Setup time th Hold time CLK A, B, or C LE A, B, or C MAX MAX MAX OE A, B, or C MAX OE A, B, or C MAX MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE STORAGE† INPUTS OUTPUT † A-port register shown, B and C ports are similar but use CLKB, CLKC, LEB, and LEC. ‡O utpu level befor the indicated steady-state input conditions were established. H L A L H L H LEACLKA X X L L L X X H L H H L H L Q0‡ Q0‡ A-PORT OUTPUT INPUTS L SELA H OUTPUT AOEA ZH Output of C register LL X Output of B register B-PORT OUTPUT INPUTS L SELB H OUTPUT BOEB ZH Output of A register LL X Output of C register C-PORT OUTPUT INPUTS L SELC H OUTPUT COEC ZH Output of B register LL X Output of A register

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS732 Logic Diagram 1OE 1LE 1D1 To Seven Other Channels 1Q1 2OE 2LE 2D1 To Seven Other Channels 2Q1 3OE 3LE 3D1 To Seven Other Channels 3Q1 4OE 4LE 4D1 To Seven Other Channels 4Q1 32373 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS INPUTS L H H LE OUTPUT Q Z OE H L L L X D X X HH L L FUNCTION TABLE

733PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN LVTH ALVTH LVCH 3V UNIT ICC MAX 10 5 0.04 mA IOH MAX -32 -32 -24 mA IOL MAX 64 64 24 mA PARAMETER INPUT OUTPUT MAX or MIN LVTH ALVTH LVCH tw Pulse duration, LE high or low MIN 3 1.5 3.3 Data before LE ↓ , data high MIN 1 1.4 1.7 Data before LE ↓ , data low MIN 1 0.9 1.7 Data after LE ↓ , data high MIN 1 0.9 1.2 Data after LE ↓ , data low MIN 1 1.4 1.2 tPLH 3.8 3.1 4.2 tPHL 3.6 3.3 4.2 tPLH 4.3 3.3 4.6 tPHL 4 3.5 4.6 tPZH 4.3 4 4.7 tPZL 4.3 3.4 4.7 tPHZ 5 4.9 5.9 tPLZ 4.7 4.5 5.9 UNIT: ns OE Q MAX OE Q MAX th Hold time tsu Setup time MAX MAX DQ QLE LVC 3.3 1.7 1.7 1.2 1.2 4.2 4.2 4.6 4.6 4.7 4.7 5.9 5.9 LVC 0.04 -24 ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 32374 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

735PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN LVTH ALVTH LVC LVCH ALVCH AUC 1.8V AUC 2.3V AUCH 1.8V AUCH 2.3V UNIT IOH MAX -32 -32 -24 -24 -24 -8 -9 -8 -9 mA IOL MAX 64 64 24 24 24 8989 m A PARAMETER INPUT OUTPUT MAX or MIN LVTH ALVTH LVC LVCH ALVCH AUC 1.8V AUC 2.3V fmax 160 250 150 150 150 250 250 PARAMETER INPUT OUTPUT MAX or MIN AUCH 1.8V AUCH 2.3V fmax 250 250 tw Pulse duration, CLK high or low MIN 1.9 1.9 Data before CLK ↑ , data high MIN 0.6 0.6 Data before CLK ↑ , data low MIN 0.6 0.6 Data after CLK ↑ , data high MIN 0.4 0.4 Data after CLK ↑ , data low MIN 0.4 0.4 tPLH 2.8 2.2 tPHL 2.8 2.2 tPZH 2.9 2.2 tPZL 2.9 2.2 tPHZ 4.5 2.2 tPLZ 4.5 2.2 UNIT fmax : MHz other : ns tsu Setup time MAXCLK Q OE Q MAX th Hold time MAX OE Q MAX OE Q MAX tsu Setup time th Hold time CLK Q MAX OE Q ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUTS H or L CLK OUTPUT Q Z OE H L L L X D X X HH L L FUNCTION TABLE (each flip-flop)

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 32501 36-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

737PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ABTH ALVCH 3V UNIT ICC MAX 90 0.08 mA IOH MAX -32 -24 mA IOL MAX 64 24 mA PARAMETER INPUT OUTPUT MAX or MIN ABTH ALVCH fmax MIN 150 150 LEAB or LEBA high MIN 3.3 3.3 CLKAB or CLKBA high or low MIN 3.3 3.3 A before CLKAB ↑ MIN 3.5 1.7 B before CLKBA ↑ MIN 3.5 1.7 A before LEAB ↓ or LEBA ↓ CLK high MIN 1.6 1.5 A before LEAB ↓ or LEBA ↓ CLK low MIN 1.6 1 A after CLKAB ↑ or B after CLKBA ↑ MIN 0 0.7 A after LEAB ↓ or B after LEBA ↓ MIN 1.6 1.4 tPLH 4.8 3.9 tPHL 5.4 3.9 tPZH 5.3 4.6 tPZL 5.5 4.6 tPHZ 5.3 4.9 tPLZ 5.4 4.9 tPZH 5.6 4.6 tPZL 6 4.6 tPHZ 5.9 5 tPLZ 5.6 5 tPZH 5.6 5 tPZL 65 tPHZ 5.9 4.2 tPLZ 5.6 4.2 UNIT fmax : MHz other : ns tw Pulse duration MAX LEAB or LEBA MAX tsu Setup time th Hold time CLKAB or CLKBA MAX OEBA B MAX B MAX MAX OEBA A MAX A or B B or A B or A B or A A OEAB OEAB ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE† INPUTS X H ACLKAB L L OUTPUT B Z HH OEAB L H X H X X H L LEAB X L HH H HL X H B0‡L L X B0§L H H L † A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. ‡ Outoput level before the indicated steady-state input conditions were established § Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS738 32543 36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS Logic Diagram 1OEBA 1CEBA 1LEBA 1OEAB 1CEAB 1LEAB 1A1 1B1 To 17 Other Channels 2OEBA 2CEBA 2LEBA 2OEAB 2CEAB 2LEAB 2A1 2B1 To 17 Other Channels

739PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ABTH UNIT ICC MAX 20 mA IOH MAX -32 mA IOL MAX 64 mA PARAMETER INPUT OUTPUT MAX or MIN ABTH tw Pulse duration, LEAB or LEBA low MIN 3.3 Data before LEAB ↑ or LEBA ↑ MIN 2.1 Data before CEAB ↑ or CEBA ↑ MIN 1.7 Data after LEAB ↑ or LEBA ↑ MIN 0.6 Data after CEAB ↑ or CEBA ↑ MIN 0.9 tPLH 5.9 tPHL 5.7 tPLH 7.5 tPHL 6.6 tPZH 8 tPZL 8.8 tPHZ 7.1 tPLZ 7.5 tPZH 7.3 tPZL 8.1 tPHZ 6.5 tPLZ 6.9 UNIT: ns MAX MAXA or B B or A LE A or B MAX MAX OE A or B MAX OE A or B MAX tsu Setup time th Hold time CE A or B CE A or B ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS X X AOEAB L OUTPUT Y Z CEAB H L X L H LEAB X L HL L L X B0‡L L L X H H X Z † A-to-B data flow is shown: B-to-A flow conditions is the same that it uses CEBA, LEBA, and OEBA. ‡ Outoput level before the indicated steady-state input conditions were established

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 32973 16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH WITH EIGHT INDEPENDENT BUFFERS

741PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ALVCH 3V UNIT ICC MAX 0.06 mA IOH MAX -24 mA IOL MAX 24 mA PARAMETER INPUT OUTPUT MAX or MIN ALVCH tw Pulse duration LE high MIN 2 tsu Setup time data before LE ↓ MIN 0.9 th Hold time data after LE ↓ MIN 0.9 tPLH 3 tPHL 3 tPLH 3 tPHL 3 tPLH 3 tPHL 3 tPLH 3 tPHL 3 tPZH 4.7 tPZL 4.7 tPZH 4.4 tPZL 4.4 tPZH 4.7 tPZL 4.7 tPHZ 4.1 tPLZ 4.1 tPHZ 4.1 tPLZ 4.1 tPHZ 4.7 tPLZ 4.7 UNIT: ns D MAXY AQ MAX MAX A or B LOE DIR Q TOE A or B A or BDIR Q A or B B or A MAX MAX MAX LE MAX MAX LOE TOE Q MAX A or B MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS INPUTS TOE DIR OPERATION LL B data to A bus LH A data to B bus HX A bus and B bus Isolation INPUTS OUTPUT LOE LE A Q LHH H LH L LL L XQ o HXX Z INPUT D OUTPUT Y LL HH FUNCTION TABLE

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS742 40103 8-STAGE SYNCHRONOUS DOWN COUNTERS Function Diagram GND VCC CP 1215 MR TE PE TC PL 16 8 FUNCTION TABLE CONTROL INPUTS ACTIONPRESET MODE Synchronous Asynchronously Preset On Next Positive Clock Transition Cownt Down Inhibit Counter Preset Asychronously Clear to Maximum Count XX PLMR XH PE L L XL X X H HL LH L L L TE L L

743PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN CD74 HC CD74 HCT UNIT ICC MAX 0.16 0.16 mA IOH MAX -4 -4 mA IOL MAX 4 4 mA PARAMETER INPUT OUTPUT MAX or MIN CD74 HC CD74 HCT tw 50 53 38 65 38 53 t su 30 36 22 30 45 60 t h 55 t PLH 90 90 tPHL 90 90 tPLH 90 95 tPHL 90 95 tPLH 60 75 tPHL 60 75 tPLH 83 102 tPHL 83 102 tPLH 83 83 tPHL 83 83 UNIT : ns MIN MIN MIN PE to CP TE to CP TE to CP PL MR MAX TC (Async Preset) TC (Sync Preset) TC TC TC MAX MAX MAX MAX MR P to CP CP P to CP CP CP TE PL PE to CP ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS744 Logic Diagram 162240 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

• SN74LVT162240, SN74LVTH162240: Output Ports Have Equivalent 22-Ω Series Resistors 1OE 1A1 1A2 1A3 1A4 1Y1 1Y2 1Y3 1Y4 2OE 2A1 2A2 2A3 2A4 2Y1 2Y2 2Y3 2Y4 3OE 3A1 3A2 3A3 3A4 3Y1 3Y2 3Y3 3Y4 4OE 4A1 4A2 4A3 4A4 4Y1 4Y2 4Y3 4Y4 OE FUNCTION TABLE INPUTS L A X H OUTPUT Y L Z L L H H PARAMETER MAX or MIN LVT LVTH 3V UNIT ICC MAX 5 5 mA IOH MAX -12 -12 mA IOL MAX 12 12 mA PARAMETER INPUT OUTPUT MAX or MIN LVT LVTH tPLH 44 tPHL 44 tPZH 4.8 4.8 tPZL 4.7 4.7 tPHZ 4.7 4.7 tPLZ 4.5 4.5 UNIT: ns MAX Y MAX Y MAX A OE OE Y ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram 1OE 1A1 1A2 1A3 1A4 1Y1 1Y2 1Y3 1Y4 2OE 2A1 2A2 2A3 2A4 2Y1 2Y2 2Y3 2Y4 3OE 3A1 3A2 3A3 3A4 3Y1 3Y2 3Y3 3Y4 4OE 4A1 4A2 4A3 4A4 4Y1 4Y2 4Y3 4Y4 745 162241 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS FUNCTION TABLE INPUTS L 1A, 4A1OE, 4OE X H OUTPUT 1Y, 4Y LL H L Z H INPUTS 2A, 3A2OE, 3OE X H OUTPUT 2Y, 3Y LLH H L Z H PARAMETER MAX or MIN LVTH 3V UNIT ICC MAX 5 mA IOH MAX -12 mA IOL MAX 12 mA PARAMETER INPUT OUTPUT MAX or MIN LVTH tPLH 4.1 tPHL 4.1 tPZH 4.9 tPZL 4.8 tPHZ 5.3 tPLZ 4.9 UNIT: ns OE or OE Y MAX AY M A X OE or OE Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

PARAMETER MAX or MIN ABT LVT LVTH ALVTH LVC LVCH ALVCH 3V UNIT ICC MAX 30 555 0.02 0.02 0.04 mA IOH MAX -12 -12 -12 -12 -12 -12 -12 mA IOL MAX 12 12 12 12 12 12 12 mA PARAMETER INPUT OUTPUT MAX or MIN ABT LVT LVTH ALVTH LVC LVCH ALVCH UNIT: ns OE Y MAX AY MAX OE Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS : OBSOLETED or NOT RECOMMENDED NEW DESIGNS746 Logic Diagram 162244 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

• SN74ABT162244: Output Ports Have Equivalent 25-Ω Series Resistors
• SN74LVT162244A, LVTH162244: Output Ports Have Equivalent 22-Ω Series Resistors
• SN74ALVTH162244: Output Ports Have Equivalent 30-Ω Series Resistors
• SN74LVC162244A: Output Ports Have Equivalent 26-Ω Series Resistors
• SN74LVCH162244A: Output Ports Have Equivalent 26-Ω Series Resistors
• SN74ALVCH162244: Output Ports Have Equivalent 26-Ω Series Resistors 1OE 1A1 1A2 1A3 1A4 1Y1 1Y2 1Y3 1Y4 2OE 2A1 2A2 2A3 2A4 2Y1 2Y2 2Y3 2Y4 3OE 3A1 3A2 3A3 3A4 3Y1 3Y2 3Y3 3Y4 4OE 4A1 4A2 4A3 4A4 4Y1 4Y2 4Y3 4Y4 FUNCTION TABLE (each 4-bit buffer) INPUTS H L A H X OUTPUT Y H Z LL OE L

747PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE (each 8-bit section) INPUTS L DIR OPERATION L OE H Isolation LH X B data to A bus A data to B bus PARAMETER MAX or MIN ABT ABTH LVT LVTH ALVTH 3V UNIT ICC MAX 32 32 555 m A IOH (A port) MAX -12 -12 -12 -12 -12 mA IOH (B port) MAX -32 -32 -32 -32 -32 mA IOL (A port) MAX 12 12 12 12 12 mA IOL (B port) MAX 64 64 64 64 64 mA PARAMETER INPUT OUTPUT MAX or MIN ABT ABTH LVT LVTH ALVTH tPHL 4.2 4.2 3.3 3.3 3 tPLH 4.6 4.6 4 4 3.7 tPZL 77 5.1 5.1 3.9 tPHZ 6.6 6.6 5.6 5.6 5 UNIT: ns AOE MAX A MAX OE B MAX OE A MAX AB MAX OE B MAX B ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS 162245 16-BIT TRANSCEIVER WITH 3-STATE OUTPUTS

• SN74ABT162245, SN74ABTH162245: A-Port Outputs Have Equivalent 25-Ω Series Resistors
• SN74LVT162245A, SN74LVTH162245: A-Port Outputs Have Equivalent 22-Ω Series Resistors
• SN74ALVTH162245: A-Port Outputs Have Equivalent 30-Ω Series Resistors
• SN74LVCR162245: All Outputs Have Equivalent 26-Ω Series Resistors To Seven Other Channels 1DIR 1A1 1B1 1OE

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS

• SN74ABTH162260: B-Port Outputs Have Equivalent 25-Ω Series Resistors
• SN74ALVCH162260: B-Port Outputs Have Equivalent 26-Ω Series Resistors

749PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. OEA INPUTS L L L L L L L L L H H H L L OUTPUTS 1B0 1B0 1B0 H H L L L L L L L 2B1B H X X Z Z L H L H L H X X X H H X L H H L L L L X X X H H H H X L X X X Active Active L L 2B0 2B0 2B0 Active Active L H L H Z Z A TO B (OEA = H) INPUTS 1B SEL H X OUTPUT A Z L H X X X X H X X X X L X L X H L H X LE1B L H HX LE2B L H H L L H H L L X XL X XL XX L HL L FUNCTION TABLE B TO A (OEB = H) OE2BLEA1BA LEA2B OE1B PARAMETER MAX or MIN ABTH ALVCH 3V UNIT ICC MAX 63 0.04 mA IOH (A port) MAX -32 -24 mA IOH (B port) MAX -32 -12 mA IOL (A port) MAX 64 24 mA IOL (B port) MAX 12 12 mA PARAMETER INPUT OUTPUT MAX or MIN ABTH ALVCH fmax - 150 tw Pulse duration, LE1B, LE2B, LEA1B, or LEA2B high MIN 3.3 3.3 tsu Setup time, data before LE1B, LE2B, LEA1B, or LEA2B ↓ MIN 1.5 1.1 th Hold time, data after LE1B, LE2B, LEA1B, or LEA2B ↓ MIN 11 . 5 tPLH 6.1 4.9 tPHL 7.1 4.9 tPLH 6 4.3 tPHL 6.2 4.3 tPLH 6.3 4.4 tPHL 5.8 4.4 tPLH 6.1 5 tPHL 7.1 5 SEL (1B) 5.6 5.6 SEL (2B) 6.3 5.6 SEL (1B) 5 5.6 SEL (2B) 6.2 5.6 t PZH 6.3 5.4 tPZL 6.5 5.4 tPZH 6.3 6 tPZL 8.2 6 tPHZ 6.7 4.6 tPLZ 5.2 4.6 tPHZ 7.5 5.1 tPLZ 6.2 5.1 UNIT fmax : MHz other : ns MAX MAX BA MAX LE A MAX LE OE MAX MAX t PLH tPHL A MAX MAX AB B MAX OE B MAX OE A A OE B ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

• SN74ALVCH162268: B-Port Outputs Have Equivalent 26-Ω Series Resistors

751PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE INPUTS OUTPUTS CLK Z H L H L H L OEA A 1B, 2B H L OEB OUTPUT ENABLE Active Z ActiveZ Active Z Active 1B0‡2 B 0‡ INPUTS OUTPUTS CLK H X L LH L CLKENA1 1B 2B L H L A A-TO-B STORAGE (OEB = L) X X X X X X X XXH L CLKENA2 L H † Two CLK edges are needed to propagate data. ‡ Output level before the indicated steady-state input conditions were established H X L L CLKEN1B X X X X X H L CLKEN2B L A0‡ INPUTS OUTPUT ACLK X L X H L 2B1BSEL B-TO-A STORAGE (OEA = L) XX A0‡ H L XX H H L X X X X H L L H L H ‡ Output level before the indicated steady-state input conditions were established PARAMETER MAX or MIN ALVCH 3V UNIT ICC MAX 0.04 mA IOH (A port) MAX -24 mA IOH (B port) MAX -12 mA IOL (A port) MAX 24 mA IOL (B port) MAX 12 mA PARAMETER INPUT OUTPUT MAX or MIN ALVCH fmax MIN 150 tw Pulse duration, CLK high or low MIN 3.3 A data before CLK ↑ MIN 3.4 B data before CLK ↑ MIN 1 SEL before CLK ↑ MIN 1.3 CLKENA1 or CLKENA2 before CLK ↑ MIN 2.8 CLKENB1 or CLKENB2 before CLK ↑ MIN 2.5 OE before CLK ↑ MIN 3.2 A data after CLK ↑ MIN 0.2 B data after CLK ↑ MIN 1.3 SEL after CLK ↑ MIN 1 CLKENA1 or CLKENA2 after CLK ↑ MIN 0.4 CLKENB1 or CLKENB2 after CLK ↑ MIN 0.5 OE after CLK ↑ MIN 0.2 B5 . 4 A (1B) 4.8 A (2B) 4.8 A (SEL) 5.8 B6 . 1 A5 . 1 B5 . 9 UNIT fmax : MHz other : ns t h Hold time MAXCLK CLK tsu Setup time tpd MAX CLKten MAX tdis ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS752 162280 16-BIT TO 32-BIT REGISTERED BUS EXCHANGER WITH BYTE MASKS AND 3-STATE OUTPUTS

• SN74ALVCHG162280: A-Port Outputs Have Equivalent 50- Ω Series Resistors
• B-Port Outputs Have Equivalent 20-Ω Series Resistors Logic Diagram CE CE CE CE 1 of 16 Channels CLK SEL OE DIR 1B1 2B1

753PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ALVCHG 3V UNIT ICC MAX 0.04 mA IOH (A to B) MAX 8 mA IOH (B to A) MAX 6 mA IOL (A to B) MAX 8 mA IOL (B to A) MAX 6 mA PARAMETER INPUT OUTPUT MAX or MIN ALVCHG fmax MIN 160 tw Pulse duration, CLK high or low MIN 2.3 A data before CLK ↑ , high or low MIN 1.4 B data before CLK ↑ , high or low MIN 2 C data before CLK ↑ , high or low MIN 1.3 DIR before CLK ↑ , high or low MIN 2 SEL before CLK ↑ , high or low MIN 2 A data after CLK ↑ , high or low MIN 0.3 B data after CLK ↑ , high or low MIN 0.3 C data after CLK ↑ , high or low MIN 0.3 DIR after CLK ↑ , high or low MIN 0.3 SEL after CLK ↑ , high or low MIN 0.3 B7 . 4 D7 . 2 A6 . 2 B9 . 4 B9 . 5 D7 . 9 A6 . 4 B7 . 8 B7 . 6 D6 . 7 UNIT fmax : MHz other : ns OE MAX t dis OE ten CLK MAX CLK MAX MAX MAX tsu Setup time th Hold time tpd CLK ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS X A H L OUTPUTS 1B0† CLK 2B 1B HX L L 2B0† X X A-TO-B STORAGE (OE = L, DIR = H) SEL † Output level before indicated steady-state input conditions were established ‡ Two CLK edges are needed to propagate the data. OUTPUT ENABLE INPUTS X DIR L OE OUTPUT H L HL Z Active 1B, 2BA Z Z Z Active 1D, 2D Z Active Active CLK INPUTS X C H L OUTPUT 1B0† CLK 2D 1D H X L L L‡ 2B0† H L C-TO-D STORAGE (OE = L) SEL † Output level before indicated steady-state input conditions were established ‡ Two CLK edges are needed to propagate the data. INPUTS 1BSEL H OUTPUT A H L CLK X X H X X L L H H L L § Two CLK edges are needed to propagate the data. The data is loaded in the first register when SEL is low and propagates to the second register when SEL is high. B-TO-A STORAGE (OE = L, DIR = L)

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS754 162282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

• SN74ALVCHG162282: A-Port Outputs Have Equivalent 50- Ω Series Resistors
• B-Port Outputs Have Equivalent 20-Ω Series Resistors Logic Diagram CE CE CE CE 1 of 18 Channels CLK SEL OE DIR 1B1 2B1

755PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. PARAMETER MAX or MIN ALVCHG 3V UNIT ICC MAX 0.04 mA IOH (A to B) MAX 8 mA IOH (B to A) MAX 6 mA IOL (A to B) MAX 8 mA IOL (B to A) MAX 6 mA PARAMETER INPUT OUTPUT MAX or MIN ALVCHG fmax MIN 160 tw Pulse duration, CLK high or low MIN 2.3 A data before CLK ↑ MIN 1.5 B data before CLK ↑ MIN 2 DIR before CLK ↑ MIN 2 SEL before CLK ↑ MIN 2 A data after CLK ↑ MIN 0.3 B data after CLK ↑ MIN 0.3 DIR after CLK ↑ MIN 0.3 SEL after CLK ↑ MIN 0.3 B7 . 4 A6 . 3 B9 . 4 B9 . 5 A6 . 4 B7 . 8 B7 . 6 UNIT fmax : MHz other : ns OE MAX t dis ten MAX CLK MAX OE MAX CLK MAXtpd tsu Setup time th Hold time CLK ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS FUNCTION TABLE INPUTS L L H CLK X OUTPUTS 1B0† H‡ H L 2B0† 2B1B † Output level before indicated steady-state input conditions were established ‡ Two CLK edges are needed to propagate the data. A-TO-B STORAGE (OE = L, DIR = H) INPUTS CLK SEL H L L H OUTPUT H L A § Two CLK edges are needed to propagate the data. The data is loaded in the first register when SEL is low and proparates to the second register when SEL is high. B-TO-A STORAGE (OE = L, DIR = L) INPUTS CLK OE L L H A H L X H L X X X X L H DIR L X H OUTPUTS Z Z Active Z Z Active 1B, 2BA OUTPUT ENABLE SEL

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS756 Logic Diagram 162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

• SN74ALVC162334: Output Ports Have Equivalent 26-Ω Series Resistors
• SN74ALVCH162334: Output Port Has Equivalent 26-Ω Series Resistors CLK To 15 Other Channels OE CLK LE

757PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE INPUTS X L ACLK L L OUTPUT Y Z HH OE H L X L X X L or H L † Output level before the indicated steady-state input conditions were established LE X H HL HH XL Y0†H L L L PARAMETER MAX or MIN ALVC ALVCH 3V UNIT ICC MAX 0.04 0.04 mA IOH MAX -12 -12 mA IOL MAX 12 12 mA PARAMETER INPUT OUTPUT MAX or MIN ALVC ALVCH fmax MIN 150 150 LE low 3.3 3.3 CLK high or low MIN 3.3 3.3 Data before CLK ↑ MIN 1.5 1.5 Data before LE ↑ CLK high MIN 1.3 1.3 Data before LE ↑ CL K low MIN 1.2 1.2 Data after CLK ↑ MIN 0.9 0.9 Data after LE ↑ CLK high MIN 1.1 1.1 Data after LE ↑ CL K low MIN 1.1 1.1 A MAX 3.9 3.9 LE 55 CLK MAX 4.9 4.9 ten OE Y 5.4 5.4 tdis OE Y MAX 5 5 UNIT fmax : MHz other : ns tpd Y tw Pulse duration tsu Setup time th Hold time ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 162344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS

• SN74ALVCH162344: Output Ports Have Equivalent 26-Ω Series Resistors

759PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. OE FUNCTION TABLE INPUTS L A X H OUTPUT Bn H Z L L H L PARAMETER MAX or MIN ALVCH 3V UNIT ICC MAX 0.04 mA IOH MAX -12 mA IOL MAX 12 mA PARAMETER INPUT OUTPUT MAX or MIN ALVCH tPLH 4.4 tPHL 4.4 tPZH 5.7 tPZL 5.7 tPHZ 4.5 tPLZ 4.5 UNIT: ns OE B MAX AB MAX OE B MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 162373 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

• SN74LVTH162373: Output Ports Have Equivalent 22-Ω Series Resistors 1OE 1LE 1D1 To Seven Other Channels 1Q1 2OE 2LE 2D1 2Q1 To Seven Other Channels 2C1 FUNCTION TABLE (each 8-bit section) INPUTS H L D H X OUTPUT Q H Z LL OE X LE L X Q0L H H L PARAMETER MAX or MIN UNIT ICC MAX mA IOH MAX mA IOL MAX mA PARAMETER INPUT OUTPUT MAX or MIN tw Pulse duration, LE high or low MIN Data before LE ↓ , data high MIN Data before LE ↓ , data low MIN Data after LE ↓ , data high MIN Data after LE ↓ , data low MIN tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ UNIT: ns OE Q MAX OE Q MAX th Hold time tsu Setup time MAX MAX DQ QLE ALVC 3.3 1.1 1.1 1.1 1.1 4.2 4.2 4.5 4.5 LVTH 4.6 5.1 4.6 5.4 4.9 5.4 5.1 ALVCH 0.04 -12 LVTH -12 ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 162374 3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

• SN74LVTH162374: Output Ports Have Equivalent 22-Ω Series Resistors
• SN74ALVCH162374: Output Ports Have Equivalent 26-Ω Series Resistors 1OE 1CLK 1D1 To Seven Other Channels 1Q1 2OE 2CLK 2D1 2Q1 To Seven Other Channels 2C1 FUNCTION TABLE (each fllp-flop) INPUTS H L D H X OUTPUT Q H Z LL OE X CLK L XQ 0LL PARAMETER MAX or MIN LVTH ALVCH 3V UNIT ICC MAX 5 0.04 mA IOH MAX -12 -12 mA IOL MAX 12 12 mA PARAMETER INPUT OUTPUT MAX or MIN LVTH ALVCH fmax 160 150 tw Pulse duration, CLK high or low MIN 33 . 3 Data before CLK ↑ , data high MIN 1.8 1.9 Data before CLK ↑ , data low MIN 1.8 1.9 Data after CLK ↑ , data high MIN 0.8 0.5 Data after CLK ↑ , data low MIN 0.8 0.5 tPLH 5.3 4.6 tPHL 4.9 4.6 tPZH 5.6 5.2 tPZL 4.9 5.2 tPHZ 5.4 4.5 tPLZ 5 4.5 UNIT fmax : MHz other : ns th Hold time tsu Setup time MAXCLK Q OE Q MAX OE Q MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

D CLK CE LE D CLK CE CLK CE D LE CLK CE D LE LE CLK CE D LE CLK CE D LE CLK CE D LE CLK CE D M U X CE CLK D LE P CE_SEL0 CE_SEL1 CLKENAB 1B1 1B2 1B3 1B4 CLKENAB Selector One of Four Channels CLKAB OEA OEB OEB4 OEB3 OEB2 OEB1 CLKENBA CLKBA LEBA SEL0 SEL1 CLKENB LEB1 LEB2 LEB3 LEB4 LEAB4 LEAB3 LEAB2 LEAB1 : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 162460 4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

• SN74ABTH162460: B-Port Outputs Have Equivalent 25-Ω Series Resistors

CLKAB high or low MIN 3.8 CLKBA high or low MIN 4.5 LEAB1, 2, 3 or 4 high MIN 2.8 LEBA high MIN 2.8 LEB1, 2, 3 or 4 high MIN 3 A bus MIN 2.5 CE_SEL0/1 MIN 3.2 CLKENAB MIN 3.2 Before LEAB1, 2, 3, or 4 ↓ A bus MIN 3.6 B bus MIN 3.8 CLKENB MIN 2.3 CLKENBA MIN 2.5 LEB1, 2, 3 or 4 MIN 4.3 SEL0/1 MIN 4.5 Before LEB1, 2, 3, or 4 ↓ B bus MIN 3.2 B bus MIN 4 LEB1, 2, 3 or 4 MIN 4.4 SEL0/1 MIN 4.3 A bus MIN 0.5 CE_SEL0/1 MIN 1.1 CLKENAB MIN 0.5 after LEAB1, 2, 3, or 4 ↓ A bus MIN 1.2 B bus MIN 1.3 CLKENB MIN 1 CLKENBA MIN 1 SEL0/1 MIN 0 after LEB1, 2, 3, or 4 ↓ B bus MIN 1.5 B bus MIN 0.4 SEL0/1 MIN 0.1 Before CLKBA th Hold time after CLKAB ↑ after CLKBA ↑ after CLKBA ↑ tsu Setup time PARAMETER tw Pulse duration Before CLKAB ↑ Before CLKBA ↑ PARAMETER INPUT OUTPUT MAX or MIN ABTH tPLH 6.5 tPHL 6.5 tPZH 5.6 tPZL 5.5 tPHZ 5.9 tPLZ 6.5 tPLH 6.2 tPHL 6.5 tPZH 6.8 tPZL 6.3 tPHZ 6.2 tPLZ 5.8 tPZH 6.6 tPZL 6.2 tPHZ 5.3 tPLZ 4.9 tPLH 7.4 tPHL 7.7 tPLH 6.5 tPHL 6.5 tPLH 5.8 tPHL 5.8 tPLH 6.2 tPHL 6.2 tPLH 7.2 tPHL 6.8 tPLH 7.5 tPHL 6.9 UNIT fmax : MHz other : ns BA MAX OEA A MAX OEA A MAX AB MAX OEB B MAX OEB B MAX OEB1, 2, 3, 4 B MAX OEB1, 2, 3, 4 B MAX CLKBA A MAX CLKAB B MAX LEBA A MAX LEAB1, 2, 3, 4 B MAX LEBA1, 2, 3, 4 A MAX SEL A MAX PARAMETER MAX or MIN ABTH UNIT ICC MAX 32 mA IOH (A port) MAX -32 mA IOH (B port) MAX -12 mA IOL (A port) MAX 64 mA IOL (B port) MAX 12 mA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS 763PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE INPUTS H L H L OUTPUT BnOEB H H L L OEBn Z Z ZA-TO-B OUTPUT ENABLE INPUTS H L L L L L OUTPUTS CLKENAB X X H or L H or L L CLKAB H L H L CE_SEL0 X X X X H L H L CE_SEL1 X X X X H L H L L LEAB1 H L LEAB2 H L LL LEAB3 L L L L L L LEAB4 B1 A A A A A A A A0 A0 A0 A0 A0 A0 A A-TO-B STORAGE (assuming OEB = L, OEBn = L) Active † Output level before the indicated steady-state input conditions were established †n = 1, 2, 3, 4 L LL LL L L LL LL LL LL INPUTS X L L L H OUTPUT ACLKENBA X X X X X X L CLKBA XX H H L L LEBA H L OEA H L X X H L L B H L A0† H L A0† X B-TO-A STORAGE (after point P) L L L L L L INPUTS L L PCLKENB X X X X X X L CLKBA H L LEB1 B40† B30† B20† B10† B-TO-A STORAGE (after point P) L L H L LEB2 L L H L LL LL LL LEB3 L L H L X L X L LEB4 L L H H H L SEL1 L L H H H H H L H L H HH L SEL0 L L L L L L

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 162500 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

• SN74ABT162500: B-Port Outputs Have Equivalent 25-Ω Series Resistors

765PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE INPUTS H OUTPUT B H B0‡ X L LEAB ‡O utput level before the indicated steady-state input conditions were established. §O utput level before the indicated steady-state input conditions were established, provided that CLKAB was low before LEAB went low. L OEAB H X H L A X L LL X X Z L L H H H H H H H H LX X B0§ H L CLKAB PARAMETER MAX or MIN ABT UNIT ICC MAX 36 mA IOH (A port) MAX -32 mA IOH (B port) MAX -12 mA IOL (A port) MAX 64 mA IOL (B port) MAX 12 mA PARAMETER INPUT OUTPUT MAX or MIN ABT fmax MIN 150 LEAB or LEBA high MIN 2.5 CLKAB or CLKBA high or low MIN 3 A before CLKAB ↓ MIN 3.3 B before CLKBA ↓ MIN 3.3 A before LEAB ↓ or LEBA ↓ CLK high MIN 1 A before LEAB ↓ or LEBA ↓ CLK low MIN 2.5 A after CLKAB ↓ or B after CLKBA ↓ MIN 0 A after LEAB ↓ or B after LEBA ↓ MIN 2 tPLH 4.8 tPHL 5.7 tPZH 5.6 tPZL 5.9 tPHZ 5.9 tPLZ 6 tPZH 5.3 tPZL 5.4 tPHZ 6.5 tPLZ 5.8 tPZH 5.3 tPZL 5.4 tPHZ 6.5 tPLZ 5.8 UNIT fmax : MHz other : ns OEBA A MAX A or B B or A B or A B or A A OEAB OEAB OEBA B MAX B MAX MAX LEAB or LEBA MAX CLKAB or CLKBA MAX t w Pulse duration tsu Setup time th Hold time MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 162501 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

• SN74ABT162501: B-Port Outputs Have Equivalent 25-Ω Series Resistors

767PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE† INPUTS X H ACLKAB L L OUTPUT Y Z HH OEAB L H X H X X H L LEAB X L HH H HL X H B0‡L L X B0§L H H L † A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. ‡ Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low § Outoput level before the indicated steady-state input conditions were established PARAMETER MAX or MIN ABT UNIT ICC MAX 36 mA IOH (A port) MAX -32 mA IOH (B port) MAX -12 mA IOL (A port) MAX 64 mA IOL (B port) MAX 12 mA PARAMETER INPUT OUTPUT MAX or MIN ABT fmax MIN 150 LEAB or LEBA high MIN 3 CLKAB or CLKBA high or low MIN 3.3 A before CLKAB ↑ MIN 4.3 B before CLKBA ↑ MIN 4.3 A before LEAB ↓ or LEBA ↓ CLK high MIN 2.5 A before LEAB ↓ or LEBA ↓ CLK low MIN 1 A after CLKAB ↑ or B after CLKBA ↑ MIN 0 A after LEAB ↓ or B after LEBA ↓ MIN 2 tPLH 4.8 tPHL 5.7 tPZH 5.6 tPZL 5.9 tPHZ 5.5 tPLZ 5.3 tPZH 5.3 tPZL 5.4 tPHZ 6.5 tPLZ 5.8 tPZH 5.3 tPZL 5.4 tPHZ 6.5 tPLZ 5.8 UNIT fmax : MHz other : ns tw Pulse duration MAX LEAB or LEBA MAX tsu Setup time th Hold time CLKAB or CLKBA MAX OEBA B MAX B MAX MAX OEBA A MAX A or B B or A B or A B or A A OEAB OEAB ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 162525 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS

• SN74ALVCH162525: B-Port Outputs Have Equivalent 26-Ω Series Resistors

769PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE INPUTS OUTPUT CLKNAB XH H L L OLKAB B X L A A-TO-B STORAGE(OEAB = L) L A0† B0† H INPUTS OUTPUT CLK1BA L L L HH H L L H L L‡L CLKENBA B ASEL B-TO-A STORAGE (OEBA = L) X X CLK2BA HX X X X LH L † Output level before the indicated steady-state input conditions were established ‡ Three CLK1BA edges and one CLK2BA edge are needed to propagate data from B to A when SEL is low. † Output level before the indicated steady-state input conditions were established ↑ ↑ PARAMETER MAX or MIN ALVCH 3V UNIT ICC MAX 0.04 mA IOH (A port) MAX -24 mA IOH (B port) MAX -12 mA IOL (A port) MAX 24 mA IOL (B port) MAX 12 mA PARAMETER INPUT OUTPUT MAX or MIN ALVCH fmax MIN 150 tw Pulse duration, CLK high or low MIN 3 A data before CLKAB ↑ MIN 1.3 B data before CLK2BA ↑ MIN 1.7 B data before CLK1BA ↑ MIN 1.1 SEL before CLK2BA ↑ MIN 3.3 CLKENAB before CLKAB ↑ MIN 1.6 CLKENBA before CLK1BA ↑ MIN 2.1 CLKENBA before CLK2BA ↑ MIN 2.2 A data after CLKAB ↑ MIN 0.9 B data after CLK2BA ↑ MIN 0.6 B data after CLK1BA ↑ MIN 1 SEL after CLK2BA ↑ MIN 0.1 CLKENAB after CLKAB ↑ MIN 0.3 CLKENBA after CLK1BA ↑ MIN 0.1 CLKENBA after CLK2BA ↑ MIN 0 CLKAB B 4.7 CLK2BA A 4.2 OEBA A 5.1 OEAB B 5.7 OEBA A 4.9 OEAB B 4.9 UNIT fmax : MHz other : ns tdis MAX MAX tsu Setup time th Hold time tpd MAX ten ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS770 Logic Diagram 162541 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

• SN74LVTH162541: Output Ports Have Equivalent 22-Ω Series Resistors 1OE1 1OE2 2OE1 2OE2 1A1 1Y1 2Y12A1 To Seven Other Channels To Seven Other Channels

771PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE (each 8-bit section) INPUTS L A X L OUTPUT Y HH OE1 H X L Z OE2 Z X XH L L L PARAMETER MAX or MIN LVTH 3V UNIT ICC MAX 5 mA IOH MAX -12 mA IOL MAX 12 mA PARAMETER INPUT OUTPUT MAX or MIN LVTH tPLH 4.1 tPHL 4.1 tPZH 5 tPZL 4.8 tPHZ 5.9 tPLZ 5.4 UNIT: ns OE Y MAX AY MAX OE Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 162601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

• SN74ABT162601: B-Port Outputs Have Equivalent 25-Ω Series Resistors
• SN74ALVCH162601: B-Port Outputs Have Equivalent 26-Ω Series Resistors

773PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. FUNCTION TABLE INPUTS H OUTPUT B H B0‡ X L † A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CLKBA, and CLKENBA. ‡ Output level before the indicated steady-state input conditions were established. § Output level before the indicated steady-state input conditions were established, provided that CLKAB was low before LEAB went low. H X H L X L L L X X Z L L H H H H LX X B0§ H L L H CLKENAB OEAB X L X X B0‡ B0‡ L X L X L L X L X L L L L L L L LEAB CLKAB A PARAMETER MAX or MIN ABT ALVCH 3V UNIT ICC MAX 36 0.04 mA IOH (A port) MAX -32 -24 mA IOH (B port) MAX -12 -12 mA IOL (A port) MAX 64 24 mA IOL (B port) MAX 12 12 mA PARAMETER INPUT OUTPUT MAX or MIN ABT ALVCH fmax MIN 150 150 LEAB or LEBA high MIN 2.5 3.3 CLKAB or CLKBA high or low MIN 33 . 3 Data before CLK ↑ MIN 4.3 2.1 A before LEAB ↓ or B before LEBA ↓ , CLK high MIN 2.5 1.6 A before LEAB ↓ or B before LEBA ↓ , CLK low MIN 11 . 1 CLKEN before ↑ MIN 2.7 1.7 Data after CLK ↑ MIN 00 . 8 A after LEAB ↓ or B after LEBA ↓ , CLK high MIN 0.5 1.4 A after LEAB ↓ or B after LEBA ↓ , CLK low MIN 0.5 1.7 CLKEN after ↑ MIN 00 . 6 tPLH 4.8 4.5 tPHL 5.7 4.5 tPLH 4 4.1 tPHL 4.9 4.1 tPLH 5 4.7 tPHL 5 4.7 tPLH 5.6 5.1 tPHL 5.9 5.1 tPLH 5.3 5 tPHL 55 tPLH 5.5 5.5 tPHL 5.3 5.5 tPZH 5.1 5.2 tPZL 5.4 5.2 tPZH 6.1 5.7 tPZL 5.7 5.7 tPHZ 6.2 4.4 tPLZ 5.4 4.4 tPHZ 5.4 4.8 tPLZ 5.2 4.8 UNIT fmax : MHz other : ns CLKBA A B MAX CLKAB MAX LEAB A B MAX MAX tw Pulse duration MAX LEBA MAX BA tsu Setup time th Hold time B MAX MAX A OEAB B MAX AB OEBA OEAB OEBA A MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 162721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

• SN74ALVCH162721: Output Ports Have Equivalent 26-Ω Series Resistors CLK CLKEN To 19 Other Channels OE 55 2 CE FUNCTION TABLE INPUTS (each flip-flop) OUTPUT Q L X L DCLK ZH H L OE CLKEN L X L X L H X L H L LX L or H X PARAMETER MAX or MIN ALVCH 3V UNIT ICC MAX 0.04 mA IOH MAX -12 mA IOL MAX 12 mA PARAMETER INPUT OUTPUT MAX or MIN ALVCH fmax MIN 150 tw Pulse duration CLK high or low MIN 3.3 Data before CLK ↑ MIN 3.1 CLKEN before CLK ↑ MIN 2.7 Data after CLK ↑ MIN 0 CLKEN after CLK ↑ MIN 0 tPLH 5.3 tPHL 5.3 tPZH 5.8 tPZL 5.8 tPHZ 5 tPLZ 5 UNIT fmax : MHz other : ns tsu Setup time th Hold time CLK Q OE OE MAX MAXQ Q MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 162820 3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS

• SN74ALVCH162820: Output Ports Have Equivalent 26-Ω Series Resistors To Nine Other Channels 1OE 2OE CLK 1Q1 1Q2 FUNCTION TABLE INPUTS (each flip flop) H L D H X OUTPUT H Z LL OEn† L CLK X X L L Q † n = 1,2 PARAMETER MAX or MIN ALVCH 3V UNIT ICC MAX 0.04 mA IOH MAX -12 mA IOL MAX 12 mA PARAMETER INPUT OUTPUT MAX or MIN ALVCH fmax MIN 150 tw Pulse duration CLK high or low MIN 3.3 tsu Setup time Data before CLK ↑ MIN 1.4 th Hold time Data after CLK ↑ MIN 1 tPLH 5.4 tPHL 5.4 tPZH 5.6 tPZL 5.6 tPHZ 5 tPLZ 5 UNIT fmax : MHz other : ns CLK Q OE OE MAX MAXQ Q MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

PARAMETER MAX or MIN ABT UNIT ICC MAX 80 mA IOH MAX -12 mA IOL MAX 12 mA PARAMETER INPUT OUTPUT MAX or MIN ABT fmax MIN 150 CLR low MIN 3.3 CLK high or low MIN 3.3 CLR inactive MIN 1.6 Data before CLK ↑ MIN 2 CLKEN low before CLK ↑ MIN 2.8 Data after CLK ↑ MIN 1.2 CLKEN low after CLK ↑ MIN 0.6 tPLH 7.5 tPHL 6.7 tPHL CLR Q MAX 7 tPZH 5.9 tPZL 7 tPHZ 6.6 tPLZ 9 UNIT fmax : MHz other : ns tw Pulse duration CLK tsu Setup time th Hold time QM A X Q OE OE MAX MAXQ ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS 776 Logic Diagram To Eight Other Channels 1D1 1Q1 1CLKEN 1OE 1CLR R C1 3 CE 1CLK To Eight Other Channels 2D1 2Q1 2CLKEN 2OE 2CLR R C1 15 CE 2CLK : OBSOLETED or NOT RECOMMENDED NEW DESIGNS 162823 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

• SN74ABT162823A: Output Ports Have Equivalent 25-Ω Series Resistors FUNCTION TABLE INPUTS X L DCLENK CLK L L OUTPUT Q L L X OE L L X L L L X CLR L H HL H Z H X X X H L X X X H H H↑

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 777 162825 18-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

• SN74ABT162825: Output Ports Have Equivalent 25-Ω Series Resistors Logic Diagram 1A1 1Y1 2 To Eight Other Channels 2A1 2Y1 16 To Eight Other Channels 1OE1 1OE2 2OE1 2OE2 FUNCTION TABLE INPUTS H L A H X OUTPUT Y H Z X L OE2 H L X OE1 L LL X Z PARAMETER MAX or MIN ABT UNIT ICC MAX 32 mA IOH MAX -12 mA IOL MAX 12 mA PARAMETER INPUT OUTPUT MAX or MIN ABT tPLH 3.9 tPHL 4.7 tPZH 6.9 tPZL 6.3 tPHZ 6.6 tPLZ 6.3 UNIT: ns OE Y MAX AY MAX OE Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS778 Logic Diagram 162827 20-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

• SN74ABT162827A: Output Ports Have Equivalent 25-Ω Series Resistors
• SN74ALVTH162827: Output Ports Have Equivalent 30-Ω Series Resistors
• SN74ALVCH162827: Output Ports Have Equivalent 26-Ω Series Resistors 1Y12 1OE1 1OE2 56 2Y115 292OE1 2OE2 To Nine Other Channels To Nine Other Channels 1A1 2A1 FUNCTION TABLE INPUTS (each flip flop) X H A L X OUTPUT L Z HH OE1 X OE2 H Z X L L L L Y PARAMETER MAX or MIN ABT ALVTH ALVCH 3V UNIT ICC MAX 32 5.5 0.04 mA IOH MAX -12 -12 -12 mA IOL MAX 12 12 12 mA PARAMETER INPUT OUTPUT MAX or MIN ABT ALVTH ALVCH tPLH 3.9 3.9 3.8 tPHL 4.7 3.7 3.8 tPZH 6.9 5.6 5.1 tPZL 6.3 4.1 5.1 tPHZ 6.6 6.3 4.7 tPLZ 6.3 5.1 4.7 UNIT: ns OE Y MAX AY MAX OE Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

779PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram 162830 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS

• SN74ALVCH162830, SN74ALVCHS162830: Output Ports Have Equivalent 26-Ω Series Resistors To 17 Other Channels 1Y1 2Y1 OE2 OE1 FUNCTION TABLE INPUTS OUTPUTS L A L L H L H H OE1 H H L L H L OE2 L X 1Yn Z L H Z L H Z 2Yn Z L H Z L H ZH L H H L L PARAMETER MAX or MIN ALVCH ALVCHS 3V UNIT ICC MAX 0.04 0.04 mA IOH MAX -12 -12 mA IOL MAX 12 12 mA PARAMETER INPUT OUTPUT MAX or MIN ALVCH ALVCHS tPLH 3.5 3.5 tPHL 3.5 3.5 tPZH 4.8 4.8 tPZL 4.8 4.8 tPHZ 5.2 5.2 tPLZ 5.2 5.2 UNIT: ns OE Y MAX AY MAX OE Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS780 CLK D Q To Eight Other Channels OE1 OE2 CLK SEL 1Y1 2Y1 3Y1 4Y1 162831 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS

• SN74ALVC162831, SN74ALVCH162831: Output Ports Have Equivalent 26-Ω Series Resistors FUNCTION TABLE INPUTS X H H CLKSEL OUTPUT Y Z OE H L L L L X X X A X L L L H L H L H L H PARAMETER MAX or MIN ALVC ALVCH 3V UNIT ICC MAX 0.04 0.04 mA IOH MAX -12 -12 mA IOL MAX 12 12 mA PARAMETER INPUT OUTPUT MAX or MIN ALVC ALVCH fmax MIN 150 150 tw Pulse duration CLK high or low MIN 3.3 3.3 tsu Setup time A data before CLK ↑ MIN 1.6 1.6 th Hold time A data after CLK ↑ MIN 1.1 1.1 tPLH 4.3 4.3 tPHL 4.3 4.3 tPLH 4.7 4.7 tPHL 4.7 4.7 tPLH 4.8 4.8 tPHL 4.8 4.8 tPZH 5.1 5.1 tPZL 5.1 5.1 tPHZ 5.1 5.1 tPLZ 5.1 5.1 UNIT fmax : MHz other : ns MAX MAX MAX Y OE OE Y AY MAX SEL Y MAX YCLK ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 781 Logic Diagram CLK D Q To Six Other Channels OE1 OE2 CLK SEL 1Y1 2Y1 3Y1 4Y1 162832 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS

• SN74ALVCH162832: Output Ports Have Equivalent 26-Ω Series Resistors FUNCTION TABLE INPUTS X H H CLKSEL OUTPUT Y Z OE H L L L L X X X A X L L L H L H L H L H PARAMETER MAX or MIN ALVCH 3V UNIT ICC MAX 0.04 mA IOH MAX -12 mA IOL MAX 12 mA PARAMETER INPUT OUTPUT MAX or MIN ALVCH fmax MIN 150 tw Pulse duration CLK high or low MIN 3.3 tsu Setup time A data before CLK ↑ MIN 1.6 th Hold time A data after CLK ↑ MIN 1.1 tPLH 4.3 tPHL 4.3 tPLH 4.7 tPHL 4.7 tPLH 4.8 tPHL 4.8 tPZH 5.1 tPZL 5.1 tPHZ 5.1 tPLZ 5.1 UNIT fmax : MHz other : ns MAX SEL Y MAX YCLK OE OE Y AY MAX MAX MAX Y ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS782 Logic Diagram 162834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

• SN74ALVC162834: Outputs Have Equivalent 26-Ω Series Resistors OE CLK CLK To 17 Other Channels LE FUNCTION TABLE INPUTS X L ACLK L L OUTPUT Y Z HH OE H L X L X X H L LE X H HL L HH X L Y0†H L X Y0‡H L L L † Output level before the indicated steady-state input conditions were established, provided that CLK is high before LE goes high ‡ Output level before the indicated steady-state input conditions were established PARAMETER MAX or MIN ALVC ALVCF 3V UNIT ICC MAX 0.04 0.04 mA IOH MAX -12 -18 mA IOL MAX 12 18 mA PARAMETER INPUT OUTPUT MAX or MIN ALVC ALVCF fmax MIN 150 150 LE low MIN 3.3 3.3 CLK high or low MIN 3.3 3.3 Data before CLK ↑ MIN 1.7 1.0 Data before LE ↑ , CLK high MIN 1.9 1.5 Data before LE ↑ , CLK low MIN 1.5 1.0 A data after CLK ↑ MIN 0.7 0.6 Data after LE ↑ , CLK high MIN 0.9 1.4 Data after LE ↑ , CLK low MIN 0.9 1.4 tPLH 4.2 3.5 tPHL 4.2 3.5 tPLH 5.8 4.6 tPHL 5.8 4.6 tPLH 5.4 3.5 tPHL 5.4 3.5 tPZH 5.9 5.0 tPZL 5.9 5.0 tPHZ 5 4.2 tPLZ 5 4.2 UNIT fmax : MHz other : ns MAX MAX th Hold time OE tsu Setup time tw Pulse duration OE Y AY LE Y YCLK MAX MAX MAX Y ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 783 Logic Diagram162835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

• SN74ALVC162835, SN74ALVCH162835: Output Port Has Equivalent 26-Ω Series Resistors OE CLK CLK To 17 Other Channels LE FUNCTION TABLE INPUTS X L ACLK L L OUTPUT Y Z HH OE H L X L X X L or H L † Output level before the indicated steady-state input conditions were established LE X L HL HL XL Y0†L H H L PARAMETER MAX or MIN ALVC ALVCF ALVCH 3V UNIT ICC MAX 0.04 0.04 0.04 mA IOH MAX -12 -18 -12 mA IOL MAX 12 18 12 mA PARAMETER INPUT OUTPUT MAX or MIN ALVC ALVCF ALVCH fmax MIN 150 150 150 LE low MIN 3.3 3.3 3.3 CLK high or low MIN 3.3 3.3 3.3 Data before CLK ↑ MIN 1.7 1.0 1.7 Data before LE ↓ , CLK high MIN 1.5 1.5 1.5 Data before LE ↓ , CLK low MIN 1 1.0 1 A data after CLK ↑ MIN 0.7 0.6 0.7 Data after LE ↓ , CLK high MIN 1.4 1.4 1.4 Data after LE ↓ , CLK low MIN 1.4 1.4 1.4 tPLH 4.2 3.5 4.2 tPHL 4.2 3.5 4.2 tPLH 5.1 4.6 5.1 tPHL 5.1 4.6 5.1 tPLH 5.4 3.5 5.4 tPHL 5.4 3.5 5.4 tPZH 5.5 5.0 5.5 tPZL 5.5 5.0 5.5 tPHZ 4.5 4.2 4.5 tPLZ 4.5 4.2 4.5 UNIT fmax : MHz other : ns tsu Setup time tw Pulse duration MAX MAX MAX Y OE OE Y A YCLK t h Hold time MAXY LE Y MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS784 Logic Diagram162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

• SN74ALVC162836, SN74ALVCH162836: Output Port Has Equivalent 26-Ω Series Resistors CLK To 19 Other Channels OE CLK LE FUNCTION TABLE INPUTS X L ACLK L L OUTPUT Y Z HH OE H L X L X X L or H L LE X H H L HH X Y0†H L L L † Output level before the indicated steady-state input conditions were established PARAMETER MAX or MIN ALVC ALVCH 3V UNIT ICC MAX 0.04 0.04 mA IOH MAX -12 -12 mA IOL MAX 12 12 mA PARAMETER INPUT OUTPUT MAX or MIN ALVC ALVCH fmax MIN 150 150 LE low MIN 3.3 3.3 CLK high or low MIN 3.3 3.3 Data before CLK ↑ MIN 1.5 1.5 Data before LE ↓ , CLK high MIN 1.3 1.3 Data before LE ↓ , CLK low MIN 1.2 1.2 A data after CLK ↑ MIN 0.9 0.9 Data after LE ↓ , CLK high MIN 1.1 1.1 Data after LE ↓ , CLK low MIN 1.1 1.1 tPLH 44 tPHL 44 tPLH 5.1 5.1 tPHL 5.1 5.1 tPLH 55 tPHL 55 tPZH 5.5 5.5 tPZL 5.5 5.5 tPHZ 5.1 5.1 tPLZ 5.1 5.1 UNIT fmax : MHz other : ns YCLK th Hold time MAXY LE Y MAX tsu Setup time tw Pulse duration MAX MAX MAX Y OE OE Y A ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. 785 Logic Diagram 162841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS

• SN74ABT162841: Output Ports Have Equivalent 25-Ω Series Resistors
• SN74ALVCH162841: Output Ports Have Equivalent 26-Ω Series Resistors 1OE To Nine Other Channels 1LE 1D1 1Q1 2OE To Nine Other Channels 2LE 2D1 2Q1 FUNCTION TABLE (each 10-bit latch) INPUTS L D L OUTPUT Q Z HH OE H L X L L LE X H X H LQ 0 PARAMETER MAX or MIN ABT ALVCH 3V UNIT ICC MAX 89 0.04 mA IOH MAX -12 -12 mA IOL MAX 12 12 mA MAX or MIN ABT ALVCH tw Pulse duration MIN 43 . 3 0.8 - -1 . 1 MIN 1.8 - MIN -1 . 1 5.2 4.3 6 4.3 5.4 4.7 5.8 4.7 5.7 5.3 6.5 5.3 6.5 4.4 7.1 4.4 UNIT : ns MIN tPLH tPHL tPLH Setup timetsu Data before LE ↓ Data before LE ↑ Q Q OE OE Data after LE ↓ Data after LE ↑ tPZH tPZL tPHZ tPLZ MAX D LE Q Q MAX MAX PARAMETER INPUT OUTPUT tPHL LE highor low th Hold time MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS

: OBSOLETED or NOT RECOMMENDED NEW DESIGNS 322244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS PARAMETER MAX or MIN LVCH 3V UNIT ICC MAX 0.04 mA IOH MAX -12 mA IOL MAX 12 mA PARAMETER INPUT OUTPUT MAX or MIN LVCH tPLH 4.4 tPHL 4.4 tPZH 5.5 tPZL 5.5 tPHZ 6.3 tPLZ 6.3 UNIT: ns MAXOE Y A MAXY Y MAXOE ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS

787PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets. Logic Diagram 1OE 1CLK 1D1 To Seven Other Channels 1Q1 2OE 2CLK 2D1 2Q1 To Seven Other Channels E2A2C1 3OE 3CLK 3D1 To Seven Other Channels 3Q1 4OE 4CLK 4D1 4Q1 To Seven Other Channels J2C1 INPUTS H or L CLK OUTPUT Q Z OE H L L L X D X X HH L L FUNCTION TABLE (each 8bit flip-flop) PARAMETER MAX or MIN LVTH 3V UNIT ICC MAX 10 mA IOH MAX -12 mA IOL MAX 12 mA PARAMETER INPUT OUTPUT MAX or MIN LVTH fmax 160 tw Pulse duration, CLK high or low MIN 3 Data before CLK ↑ , data high MIN 1.8 Data before CLK ↑ , data low MIN 1.8 Data after CLK ↑ , data high MIN 0.8 Data after CLK ↑ , data low MIN 0.8 tPLH 5.3 tPHL 4.9 tPZH 5.6 tPZL 4.9 tPHZ 5.4 tPLZ 5 UNIT fmax : MHz other : ns OE Q MAX OE Q MAX th Hold time tsu Setup time MAXCLK Q ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS 322374 3.3-V ABT 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP

• Output Ports Have Equivalent 22-Ω Series Resistors

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