47L64

47L64 MICROCHIP | Alldatasheet

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Technical content

 2019-2020 Microchip Technology Inc. Preliminary DS20006168B-page 1 47L64 Serial SRAM Features

• Unlimited Reads/Unlimited Writes: - Standard serial SRAM protocol - Symmetrical timing for reads and writes
• SRAM Array: - 8,192 x 8 bits
• High-Speed I2C Interface: - Industry standard: 1 MHz, 400 kHz, and 100 kHz - Zero cycle delay writes and reads to SRAM array - Schmitt Trigger inputs for noise suppression
• Low-Power CMOS Technology: - Active current: 1 mA (maximum) - Standby current: 200 µA (maximum) Hidden EEPROM Backup Features
• Cell-Based Nonvolatile Backup: - Mirrors SRAM array cell-for-cell - Transfers all data to/from SRAM cells in parallel (all cells at same time)
• Invisible-to-User Data Transfers: - VCC level monitored inside device - SRAM automatically saved on power disrupt - SRAM automatically restored on VCC return
• 100,000 Backups Minimum
• 100 Years Retention (at 55°C) Other Features of the 47L64
• Operating Voltage Range: 2.7V to 3.6V
• Temperature Ranges: - Industrial (I): -40°C to +85°C
• ESD protection: >2,000V Packages
• 8-Lead SOIC
• 8-Lead TDFN Package Types (not to scale) Pin Descriptions Pin Name Description VCAP External Capacitor A1, A2 Hardware Address Pins VSS Ground SCL Serial Clock Input SDA Serial Data Input/Output WP Write-Protect Input VCC Power Supply 8-Lead SOIC VCAP VSS VCC WP SCL SDA (Top View) Note 1: Includes Exposed Thermal Pad (EP) TDFN(1) (Top View) VSS WP SCL

5 SDA

 2019-2020 Microchip Technology Inc. Preliminary DS20006168B-page 2 47L64 General Description The Microchip Technology Inc. 47L64 serial EERAM has an SRAM memory core with hidden EEPROM backup. The device can be treated by the user as a full symmetrical read/write SRAM. Backup to EEPROM is handled by the device on any power disrupt, so the user can effectively view this device as an SRAM that never loses its data. The device is structured as a 64-Kbit SRAM with EEPROM backup in each memory cell. The SRAM is organized as 8,192 x 8 bits and uses the I 2C serial interface. The I 2C bus uses two signal lines for communication: clock input (SCL) and data (SDA). Access to the device is controlled through a chip address and address pins, allowing up to four devices to share the same bus. The SRAM is a conventional serial SRAM: it allows symmetrical reads and writes and has no limits on cell usage. The backup EEPROM is invisible to the user and cannot be accessed by the user independently. The device includes circuitry that detects V CC dropping below a certain threshold, shuts its connection to the outside environment, and transfers all SRAM data to the EEPROM portion of each cell for safe keeping. When V CC returns, the circuitry automatically returns the data to the SRAM and the user’s interaction with the SRAM can continue with the same data set. Block Diagram Powering the Device During SRAM to EEPROM Backup (VCAP) A small capacitor (typically 22 µF) is required for the proper operation of the device. This capacitor is placed between VCAP (pin 1) and the system VSS (see Normal Device Operation). When power is first applied to the device, this capacitor is charged to V CC through the device (see Normal Device Operation). During normal SRAM operation, the capacitor remains charged to VCC and the level of system V CC is monitored by the device. If system VCC drops below a set threshold, the device interprets this as a power-off or brown-out event. The device suspends all I/O operation, shuts off its connection with the V CC pin, and uses the saved energy in the capacitor to power the device through the VCAP pin as it transfers all SRAM data to EEPROM (see Vcc Power-Off Event ). On the next power-up of VCC, the data is transfered back to SRAM, the capacitor is recharged, and the SRAM operation continues. Normal Device Operation VCC Power-Off Event Power I2C Control Logic Memory Address and Data Control Logic and Address VCC Control BlockVCAP Decoder EEPROM RECALL STORE SDA SCL SRAM 8K x 8 8K x 8 WP VCC Monitor Normal SRAM Operation VCC (pin 8) VCAP (pin ) CVCAP Charged to VCC VSS (pin 4) System VCC 6&/ 6'$ System VSS Automatic Backup SRAM SRAM to EEPROM Transfer EEPROM VCC (pin 8) System VCC 6&/ 6'$ VCAP (pin ) CVCAP Temporary VCC VSS (pin 4) System VSS

 2019-2020 Microchip Technology Inc. Preliminary DS20006168B-page 3 47L64

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings† † NOTICE: Stresses above those listed under ‘Maximum ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Industrial (I): TAMB = -40°C to +85°C, VCC = 2.7V to 3.6V Param. No. Symbol Characteristic Min. Typ. Max. Units Conditions D1 VIH High-Level input Voltage 0.8 X VCC — VCC+0.5 V D2 VIL Low-Level Input Voltage -0.5 — 0.2*VCC V D3 VOL Low-Level Output Voltage — — 0.4 V IOL = 2.0 mA D4 VHYS Hysteresis of Schmitt Trigger Inputs (SDA, SCL pins)

0.05 X VCC — — V Note 1

D5 ILI Input Leakage Current (SDA, SCL pins) — — ±3 A VIN = VSS or VCC D6 ILO Output Leakage Current (SDA pin) — — ±3 A VOUT = VSS or VCC D7 RIN Input Resistance to VSS (A1, A2, WP pins) 50 — — k VIN = VIL (max) D8 CINT Internal Capacitance (all inputs and outputs) — — 7 pF TAMB = 25°C, FREQ = 1 MHz, VCC = 3.3V (Note 1) D9 ICC Active 1 Operating Current @ 1 MHz — — 1 mA VCC = 3.6 V, FCLK = 1 MHz D10 ICC Active 2 Operating Current @ 400 kHz — — 700 µA VCC = 3.6 V, FCLK = 400 kHz D11 ICCS Standby Current — — 200 µA SCL, SDA, VCAP, VCC = 3.6V D12 VTRIP AutoStore/AutoRecall Trip Voltage 2.3 — 2.65 V Note 1 D13 VPOR Power-on Reset Voltage — — 2.1 V D14 CB Bus Capacitance — — 400 pF D15 CVCAP VCAP Capacitor 10 22 50 µF Note 1 Note 1: This parameter is periodically sampled and not 100% tested.

 2019-2020 Microchip Technology Inc. Preliminary DS20006168B-page 4 47L64

1.1 AC CHARACTERISTICS

TABLE 1-1: AC CHARACTERISTICS FIGURE 1-1: BUS TIMING DATA AC CHARACTERISTICS Industrial (I): TAMB = -40°C to +85°C, VCC = 2.7V to 3.6V Param. No. Symbol Characteristic Min. Max. Units Conditions

1 FCLK Clock Frequency — 1000 kHz

2 THIGH Clock High Time 400 — ns

3 TLOW Clock Low Time 600 — ns

4 TR SDA and SCL Input Rise Time — 300 ns Note 1

5 TF SDA and SCL Input Fall Time — 100 ns Note 1

6 THD:STA Start Condition Hold Time 250 — ns

7 TSU:STA Start Condition Setup Time 250 — ns

8 THD:DAT Data Input Hold Time 0 — ns

9 TSU:DAT Data Input Setup Time 100 — ns

10 TSU:STO Stop Condition Setup Time 250 — ns

11 TAA Output Valid from Clock — 550 ns

12 TBUF Bus Free Time: Time the bus must

be free before a new transmission can start 500 — ns

13 TOF Output Fall Time from VIH

CB  100pF 20+0.1CB 250 ns CB  100 pF (Note 1)

14 TSP Input Filter Spike Suppression

(SDA and SCL pins) — 50 ns

15 TRESTORE Power-up Recall Operation

— 550 µs

16 TSTORE Store Operation Duration — 10 ms

17 TVRISE VCC Rise Rate 30 — µs/V Note 1

18 TvFALL VCC Fall Rate 30 — µs/V Note 1

19 — Endurance 100,000 — Store Cycles 25°C, VCC = 3.6V (Note 1, Note 2)

20 Retention 100 Years 55°C

Note 1: This parameter is not tested but ensured by characterization. 2: For endurance estimates in a specific application, consult the Total Endurance Model which can be obtained on Microchip’s website at www.microchip.com. SCL SDA IN SDA OUT 8 9 D4 4

 2019-2020 Microchip Technology Inc. Preliminary DS20006168B-page 5 47L64 FIGURE 1-2: AUTOSTORE/AUTORECALL TIMING DATA AutoStore AutoRecall 16 16 D12 VCC Device Access Enabled D13 1817

 2019-2020 Microchip Technology Inc. Preliminary DS20006168B-page 6 47L64

2.0 PIN DESCRIPTION

The description of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE

2.1 A1, A2 Chip Address Inputs

The A1, A2 inputs are used by the 47L64 for multiple device operation. The levels on these inputs are compared with the corresponding Chip Select bits in the slave address. The chip is selected if the comparison is true. Up to four devices may be connected to the same bus by using different Chip Select bit combinations. These pins are not pulled up or down internally, so they must be externally connected to VCC or VSS.

2.2 Serial Data (SDA)

This is a bi directional pin used to transfer addresses and data into and data out of the device. It is an open- drain terminal, therefore, the SDA bus requires a pull- up resistor to VCC (typical 10 k for 100 kHz, 2 kfor 400 kHz and 1 MHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions.

2.3 Serial Clock (SCL)

This input is used to synchronize the data transfer from and to the device.

2.4 Write-Protect Input

When the WP pin is set high, then writes within the upper 1/4 of memory will not be allowed. Attempts to write in that protected region over the I2C bus will return an ACK (Acknowledge) for the WRITE instruction and address byte portions of the command , and w ill also return an ACK (Acknowledge) for the data portion of the command , despite the fact that no data will be written. See Table 4-1. The WP pin has no effect on random or sequential read operations. If left floating, this pin is internally pulled low. Name 8-Lead SOIC 8-Lead TDFN(1) Function VCAP 1 1 External Capacitor A1 2 2 Chip Select Input A2 3 3 Chip Select Input Vss 4 4 Ground SDA 5 5 Serial Data SCL 6 6 Serial Clock WP 7 7 Write Protect Vcc 8 8 2.7V to 3.6V Note 1: The exposed pad on the TDFN package can be connected to VSS or left floating.

 2019-2020 Microchip Technology Inc. Preliminary DS20006168B-page 7 47L64

3.0 MEMORY ORGANIZATION

3.1 Data Array Organization

The 47L64 is internally organized as a continuous SRAM array for both reading and writing, along with a nonvolatile EEPROM version that is not directly accessible to the user, but which can be refreshed or recalled on power cycles.

3.2 STORE/RECALL OPERATIONS

In order to provide nonvolatile storage of the SRAM data, an EEPROM array is included on the 47L64. During normal operation, the EEPROM array is not directly accessible to the user. Instead, the 47L64 preserves the SRAM data by automatically performing store and recall operations on power-down and power- up, respectively.

3.2.1 AUTOSTORE

To simplify device usage, the 47L64 features an AutoStore mechanism. To enable this feature, the user must place a capacitor on the VCAP pin. The capacitor is charged through the VCC pin. When the 47L64 detects a power-down event, the device automatically switches to the capacitor for power and initiates the AutoStore operation. To avoid extraneous store operations, the AutoStore will only be initiated if the SRAM array has been modified since the last Store or Recall operation. The AutoStore is initiated when VCAP falls below VTRIP. Even if power is restored, the 47L64 cannot be accessed for TSTORE time and T RESTORE after the AutoStore is initiated.

3.2.2 AUTORECALL

The 47L64 devices features an AutoRecall mechanism that is performed on power-up. This feature ensures that the SRAM data duplicates the EEPROM data on power-up. The AutoRecall is initiated when VCAP rises above VTRIP, and the 47L64 cannot be accessed for TRESTORE time after the AutoRecall is initiated.

3.2.3 POLLING ROUTINE

Since the device will not acknowledge during store and recall operations, checking for the Acknowledge signal can be used to determine when those events are complete. Once such an event has started, Acknowledge polling can be initiated immediately. This involves the master sending a Start condition, followed by the write control byte (R/W = 0) for the SRAM array. If the device is still busy, then no Acknowledge will be returned. In this case, the Start condition and control byte must be resent. If the Store or Recall are complete, then the device will return an Acknowledge, and the master can then proceed with the next read or write command. See Figure 3-1 for flow diagram. FIGURE 3-1: POLLING FLOW Note: If power is restored during an AutoStore operation, the AutoStore will continue and then the AutoRecall will be performed. Note 1: If power is lost during an AutoRecall operation, the AutoRecall is aborted and the AutoStore is not performed. 2: AutoRecall is performed every time VCAP rises above VTRIP. Send Start Initiate SRAM Write Event Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? Next Operation NO YES

 2019-2020 Microchip Technology Inc. Preliminary DS20006168B-page 8 47L64 FIGURE 3-2: AUTOSTORE/AUTORECALL SCENARIOS (WITH ARRAY MODIFIED) TSTORE VCC AutoStore AutoRecall Device Access Enabled Array Modified VTRIP VCAP TRESTORE CHARGE_CAP(1) Note 1: When CHARGE_CAP is a ‘ 0’, VCC is connected to VCAP, allowing VCC to charge the external capacitor. See Section 3.2.5 “Power Switchover” for details. TSTORE VCC AutoStore AutoRecall Device Access Enabled Array Modified VTRIP VCAP CHARGE_CAP(1) VPOR VPOR VTRIP VCAP TSTORE AutoStore AutoRecall Device Access Enabled Array Modified TRESTORE VCC CHARGE_CAP(1) VPOR TRESTORE TRESTORE

 2019-2020 Microchip Technology Inc. Preliminary DS20006168B-page 9 47L64 FIGURE 3-3: AUTOSTORE/AUTORECALL SCENARIOS (WITH ARRAY NOT MODIFIED)

3.2.4 TRIP VOLTAGE

The 47L64 has an internal voltage reference that is used to create a trip voltage threshold ( VTRIP). When VCAP rises above VTRIP, a power-up event is detected. If this is the first power-up event after a POR, then an AutoRecall operation is initiated. When VCAP falls below VTRIP, a power-down event is detected and an AutoStore operation is initiated if the array has been modified.

3.2.5 POWER SWITCHOVER

To support the AutoStore feature, the 47L64 must be able to charge the capacitor connected to the VCAP pin when power is available on VCC, and also automatically switch to being powered from the VCAP pin when power is removed from VCC. Since the VCAP pin is used as part of the internal power bus, this means that VCC must be disconnected when power is removed. To accomplish this, the 47L64 has an intelligent power switchover circuit that continuously monitors the voltages on both VCC and VCAP. During a power-up event, VCC is initially disconnected, allowing it to rise above VCAP. Once VCC is above VCAP, VCAP is connected to the VCC, charging the external capacitor. When VCAP reaches VTRIP, the AutoRecall operation is triggered. During a power-down event, VCC is initially connected to the internal power bus. As Vcc falls, it discharges the external cap, causing VCAP to also fall. Once VCAP falls below VTRIP, the AutoStore operation is triggered, and VCC is disconnected to prevent discharging the capacitor further through VCC. VTRIP VCAP VTRIP VCAP AutoStore AutoRecall Device Access Enabled Array Modified AutoStore AutoRecall Device Access Enabled Array Modified TRESTORE VCC CHARGE_CAP(1) VCC CHARGE_CAP(1) Note 1: When CHARGE_CAP is a ‘0’, VCC is connected to VCAP, allowing VCC to charge the external capacitor. See Section 3.2.5 “Power Switchover” for details. VPOR VPOR Note: When VCAP is below VTRIP, the 47L64 cannot be accessed and will not acknowledge any commands.

 2019-2020 Microchip Technology Inc. Preliminary DS20006168B-page 10 47L64 Once VCC is disconnected, it will not be reconnected until both VCC is greater than VCAP and any internal store cycles (AutoStore) is complete. This guards against continuously connecting and disconnecting VCC when VCAP falls faster than VCC.

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4.0 FUNCTIONAL DESCRIPTION

4.0.1 PRINCIPLES OF OPERATION

The 47L64 is a 64-Kbit serial EERAM designed to support a bi directional two-wire bus and data transmission protocol (I 2C). A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the Start and Stop conditions, while the 47L64 works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is active.

4.1 BUS CHARACTERISTICS

4.1.1 SERIAL INTERFACE

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus is not busy.
• During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 4-1).

4.1.1.1 Bus Not Busy (A)

Both data and clock lines remain high.

4.1.1.2 Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock (SCL) is high d etermines a Start condition. All com - mands must be preceded by a Start condition.

4.1.1.3 Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All opera - tions must end with a Stop condition.

4.1.1.4 Data Valid (D)

The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device.

4.1.1.5 Acknowledge

Each receiving device, when addressed, is obliged to generate an Acknowledge signal after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the Acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (47L64) will leave the data line high to enable the master to generate the Stop condition. The 47L64 will generate an Acknowledge bit on receiving a correct control byte and following address and data bytes. Table 4-1 summarizes these situations. The device will not generate Acknowledge bits for any bytes following if the control byte is incorrect, such as when the address bits do not match the A1, A2 pins, see Section 4.2 “Device Addressing”. FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS ADDRESS OR ACKNOWLEDGE VALID DATA ALLOWED TO CHANGE STOP CONDITION START CONDITION SCL SDA (A) (B) (D) (D) (C) (A)

 2019-2020 Microchip Technology Inc. Preliminary DS20006168B-page 12 47L64 FIGURE 4-2: ACKNOWLEDGE TIMING TABLE 4-1: ACKNOWLEDGE TABLE FOR SRAM WRITES Instruction ACK Address MSB ACK Address LSB ACK Data Byte ACK SRAM Write in Unprotected Block ACK Address ACK Address ACK Data ACK SRAM Write in Protected Block ACK Address ACK Address ACK Data ACK SCL 987654321 1 2 3 Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data. Receiver must release the SDA line at this point so the Transmitter can continue sending data. Data from transmitter Data from transmitterSDA Acknowledge Bit

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4.2 DEVICE ADDRESSING

The control byte is the first byte received following the Start condition from the master device (Figure 4-3). The control byte begins with a 4-bit op code. The next two bits are the user-configurable chip select bits, A 2 and A1. The next bit is a non-configurable chip select bit that must always be set to ‘ 1’. The chip select bits A2 and A 1 in the control byte must match the logic levels on the corresponding A2 and A1 pins for the device to respond. The last bit of the control byte defines the operation to be performed. When set to a ‘ 1’ a read operation is selected, and when set to a ‘ 0’ a write operation is selected. The combination of the 4-bit op code and the three chip select bits is called the slave address. Upon receiving a valid slave address, the slave device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/ W bit, the 47L64 will select a read or a write operation. FIGURE 4-3: CONTROL BYTE FORMAT The 47L64 is divided into two functional units: the SRAM array and the Control registers. Section 4.3 “SRAM Array ” describes the functionality for the SRAM array. The 4-bit op code in the control byte determines which unit will be accessed during an operation. Table 4-2 shows the standard control bytes used by the 47L64. TABLE 4-2: CONTROL BYTES Note: When VCAP is below VTRIP, the 47L64 cannot be accessed and will not acknowledge any commands. 1 0 1 0 A2 A1 1S ACKR/W Op Code Chip Select Bits Slave Address Acknowledge Bit Start Bit Read/Write Bit Operation Op Code Chip Select R/W Bit SRAM Read 1010 A2 A1 1 1 SRAM Write 1010 A2 A1 1 0

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4.3 SRAM ARRAY

The SRAM array is the only user-accessible memory panel available on the 47L64. The EEPROM array, which can only be directly accessed through test mode operations, provides nonvolatile storage to back up the SRAM data. To select the SRAM array, the master device must use the respective 4-bit op code, ‘1010’, when transmitting the control byte.

4.3.1 WRITE OPERATION

When the SRAM array is selected and the R/ W bit in the control byte is set to ‘ 0’, a write operation is selected and the next two bytes received are interpreted as the array address. The Most Significant address bits are transferred first, followed by the Least Significant bits, and are shifted directly into the internal Address Pointer. The Address Pointer determines where in the SRAM array the next read or write operation begins. Data is stored into the SRAM array as soon as it is received, specifically on the rising edge of SCL during each Acknowledge bit. If a write operation is aborted for any reason, all received data will already be stored in SRAM, except for the last data byte if the rising edge of SCL during the Acknowledge for that byte has not yet been reached.

4.3.1.1 Byte Write

After the 47L64 has received the 2-byte array address, responding with an Acknowledge after each address byte, the master device will transmit the data byte to be written into the addressed memory location. The 47L64 acknowledges again and the master generates a Stop condition (Figure 4-4). The data byte is latched into the SRAM array on the rising edge of SCL during the Acknowledge. After a byte write command, the internal Address Pointer will point to the address location following the location that was just written.

4.3.1.2 Sequential Write

To write multiple data bytes in a single operation, the SRAM write control byte, array address, and the first data byte are transmitted to the 47L64 in the same way as for a byte write. However, instead of generating a Stop condition, the master transmits additional data bytes ( Figure 4-5). Upon receipt of each byte, the 47L64 responds with an Acknowledge, during which the data is latched into the SRAM array on the rising edge of SCL, and the Address Pointer is incremented by one. Sequential write operations are limited to the address 0x1FFF, and if the master should transmit enough bytes further, the Address Pointer will roll over to 0x0000 and continue writing. There is no limit to the number of bytes that can be written in a single command. In the event that the WP pin is set high, writes to addresses in the upper 1/4 portion of the array will not be allowed. Attempts to write in that region will receive an ACK response from the device for the address bytes, but will receive a NACK for data bytes written (see Table 4-1). Note: If an AutoStore is triggered during an SRAM read or write operation, the operation is aborted in order to execute the Store. Note: If an attempt is made to write to a pro - tected portion of the array, the device will not respond with an Acknowledge after the data byte is received, the cur - rent operation will be terminated without incrementing the Address Pointer, and any data transmitted on the SDA line will be ignored until a new operation is begun with a Start condition.

 2019-2020 Microchip Technology Inc. Preliminary DS20006168B-page 16 47L64

4.3.2 READ OPERATION

When the SRAM array is selected and the R/ W bit is set to ‘ 1’, a read operation is selected. For read operations, the array address is not transmitted, instead, the internal Address Pointer is used to determine where the read starts. During read operations, the master device generates the Acknowledge bit after each data byte, and it is this bit which determines whether the operation will continue or end. A ‘ 0’ (Acknowledge) bit requests more data and continues the read, while a ‘ 1’ (No Acknowledge) bit ends the read operation.

4.3.2.1 Current Address Read

The current address read operation relies on the current value of the Address Pointer to determine from where to start reading. The Address Pointer is automatically incremented after each data byte is read or written. Therefore, if the previous access was to address n (where n is any legal address), the next current address read operation would access data beginning with address n+1. Upon receipt of the control byte with the R/W bit set to ‘1’, the 47L64 issues an Acknowledge and transmits the 8-bit data byte. The master will not acknowledge the transfer, but does generate a Stop condition and the 47L64 discontinues transmission (Figure 4-6). FIGURE 4-6: SRAM CURRENT ADDRESS READ

4.3.2.2 Random Read

Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the Address Pointer must be set. This is done by sending the array address to the 47L64 as part of a write operation (R/ W bit set to ‘0’). After the array address is sent, the master generates a Start condition following the Acknowledge. This terminates the write operation, but not before the Address Pointer has been set. Then, the master issues the SRAM control byte again but with the R/W bit set to a ‘1’. The 47L64 will then issue an Acknowledge and transmit the 8-bit data byte. The master will not Acknowledge the transfer but does generate a Stop condition, which causes the 47L64 to discontinue transmission ( Figure 4-7). After a random read operation, the Address Pointer will point to the address location following the one that was just read.

4.3.2.3 Sequential Read

Sequential reads are initiated in the same way as a random read except that after the 47L64 transmits the first data byte, the master issues an Acknowledge as opposed to the Stop condition used in a random read. The Acknowledge directs the 47L64 to transmit the next sequentially addressed 8-bit byte (Figure 4-8). Following the final byte transmitted to the master, the master will NOT generate an Acknowledge but will generate a Stop condition. To provide sequential reads, the 47L64 increments the internal Address Pointer by one after the transfer of each data byte. This allows the entire memory contents to be serially read during one operation. The Address Pointer will automatically roll over at the end of the array to address 0x0000 after the last data byte in the array has been transferred. FIGURE 4-7: SRAM RANDOM READ BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY PS S T O P CONTROL BYTE S T A R T DATA A C K N O A C K 1 10 0 A A 1 BYTE 2 1 1 BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY A C K N O A C K A C K A C K A C K S T O P S T A R T CONTROL BYTE ADDRESS HIGH BYTE ADDRESS LOW BYTE CONTROL BYTE DATA BYTE S T A R T S 1 0 1 0 A A 02 1 S 1 0 1 0 A A 12 1 P1 X X X 1 X = Don’t Care

 2019-2020 Microchip Technology Inc. Preliminary DS20006168B-page 17 47L64 FIGURE 4-8: SRAM SEQUENTIAL READ BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY CONTROL BYTE DATA n DATA n + 1 DATA n + 2 DATA n + X N O A C K A C K A C K A C K A C K S T O P P

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5.0 PACKAGING INFORMATION

5.1 Package Marking Information

8-Lead SOIC (3.90 mm) Example XXXXXXXX XXXXYYWW NNN 47L64 SN 1849 13F 8-Lead 2x3 TDFN XXX YWW NN EK4 849 Example 1st Line Marking Part No. SOIC TDFN 47L64 47L64 EK4 Legend: XX...X Part number or part number code Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code (2 characters for small packages) JEDEC® designator for Matte Tin (Sn)3e

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0.25 C A–B D

C SEATING PLANE TOP VIEW SIDE VIEW VIEW A–A 0.10 C 0.10 C Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] 1 2 N h h A2A A B e D E E 2E1 NOTE 5 NOTE 5 NX b

0.10 C A–B

H 0.23 (L1) L R0.13 R0.13 VIEW C SEE VIEW C NOTE 1 D

 2019-2020 Microchip Technology Inc. Preliminary DS20006168B-page 20 47L64 Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Foot Angle 0° - 8° 15°-5°Mold Draft Angle Bottom 15°-5°Mold Draft Angle Top 0.51-0.31bLead Width 0.25-0.17cLead Thickness 1.27-0.40LFoot Length 0.50-0.25hChamfer (Optional)

4.90 BSCDOverall Length

3.90 BSCE1Molded Package Width

6.00 BSCEOverall Width

0.25-0.10A1Standoff --1.25A2Molded Package Thickness 1.75-- AOverall Height

1.27 BSCePitch

protrusions shall not exceed 0.15mm per side. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 4. Dimensioning and tolerancing per ASME Y14.5M Notes: Footprint L1 1.04 REF 5. Datums A & B to be determined at Datum H.

 2019-2020 Microchip Technology Inc. Preliminary DS20006168B-page 21 47L64 RECOMMENDED LAND PATTERN Microchip Technology Drawing C04-2057-SN Rev E 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M1. For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Dimension Limits Units CContact Pad Spacing Contact Pitch MILLIMETERS

1.27 BSC

E MAX 5.40 Contact Pad Length (X8) Contact Pad Width (X8) 1.55 0.60 NOM E C SILK SCREEN

 2019-2020 Microchip Technology Inc. Preliminary DS20006168B-page 22 47L64 BA 0.15 C 0.15 C

0.10 C A B

0.05 C (DATUM B) (DATUM A) C SEATING PLANE NOTE 1 N TOP VIEW SIDE VIEW BOTTOM VIEW NOTE 1 N 0.10 C 0.08 C Microchip Technology Drawing No. C04-129-MN Rev E Sheet 1 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN] D E A (A3) e 8X b L K With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)

 2019-2020 Microchip Technology Inc. Preliminary DS20006168B-page 23 47L64 Microchip Technology Drawing No. C04-129-MN Rev E Sheet 2 of 2 8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: NOM MILLIMETERS

0.50 BSC

2.00 BSC

3.00 BSC

0.20 REF

1. Pin 1 visual index feature may vary, but must be located within the hatched area. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Contact-to-Exposed Pad Contact Thickness Exposed Pad Width Exposed Pad Length 4. Dimensioning and tolerancing per ASME Y14.5M 3. Package is saw singulated 2. Package may have one or more exposed tie bars at ends. Notes: Contact Width Overall Width Overall Length Contact Length Standoff Number of Pins Overall Height Pitch K 0.20 Units N e A Dimension Limits D b E L 0.20 1.35 1.25 0.25 0.00 0.70 MIN 0.25 0.30 1.30 1.40 1.35 0.30 0.45 1.45 0.75 0.02 0.05 0.80 MAX With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)

 2019-2020 Microchip Technology Inc. Preliminary DS20006168B-page 24 47L64 RECOMMENDED LAND PATTERN Dimension Limits Units Optional Center Pad Width Optional Center Pad Length Contact Pitch 1.50 1.60 MILLIMETERS E MAX Contact Pad Length (X8) Contact Pad Width (X8) 0.85 0.25 Microchip Technology Drawing No. C04-129-MN Rev. B NOM 8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN] CContact Pad Spacing 2.90 Thermal Via Diameter V Thermal Via Pitch EV 0.30 1.00 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: C E EV EV ØV SILK SCREEN With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)

 2019-2020 Microchip Technology Inc. Preliminary DS20006168B-page 25 47L64 APPENDIX A: REVISION HISTORY Revision B (01/2020) Updated V CAP Capacitor values and Section 2.4 Write-Protect Input; Updated Section 4.1.1.5. Revision A (03/2019) Initial release of the document.

 2019-2020 Microchip Technology Inc. Preliminary DS20006168B-page 26 47L64 THE MICROCHIP WEBSITE Microchip provides online support via our website at www.microchip.com. This website is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the website contains the following information:

• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip website at www.microchip.com . Under “Support”, click on “Customer Change Notification” and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the website at: http://microchip.com/support

 2019-2020 Microchip Technology Inc. Preliminary DS20006168B-page 27 47L64 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX PatternPackageTemperature Range Device Device: 47L64 = 64 Kbit I2C EERAM Tape and Reel Option: Blank = Standard packaging (tube or tray) T = Tape and Reel(1) Temperature Range: I = -40C to +85C (Industrial) Package: SN = Plastic Small Outline - Narrow, 3.90 mm Body, 8-lead (SOIC) MNY = Plastic Dual Flat, No Lead Package - 2x3x0.8 mm Body, 8-lead (TDFN) Examples: a) 47L64T-I/SN = Tape and Reel, Industrial temp., SOIC package, b) 47L64-I/SN = Industrial temp., SOIC package c) 47L64T-I/MNY = Tape and Reel, Industrial temp., TDFN package Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. X Tape and Reel Option

 2019-2020 Microchip Technology Inc. Preliminary DS20006168B-page 28 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2019-2020, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-5518-9 Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.

 2019-2020 Microchip Technology Inc. Preliminary DS20006168B-page 29 AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Austin, TX Tel: 512-257-3370 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Tel: 317-536-2380 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Tel: 951-273-7800 Raleigh, NC Tel: 919-844-7510 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Tel: 408-436-4270 Canada - Toronto Tel: 905-695-1980 Fax: 905-695-2078 ASIA/PACIFIC Australia - Sydney Tel: 61-2-9868-6733 China - Beijing Tel: 86-10-8569-7000 China - Chengdu Tel: 86-28-8665-5511 China - Chongqing Tel: 86-23-8980-9588 China - Dongguan Tel: 86-769-8702-9880 China - Guangzhou Tel: 86-20-8755-8029 China - Hangzhou Tel: 86-571-8792-8115 China - Hong Kong SAR Tel: 852-2943-5100 China - Nanjing Tel: 86-25-8473-2460 China - Qingdao Tel: 86-532-8502-7355 China - Shanghai Tel: 86-21-3326-8000 China - Shenyang Tel: 86-24-2334-2829 China - Shenzhen Tel: 86-755-8864-2200 China - Suzhou Tel: 86-186-6233-1526 China - Wuhan Tel: 86-27-5980-5300 China - Xian Tel: 86-29-8833-7252 China - Xiamen Tel: 86-592-2388138 China - Zhuhai Tel: 86-756-3210040 ASIA/PACIFIC India - Bangalore Tel: 91-80-3090-4444 India - New Delhi Tel: 91-11-4160-8631 India - Pune Tel: 91-20-4121-0141 Japan - Osaka Tel: 81-6-6152-7160 Japan - Tokyo Tel: 81-3-6880- 3770 Korea - Daegu Tel: 82-53-744-4301 Korea - Seoul Tel: 82-2-554-7200 Malaysia - Kuala Lumpur Tel: 60-3-7651-7906 Malaysia - Penang Tel: 60-4-227-8870 Philippines - Manila Tel: 63-2-634-9065 Singapore Tel: 65-6334-8870 Taiwan - Hsin Chu Tel: 886-3-577-8366 Taiwan - Kaohsiung Tel: 886-7-213-7830 Taiwan - Taipei Tel: 886-2-2508-8600 Thailand - Bangkok Tel: 66-2-694-1351 Vietnam - Ho Chi Minh Tel: 84-28-5448-2100 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 Finland - Espoo Tel: 358-9-4520-820 France - Paris Germany - Garching Tel: 49-8931-9700 Germany - Haan Tel: 49-2129-3766400 Germany - Heilbronn Tel: 49-7131-72400 Germany - Karlsruhe Tel: 49-721-625370 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Germany - Rosenheim Tel: 49-8031-354-560 Israel - Ra’anana Tel: 972-9-744-7705 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Italy - Padova Tel: 39-049-7625286 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Norway - Trondheim Tel: 47-7288-4388 Poland - Warsaw Tel: 48-22-3325737 Romania - Bucharest Tel: 40-21-407-87-50 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Gothenberg Tel: 46-31-704-60-40 Sweden - Stockholm Tel: 46-8-5090-4654 UK - Wokingham Tel: 44-118-921-5800 Fax: 44-118-921-5820 Worldwide Sales and Service 05/14/19