47L16T-I

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Document overview

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Technical content

Features

• 4 Kbit/16 Kbit SRAM with EEPROM Backup: - Internally organized as 512 x 8 bits (47X04) or 2,048 x 8 bits (47X16) - Automatic Store to EEPROM array upon power-down (using optional external capacitor) - Automatic Recall to SRAM array upon power-up - Hardware Store pin for manual Store operations - Software commands for initiating Store and Recall operations - Store time 8 ms maximum (47X04) or 25 ms maximum (47X16)
• Nonvolatile External Event Detect Flag
• High Reliability: - Infinite read and write cycles to SRAM - More than one million store cycles to EEPROM - Data retention: >200 years - ESD protection: >4,000V
• High-Speed I 2C Interface: - Industry standard 100 kHz, 400 kHz and 1M H z - Zero cycle delay reads and writes - Schmitt Trigger inputs for noise suppression - Cascadable up to four devices
• Write Protection: - Software write protection from 1/64 of SRAM array to whole array
• Low-Power CMOS Technology: - 200 µA active current typical - 40 µA standby current (maximum)
• 8-Lead PDIP , SOIC, and TSSOP Packages
• Available Temperature Ranges:

Description

The Microchip Technology Inc. 47L04/47C04/47L16/47C16 (47XXX) is a 4/16 Kbit SRAM with EEPROM backup. The device is organized as 512 x 8 bits or 2,048 x 8 bits of memory, and utilizes the I 2C serial interface. The 47XXX provides infinite read and write cycles to the SRAM while EEPROM cells provide high-endurance nonvolatile storage of data. With an external capacitor, SRAM data is automatically transferred to the EEPROM upon loss of power. Data can also be transferred manually by using either the Hardware Store pin or software control. Upon power-up, the EEPROM data is automatically recalled to the SRAM. Recall can also be initiated through software control. The 47XXX is available in the 8-lead PDIP , SOIC, and TSSOP packages. Block Diagram Part Number Density (bits) VCC Range Max. Clock Frequency Temperature Ranges Packages 47L04 4K 2.7-3.6V 1 MHz I, E P , SN, ST 47C04 4K 4.5-5.5V 1 MHz I, E P , SN, ST 47L16 16K 2.7-3.6V 1 MHz I, E P , SN, ST 47C16 16K 4.5-5.5V 1 MHz I, E P , SN, ST - Industrial (I): -40°C to +85°C - Automotive (E): -40°C to +125°C Power I2C Control Logic Memory Address and Data Control Logic Slave Address VCC Control BlockVCAP Decoder EEPROM 512 x 8 RECALL STORE SDA SCL A2, A1 HS 2K x 8 SRAM 512 x 8 Status Register 2K x 8 4K/16K I2C Serial EERAM

DS20005371C-page 2  2015-2016 Microchip Technology Inc. Typical Application Schematic Auto Store Mode (ASE = 1) Typical Application Schematic Manual Store Mode (ASE = 0) Package Types VCC VCC SCL SDA HS V SS VCC PIC® MCU 47XXX VCAP VCC CVCAP VCC VCC SCL SDA HS V SS VCC PIC® MCU 47XXX VCAP VCC VCAP VSS VCC HS SCL SDA PDIP/SOIC/TSSOP (8-pin)

 2015-2016 Microchip Technology Inc. DS20005371C-page 3 47L04/47C04/47L16/47C16

1.0 ELECTRICAL CHARACTERISTICS

1.1 Absolute Maximum Ratings (†)

† NOTICE: Stresses above those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS 47LXX: V CC = 2.7V to 3.6V 47CXX: V CC = 4.5V to 5.5V Industrial (I): T A = -40°C to +85°C Automotive (E): T A = -40°C to +125°C Param. No. Symbol Characteristic Min. Typ. Max. Units Conditions D1 V IH High-Level Input Voltage 0.7 VCC —V CC+1 V D2 V IL Low-Level Input Voltage -0.3 — 0.3 VCC V D3 V OL Low-Level Output Voltage — — 0.4 V I OL = 3.0 mA D4 V HYS Hysteresis of Schmitt Trigger Inputs (SDA, SCL pins) 0.05VCC —— V Note 1 D5 I LI Input Leakage Current (SDA, SCL pins) —— ± 1 µ A V IN = VSS or VCC D6 I LO Output Leakage Current (SDA pin) —— ± 1 µ A V OUT = VSS or VCC D7 R IN Input Resistance to VSS (A1, A2, HS pins) 50 — — k Ω VIN = VIL (max.) 750 — — k Ω VIN = VIH (min.) D8 C INT Internal Capacitance (all inputs and outputs) ——7p F T A = +25°C, FREQ = 1 MHz, VCC = 5.5V (Note 1) D9 I CC Active Operating Current — 200 400 µA V CC = 5.5V, FCLK = 1 MHz — 150 300 µA V CC = 3.6V, FCLK = 1 MHZ D10 I CC Recall Recall Current ( Note 2) — — 700 µA V CC = 5.5V — 300 500 µA V CC = 3.6V D11 I CC Store Manual Store Current (Note 2) — — 2000 µA V CC = 5.5V — — 1000 µA V CC = 3.6V D12 I CC Auto-Store Auto-Store Current (Notes 1, 2 and 3) — 400 — µA V CC, VCAP = VTRIP (min.) 47CXX — 300 — µA V CC, VCAP = VTRIP (min.) 47LXX Note 1: This parameter is periodically sampled and not 100% tested. 2: Store and Recall currents are specified as an average current across the entire operation. 3: CVCAP required when Auto-Store is enabled (ASE = 1).

DS20005371C-page 4  2015-2016 Microchip Technology Inc. D13 I CC Status Write Status Write Current — — 1000 µA V CC = 5.5V —— 8 0 0 µ A V CC = 3.6V D14 I CCS Standby Current — — 40 µA SCL, SDA, V CAP, VCC =5 . 5 V — — 40 µA SCL, SDA, V CAP, VCC =3 . 6 V D15 V TRIP Auto-Store/Auto-Recall Trip Voltage 4.0 — 4.4 V 47CXX 2.4 — 2.6 V 47LXX D16 V POR Power-On Reset Voltage — 1.1 — V D17 C B Bus Capacitance — — 400 pF D18 C VCAP Auto-Store Capacitance (Notes 1 and 3) 3.5 4.7 — µF 47C04 56 . 8 — µ F 4 7 C 1 6 5 6.8 — µF 47L04 8 10 — µF 47L16 TABLE 1-1: DC CHARACTERISTICS (CONTINUED) DC CHARACTERISTICS 47LXX: V CC = 2.7V to 3.6V 47CXX: V CC = 4.5V to 5.5V Industrial (I): T A = -40°C to +85°C Automotive (E): T A = -40°C to +125°C Param. No. Symbol Characteristic Min. Typ. Max. Units Conditions Note 1: This parameter is periodically sampled and not 100% tested. 2: Store and Recall currents are specified as an average current across the entire operation. 3: CVCAP required when Auto-Store is enabled (ASE = 1).

 2015-2016 Microchip Technology Inc. DS20005371C-page 5 47L04/47C04/47L16/47C16 TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS 47LXX: V CC = 2.7V to 3.6V 47CXX: V CC = 4.5V to 5.5V Industrial (I): T AMB = -40°C to +85°C Automotive (E): T AMB = -40°C to +125°C Param. No. Symbol Characteristic Min. Max. Units Conditions 1F CLK Clock Frequency — 1000 kHz 2T HIGH Clock High Time 500 — ns 3T LOW Clock Low Time 500 — ns 4T R SDA and SCL Input Rise Time — 300 ns Note 1 5T F SDA and SCL Input Fall Time — 300 ns Note 1 6T HD:STA Start Condition Hold Time 250 — ns 7T SU:STA Start Condition Setup Time 250 — ns 8T HD:DAT Data Input Hold Time 0 — ns 9T SU:DAT Data Input Setup Time 100 — ns

10 T SU:STO Stop Condition Setup

250 — ns

11 T AA Output Valid from Clock — 400 ns

12 T BUF Bus Free Time: Bus time

500 — ns

13 T SP Input Filter Spike

Suppression (SDA, SCL and HS pins) —5 0 n s Note 1

14 T HSPW Hardware Store Pulse

150 — ns

15 T RECALL Recall Operation Duration — 5 ms 47X16

—2 m s 4 7 X 0 4

16 T STORE Store Operation Duration — 25 ms 47X16

—8 m s 4 7 X 0 4

17 T WC STATUS Register Write

—1 m s

18 T VRISE VCC Rise Rate 70 — µs/V Note 1

19 Tv FALL VCC Fall Rate 70 — µs/V Note 1

20 EEPROM Endurance 1,000,000 — Store

+25°C, VCC = 5.5V (Notes 1 and 2) Note 1: This parameter is not tested but ensured by characterization. 2: For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on Microchip’s website at www.microchip.com.

 2015-2016 Microchip Technology Inc. DS20005371C-page 7 47L04/47C04/47L16/47C16 FIGURE 1-4: HARDWARE STORE TIMING DATA (WITH AM = 0) Device Access Enabled STATUS Register HS Pin Write Cycle

DS20005371C-page 8  2015-2016 Microchip Technology Inc.

2.0 FUNCTIONAL DESCRIPTION

2.0.1 PRINCIPLES OF OPERATION

The 47XXX is a 4/16 Kbit serial EERAM designed to support a bidirectional two-wire bus and data transmission protocol (I 2C). A device that sends data onto the bus is defined as transmitter, and a device receiving data is defined as receiver. The bus has to be controlled by a master device which generates the Start and Stop conditions, while the 47XXX works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is active.

2.1 Bus Characteristics

2.1.1 SERIAL INTERFACE

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus is not busy.
• During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 2-1).

2.1.1.1 Bus Not Busy (A)

Both data and clock lines remain high.

2.1.1.2 Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition.

2.1.1.3 Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must end with a Stop condition.

2.1.1.4 Data Valid (D)

The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop con- ditions is determined by the master device.

2.1.1.5 Acknowledge

Each receiving device, when addressed, is obliged to generate an Acknowledge signal after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. A device that Acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the Acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (47XXX) will leave the data line high to enable the master to generate the Stop Condition. There are situations where the 47XXX will NOT generate an Acknowledge bit in order to signal that an error has occurred. Table 2-1 and Table 2-2 summarize these situations. FIGURE 2-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS Address or Acknowledge Valid Data Allowed to Change Stop Condition Start Condition SCL SDA (A) (B) (D) (D) (C) (A)

 2015-2016 Microchip Technology Inc. DS20005371C-page 9 47L04/47C04/47L16/47C16 FIGURE 2-2: ACKNOWLEDGE TIMING TABLE 2-1: ACKNOWLEDGE TABLE FOR SRAM WRITES Instruction ACK Address MSB ACK Address LSB ACK Data Byte ACK SRAM Write in Unprotected Block ACK Address ACK Address ACK Data ACK SRAM Write in Protected Block ACK Address ACK Address ACK Data NoACK TABLE 2-2: ACKNOWLEDGE TABLE FOR CONTROL REGISTER WRITES Instruction ACK Address ACK Data Byte ACK STATUS Register Write ACK 00h ACK Data ACK Software Store Command ACK 55h ACK 33h ACK Software Recall Command ACK 55h ACK DDh ACK Write Invalid Value to COMMAND Register ACK 55h ACK Invalid Command NoACK Write to Invalid Register Address ACK Invalid Address NoACK Don’t Care NoACK SCL 9876543211 2 3 Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data. Receiver must release the SDA line at this point so the Transmitter can continue sending data. Data from transmitter Data from transmitterSDA Acknowledge Bit

DS20005371C-page 10  2015-2016 Microchip Technology Inc.

2.2 Device Addressing

The control byte is the first byte received following the Start condition from the master device ( Figure 2-3). The control byte begins with a 4-bit operation code. The next two bits are the user-configurable Chip Select bits: A2 and A1. The next bit is a non-configu- rable Chip Select bit that must always be set to ‘ 0’. The Chip Select bits A2 and A1 in the control byte must match the logic levels on the corresponding A2 and A1 pins for the device to respond. The last bit of the control byte defines the operation to be performed. When set to a ‘ 1’ a read operation is selected, and when set to a ‘ 0’ a write operation is selected. The combination of the 4-bit operation code and the three Chip Select bits is called the slave address. Upon receiving a valid slave address, the slave device outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 47XXX will select a read or a write operation. FIGURE 2-3: CONT ROL BYTE FORMAT The 47XXX is divided into two functional units: the SRAM array and the Control registers. Section 2.3 “SRAM Array” describes the functionality for the SRAM array and Section 2.4 “Control Registers” describes the Control registers. The 4-bit op code in the control byte determines which unit will be accessed during an operation. Table 2-3 shows the standard control bytes used by the 47XXX. Note: When VCAP is below V TRIP, the 47XXX cannot be accessed and will not acknowledge any commands.

1010 A2 A1 0SA C K R/W

0011 A2 A1 0SA C K R/W

TABLE 2-3: CONTROL BYTES Operation Op Code Chip Select R/W Bit SRAM Read 1010 A2 A1 01 SRAM Write 1010 A2 A1 00 Control Register Read 0011 A2 A1 01 Control Register Write 0011 A2 A1 00

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2.3 SRAM Array

The SRAM array is the only directly-accessible memory on the 47XXX. The EEPROM array provides nonvolatile storage to back up the SRAM data. To select the SRAM array, the master device must use the respective 4-bit op code ‘1010’ when transmitting the control byte.

2.3.1 WRITE OPERATION

When the SRAM array is selected and the R/W bit in the control byte is set to ‘ 0’, a write operation is selected and the next two bytes received are interpreted as the array address. The Most Significant address bits are transferred first, followed by the less significant bits, and are shifted directly into the internal Address Pointer. The Address Pointer determines where in the SRAM array the next read or write operation begins. Data bytes are stored into the SRAM array as soon as each byte is received, specifically on the rising edge of SCL during each Acknowledge bit. If a write operation is aborted for any reason, all received data will already be stored in SRAM, except for the last data byte if the rising edge of SCL during the Acknowledge for that byte has not yet been reached.

2.3.1.1 Byte Write

After the 47XXX has received the 2-byte array address, responding with an Acknowledge after each address byte, the master device will transmit the data byte to be written into the addressed memory location. The 47XXX acknowledges again, and the master generates a Stop condition (Figure 2-4). The data byte is latched into the SRAM array on the rising edge of SCL during the Acknowledge. After a byte Write command, the internal Address Pointer will point to the address location following the location that was just written.

2.3.1.2 Sequential Write

To write multiple data bytes in a single operation, the SRAM write control byte, array address, and the first data byte are transmitted to the 47XXX in the same way as for a byte write. However, instead of generating a Stop condition, the master transmits additional data bytes ( Figure 2-5). Upon receipt of each byte, the 47XXX responds with an Acknowledge: during which the data is latched into the SRAM array on the rising edge of SCL, and the Address Pointer is incremented by one. Sequential write operations are limited only by the size of the SRAM array, and if the master should transmit enough bytes to reach the end of the array, the Address Pointer will roll over to 0x000 and continue writing. There is no limit to the number of bytes that can be written in a single command. FIGURE 2-4: SRAM BYTE WRITE Note: If an Auto-Store or Hardware Store is triggered during an SRAM read or write operation, the operation is aborted in order to execute the Store. Note: If an attempt is made to write to a pro- tected portion of the array, the device will not respond with an Acknowledge after the data byte is received, the cur- rent operation will be terminated without incrementing the Address Pointer, and any data transmitted on the SDA line will be ignored until a new operation is begun with a Start condition. Note: If a sequential write crosses into a pro- tected block, the device will not respond with an Acknowledge after the data byte is received, the current operation will be terminated without incrementing the Address Pointer, and any data transmit- ted on the SDA line will be ignored until a new operation is begun with a Start condition. Bus Activity Master SDA Line Bus Activity S T A R T Control Byte Address High Byte Address Low Byte Data S T O P A C K A C K A C K A C K S 1010 0 A A 1 P0 X = Don’t Care Y = Don’t Care for 47X04 Data Latched into SRAM XXXXXYY

DS20005371C-page 12  2015-2016 Microchip Technology Inc. FIGURE 2-5: SRAM SEQUENTIAL WRITE Bus Activity Master SDA Line Bus Activity S T A R T Control Byte Address High Byte Address Low Byte Data Byte 0 S T O P A C K A C K A C K A C K Data Byte N A C K S 1010 0A A 1 0 PXXXXXYY X = Don’t Care Y = Don’t Care for 47X04 Data Latched into SRAM

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2.3.2 READ OPERATION

When the SRAM array is selected and the R/W bit is set to ‘1’, a read operation is selected. For read opera- tions, the array address is not transmitted. Instead, the internal Address Pointer is used to determine where the read starts. During read operations, the master device generates the Acknowledge bit after each data byte, and it is this bit which determines whether the operation will con- tinue or end. A ‘ 0’ (Acknowledge) bit requests more data and continues the read, while a ‘1’ (No Acknowl- edge) bit ends the read operation.

2.3.2.1 Current Address Read

The current address read operation relies on the current value of the Address Pointer to determine from where to start reading. The Address Pointer is automatically incremented after each data byte is read or written. Therefore, if the previous access was to address ‘n’ (where ‘n’ is any legal address), the next current address read operation would access data beginning with address ‘n+1’. Upon receipt of the control byte with the R/W bit set to ‘1’, the 47XXX issues an Acknowledge and transmits the 8-bit data byte. The master will not acknowledge the transfer, but does generate a Stop condition and the 47XXX discontinues transmission (Figure 2-6). FIGURE 2-6: SRAM CURRENT ADDRESS READ

2.3.2.2 Random Read

Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the Address Pointer must be set. This is done by sending the array address to the 47XXX as part of a write operation (R/W bit set to ‘0’). After the array address is sent, the master generates a Start condition following the Acknowledge. This terminates the write operation, but not before the Address Pointer has been set. Then, the master issues the SRAM control byte again, but with the R/W bit set to a ‘1’. The 47XXX will then issue an Acknowledge and transmit the 8-bit data byte. The master will not Acknowledge the transfer but does generate a Stop condition, which causes the 47XXX to discontinue transmission ( Figure 2-7). After a random read operation, the Address Pointer will point to the address location following the one that was just read.

2.3.2.3 Sequential Read

Sequential reads are initiated in the same way as a random read, except that after the 47XXX transmits the first data byte, the master issues an Acknowledge as opposed to the Stop condition used in a random read. The Acknowledge directs the 47XXX to transmit the next sequentially addressed 8-bit byte (Figure 2-8). Following the final byte transmitted to the master, the master will NOT generate an Acknowledge but will generate a Stop condition. To provide sequen- tial reads, the 47XXX increments the internal Address Pointer by one after the transfer of each data byte. This allows the entire memory contents to be serially read during one operation. The Address Pointer will automatically roll over at the end of the array to address 0x000 after the last data byte in the array has been transferred. FIGURE 2-7: SRAM RANDOM READ Bus Activity Master SDA Line Bus Activity PS S T O P Control Byte S T A R T Data A C K N O A C K

1100 AA 1

A C K N O A C K A C K A C K A C K S T O P S T A R T Control Byte Address High Byte Address Low Byte Control Byte Data Byte S T A R T S 1010 AA 021 S 1010 AA 121 P

0 XXXXX 0YY

X = Don’t Care Y = Don’t Care for 47X04

DS20005371C-page 14  2015-2016 Microchip Technology Inc. FIGURE 2-8: SRAM SEQUENTIAL READ Bus Activity Master SDA Line Bus Activity Control Byte DATA n DATA n + 1 DATA n + 2 DATA n + X N O A C K A C K A C K A C K A C K S T O P P

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2.4 Control Registers

To support device configuration features such as software write protection, as well as software-controllable Store and Recall operations, the 47XXX features a set of Control registers that are accessed using a different 4-bit op code than the op code for the SRAM array (refer to Table 2-3 for op code values). Table 2-4 lists the available Control registers. The STATUS register allows the user to configure the 47XXX. The COMMAND register is used to execute special Software commands.

2.4.1 STATUS REGISTER

The STATUS register controls the software write protection, enables/disables the Auto-Store function, reports whether or not the array has been modified since the last Store or Recall operation, and contains the Hardware Store event flag. There are several bits contained within the STATUS register:

• T h e AM bit indicates whether or not the SRAM array has been written to since the last Store or Recall operation. When set to a ‘ 0’, the SRAM array matches the data in the EEPROM array. When set to a ‘ 1’, the SRAM array no longer matches the EEPROM array. The AM bit is set whenever a data byte is written to the SRAM, and is cleared after a Store or Recall operation is completed. The AM bit must be a ‘1’ to enable the Auto-Store and Hardware Store functions. However, the Software Store command is always enabled. The AM bit is volatile and is read-only.
• T h e BP bits control the SRAM array software write protection. Table 2-5 lists the address ranges that can be protected for each device. The BP bits are nonvolatile.
• T h e ASE bit determines whether or not the Auto-Store function is enabled. When set to a ‘1’, the Auto-Store function is enabled and will exe- cute automatically on power-down if the array has been modified. When set to a ‘ 0’, the Auto-Store function is disabled. The ASE bit is nonvolatile.
• T h e EVENT bit indicates whether or not an exter- nal event has been detected on the HS pin. When the HS pin is driven high, a STATUS register write operation is automatically initiated following the Hardware Store operation to set this bit to a ‘ 1’. This bit can also be set and cleared through a STATUS register Write command. The EVENT bit is nonvolatile. To store the nonvolatile bits in the STATUS register, a write cycle occurs after a STATUS register write operation, during which the 47XXX cannot be accessed for T WC time after the Stop condition. Note: If an Auto-Store or Hardware Store is triggered during a Control register read or write operation, the operation is aborted in order to execute the Store. Note: The COMMAND register is write-only. TABLE 2-4: CONTROL REGISTERS Register Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STATUS 00h AM — — BP2 BP1 BP0 ASE EVENT COMMAND 55h CMD7 CMD6 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 Note: If a capacitor is not connected to the VCAP pin, then the V CAP pin must be connected to V CC and the Auto-Store feature must be disabled by writing the ASE bit to a ‘0’ to prevent data corrup- tion in the EEPROM array when power is lost. Note: The HS pin is ignored when V CAP is below V TRIP, and during Store and Recall operations. In these cases, the EVENT bit will not be written. Note: During a STATUS register write cycle, an Auto-Store or Hardware Store can still be triggered, but the Store operation will not execute until the STATUS register write cycle is complete ( Figure 2-13). In this situation, the new value of the ASE bit will be used to determine if the Auto-Store is executed.

DS20005371C-page 16  2015-2016 Microchip Technology Inc. TABLE 2-5: PROTECTED ARRAY ADDRESS LOCATIONS Protected Range BP2 BP1 BP0 47X04 47X16 None 000 —— Upper 1/64 001 1F8h-1FFh 7E0h-7FFh Upper 1/32 010 1F0h-1FFh 7C0h-7FFh Upper 1/16 011 1E0h-1FFh 780h-7FFh Upper 1/8 100 1C0h-1FFh 700h-7FFh Upper 1/4 101 180h-1FFh 600h-7FFh Upper 1/2 110 100h-1FFh 400h-7FFh All Blocks 111 000h-1FFh 000h-7FFh REGISTER 2-1: STATUS REGISTER R-0 U-0 U-0 R/W R/W R/W R/W R/W AM — — BP2 BP1 BP0 ASE EVENT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 AM: Array Modified bit 1 = SRAM array has been modified 0 = SRAM array has not been modified bit 6-5 Unimplemented: Read as ‘0’ bit 4-2 BP<2:0>: Block Protect bits 000 = Entire array is unprotected 001 = Upper 1/64 of array is write-protected 010 = Upper 1/32 of array is write-protected 011 = Upper 1/16 of array is write-protected 100 = Upper 1/8 of array is write-protected 101 = Upper 1/4 of array is write-protected 110 = Upper 1/2 of array is write-protected 111 = Entire array is write-protected bit 1 ASE: Auto-Store Enable bit 1 = Auto-Store feature is enabled 0 = Auto-Store feature is disabled bit 0 EVENT: Event Detect bit 1 = An event was detected on the HS pin 0 = No event was detected on the HS pin

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2.4.2 COMMAND REGISTER

The COMMAND register is a write-only register that allows the user to execute software-controlled Store and Recall operations. There are two commands that can be executed, as shown in Table 2-6:

• The Software Store command initiates a manual Store operation. The 47XXX cannot be accessed for T STORE time after this command has been received. During this time, the 47XXX will not acknowledge any communication. The Software Store command will execute regardless of the state of the AM and ASE bits in the STATUS register. The AM bit will be cleared at the end of the Store operation.
• The Software Recall command initiates a manual Recall operation. The 47XXX cannot be accessed for T RECALL time after this command has been received. During this time, the 47XXX will not acknowledge any communication. The AM bit will be cleared at the end of the Recall operation. Note: If a capacitor is not connected to the VCAP pin, then the V CAP pin must be connected to V CC and the user must ensure that power is not lost during a Store operation, otherwise data corrup- tion may occur. TABLE 2-6: COMMAND SET Command Value Description Software Store 0011 0011 Store SRAM data to EEPROM Software Recall 1101 1101 Recall data from EEPROM to SRAM REGISTER 2-2: COMMAND REGISTER WW W W W WW W CMD7 CMD6 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 CMD<7:0>: Command bits 00110011 = Executes a Software Store command 11011101 = Executes a Software Recall command

DS20005371C-page 18  2015-2016 Microchip Technology Inc.

2.4.3 CONTROL REGISTER WRITE

When the Control registers are selected and the R/W bit in the control byte is set to ‘ 0’, a write operation is selected and the next byte received is interpreted as the register address. The Most Significant address bits are transferred first, followed by the less significant bits. The register address is decoded as soon as it is received and has no effect on future operations. The register address must be a valid Control register address listed in Table 2-4, otherwise the 47XXX will not acknowledge the address, the current operation will be terminated, and any data transmitted on the SDA line will be ignored until a new operation is begun with a Start condition. After receiving the Acknowledge signal from the 47XXX following the register address, the master will transmit the data byte to be written to the addressed register. If the data byte is valid, the 47XXX acknowledges again and the master generates a Stop condition. For a STATUS register write operation, any data byte value is valid. However, for COMMAND register write operations, only the commands listed in Table 2-6 are valid. If a different command value is received, the 47XXX will not acknowledge the command, the current operation will be terminated, and any data transmitted on the SDA line will be ignored until a new operation is begun with a Start condition. FIGURE 2-9: CONTRO L REGISTER WRITE

2.4.4 CONTROL REGISTER READ

When the Control registers are selected and the R/W bit in the control byte is set to ‘ 1’, a read operation is selected. For read operations, the register address is not transmitted. Since the COMMAND register is write-only, all Control register read operations access the STATUS register. During read operations, the master device generates the Acknowledge bit after each data byte, and it is this bit which determines whether the operation will con- tinue or end. A ‘ 0’ (Acknowledge) bit requests more data and continues the read, while a ‘1’ (No Acknowl- edge) bit ends the read operation. Upon receipt of the control byte with the R/W bit set to ‘1’, the 47XXX issues an Acknowledge and transmits the 8-bit STATUS register value. The master will not acknowledge the transfer, but does generate a Stop condition and the 47XXX discontinues transmission (Figure 2-10). FIGURE 2-10: CONTROL REGISTER READ Note 1: When writing to the COMMAND register, the master must send exactly one data byte. If additional data bytes are sent, then the 47XXX will not acknowledge the data bytes and will abort the operation. 2: Multiple data bytes are allowed when writing to the STATUS register. The last data byte received will be written. Bus Activity Master SDA Line Bus Activity S T A R T Control Byte Address Byte Data S T O P A C K A C K A C K S 0011 0 A A 1 P0 TWC(1) TSTORE(1) TRECALL(1) Note 1: After the Stop condition, a delay must be observed for the command to execute: T WC for STATUS register writes, TSTORE for Software Store commands, and TRECALL for Software Recall commands. Note: If the master acknowledges the data byte, the 47XXX will retransmit the 8-bit STATUS register value. Bus Activity Master SDA Line Bus Activity PS S T O P Control Byte S T A R T Register A C K N O A C K

0101 AA 1

 2015-2016 Microchip Technology Inc. DS20005371C-page 19 47L04/47C04/47L16/47C16

2.5 STORE/RECALL OPERATIONS

In order to provide nonvolatile storage of the SRAM data, an EEPROM array is included on the 47XXX. The EEPROM array is not directly accessible to the user. Instead, data is written to and read from the EEPROM array using the various Store and Recall operations, respectively. To provide design flexibility for the user, the 47XXX can automatically perform Store and Recall operations on power-down and power-up, respectively, and also offers Software commands and a Hardware Store pin for manual control. Refer to Section 2.4.2 “Command Register” for details of the Software Store and Software Recall commands.

2.5.1 AUTO-STORE

To simplify device usage, the 47XXX features an Auto-Store mechanism. To enable this feature, the user must place a capacitor on the V CAP pin and ensure the ASE bit in the STATUS register is set to ‘ 1’. The capacitor is charged through the V CC pin. When the 47XXX detects a power-down event, the device automatically switches to the capacitor for power and initiates the Auto-Store operation. The Auto-Store is initiated when V CAP falls below VTRIP. Even if power is restored, the 47XXX cannot be accessed for TSTORE time after the Auto-Store is initi- ated. To avoid extraneous Store operations, the Auto-Store will only be initiated if the AM bit in the STATUS register is set to a ‘ 1’, indicating the SRAM array has been modified since the last Store or Recall operation. The AM bit in the STATUS register is cleared at the completion of the Auto-Store operation.

2.5.2 HARDWARE STORE

The HS pin provides a method for manually initiating a Store operation through an external trigger. Driving the HS pin high for a minimum of THSPW time will initiate a Hardware Store operation if the AM bit in the STATUS register is a ‘1’. Driving the HS pin high will also automatically initiate a STATUS register write cycle to write the EVENT bit to a ‘1’, regardless of the state of the AM bit. If the AM bit is a ‘1’, the Hardware Store is initiated on the rising edge of the HS pin, and then the 47XXX cannot be accessed for (T STORE + TWC) time. If the AM bit is a ‘0’, only the EVENT bit write is initiated on the rising edge of the HS pin, and then the 47XXX cannot be accessed for T WC time while the STATUS register is written. The AM bit in the STATUS register is cleared at the completion of the Hardware Store operation.

2.5.3 AUTO-RECALL

The 47XXX features an Auto-Recall mechanism that is performed on power-up, regardless of the state of the ASE bit. This feature ensures that the SRAM data duplicates the EEPROM data on power-up. The Auto-Recall is only initiated the first time V CAP rises above VTRIP after a POR event, and the 47XXX can- not be accessed for TRECALL time after the Auto-Recall is initiated. The AM bit in the STATUS register is cleared at the completion of the Auto-Recall operation. Note: Once a Store operation is initiated, it cannot be aborted. Note 1: The HS pin is ignored during Store and Recall operations, or if V CAP is below VTRIP. 2: The HS pin is triggered on the rising edge. If the HS pin remains high after the Hardware Store and STATUS register write are complete, the device can still be accessed normally just as if the HS pin were low. Initiating a subsequent Hard- ware Store operation requires toggling HS low then high again. Note 1: If power is lost during an Auto-Recall operation, the Auto-Recall is aborted and the Auto-Store is not performed. 2: Auto-Recall is only performed the first time V CAP rises above VTRIP after a POR event. However, SRAM data will be retained as long as Vcc remains above V POR. TABLE 2-7: STORE ENABLE TRUTH TABLE ASE Bit AM Bit Auto-Store Enabled Hardware Store Enabled Software Store Enabled Auto-Recall Enabled Software Recall Enabled x 0 No No Yes Yes Yes

01 No Yes Yes Yes Yes

11 Yes Yes Yes Yes Yes

DS20005371C-page 20  2015-2016 Microchip Technology Inc. FIGURE 2-11: AUTO-STORE/AUTO-RECALL SCENARIOS (WITH ASE = 1, AM = 1) TSTORE VCC Auto-Store Auto-Recall Device Access Enabled Array Modified VTRIP VCAP TRECALL Bit TSTORE VCC Auto-Store Auto-Recall Device Access Enabled Array Modified VTRIP VCAP Bit VPOR VPOR VTRIP VCAP TSTORE Auto-Store Auto-Recall Device Access Enabled Array Modified TRECALL VCC Bit VPOR

 2015-2016 Microchip Technology Inc. DS20005371C-page 21 47L04/47C04/47L16/47C16 FIGURE 2-12: AUTO-STORE/AUTO-RE CALL SCENARIOS (WITH ASE = 0 OR AM = 0) VTRIP VCAP VTRIP VCAP Auto-Store Auto-Recall Device Access Enabled Array Modified Bit Auto-Store Auto-Recall Device Access Enabled Array Modified Bit TRECALL VCC VCC VPOR VPOR

DS20005371C-page 22  2015-2016 Microchip Technology Inc. FIGURE 2-13: STORE DURING STATUS REGIST ER WRITE CYCLE SCENARIOS (WITH AM = 1) Note 1: Store operation will only execute if ASE bit = 1. 2: The second STATUS register write cycle is performed to set the EVENT bit to a ‘1’. TSTORE HS Hardware Store Device Access Enabled Array Modified Bit TWC STATUS Register Write Cycle TSTORE(1) VCC Auto-Store Auto-Recall Device Access Enabled Array Modified VTRIP VCAP Bit TWC STATUS Register Write Cycle TWC(2) VPOR

 2015-2016 Microchip Technology Inc. DS20005371C-page 23 47L04/47C04/47L16/47C16 FIGURE 2-14: STORE DURING STATUS REGIST ER WRITE CYCLE SCENARIOS (WITH AM = 0) HS Hardware Store Device Access Enabled Array Modified Bit TWC STATUS Register Write Cycle TWC(1) VCC Auto-Store Auto-Recall Device Access Enabled Array Modified VTRIP VCAP Bit TWC STATUS Register Write Cycle Note 1: The second STATUS register write cycle is performed to set the EVENT bit to a ‘1’. VPOR

DS20005371C-page 24  2015-2016 Microchip Technology Inc.

2.6 ACKNOWLEDGE POLLING

Since the device will not acknowledge during Store and Recall operations, nor during the internal STATUS register write cycles, checking for the Acknowledge signal can be used to determine when those events are complete. Once such an event has started, Acknowledge polling can be initiated immediately. This involves the master sending a Start condition, followed by the write control byte (R/W = 0) for either the SRAM array or the Control registers. If the device is still busy, then no Acknowledge will be returned. In this case, then the Start condition and control byte must be resent. If the Store or Recall is complete, then the device will return an Acknowledge, and the master can then proceed with the next Read or Write command. See Figure 2-15 for flow diagram. FIGURE 2-15: ACKNOWLEDGE POLLING FLOW Send Start Initiate Store, Recall, or STATUS Register Write Event Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? Next Operation NO YES Note: Either the SRAM or Control register control byte can be used for Acknowl- edge Polling

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3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

3.1 Pin Descriptions

3.1.1 CAPACITOR INPUT (V CAP)

The VCAP pin is connected to the internal power bus of the 47XXX. If the Auto-Store feature is used, a C VCAP capacitor must be connected to the V CAP pin in order to store the energy required to complete the Auto-Store operation on power-down. The capacitor is automatically charged through V CC. See Table 1-1 for recommended CVCAP values. If a capacitor is not connected to the V CAP pin, then the VCAP pin must be connected to the V CC pin and the Auto-Store feature must be disabled by writing the ASE bit in the STATUS register to a ‘0’ to prevent data corruption in the EEPROM array when power is lost.

3.1.2 CHIP ADDRESS INPUTS (A1, A2)

The A1, A2 inputs are used by the 47XXX for multiple device operation. The levels on these inputs are compared with the corresponding Chip Select bits in the slave address. The chip is selected if the comparison is true. Up to four devices may be connected to the same bus by using different Chip Select bit combinations. If left unconnected, these inputs will be pulled down internally to V SS.

3.1.3 SERIAL DATA (SDA)

This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open-drain terminal, therefore, the SDA bus requires a pull-up resistor to V CC (typical 10 kΩ for 100 kHz, 2 kΩ for 400 kHz and 1 MHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions.

3.1.4 SERIAL CLOCK (SCL)

This input is used to synchronize the data transfer from and to the device.

3.1.5 HARDWARE STORE/EVENT

DETECT (HS) This pin is used to initiate a Hardware Store operation by driving the pin high for T HSPW time. This will also trigger a STATUS register write cycle to write the EVENT bit to a ‘1’. This pin is ignored during Store and Recall operations, or if VCAP is below VTRIP. If the AM bit in the STATUS register is set to a ‘0’, the Hardware Store will not be initiated, but the EVENT bit will still be written to a ‘1’. If left unconnected, this input will be pulled down internally to VSS.

3.2 Input Pull-down Circuitry

The A1, A2, and HS pins are internally pulled down to VSS using dual-strength pull-down circuits. Figure 3-1 shows the block diagram of the circuit. The circuit is designed to have a relatively strong pull-down strength when the input voltage is below VIL, and a much weaker pull-down when the input is above VIH. See Table 1-1 for actual resistance values. FIGURE 3-1: PULL-DOWN CIRCUIT BLOCK DIAGRAM TABLE 3-1: PIN FUNCTION TABLE Name 8-pin PDIP SOIC TSSOP Function VCAP 1 Capacitor Input A1 2 Chip Select Input A2 3 Chip Select Input V SS 4 Ground SDA 5 Serial Data SCL 6 Serial Clock HS 7 Hardware Store/ Event Detect Input V CC 8 Power Supply I/O PIN

DS20005371C-page 26  2015-2016 Microchip Technology Inc.

4.0 PACKAGING INFORMATION

4.1 Package Marking Information

Legend: XX...X Customer-specific information YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code JEDEC ® designator for Matte Tin (Sn) * This package is RoHS compliant. The JEDEC® designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 8-Lead PDIP (300 mil) Example 8-Lead SOIC (3.90 mm) Example 8-Lead TSSOP Example Part Number 1st Line Marking Codes PDIP SOIC TSSOP 47L04 47L04 47L04 AAAQ 47C04 47C04 47C04 AAAR 47L16 47L16 47L16 AAAS 47C16 47C16 47C16 AAAT 47C04 P 017 1621 47L16 SN 16213e 017 AAAT 1621 017

 2015-2016 Microchip Technology Inc. DS20005371C-page 27 47L04/47C04/47L16/47C16 B A For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Microchip Technology Drawing No. C04-018D Sheet 1 of 2 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] eB E A L 8X b 8X b1 D c C PLANE .010 C N NOTE 1 TOP VIEW END VIEWSIDE VIEW e

DS20005371C-page 28  2015-2016 Microchip Technology Inc. Microchip Technology Drawing No. C04-018D Sheet 2 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A - - .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing eB - - .430 BSC: Basic Dimension. Theoretically exact value shown without tolerances. protrusions shall not exceed .010" per side. Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or Pin 1 visual index feature may vary, but must be located within the hatched area. § Significant Characteristic Dimensioning and tolerancing per ASME Y14.5M e DATUM A DATUM A e b e b e ALTERNATE LEAD DESIGN (VENDOR DEPENDENT)

 2015-2016 Microchip Technology Inc. DS20005371C-page 29 47L04/47C04/47L16/47C16 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

DS20005371C-page 30  2015-2016 Microchip Technology Inc. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

 2015-2016 Microchip Technology Inc. DS20005371C-page 31 47L04/47C04/47L16/47C16 /g27/g16/g47/g72/g68/g71/g3/g51/g79/g68/g86/g87/g76/g70/g3/g54/g80/g68/g79/g79/g3/g50/g88/g87/g79/g76/g81/g72/g3/g11/g54/g49/g12/g3/g177/g3/g49/g68/g85/g85/g82/g90/g15/g3/g22/g17/g28/g19/g3/g80/g80/g3/g37/g82/g71/g92/g3/g62/g54/g50/g44/g38/g64 /g49/g82/g87/g72/g29/g41/g82/g85/g3/g87/g75/g72/g3/g80/g82/g86/g87/g3/g70/g88/g85/g85/g72/g81/g87/g3/g83/g68/g70/g78/g68/g74/g72/g3/g71/g85/g68/g90/g76/g81/g74/g86/g15/g3/g83/g79/g72/g68/g86/g72/g3/g86/g72/g72/g3/g87/g75/g72/g3/g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g51/g68/g70/g78/g68/g74/g76/g81/g74/g3/g54/g83/g72/g70/g76/g73/g76/g70/g68/g87/g76/g82/g81/g3/g79/g82/g70/g68/g87/g72/g71/g3/g68/g87/g3 /g75/g87/g87/g83/g29/g18/g18/g90/g90/g90/g17/g80/g76/g70/g85/g82/g70/g75/g76/g83/g17/g70/g82/g80/g18/g83/g68/g70/g78/g68/g74/g76/g81/g74

DS20005371C-page 32  2015-2016 Microchip Technology Inc. /g27/g16/g47/g72/g68/g71/g3/g51/g79/g68/g86/g87/g76/g70/g3/g55/g75/g76/g81/g3/g54/g75/g85/g76/g81/g78/g3/g54/g80/g68/g79/g79/g3/g50/g88/g87/g79/g76/g81/g72/g3/g11/g54/g55/g12/g3/g177/g3/g23/g17/g23/g3/g80/g80/g3/g37/g82/g71/g92/g3/g62/g55/g54/g54/g50/g51/g64 /g49/g82/g87/g72/g86/g29 /g20/g17 /g51/g76/g81/g3/g20/g3/g89/g76/g86/g88/g68/g79/g3/g76/g81/g71/g72/g91/g3/g73/g72/g68/g87/g88/g85/g72/g3/g80/g68/g92/g3/g89/g68/g85/g92/g15/g3/g69/g88/g87/g3/g80/g88/g86/g87/g3/g69/g72/g3/g79/g82/g70/g68/g87/g72/g71/g3/g90/g76/g87/g75/g76/g81/g3/g87/g75/g72/g3/g75/g68/g87/g70/g75/g72/g71/g3/g68/g85/g72/g68/g17 /g21/g17 /g39/g76/g80/g72/g81/g86/g76/g82/g81/g86/g3/g39/g3/g68/g81/g71/g3/g40/g20/g3/g71/g82/g3/g81/g82/g87/g3/g76/g81/g70/g79/g88/g71/g72/g3/g80/g82/g79/g71/g3/g73/g79/g68/g86/g75/g3/g82/g85/g3/g83/g85/g82/g87/g85/g88/g86/g76/g82/g81/g86/g17/g3/g48/g82/g79/g71/g3/g73/g79/g68/g86/g75/g3/g82/g85/g3/g83/g85/g82/g87/g85/g88/g86/g76/g82/g81/g86/g3/g86/g75/g68/g79/g79/g3/g81/g82/g87/g3/g72/g91/g70/g72/g72/g71/g3/g19/g17/g20/g24/g3/g80/g80/g3/g83/g72/g85/g3/g86/g76/g71/g72/g17 /g22/g17 /g39/g76/g80/g72/g81/g86/g76/g82/g81/g76/g81/g74/g3/g68/g81/g71/g3/g87/g82/g79/g72/g85/g68/g81/g70/g76/g81/g74/g3/g83/g72/g85/g3/g36/g54/g48/g40/g3/g60/g20/g23/g17/g24/g48/g17 /g37/g54/g38/g29 /g37/g68/g86/g76/g70/g3/g39/g76/g80/g72/g81/g86/g76/g82/g81/g17/g3/g55/g75/g72/g82/g85/g72/g87/g76/g70/g68/g79/g79/g92/g3/g72/g91/g68/g70/g87/g3/g89/g68/g79/g88/g72/g3/g86/g75/g82/g90/g81/g3/g90/g76/g87/g75/g82/g88/g87/g3/g87/g82/g79/g72/g85/g68/g81/g70/g72/g86/g17 /g53/g40/g41/g29 /g53/g72/g73/g72/g85/g72/g81/g70/g72/g3/g39/g76/g80/g72/g81/g86/g76/g82/g81/g15/g3/g88/g86/g88/g68/g79/g79/g92/g3/g90/g76/g87/g75/g82/g88/g87/g3/g87/g82/g79/g72/g85/g68/g81/g70/g72/g15/g3/g73/g82/g85/g3/g76/g81/g73/g82/g85/g80/g68/g87/g76/g82/g81/g3/g83/g88/g85/g83/g82/g86/g72/g86/g3/g82/g81/g79/g92/g17 /g49/g82/g87/g72/g29/g41/g82/g85/g3/g87/g75/g72/g3/g80/g82/g86/g87/g3/g70/g88/g85/g85/g72/g81/g87/g3/g83/g68/g70/g78/g68/g74/g72/g3/g71/g85/g68/g90/g76/g81/g74/g86/g15/g3/g83/g79/g72/g68/g86/g72/g3/g86/g72/g72/g3/g87/g75/g72/g3/g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g51/g68/g70/g78/g68/g74/g76/g81/g74/g3/g54/g83/g72/g70/g76/g73/g76/g70/g68/g87/g76/g82/g81/g3/g79/g82/g70/g68/g87/g72/g71/g3/g68/g87/g3 /g75/g87/g87/g83/g29/g18/g18/g90/g90/g90/g17/g80/g76/g70/g85/g82/g70/g75/g76/g83/g17/g70/g82/g80/g18/g83/g68/g70/g78/g68/g74/g76/g81/g74 /g56/g81/g76/g87/g86 /g48/g44/g47/g47/g44/g48/g40/g55/g40/g53/g54 /g39/g76/g80/g72/g81/g86/g76/g82/g81/g3/g47/g76/g80/g76/g87/g86 /g48/g44/g49 /g49/g50/g48 /g48/g36/g59 /g49/g88/g80/g69/g72/g85/g3/g82/g73/g3/g51/g76/g81/g86 /g49 /g27 /g51/g76/g87/g70/g75 /g72 /g19/g17/g25/g24/g3/g37/g54/g38 /g50/g89/g72/g85/g68/g79/g79/g3/g43/g72/g76/g74/g75/g87 /g36 /g177 /g177 /g20/g17/g21/g19 /g48/g82/g79/g71/g72/g71/g3/g51/g68/g70/g78/g68/g74/g72/g3/g55/g75/g76/g70/g78/g81/g72/g86/g86 /g36/g21 /g19/g17/g27/g19 /g20/g17/g19/g19 /g20/g17/g19/g24 /g54/g87/g68/g81/g71/g82/g73/g73/g3 /g36/g20 /g19/g17/g19/g24 /g177 /g19/g17/g20/g24 /g50/g89/g72/g85/g68/g79/g79/g3/g58/g76/g71/g87/g75 /g40 /g25/g17/g23/g19/g3/g37/g54/g38 /g48/g82/g79/g71/g72/g71/g3/g51/g68/g70/g78/g68/g74/g72/g3/g58/g76/g71/g87/g75 /g40/g20 /g23/g17/g22/g19 /g23/g17/g23/g19 /g23/g17/g24/g19 /g48/g82/g79/g71/g72/g71/g3/g51/g68/g70/g78/g68/g74/g72/g3/g47/g72/g81/g74/g87/g75 /g39 /g21/g17/g28/g19 /g22/g17/g19/g19 /g22/g17/g20/g19 /g41/g82/g82/g87/g3/g47/g72/g81/g74/g87/g75 /g47 /g19/g17/g23/g24 /g19/g17/g25/g19 /g19/g17/g26/g24 /g41/g82/g82/g87/g83/g85/g76/g81/g87 /g47/g20 /g20/g17/g19/g19/g3/g53/g40/g41 /g41/g82/g82/g87/g3/g36/g81/g74/g79/g72 /g73 /g19/g131 /g177 /g27/g131 /g47/g72/g68/g71/g3/g55/g75/g76/g70/g78/g81/g72/g86/g86 /g70 /g19/g17/g19/g28 /g177 /g19/g17/g21/g19 /g47/g72/g68/g71/g3/g58/g76/g71/g87/g75 /g69 /g19/g17/g20/g28 /g177 /g19/g17/g22/g19 D N E NOTE 1 b e c A L1 L φ /g48/g76/g70/g85/g82/g70/g75/g76/g83 /g55/g72/g70/g75/g81/g82/g79/g82/g74/g92 /g39/g85/g68/g90/g76/g81/g74 /g38/g19/g23/g16/g19/g27/g25/g37

 2015-2016 Microchip Technology Inc. DS20005371C-page 33 47L04/47C04/47L16/47C16 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

DS20005371C-page 34  2015-2016 Microchip Technology Inc. APPENDIX A: REVISION HISTORY Revision A (January 2015) Initial release of the document. Revision B (July 2016) Removed Advance Information status; Updated AC/DC Characteristics table; Minor typographical corrections. Revision C (October 2016) Updated AC/DC parameters with final limits.

 2015-2016 Microchip Technology Inc. DS20005371C-page 35 47L04/47C04/47L16/47C16 THE MICROCHIP WEBSITE Microchip provides online support via our website at www.microchip.com. This website is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the website contains the following information:

• Product Support – Data sheets and errata, appli- cation notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Micro- chip sales offices, distributors and factory repre- sentatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a spec- ified product family or development tool of interest. To register, access the Microchip website at www.microchip.com. Under “Support”, click on “Cus- tomer Change Notification” and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support Customers should contact their distributor, representa- tive or Field Application Engineer (FAE) for support. Local sales offices are also available to help custom- ers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the website at: http://www.microchip.com/support

DS20005371C-page 36  2015-2016 Microchip Technology Inc. NOTES:

 2015-2016 Microchip Technology Inc. DS20005371C-page 37 47L04/47C04/47L16/47C16 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device Device: 47L04: 4 Kbit, 3V SRAM with EEPROM backup 47C04: 4 Kbit, 5V SRAM with EEPROM backup 47L16: 16 Kbit, 3V SRAM with EEPROM backup 47C16: 16 Kbit, 5V SRAM with EEPROM backup Tape and Reel Option: Blank = Standard packaging (tube or tray) T = Tape & Reel Temperature Range: I= - 4 0 C to +85C E= - 4 0 C to +125C Package: P = Plastic DIP (300 mil body), 8-lead SN = Plastic SOIC (3.90 mm body), 8-lead ST = Plastic TSSOP (4.4 mm), 8-lead Examples: a) 47L04-E/P: 4 Kbit Extended Temperature, 3V, 8-LD PDIP package. b) 47L04-E/SN: 4 Kbit Extended Temperature, 3V, 8-LD SOIC package. c) 47L04-I/ST: 4 Kbit Industrial Temperature, 3V, 8-LD TSSOP package. d) 47L04T-E/SN: Tape and Reel, 4 Kbit Extended Temperature, 3V, 8-LD SOIC package. e) 47L04T-I/ST: Tape and Reel, 4 Kbit Industrial Temperature, 3V, 8-LD TSSOP package. a) 47C04-E/P: 4 Kbit Extended Temperature, 5V, 8-LD PDIP package. b) 47C04-E/SN: 4 Kbit Extended Temperature, 5V, 8-LD SOIC package. c) 47C04-I/ST: 4 Kbit Industrial Temperature, 5V, 8-LD TSSOP package. d) 47C04T-E/SN: Tape and Reel, 4 Kbit Extended Temperature, 5V, 8-LD SOIC package. e) 47C04T-I/ST: Tape and Reel, 4 Kbit Industrial Temperature, 5V, 8-LD TSSOP package. a) 47L16-E/P: 16 Kbit Extended Temperature, 3V 8-LD PDIP package. b) 47L16-E/SN: 16 Kbit Extended Temperature, 3V 8-LD SOIC package. c) 47L16-I/ST: 16 Kbit Industrial Temperature, 3V 8-LD TSSOP package. d) 47L16T-E/SN: Tape and Reel, 16 Kbit Extended Temperature, 3V 8-LD SOIC package. e) 47L16T-I/ST: Tape and Reel, 16 Kbit Industrial Temperature, 3V 8-LD TSSOP package. a) 47C16-E/P: 16 Kbit Extended Temperature, 5V, 8-LD PDIP package. b) 47C16-E/SN: 16 Kbit Extended Temperature, 5V, 8-LD SOIC package. c) 47C16-I/ST: 16 Kbit Industrial Temperature, 5V, 8-LD TSSOP package. d) 47C16T-E/SN: Tape and Reel, 16 Kbit Extended Temperature, 5V, 8-LD SOIC package. e) 47C16T-I/ST: Tape and Reel, 16 Kbit Industrial Temperature, 5V, 8-LD TSSOP package. /XX PackageTemp. Range X Tape & Reel X Option Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option.

DS20005371C-page 38  2015-2016 Microchip Technology Inc. NOTES:

 2015-2016 Microchip Technology Inc. DS20005371C-page 39 47L04/47C04/47L16/47C16 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY , PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2015-2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-1002-7 Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification cont ained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are co mmitted to continuously improvin g the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT S YSTEM CERTIFIED BY DNV == ISO/TS 16949 ==

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