47C634AN

TMP47C434 TOSHIBA | Alldatasheet

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CMOS 4-BIT MICROCONTROLLER TMP47C434N, TMP47C634N TMP47C434F, TMP47C634F The 47C434/634 are based on the TLCS-470 CMOS series. The 47C434/634 have on-screen display circuit to display characters and marks which indicate channel or time on TV screen, A/D converter input, and D/A converter output. TMP47C434F QFP44 | TMP47C634F QFPa4a FEATURES | @4-bit single chip microcomputer spipaz @instruction execution time : 1.95 (at 4.2 MHz) #92 basic instructions #Table look-up instructions Subroutine nesting : 15 levels max. a 6 interrupt sources (External : 2, Internal : 4) a aat All sources have independent latches each, and multiple a a interrupt control is available fog sit" 1/0 port (30 pins) age * Input 2 ports 5 pins TMPA7Ca34N * 10 Tports 25 pins TMPA7CE34N interval Timer @Two 12-bit Timer/Counters QFpaa Timer, event counter, and pulse width measurement mode Watchdog timer #Serial Interface with 8-bit buffer * Simultaneous transmission and reception capability * External/internal clock, leading/trailing edge shift, 4/8-bit a oy On-screen display circuit eg . Character patterns: 48 characters Ri * Charactersdisplayed: 16 columns x2 lines © Composition : 8 x 8 dots (smoothing function) Mearceaae * Size of character: 2 kinds (line by line) © Color of character 7 kinds (character by character) spices * Variable display position : horizontal / vertical 64 steps @D/A converter (Pulse width modulation) outputs * 14-bit resolution 1 channel © 6-bit resolution 4 channels we, 3-bit A/D converter input ya ee Auto frequency control signal (S-shaped curve) detection oe Po Horizontal synchronous signal is detected by timer/counter KAO Remote control signal preprocessing capability SZ @High current outputs aid LED direct drive capability (typ, 20mA x 4 bits) TMPA7CO34E @HOLD function : Battery/Capacitor back-up Real Time Emulator : BM47C834A 4-113

PIN ASSIGNMENT (TOP VIEW) = aie (1) soipaa (2) QrPaa EeEE. nao we) <> O1 42 [=< voo ase He 32283 —— eeele xx rose rai (Pwan) <> 2 41 1 <> r92 BCR) thd i] oom =o 40 b == s60 preiitiis ds aso Pwed) <> G5 38 “<> R83 (71) 33 32 31 30 29 28.27 26 25 24 23 asi «> (16 37 [] <> Rez (inti) — _ » bro > 36 1) <> narra 8371) a asa <> 8 35 fl <> RB0INF) —pgy(s0) = CIT 36 20 [os R70 (CIN) > 9 34 [] ~— HOLD (KES) R92(SCK) =~ C0437 19 —eeaeien —— NC coo438 1g Poo R(RAO) a7 (WTO) 10 33 ee coms vio ne a2 <> 1 32 P— xouT —gagewatdy + aEd]a0 16 FI vss n73 <> 12 31 DP <—xin Ray(ewani) > Co) 15 Poo R63 al es a R62 koo —> 13 30 [| <— test Ra2(PWAR) =~ FT 82 3 foe ae Ra3(PWMa) > C443 1 Kor —> G14 29 ]—> oscz Rso(pwmia) => Coons ° 12 FI R60 «x03 —> [16 27 <—vo aE ECELE BBO c0 cB sco <> G17 26 | <— FO UOUYCUCUDU er <> (18 25 D— ven rriggddrte nes <> (] 20 23 <> Giraty ° pS vss —> []21 22 1) <> Rirao) aa Forcus signa! output. RGB output (VO port) ny vo Y(BL) ry . e: one ics Yl Ear yo To TT | oS since oer] (Sense mput) (EO) (ROM) Timming generator Interval 12-bit abit ova i - mer Timer! converter Connecting |xOUT (2ch) interface output ha? | 3-bit AD rT D O O O O ia oon conten ft 8] ls) bs} y Gd R73 R63 Re3 (Tt) R92 (ck) RSS a3 (PWNS) KOs R7O(CIN) Reo (INT2) vOport Woport VOPort WO port (Serial port) VO port input port ( AND converter input ) ( TiC input ) (O/A converter output) rr ee ee EO 4-114

R43 (PWM3) en 4-bit /O port with latch 6-bit D/A converter (PWM) output “Rai (PWM) VO (output) When used as input port or D/A R40 (PWMO) converter outputs pins, the latch 14-bit D/A converter (PWM) output must be set to "1" R53 - R51 vo R50 (PWiid) 1/0 (output) 6-bit D/A converter (PWM) output 4-bit VO port with latch R63 - vo

63 R60 | wo | When used as input port, the latch must be set to “1”

• ua R73 = R72 ° 4-bit VO port with latch. | _ ‘When used as input port, watchdog . R71 (WTO) VO (output) timer output pin, or A/D converter | Werchdos timer output input pin, the latch must be set to R70 (CIN) V0 (input) as 3-bit A/D converter input R83 (T1) Timer/counter 1 external input aa 4-bit /O port with latch . R82 (INTT) When used as input port, external __ | External interrupt 1 input WO (input) interrupt input pin, or R81 (2) timericounter external input pin, _ | Timericounter 2 external input R80 (INT?) the latch must be set to “1 External interrupt 2 input R92 (SCK) vO (VO) Serial clock VO 3-bit I/O port with latch. R91 (SO) VO (output) When used as input port or serial Serial data output . port, the latch must be set to "1" R90 (SI) VO (input) Serial data input G (RAI) 2-bit /O port with latch Output (0) When used as input port, the latch must be R (RAO) RGB output setto "1"

8 Output

HD, VD Input Horizontal synchronous signai input, Vertical synchronous signal input OSC1, O5C2 input, output | Resonator connecting pin of on-screen display circuit xins, xour input, outpit Resonator connecting pin. For inputting external clock, XIN is used and XOUT is opened. RESET input Reset signal input HOLD (KEO) input (input) | HOLD requestrelease signalinput —_| Sense input TEST input Test pin for out-going test. Be opened or fixed to low level vDD +5V Power supply vss OV (GND) 780290 4-115

Concerning the 47C434/634, the configuration and functions of hardwares are described. As the description is provided with priority on those parts differing from the 47C660/860, the technical data sheets for the 47C660/860 shall also be referred to 1. SYSTEM CONFIGURATION (1) Program Memory (ROM) (2) Data Memory (RAM) (3) Operation clock changeover control (4) VO Ports (5) On-screen display (OSD) control circuit (6) A/D converter (comparator) input (7) D/A converter (Pulse Width Modulation) output | 2. INTERNAL CPU FUNCTION

2.1 Program Memory(ROM)

Programs are stored in address 0000 to 17FFy of 47C634 and in address 0000 to OFFFH of 47C434. By the ROM data reference instruction [LDH A,@DC +, LDL A,@DC}, the fixed data in address 1000} to 17FFH and 0000 to OFFFy can be loaded to the accumulator, respectively. Address Address 0000), 0000, Program and : Fixed Program Data OFFFy OFFFy, 1000}, Program and Fixed Data A7FF (a) 470434 (vb) 47¢634 Figure 2-1. Program Memory Note. With the 47C434, permanent data are stored at addresses 0000 - OFFFy but, when checking 47C434 operation using a piggy-back chip, it is necessary to store the permanent data to addresses 1000 ~ 1FFFy, either. cc 4-116

2.2 Data memory (RAM)

The 47634 contains 256 x4 bits data memory bank 0 (DMBO) and 128x4 bits data memory bank 1 (DMB1). The 47C434 contains 256 x 4 bits data memory (DMBO). The bank is controlled by DMB. Address Address 00% 004 Fry, a FEY 00). OMBI 7Fu (a) 47C434 RAM Configuration (b) 47C634 RAM Configuration Figure 2-2. Data Memory (RAM)

2.3 Operation clock changeover control

On the 47C434/634 only single clock mode is available. As single clock mode is automatically selected at the initilization, there is no necessary to set system clock control command register (OP 16). Single-clock mode _ FGF yyy High-freq : Oscillating [ Normal-1 command Normal-2_\\ High-freq : Oscillating lLow-freq : Stopped operation mode} LZ \\operation mode} Low-freq : Oscillating worimand V7 Reset YU Reset yy yi i Don't select Rising edge | |command operation command g command of FOL pin Conny y, input £ Reset WY, G Reset > Ys High-freq : Oscillating Y YY High-freq : Stopped HOLD Low-freq : Stopped UY SLOW High-freq ; Stopped Low-freq : Stopped operation mode ) loperation mode] Low-freq : Oscillating 7 yy Yy UL. Li} Figure 2-3. Operation Made Transition Diagram 780290 4117

a 3. PERIPHERAL HARDWARE FUNCTION 3.1 /O ports The 47C434/634 have 9 I/O ports (30 pins) each as follows. ad KO 3 4-bit input (2 R4,R5 ; 4-bit input/output (shared with pulse width modulation output)

3 RE ; 4-bitinput/output

@ R7 : 4-bit input/output (shared with comparator input and watchdog timer output) ®& RB ; 4-bit input/output (shared with external interrupt input and timer/counter input) © rg ; 3-bit input/output (shared with serial port) @ RA ; 2-bit input/output (shared with on-screen display output) ®) KE ; 1-bit sense input (shared with hold request / release signal input) This section describes ports of @ and @,which are changed from the 47C660/860, and it describes port of @, which item of on-screen display circuit. Table 3-1 lists the port address assigments and the I/O instructions that can access the ports. (1) Port R4(R43-R40) This is a 4-bit I/O port with latch. It is a port common to D/A converter(PWM) output port. R4 port output buffers are Tri-state, and each bit of them can be controled independently by the program Controling the Tri-state is performed by the command register accessed as port address OPOO. When some bit of the OPOO is 0, the corresponding bit of the output buffers becomes high impedance state. The output latch should be set to “1” when the port is used as PWM output port,the PWM output should be to “H” level(PWM data is all "0" )when the port is used as R 4 port The output buffers should be set to high impedance state,when the port is used as input port. And the R4 output latch be set to “1”, PWM output be set to "High" level, and the output buffer be set to High-Inpedance state during reset. Rd (Port Address OP04/IP04) 3 2 1 0 Ra3 Ra2 Rat R40 (Pwiwi3) | (PWM2) | (PWT) | (PWIMO) Output data latch fr +> {—Jraa (ew) a ae H PwM2 il | [ed | am Pw }_f~ | [en a, ra PWwMo | ee or00 [Tria state control SET/CLR IN/ TEST /TESTP 3.2 1 ~0 Figure 3-1. Port R4 (PWM) eS 280290 4-118

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3.2 On-screen display (OSD) circuit

An on-screen display (OSD) circuit used to display characters and symbols in built into the TV screen. Amaximum of 32 characters,as 16 columns x 2 lines,out of 48 character patterns can be displayed at a time.

3.2.1 OSD Circuit Function

@ Number of characters 48 kinds @ Number of characters displayed 32 characters (16 columns x 2 lines) @ Composition of a character 8 x 8 dots (with smoothing function) @) Size of character 2 kinds (selectable line by line) ) Color of character 7 kinds (selectable character by character) © Display position variable horizontal 64 steps, vertical 64 steps

3.2.2 OSD Circuit Configuration |

ose (}+f orcittation 16x 2x9-bit character S [_vericaldecoser_} IE vertical Decoder col Character ROM 5 C) y/e aT ho 48x 8x B-bit > Oe HO [b+] vertical counter JU sheer] cz} +L] « oot sg} Figure 3-4. OSD Circuit

3.2.3 OSD Circuit Control

The OSD circuit is controlled by the command selector (OPOC) and control register (OP1A). Table 3-2 shows the relationship between OPOC and OP1A. OP1A is multiplexed with the six output control registers which control the display start position, color of character and character size of character, and the two transfer control registers which transter character data to the display memory. The output control registers consist of 8 bits and all bits can be written by accessing OP1A two times. However, the second access is not required unless the second data are changed. The addressed “0 to 5” are assigned to the six output contro! registers. OP1A can be accessed by writing the address of the control register where data are to be changed to OPOC. The transfer control registers can be accessed by writing "6" or “7” to OPOC. The transfer contro! registers have a 12 ~ bit configuration and can access OP1A three times succession. The first access sets which column is displayed within one line 16 columns. The second and third accesses written 6 bit of character data. The display memory has a 16-columns x 9-bit x 2 lines configuration with a one-to-one correspondence to the number of columns displayed on the screen. The display data consist of 6 character data bits and 3 color data bits for a total of 9 bits. When “6” is written to OPOC, line 1 is stored to the display memory, when "7" is written to OPOC, line 2 is stored. That is after accessing OPOC, the character data specified the second and third times are written to the display memory area specified in the first OP1A access together with the color data loaded to control register DCRSO. Thus color can be specified for each character. After setting of ali control registers is completed, the character data read from the character ROM(0O to 2Fy)are output to the R, Gand B pins together with the color data by setting OPOC to “F”. 20200 4-121

OSD command OSD control register to be accessed through OP1A selector (OPOC) Control for the horizontal start position of the first display line 3 2 1 0 ocroo {= [= T Hsi5 [514] (istaccess) OCROI HS12 HS10_] (2st access) Control for the vertical start position of the first display line 3 2 1 0 ocrio [_- | - | vsis | vsia | (istaccess) ocri vsi2 V5i0_| (2st access) Control for the horizontal start position of the second display line 3 2 1 9 2 ocwzo [= | - | sas [s2a | cist access OCR21 4522 | _HS21 (2st access) Controt for the vertical start position of the second display line. 3 2 1 o 3 ocrzo | - | - | _vs25 | vs24 | (istaccess) Control for the character sizes smoothing switch and OSD output polarities 3 2 1 0 ocrao [_cs21_| cs20 (1st access) pera | esmz (2st access) Contro! for the color register and OSD output buffers'tri-state’ 3 2 1 0 ° ocrso (istaccess) ocrs! [ears | eBF2 (2st access) display memory write mode for the first display line(address 00-0F) 3 2

6 OMA3 | DMA2 | DMA | DMAD | (Istaccess)

~_ ft - CRAG | (2st access) CRA3 | CRA2 (3st access) dispiay memory write mode for the second display line(address 10-1F) 3 2 1 0 cras_| CRA2 | CRAI (3st access) display OFF Table 3-2. OSD control commands and control registers 90290 4-122

i vst FIRST DISPLAY LINE - CTE LT) vs2 SECOND DISPLAY LINE = LEE i Figure 3-6. TV screen image ts10~Hs15 | horizontal start position of the first display line HSt= ((32xHS15S + 16x HS14 + BX HS13 + 4x HS12 + 2x HS11 +HS10) x4 +X) Tose Vsto~vsis | vertical start position of the first display line VS1= (32x VS1S + 16x VS14 + 8x VS13 +4 VS12 +2xVS11+VS10) x 4THo 4520-525 | Merizontal start position of the second display line HS2= ((32xHS25 + 16 x HS24 + Bx HS23 + 4 x HS22 + 2x HS21 +HS20) x4 +X) Tose vs20~vsag_ | vertical start position of the second display line VS2= (32x VS25 + 16x VS24 + B x VS23 + 4 x VS22 + 2x VS21 + VS20) x 4THD Note. X. Xis 17 when small character. X is 34 when large character. Table 3-6. Display start position * The vertical display positions of lines 1 and 2 can be specified independently but,to prevent overlapping of the two lines on the display, the value for the vertical display position of line 2 must satisfy { VS2>VS1 + CS11x 16THp + C510 x 32TH)

3.2.4 Y/BL signal

The Y signal (the logical or output of the R, G and B signals) makes the display clearer by deleting the background only where characters are displayed. The BL signal deletes the entire background for one character (8 x 8 dots) and is output for all data except that at address 2Fy in the character ROM. The Y/BL pin is used for both Y signal and BL signal output. Which of the two signals is to be output is determined by the upper 2 bits of OPOA. The dotted lines in Figure 3-7 show the Y/BL signal output being scanned, _ _ (2F) (2F) QF) scanning] pm pr ‘> A! i H H i i H H Hi Hi a “01235945 B?ESA | BCD BL : : : ‘ H i Figure 3-7. Example of Y and BL signal output 190290 ~ 4-124

3.2.5 Control of OSD outputs buffer

The OSD outputs for Y,BL and RGB use tri - state output buffers for which the respective polarities can be inverted. Polarity is controlled by DRC41 and tri-state is controlled by DRC51. Bit 3 of DRC41 is used for controlling the smoothing function. [eon [ome [SR | awe [ae]

3 ESMZ —_ smoozing OFF smoozing ON

2 BLIV BL active High active Low

oRcat : . 1 yiV Y active High active Low

0 RGBIV RGB active High active Low

EBF3 Y/BL output buffer OFF output buffer ON eBF2 B output buffer OFF output buffer ON ORCS) oa een . a cert G output buffer OFF output buffer ON EBFO R output buffer OFF output buffer ON ; Figure 3-7. Control of OSD output

3.2.6 RA Port Function

R signal output and G signal output ports are also used as I/O ports. When not used for color signals,use is possible as normal I/O ports. RA port and Y/BL selection is performed by OPOA. Also,the upper 2 bits of IPOA are used to input the OSD display status. Portaddress OPOA sd [Rao output [rat output control of OSD output and RA port oP0a3 | OPOA2 ers | om a Pa | rR | o|aly re |G] e fet RAO G 8 Y RAO | RAI B BL portaddress POA [_Radinput [rat input O:: first display line display ON 1: first display line display OFF 0: second display line display ON 1: second display line display OFF Figure 3-8. Port RA 130290 4-125

3.2.7 Character ROM (Standard characters)

Figure 3-9 shows the standard pattern characters and symbols available as character data. Character patterns can also be set by the user. For details, refer to the section on piggyback chip 47C034, (1) 1 02 03 04 05 a & Fi t 06 07 08 09 OA 0B = FaRaY a acai = es u | = ww E ‘ Fe ® a 4 : aac I oc (1) 13 oF 10 uN Siena porwr [Rinne [tae wane : Lead Pesaran Soliehsteo a 12 3 14 15 16 7

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3 F og we \\ t i

i : 4 a, Bowmore fe bed S ct 18 19 1A 18 1¢ 10 Ps 2 um lz E] sf : 4 & 3 rn ‘ aA Pi 1 \\ i paiak sg Leia <4 s a i i # { a. ' 4 bs 1E 1F 20 21 22 23 y 4 B iz 5 ee re rv) Wianighod 5: BE 4 « i BE Par ey “) E : El @ ih BE , ri a e" g ow Bs : & ‘a 3 8 a 8 a a 4%, bd Ee £ be a bd “s x Ze 24 25 26 27 28 29 a 8 Lo ia ‘ . Pa i My a ANE OBR SRR a tee et i a = la mt ® 2A 28 2c 20 2€ 2F Tee ee peprrcee carey (Background) Figure 3-9. Character ROM address and character pattern wa, 190290 4-126

3.3 3-bit A/D converter (Comparator) input Comparator input consists of a comparator and a 3-bit D/A comvertor. AFC input voltage can be detected in 8 steps by sensing bit 0 of 1PO7 while cahnging the reference voltage (D/A convertor output voltage) with the command register (OP 12) R70 pin is also used for comparator input. Bit 3 is used to set R70 pin for ordinary digital input. The comparator is disabled and bit 3 is set to “O” during reset. The latch should be set to “1” when R70 pin is used for comparator input and digital input.

3.3.1 Circuit Configuration

digital input _ 3-bit D/A | i converter [777 Input | relerence selector | voltage “ ‘iz 1PO7 3 2 1 «0 30 2 1 «0 Figure 3-10. Comparator input circuit

3.3.2 Control of Comparator Input

The reference voltage of the comparator is set using the lower 3 bits of the command register. Table 3- 8 shows the reference voltage when Vpp = 5V. Comparator input control command registor (Port address OP 12) 000 0.62 0 : Disable 010 1.87 1: Enable 013 2.50 100 3.12 Vaer = Vox (n + 1)/8[V] 110 437 (n= 0-7) Vt tj 5.00 Figure 3-11. Control Command Registor Table 3-8. Reference Voltage 190290 4-127

3.4 D/A converter (PWM) output

The 47C434/634 have five channels built-in D/A converter (Pulse width Modulation) outputs. PWM output can easily be obtained by connecting an external low pass filter. PWM outputs data are multiplex to the R4 port and R50 pin. When the R4 (PWM) port and R50 pin are used for PWM output, the corresponding bits of R4, R50 output latch should be set to "1". The R4, RS output latch is initialized to “1" during reset. PWM output is controlled by the buffer selector (OP17) and the data transfer buffer (OP18). PWM data written to the data transfer buffer can be sent to the PWM data latch by writing “Cy” to the buffer selector, and PWM output PWM output. PWM data transferred to the PWM data latch remain intact until overwritten. Resetting and holding clear the buffer selector, data transfer buffer and PWM data latch to "0" (PWM output is "H” level)

3.4.1 Configuration of Pulse Width Modulation circuit

Configuration of pulse width modulation circuit shown in Figure 3-13.

3.4.2 Output waveform of PWM circuit

(1) PWMO output PWM0 is a PWM output controlled by 14 bits data. The basic period of the PWM0 is Tm = 2!'5/ fc. The higher 8 bits of 14 bits data are used to control the pulse width of the pulse output with the period of Ts = Ty/ 64, which is the sub - period of the PWMO. When the 8 bits data are decimal n (0 = n + 255), this pulse width becomes n x to, where to = 2/fc. The lower 6 bits of 14 bits data are used to control the generation of an additional to wide pulse in each Ts period. When the 6 bits data are decimal m (0 = m 3 63), the additional pulse is generated in each of m periods out of 64 periods contained in a Ty period. The relationship between the 6 bits data and the position of Ts period where the additional pulse is generated is shown in Table 3-9 (2) PWM1-PWM4 output Each of PWMT to PWMG is a PWM output controlled by 6 bits data. The period of them is Tm = 27/ fc. When the 6 bits data are decimal k (0 < k < 63), the pulse width becomes k x to. The waveform is also illustrated in Figure 3-12. T= 647s, ee ee | Ts Tsay Ts (63) Pr —axig | Pwo | Pulse width =nx tg Pulse width = (n+ 1) to i —>}|.to | i] | 1 i PWM PWM4 || putse width= kxt Figure 3-12, PWM Output Waveform (it is shown to the additional pulse Ts (1) and Ts (63) of the PWMO) 190290 4-128

ori? IMAGE OF 0 3B Loo TRANSFER BUFFER 7 ea c s 14 BIT BINARY COUNTER EE _ ~s._OP18 ~ °o Ld —— | 4 w x Vv “ = Soy f 3 iS ADDITIONAL ° sf 2 vi PULSE | oR ws we | sj PY. \\X Pai < we 2 «- ° < ° é 3 <> | af * av ou pub bet g h/\\ s= Vv) oe - S o- FIF | ° 4 uy | ot & a 3 | ; a av marcrsicnar, |p / ° “SLE q me -[ = é =_ 6] “Zt Fs aN \\2 ised oi Se Be FE \\5 ° g = “oe

5 Nine MATCH SIGNAL @

| 2) LLWN a lz 2 ee < on | co - q a \\* an a S., \\ so l2 fateh <P Se ae FIF | KANN s | © “SEs = aren Q i? S % x a) or ce SN 8 | tos. OE ey Se first gi 26 g= ne FIF cf eo] bas zs|V| oo AUO” rs ° “srg < me - ia Es a ~ g a : ; « ox Ne) sftp ee 2r ae F/F of e wt BR 3¢ bu ALLO" el ~ ---2 OL. Pwina ~h MATCH SIGNAL TINY sranseen cn i REQUEST | fo Figure 3-13. Pulse Width Modulation Circuit SSS OT 4-129

Bit position of 6 vits data Relative position of Tawhere the output pulse is generated bitO 32 bitt 16, 48 bit2 8, 24, 40, 56 bit3 4, 12, 20, 28, 36, 44, 52, 60 Note . When the corresponding bit is “1”, itis output i Table 3-9. Correspondence between 6 bits data and the additional pulse generated Ts periods

3.4.3 Control of PWM circuit (Data transfer)

PWM output is controlled by writing output data to a data transfer buffer (OP18). For writing, the output data are divided using the buffer selector (OP 17). Buffer numbers are assigned to the data transfer buffers for these divided data, after which the data are written as shown in Table 3-10. () The number of the transfer buffer to which the data are to be written is written to the buffer selector (OP17) (2) The corresponding PWM data are written to the selected buffer (OP 18). @ Operations @ and @ are repeated, continuously writing data to the transfer buffer. @ When all of the output data have been written. “Cy” is written to the buffer selector. While the output data are being writen to the transfer buffer, the previously written data are being output. For PWMO output, switching to PWM output occurs at a maximum of 215/fc [sec] (at 4MHz, 8192fs) after “Cy” is written to the buffer selector. For PWM1 through PWM4 output data switching, this requires 2°/fc {sec] (at 4MHz, 1284s). Buffer Number Correspondence to bit PWM Output (P17) (oP 18)

0 Bit of PMG transfer buffer 3~0 write Preceding data

1 Bit of PWM<4 transfer buffer 5~ 4 Write Preceding data

2 Bit of PWMO transfer buffer 9~ 6 Write Preceding data

3 Bit of PWMO transfer buffer 13 ~ 10 Write Preceding data

4 Bit of PWMO transfer buffer 3~0 write Preceding data

5 Bit of PWMO transfer buffer 5s~4 Write Preceding data

6 Bit of PWM transfer buffer 3~0 Write Preceding data

7 Bit of PWM1 transfer buffer 5~ 4 Write | Preceding data

8 Bit of PWMi2 transfer buffer 3~0 Write Preceding data

9 Bit of PWM2 transfer buffer . 5~4 Write Preceding data A Bit of PWM3 transfer buffer 3~0 Write Preceding data

8 BitofPWM3 transfer buffer 5~4 Write Preceding data

Table 3-10. The bit and Buffer number of data transfer Buffer 190230 a — 4-130

ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS | (Vss5 = OV) Output Voltage oun P P P o Vv Sink open drain pin except R7 port -0.3t0 10 Output Current (Per 1 pin) mA RECOMMENDED OPERATING CONDITIONS (Vss = OV, Topr = - 30 to 70°C) Supply Voltage Vop v j . , Vop 2 4.5V Input High Voltage Ving | Hysteresis input Vop x 0.75 Voo Vv eo Input Low Voltage Vig | Hysteresis Input Voo* 4.5V Vv Note. Input Voltage Vin3, Viz: in the HOLD mode. 4-131

D.C. CHARACTERISTICS | (Vs5 = OV, Topr = - 30 to 70°C) linn | KO port, TEST, Voo=55 Tt, HOU oo = 5.5V, Input Current RESET, HOLD +2] BA R port (open drain) Vin = 5.5V/0V input Resistance lea fe | +f ano Output leakage Tristate i Current R6, RB, RY port (open drain) Voo = 5.5V, Vour = 5.5V +2] HA Vou R7, R8, RY port Vop = 4.5V, Io, = 1.6mA. Output Low Voltage R port (tri-state) Vop = 4.5V, lo, =0.7mA v RE por Yoorasvivorstov | | ao | ~ [ma en mo | reba (| elm {un the Normal mode} _| °° fo= MHz Supply Current loon Voo = 5.5V t0/ pA {in the HOLD mode) Note 1. Typ. values show those at Topr = 25°C, Vop = 5V. Note 2. Input Current liy;_ : The current through resistor is not included, when the pull-up /pull-down resistor is contained. Note 3. Supply Current : Vin=5.3V/0.2V The KO port is open when the pull-up / pull-down resistor is contained. The voltage applied to the R port is within the valid range Vu or Vi. A/D CONVERTER CHARACTERISTICS a ee ee 90290 ~ 4-132

A.C. CHARACTERISTICS (Vss = OV, Vop =4.5 to 6.0V, Top, = - 30 to 70°C) fimaincreeine wy | | For external clock operation ns Low level Clock Pulse Width Note. Shift data Hold Time External circuit for SCK pin and SO pin Serial port (Completion of transmission) ©vDD SCK 1sVv | ; 10KQ son SOpF > so 1.5V RECOMMENDED OSCILLATING CONDITIONS | (Vss = OV, Vop =4.5 to 6.0V, Topr = - 30 to 70°C) (1) 4MHz XIN XOUT Ceramic Resonator CSA4.00MG (MURATA) Gxiw = Cxour = 30pF KBR-4.00MS (KYOCERA) —— Cxin = Cxour = 30pF az Crystal Oscillator Lit t ¢ 2048-6F 4.0000 (TOYOCOM) — Cxin = Cxour = 20pF ann ae xOUT (2) 400KHz XIN xOUT Ceramic Resonator CSB400B (MURATA) Cxin = Cxour = 220pF, Ryour = 6.8K | 400KHz Rxout KBR-4008 (KYOCERA) — Cxin = Cxour = 100pF, U Cx, Cxour Ryour = 10KQ an ae (3) 6MHz (for DOS) osc) osc2 LC Resonator emt TBEKSES-30361FBY (TOUKOU) r a= | 77 190290 4-133

R R-Ta KO port R R-Ta RESET pin “TET SET aan napeaa 100 / Lit ty. GLEE Tt. -40 0 40 80 (°C) -40 0 40 80 (°C) i lou— Vou CMOSK port , I1L-Vin CMOSR port 1 Tou — Vou TRISTATE port Jou Mt OH Von=4.5V ‘A Vpp=5.5V Vpp=4.5V “ Ky] Ta 225°C “ Ta = 25°C wma yoo me vot NTE) EEN ET ERLE TT vot EAE E on HS CH SPS 200 — 400 IN -10 Saeaee PETE N | OLE LIN | “COCA, “ELFEN, (ZECCA

0 Vou 0 I\\ Vin 0 Vou

2 4 6 (V) 2 4 6 (Vv) 2 4 6 (Vv) 1 lo.- Von R port j To.- Vou PI, P2 port , lou— Vou TRISTATE port OL, Ol, ‘Ole Vip=4.5V Vip=4.5V Ay Von =4.5V (mM ree asec / || (a2 25°C ( : Ta=25°C A 8b 40 LZ BERD Z eee ae LIZ TT) fee EAT

1 A 0 L> “| 4 Z|

VET. “YEEETT,. (ZELTT TA 0 Vou, Kd Vo. 0 Vou, 04 08 1.2(V) 04 08 1.2(V) 04 08 1.2(V) \\ Ipp- Yop 1 Ipp-fe pp bp ms ee ‘a= a SMT | leodou 7) 7 ah 2 2 f. “ann MU AL ee 7,. COAT ° aa Von ° nail fe 3 5 7 Ww) or 04 1 4 10(MIIz) 190290 4-134

(1) Control pins Input/output circuitries of the 47C434/634 control pins are shown below. CONTROL PIN CIRCUITRY REMARKS OSC. enable Resonator connecting pins XIN Input RY R = 1KQ (typ.) XOUT Output R Ro Ry = 1.5MQ (typ)

1 Ro = 2k0 (typ)

a Rin Contained pull-up resistor RESET Input ‘| TR Rwy = 220KQ (typ.) R = 1KQ (typ.) Hysteresis input input OUD (KO) R (Sense input) R= 1KQ (typ.) R Contained pull-down resistor TEST Input Rin Riy = 70KQ (typ.) R= 1KQ (typ) OSC. enable Oscilation terminals for DOS osc1 Input W R = 1KQ (typ.) R Ro Ry =1.5MQ (typ.) osc2 Output Ro =2KQ (typ) osc) 0sc2 Synchronous signal input AD input «J wi tJ Hysteresis input VO R= 1KQ (typ.) 190290 ~ ~ 4-135

(2) /O ports The input/output circuitries of the 47C434/634 I/O ports are shown below, any one of the circuitries (PB, PC, PF, PU) can be chosen by a code as a mask option. 91) Pull-up evo R or KO | Input pull-down resistor Rin | Rin | Nv Rin = 70KQ (typ.) R= 1KQ (typ.) PB, PC | ° vob Tri-state { or Ra it RO Me - {_] ——_Po—-] Sink open drain loisauce ~ R Initial “Hi-2" R R= 1KQ (typ) P voo Tri-state 52 | VO RS3 DISABLE ~ k R= 1KQ (typ.) R6 R8, RO Sink open drain Initial “Hi-2” R6 | lHysteresis input (R8, R9) # | vo | ——De —DeH ysteresis input (6, Ro R R 777 R= 1KQ (typ.) ~ R70 71~ Initial "Hi-2” Ail “Migh* vob Sink open drain ——-De- and r7 | vo | R push-pull ~ Comparator input R (R70 pin) | =: Vaee R= 1KQ (typ.) R (RAO) | vop Tri-state iran) VO i Initial "Hi-2" — Pee R= 1KQ (typ) | pisaBte f 050 status, b

8 Qspstas, ieee R o— R,G Sidea

y(t) [Output a . —<fi— ° 8,Y: Sided 230290 ~~ 4-136

CMOS 4-BIT MICROCONTROLLER TMP47C034E The 47C034, which is equipped with an EPROM as program memory, is a piggyback type evaluator chip used for development and operational confirmation of the 47C434/634 application systems (programs). Conversion adapter socket BM1105 can be used to convert the 64-pin package of the 47C034 for pin compatibility with the 42-pin mask ROM 47C434/634. Conversion adapter socket BM1106 can be used to convert from 64 pins for pin compatibility with the 54-pin 47C635. PIN ASSIGNMENT (TOP VIEW) spiced Rie G1 640 «vop R326 J 2 63 R30 RAQ(PWMO)e G 3 62) «R92 (STR) RaPWMI|e C4 61 [1 R91 (SO) Ra2(PWM2)> 4 5 60 {7 «R90 (Si) Ra3(PWM3)~> J 6 59D R83 (TI) RSO(PWMid)e> G7 58D «+R82(INTI) Rsie G 8 57D «R81 (T2) nc 9 9 560 NC nc 10 55D NC Rs2e G11 s4P N.C RS3e 12 53) ++R80(INT2) R70(CIN)e* G13 vee vee 52 D HOLD (KEO) R7UWTO)™ Ho Aid vec 8 51D <RESET R72e Gis 50D >xouT R73 G16) a7 13. QS) 49 P XIN KOO. q17 48 «TEST Koim dia@® A6 a8 @ arf Sosc2 Ko2> 4 19(5) AS Ag 46D <-0sc1 X03 G20) aa att 45 VD NC G21 44 HD nc 422@) a3 OE 43 f) a Ne G23) a2 Alo ap Nc R60 (24 4ip NC. aie 425@) Al E WD aoh sev R62e J 26 G9 39P 8 Ree G $0 a0 7 @ 38 P +G (RAI) Pio 428 @) 10 16 @® 376 «+R (RAO) Pre G29@) 11 15 36D P23 PI2e 3@ @ 35D ~22 Piz 31 i 14 (8 34 p21 vss 4 32 GND 13, (5) 33 P P20 PIN FUNCTION (Top of the package) 7. 10 nput Program memory data input CE - °. Chip enable signal output utput oe Output enable signal output vec +5V (connected with VOD) GND OV (connected with VSS) A.C. CHARACTERISTICS 280290 — 4-137