47C400AN

TMP47C200AN TOSHIBA | Alldatasheet

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TOSHIBA TMP47C200A/400A/990 CMOS 4-BIT MICROCONTROLLER TMP47C200AN, TMP47C400AN TMP47C200AF, TMP47C400AF The 47C200A/400A are high speed and high performance 4-bit single chip microcomputers, integrating ROM, RAM, input/output ports, timer/counters, and a serial interface on a chip. The 47C200A/400A are the standard type devices in the TLCS-47 CMOS series, and provides high current output capability for LED direct drive LIMPATCOOAN | ooa8 a pit -Sbia2__[ Tpa7c990e TMP47C200AF Qrpaa ‘TMP47C990G -TMPATCAOOAN | ange x a.bit 2 20IPA2 __ | _TMPA7COSOE __ TMP47C400AF xe! Qrpaa TMPA7C990G FEATURES sora #4-bit single chip microcomputer #instruction execution time: 1.9ys (at 4.2MHz) . #90 basic instructions - 4 @Table look-up instructions - . agi #5-bit to 8-bit data conversion instruction a sai Subroutine nesting: 15 levels max “Asal TMP47C200AN 6 interrupt sources (External: 2, Internal: 4) TMP47C400AN All sources have independent latches each, and multiple interrupt control is available QrPaa 1/0 port (36 pins) © Input —2ports Spins © Output 2ports 8pins oN, «0 6ports 23pins ra oy @ interval Timer Rapp @Two 12-bit Timer/Counters TMP47C200AF Timer, event counter, and pulse width measurement mode TMP47C400AF @Serial Interface with a 4-bit buffer spicaz External/internal clock, and leading/trailing edge shift mode @High current outputs wee LED direct drive capability (typ. 20mA x 8 bits) ne thy #Hold function be yea te gO ath Battery/Capacitor back-up Cn et iia @Real Time Emulator: BM4721A WS ra ¢ TMP47C990E QFcaa PA Ope TMP47C990G 5-1

TOSHIBA TMP47C200A/400A/990 ee PIN ASSIGNMENTS (TOP VIEW) (1) 42-SDIP (2) 44-QFP rag <> Oi 42) ~— vod = aS = fe slkle aa <> 2 aif) <> a925e%) 2 glee sists ehanes nee 40 Pl +> 91,50) g2shPaiiese aay <> Qa a9) +> as0(51) petdddd add aso => Os 38 |) = RB3(T1) HOOGG0n ha ag asi <> 6 yy] <> asain HHHHHHHAAHH we <q ae <> nonin) 3332.31 30 29 20.27 26 25 24 29 wi +> Qe asf) <> neo away pay) == corse 2 PE = Koo roo <> D9 34 1] <— FOLo (KeO) R90(51) = C35 2) PO] — p23 61 <> Qi0 33 {] <— feseT f91(50) + T1436 20 FI — p22 r aga(scx) => C1037 19 PIO— pa ee = ns 32} —> xour i 1B foo pe nes 2 a = xn voo — Gabo 7 fone ao + G3 30] — Test Rag =~ C40 16 AI =~ vss paso Couey 4 rosea any em fia 29 f] <—~ x03 pay + Coma2 14 PII — py an == 1s 28] —xo2 nay = Coda 13 fa on an =~ Ove » 1 nso > Coea ve Bra p10 ald v 4 00 1923 4 5 6789 1011 ote as— va HHH ARTA oo =—this aa P—> v2? UUUUUUUCUOY vss —= (2s 22 —> P20 eeecek eeeeree BLOCK DIAGRAM Power {oe Supply Uvss (ele[sIs} naan —_]] counter [stacx_few |—7y — aes cca (sensesnout) (266) Memory Testpn TEST Thmng Generator (een) Intertace («| Coo D O O a in [a5] {xo} ais mes wea RD neniry, age PBK ot a2 (WT) Rorison een : R70 RGD ASO RAO mora) R90 (51) (P20._P10 00 wee ee aera f29 ae 250190 ~ 5-2

TOSHIBA TMP47C200A/400A/390 PIN FUNCTION PIN NAME InpuvOutput FUNCTIONS P13 - PIO output 4-bit output port with latch. p23. P20 vipa 8-bit data are output by the 5-bit to 8-bit data conversion instruction [OUTE @HL} Raz - R40 4-bit VO port with latch R53 - R50 When used as input port, the latch must be set to "1" vO R63 - REO Every bit data is possible to be set, cleared and tested by the bit manipulation a3 - AO instruction of the L-register indirect addressing R83 (T1) 4-bit VO port with latch Timer/Counter 1 external input R82 (INTT) When used as input port, external | External interrupt 1 input "O(Input) interrupt input pin, or timer/counter R81 (T2) Timer/Counter 2 external input external input pin, the latch must be set R80 (INT2) jto“1" External interrupt 1 input R92 (SCK) WO(vo) 3-bit /O port with latch. Serial clock /O. R93 (SO) vo(Outpur) | When used as input port or serial port, the | serial data output latch must be set to "1" R90 (SI) vOlinput) Serial data input XIN input Resonator connecting pins. xout Output For inputting external clock, XIN is used and XOUT is opened. HOLD (KEO) Input(input) Hold requesUrelease signal input Sense input TEST Input Test pin for shipping. Be opened or fixed Lo low ievel vod +5V Power Supply VSS Ov (GND) 350190 5-3

TOSHIBA TMP47C200A/400A/990 OPERATIONAL DESCRIPTION 1. SYSTEM CONFIGURATION (1) Program Counter (PC) (2) Program Memory (ROM) (3) H Register, L Register (4) Data Memory (RAM) a. Stack b. Stack Pointer Word (SPW) c. Data Counter (DC) (5) ALU, Accumulator (6) Flags (7) Clock Generator, Timing Generator (8) W/O Ports (9) Interval Timer (10) Timer/Counters (TC1, TC2) (11) Serial Interface (12) Interrupt Controller (13) Hold Controller (14) Reset Circuit Concerning the above component parts, the configuration and functions of hardwares are described. 2. INTERNAL CPU FUNCTION

2.1 Program Counter (PC)

The program counter is a 12-bit binary counter which indicates the address of the program memory storing the next instruction to be executed. Normally, the PC is incremented by the number of bytes of the instruction every time it is fetched. When a branch instruction or a subroutine instruction has been executed or an interrupt has been accepted, the specified values listed in Table 2-1 are set to the PC. The PC is initialized to “0” during reset. MsB USB PCy ' PCm ‘ PCy a a Ee PCi1 | PCig | PCy | PCa | PCy | PCa | PCs | PCa | PCy ! PCr | PCY | PCy eee OG Page assignment Address assignment in page Figure 2-1. Configuration of Program Counter The PC can directly address a 4096-byte address space. However, with the short branch and subroutine call instructions, the following points must be considered (1) Short branch instruction [BSS a] In [BSS a] instruction execution, when the branch condition is satisfied, the value specified in the instruction is set to the lower 6 bits of the PC. That is, {BSS a] becomes the in-page branch instruction. When [BSS a] is stored at the last address of the page, the upper 6 bits of the PC point the next page, so that branch is made to the next page. (2) Subroutine call instruction [CALL a] in [CALL a] instruction execution, the contents of the PC are saved to the stack then the value specified in the instruction is set to the PC. The address which can be specified by the instruction consists of 11 bits and the most significant bit of the PC is always “O". Therefore, the entry address of the subroutine should be within an addrress range of 0004 through 7FFi4 rr 5-4