ICS477-05 RENESAS | Alldatasheet

Document overview

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Technical content

Features

  • Packaged in 28-pin SSOP (QSOP)
  • Available in Pb-free packaging
  • Replaces a VCXO plus multiple crystals and os cillators
  • On-chip patented VCXO pull range 200 ppm (minim um)
  • Duty cycle of 45/55
  • Operating voltage of 3.3V
  • Advanced, low power, CMOS process
  • Input crystal frequency of 27 MHz
  • Five output clocks
  • Industrial temperature range available Block Diagram PLLA PLLC PLLBVoltage Controlled Crystal Oscillator Divide Logic and Output Enable Control

27 MHz

74.175M 54.054M

QUAD PLL WITH VCXO FOR HDTV VCXO AND SYNTHESIZER IDT™ / ICS™ QUAD PLL WITH VCXO FOR HDTV 2 ICS477-05 REV H 062404 Pin Assignment Pin Descriptions GND GND NC NC 27M NC 27M 74.175M 1811 GND 54.054M GND 54M 1910 28 pin (150 mil) SSOP 82 1 7GND GND GND

22 VDD

24 VDD

26 PDTS

1 XI Input Crystal connection. Connect to a 27 MHz fundamental mode pullable crystal. 2 GND Power Connect to ground. 3 GND Power Connect to ground. 4 VIN Input VCXO Voltage input. Zero to 3.3 V analog control voltage for VCXO. 5, 6, 22, 23, 24, 27 VDD Power Connect to +3.3 V. 7, 8, 9, 10, 19, 20, 21 GND Power Connect to ground. 11 54.054M Output 54.054 MHz clock output. Weak internal pull-down when tri-state. 12, 13, 17 NC - No connect. Do not connect anything to these pins. 14 74.175M Output 74.175 MHz clock output. Weak internal pull-down when tri-state. 15, 16 27M Output 27 MHz reference clock output . Weak internal pull-down when tri-state. 18 54M Output 54 MHz clock output. Weak internal pull-down when tri-state. 25 GND Power Connect to ground. Input Powers down entire chip. Tri-states CLK outputs when low. Internal pull-up. 28 X2 Input Crystal connection. Connect to a 27 MHz fundamental mode pullable crystal.

QUAD PLL WITH VCXO FOR HDTV VCXO AND SYNTHESIZER IDT™ / ICS™ QUAD PLL WITH VCXO FOR HDTV 3 ICS477-05 REV H 062404 External Components The ICS477-05 requires a minimum number of external components for proper operation. Decoupling Capacitors Decoupling capacitors of 0.01µF must be connected between VDD and GND, as close to these pins as possible. For optimum device performance, the decoupling capacitors should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. Series Termination Resistor When the PCB trace between the clock outputs and the loads are over 1 inch, series termination should be used. To series terminate a 50Ω trace (a commonly used trace impedance) place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Quartz Crystal The ICS477-05 VCXO function consists of the external crystal and the integrated VCXO oscillator circuit. To assure the best system performance (frequency pull range) and reliability, a crystal device with the recommended parameters (shown below) must be used, and the layout guidelines discussed in the following section must be followed. The frequency of oscillation of a quartz crystal is determined by its “cut” and by the load capacitors connected to it. The ICS477-05 incorporates on-chip variable load capacitors that “pull” (change) the frequency of the crystal. The crystal specified for use with the ICS477-05 is designed to have zero frequency error when the total of on-chip + stray capacitance is 14 pF . The external crystal must be connected as close to the chip as possible and should be on the same side of the PCB as the ICS477-05. There should be no via’s between the crystal pins and the X1 and X2 device pins. There should be no signal traces underneath or close to the crystal. See application note MAN05 for complete crystal specifications. Crystal Tuning Load Capacitors The crystal traces should include pads for small fixed capacitors, one between X1 and ground, and another between X2 and ground. Stuffing of these capacitors on the PCB is optional. The need for these capacitors is determined at system prototype evaluation, and is influenced by the particular crystal used (manufacture and frequency) and by PCB layout. The typical required capacitor value is 1 to 4 pF . To determine the need for and value of the crystal adjustment capacitors, you will need a PC board of your final layout, a frequency counter capable of about 1 ppm resolution and accuracy, two power supplies, and some samples of the crystals which you plan to use in production, along with measured initial accuracy for each crystal at the specified crystal load capacitance, CL. To determine the value of the crystal capacitors: 1. Connect VDD of the ICS477-05 to 3.3 V. Connect pi n 4 o f the ICS477-05 to the second power supply. Adjust the voltage on pin 3 to 0V. Measure and record the frequency of the 27 MHz output. 2. Adjust the voltage on pin 4 to 3.3 V. Measure and record the frequency of the same output. To calculate the centering error: Where: ftarget = nominal crystal frequency errorxtal =actual initial accuracy (in ppm) of the crystal being measured If the centering error is less than ±25 ppm, no adjustment is needed. If the centering error is more than 25 ppm negative, the PC board has excessive stray capacitance and a new PCB layout should be Error 10 6x f3.0V fte targ–() f0V fte targ–()+ fte targ

QUAD PLL WITH VCXO FOR HDTV VCXO AND SYNTHESIZER IDT™ / ICS™ QUAD PLL WITH VCXO FOR HDTV 4 ICS477-05 REV H 062404 considered to reduce stray capacitance. (Alternately, the crystal may be re-specified to a higher load capacitance. Contact ICS for details.) If the centering error is more than 25 ppm positive, add identical fixed centering capacitors from each crystal pin to ground. The value for each of these caps (in pF) is given by: External Capacitor = 2 x (centering error)/(trim sensitivity) Trim sensitivity is a parameter which can be supplied by your crystal vendor. If you do not know the value, assume it is 30 ppm/pF . After any changes, repeat the measurement to verify that the remaining error is acceptably low (typically less than ±25 ppm). PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01µF decoupling capacitors should be mounted on the component side of the board as close to the VDD pins as possible. No vias should be used between the decoupling capacitors and VDD pins. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) To minimize EMI, the 33Ω series termination resistor (if needed) should be placed close to the clock output. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS477-05. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS477-05. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature (commercial) 0 to +70 ° C Ambient Operating Temperature (industrial) -40 to +85 ° C Storage Temperature -65 to +150 ° C Junction Temperature 125 ° C Soldering Temperature 260 ° C

QUAD PLL WITH VCXO FOR HDTV VCXO AND SYNTHESIZER IDT™ / ICS™ QUAD PLL WITH VCXO FOR HDTV 5 ICS477-05 REV H 062404 Recommended Operation Conditions Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C Parameter Min. Typ. Max. Units Ambient Operating Temperature -40 +85 ° C Power Supply Voltage (measured in respect to GND) +3.15 +3.3 +3.45 V Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.15 3.3 3.45 V Supply Current IDD No load 48 mA Power Down Current IDDPD No load 0.5 mA Input High Voltage V IH PDTS pin 2 V Input Low Voltage V IL PDTS pin 0.8 V Output High Voltage V OH IOH = -4 mA VDD-0.4 V Output High Voltage V OH IOH = -12 mA 2.4 V Output Low Voltage V OL IOL = 12 mA 0.4 V Short Circuit Current I OS CLK output ±80 mA Input Capacitance, inputs C IN 5p F Nominal Output Impedance Z OUT 20 Ω Internal Pull-up Resistor R PUP PDTS pin 360 k Ω Internal Pull-down Resistor R PD CLK outputs 510 k Ω Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency f in Crystal input, Note 2 27 MHz Crystal Pullability F P 0V< VIN < 3.3 V ±100 ppm VCXO Gain K 0 VIN = VDD/2 + 1 V 150 ppm/V Output Rise Time t OR 20% to 80%, Note 1 1.2 ns Output Fall Time t OF 80% to 20%, Note 1 1.0 ns Clock Stabilization Time after Power-up 10 ms Cycle Jitter (short term jitter) t ja ±200 ps

QUAD PLL WITH VCXO FOR HDTV VCXO AND SYNTHESIZER IDT™ / ICS™ QUAD PLL WITH VCXO FOR HDTV 6 ICS477-05 REV H 062404 Note 1: Measured with a 15 pF load. Note 2:With an ICS approved crystal. Marking Diagram Marking Diagram (industrial) Marking Diagram (Pb free) Marking Diagram (Pb free, industrial) Notes: 2. YYWW is the last two digits of the year, and the week. 3. “LF” designates Pb (lead) free. 4. “I” designates industrial temperature grade. Long Term Jitter 54.054M, 54M clocks 1.0 ns 74.175M clock 1.3 ns 27M reference clock 300 ps Output Enable Time PDTS high to output locked to ±1% 250 µs Output Disable Time PDTS low to tri-state 20 ns Parameter Symbol Conditions Min. Typ. Max. Units 1 14 1528 ICS477R-05 YYWW 1 14 1528 ICS477R-05I YYWW 1 14 1528 ICS477R-05LF YYWW 1 14 1528 ICS477R-05ILF YYWW

QUAD PLL WITH VCXO FOR HDTV VCXO AND SYNTHESIZER IDT™ / ICS™ QUAD PLL WITH VCXO FOR HDTV 7 ICS477-05 REV H 062404 Package Outline and Package Dimensions (28-pin SSOP, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

“LF” denotes Pb (lead) free package. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping Packaging Package Temperature 477R-05 ICS477R-05 (top line) YYWW (3rd line) Tubes 28-pin SSOP 0 to +70° C 477R-05T Tape and Reel 28-pin SSOP 0 to +70 ° C 477R-05I ICS477R-05I (top line) YYWW (3rd line) Tubes 28-pin SSOP -40 to +85° C 477R-05IT Tape and Reel 28-pin SSOP -40 to +85 ° C 477R-05LF ICS477R-05LF (top line) YYWW (3rd line) Tubes 28-pin SSOP 0 to +70° C 477R-05LFT Tape and Reel 28-pin SSOP 0 to +70 ° C 477R-05ILF ICS477R-05ILF (top line) YYWW (3rd line) Tubes 28-pin SSOP -40 to +85° C 477R-05ILFT Tape and Reel 28-pin SSOP -40 to +85 ° C INDEX AREA 1 2 D E1 E SEATING PLANE AA2 e - C - b .10 (.004) C c L Millimeters Inches Symbol Min Max Min Max A 1 . 3 51 . 7 5. 0 5 3. 0 6 9 A1 0.10 0.25 .0040 .010 A2 -- 1.50 -- .059 b 0.20 0.30 0.008 0.012 C 0 . 1 80 . 2 5. 0 0 7. 0 1 0 D 9.80 10.00 .386 .394 E 5 . 8 06 . 2 0. 2 2 8. 2 4 4 E1 3.80 4.00 .150 .157 e 0.635 Basic 0.025 Basic L 0 . 4 01 . 2 7. 0 1 6. 0 5 0 α 0° 8° 0° 8°

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