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HEF4724B PHILIPS | Alldatasheet

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Technical content

Product specification File under Integrated Circuits, IC04 January 1995 INTEGRATED CIRCUITS HEF4724B MSI 8-bit addressable latch For a complete data sheet, please also download:

• The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

Philips Semiconductors Product specification 8-bit addressable latch HEF4724B MSI

DESCRIPTION

The HEF4724B is an 8-bit addressable latch with three address inputs (A0 to A2), a data input (D), an active LOW enable input (E), an active HIGH clear input (CL), and eight parallel latch outputs (O0 to O7). When E and CL are HIGH, all outputs (O0 to O7) are LOW. Eight-channel demultiplexing or active HIGH 1-of-8 decoding with output enable operation occurs when CL is HIGH and E is LOW. When CL andE are LOW, the selected output (O0 to O7; determined by A0 to A2) follows D. When E goes HIGH, the contents of the latch are stored. When operating in the addressable latch mode E = CL = LOW), changing more than one bit of A0 to A2 could impose a transient wrong address. Therefore, this should only be done while in the memory mode E = HIGH, CL = LOW). Fig.1 Functional diagram. PINNING FAMILY DATA, IDD LIMITS category MSI See Family Specifications HEF4724BP(N): 16-lead DIL; plastic (SOT38-1) HEF4724BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4724BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America A0 to A2 address inputs A data input E enable input (active LOW) CL clear input (active HIGH) O 0 to O7 parallel latch outputs Fig.2 Pinning diagram.

Philips Semiconductors Product specification 8-bit addressable latch HEF4724B MSI This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Fig.3 Logic diagram. Fig.4 Logic diagram (one latch).

Philips Semiconductors Product specification 8-bit addressable latch HEF4724B MSI MODE SELECTION FUNCTION TABLE Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial O n-1 = state before the positive transition ofE D 1 = either HIGH or LOW E CL MODE L L addressable latch H L memory L H active HIGH 8-channel demultiplexer H H clear CL ED A 0 A 1 A 2 O 0 O 1 O 2 O 3 O 4 O 5 O 6 O 7 MODE H H X X X X L L L L L L L L clear HLD 1 LLL D 1 LLLL L L L demultiplexer; unaddressed latch is cleared HLD

1 HL L LD 1 LLL L L L

HLD 1 HH L L L LD 1 LL L L HLD 1 L L H LLLL D 1 LLL HLD 1 H L H LLLLL D 1 LL HLD 1 L H H LLLLL L D 1 L HLD 1 H H H LLLLL L L D 1 LH XXXX O n-1 O n-1 O n-1 O n-1 O n-1 O n-1 O n-1 O n-1 memory LLD 1 LLL D 1 O n-1 O n-1 O n-1 O n-1 O n-1 O n-1 O n-1 addressable latch; unaddressed latch holds previous state LLD

1 HL L O n-1 D 1 O n-1 O n-1 O n-1 O n-1 O n-1 O n-1

LLD 1 LHL O n-1 O n-1 D 1 O n-1 O n-1 O n-1 O n-1 O n-1 LLD 1 HH L O n-1 O n-1 O n-1 D 1 O n-1 O n-1 O n-1 O n-1 LLD 1 LLH O n-1 O n-1 O n-1 O n-1 D 1 O n-1 O n-1 O n-1 LLD 1 HLH O n-1 O n-1 O n-1 O n-1 O n-1 D 1 O n-1 O n-1 LLD 1 LHH O n-1 O n-1 O n-1 O n-1 O n-1 O n-1 D 1 O n-1 LLD 1 HHH O n-1 O n-1 O n-1 O n-1 O n-1 O n-1 O n-1 D 1

Philips Semiconductors Product specification 8-bit addressable latch HEF4724B MSI AC CHARACTERISTICS VSS = 0 V; Tamb =2 5°C; input transition times≤ 20 ns AC CHARACTERISTICS VSS = 0 V; Tamb =2 5°C; CL = 50 pF; input transition times≤ 20 ns VDD V TYPICAL FORMULA FOR P ( µW) Dynamic power 5 700 f i+∑ (foC L)× VDD 2 where dissipation per 10 3700 f i+∑ (foC L)× VDD 2 fi= input freq. (MHz) package (P) 15 10 800 f i+∑ (foC L)× VDD 2 fo = output freq. (MHz) C L = load capacitance (pF) ∑ (foC L) = sum of outputs VDD = supply voltage (V) VDD V SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA Propagation delays E → O n 5 115 230 ns 88 ns + (0,55 ns/pF) CL HIGH to LOW 10 t PHL 50 95 ns 39 ns + (0,23 ns/pF) CL 15 35 70 ns 27 ns + (0,16 ns/pF) CL 5 95 195 ns 68 ns + (0,55 ns/pF) CL LOW to HIGH 10 t PLH 40 80 ns 29 ns + (0,23 ns/pF) CL 15 30 55 ns 22 ns + (0,16 ns/pF) CL D → O n 5 95 190 ns 68 ns + (0,55 ns/pF) CL HIGH to LOW 10 t PHL 35 75 ns 24 ns + (0,23 ns/pF) CL 15 25 55 ns 17 ns + (0,16 ns/pF) CL 5 85 170 ns 58 ns + (0,55 ns/pF) CL LOW to HIGH 10 t PLH 35 75 ns 24 ns + (0,23 ns/pF) CL 15 25 55 ns 17 ns + (0,16 ns/pF) CL An → O n 5 110 225 ns 83 ns + (0,55 ns/pF) CL HIGH to LOW 10 t PHL 45 95 ns 34 ns + (0,23 ns/pF) CL 15 35 70 ns 27 ns + (0,16 ns/pF) CL 5 95 190 ns 68 ns + (0,55 ns/pF) CL LOW to HIGH 10 t PLH 40 80 ns 29 ns + (0,23 ns/pF) CL 15 30 55 ns 22 ns + (0,16 ns/pF) CL CL → O n 5 85 165 ns 58 ns + (0,55 ns/pF) CL HIGH to LOW 10 t PHL 35 70 ns 24 ns + (0,23 ns/pF) CL 15 25 50 ns 17 ns + (0,16 ns/pF) CL

Philips Semiconductors Product specification 8-bit addressable latch HEF4724B MSI AC CHARACTERISTICS VSS = 0 V; Tamb =2 5°C; CL = 50 pF; input transition times≤ 20 ns Set-up times 5 40 20 ns see also waveforms Fig.5 D → E1 0 t su 15 5 ns 15 10 0 ns 54 0 2 0 n s An → E1 0 t su 20 10 ns 15 15 5 ns Hold times 5 20 0 ns D → E1 0 t hold 15 5 ns 15 15 5 ns 55 0 2 5 n s An → E1 0 t hold 20 10 ns 15 15 5 ns Minimum E 5 75 35 ns pulse width; LOW 10 t WEL 30 15 ns 15 20 10 ns Minimum CL 5 70 35 ns pulse width; HIGH 10 t WCLH 30 15 ns 15 20 10 ns VDD V SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) CL HIGH to LOW 10 t THL 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL 5 60 120 ns 10 ns + (1,0 ns/pF) CL LOW to HIGH 10 t TLH 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL VDD V SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA

Philips Semiconductors Product specification 8-bit addressable latch HEF4724B MSI Fig.5 Waveforms showing minimumE and CL pulse widths, set-up times, hold times. Set-up and hold times are shown as positive values but may be specified as negative values. (1) The address to enable set-up time is the time before the HIGH to LOW enable transition that the address must be stable so that the correct latch is addressed and the other latches are not affected.