455A

455A RENESAS | Alldatasheet

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 148

Technical content

Rev.1.01 Feb 15, 2008 Page 1 of 146 REJ03B0224-0101

DESCRIPTION

The 455A Group is a 4-bit singl e-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 Series using a simple, high-speed instruction set. The computer is equipped with two 8-bit timers (each timer has one or two reload registers), a 16-bit timer for clock count, interrupts, and oscillation circuit switch function. The various microcomputers in the 455A Group include variations of type as shown in the table below.

FEATURES

(at 6 MHz oscillation frequency, in high-speed through-mode) (It depends on operation sour ce clock, oscillation frequency and operation mode)

• T i m e r s a reload register and carrier wave output auto-control function and carrier wave generation circuit
• LCD control circuit
• V oltage drop detection circuit
• Power-on reset circuit
• Watchdog timer
• Clock generating circuit Built-in clock (high-speed/low-speed on-chip oscillator) Main clock (ceramic resonator) Sub-clock (quartz-crystal oscillation)
• LED drive directly enabled (port D) APPLICATION Remote control transmitter Note1.Shipped in blank Table 1 Support Product Part number ROM size ( × 10 bits) RAM size ( × 4 bits) Package ROM type M3455AG8FP (Note 1) 8192 words 512 words PLQP0052JA-A QzROMM3455AG8-XXXFP M3455AGCFP (Note 1) 12288 wordsM3455AGC-XXXFP 455A Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER REJ03B0224-0101 Rev.1.01 Feb 15, 2008

Rev.1.01 Feb 15, 2008 Page 2 of 146 REJ03B0224-0101 455A Group PIN CONFIGURATION Fig 1. Pin configuration (PLQP0052JA-A type) D5/INT CNVss XCIN /D6 XCOUT /D7 RESET XOUT Vss XIN VDD C/CNTR P10/SEG 20 P03/SEG 19 P02/SEG 18 P01/SEG 17 P00/SEG 16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2/VLC1 SEG1/VLC2 SEG0/VLC3 COM3 COM2 COM1 COM0 VDCE P11/SEG21 P12/SEG22 P13/SEG23 P20/SEG24 P21/SEG25 P22/SEG26 P23/SEG27 P30/SEG28 P31/SEG29 P32/SEG30 P33/SEG31 M3455AG8FP M3455AG8-XXXFP M3455AGCFP M3455AGC-XXXFP OUTLINE PLQP0052JA-A (52P6A-A) Pin configuration (top view)

Rev.1.01 Feb 15, 2008 Page 3 of 146 REJ03B0224-0101 455A Group FUNCTIONAL BLOCK DIAGRAM Fig 2. Functional block diagram Port P1 Port P2 Power-on reset circuit Watchdog timer (16 bits) LCD drive control circuit (Max.32 segments × 4 common) Common outputSegment output Port DPort P3 System clock generating circuit XIN-XOUT (Ceramic) XCIN-XCOUT (Quartz-crystal) High-speed/low-speed on-chip oscillator Voltage drop detection circuit Port C ROM 8192/12288 words × 10 bits RAM 512 words × 4 bits (including LCD display RAM 32 words × 4 bits) M em ory I/O port Internal peripheral functions

4500 Series

Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) Stack register SK (8 levels) Interrupt stack register SDP (1 level) ALU (4 bits) Port P04 Tim er 1 (8 bits) Tim er 2 (8 bits) Tim er 3 (16 bits) Tim er LC (4 bits for LCD) Timer

Rev.1.01 Feb 15, 2008 Page 4 of 146 REJ03B0224-0101 455A Group PERFORMANCE OVERVIEW Table 2 Performance overview Parameter Function Number of basic instructions 138 Minimum instruction execution time 0.5 µs (Oscillation frequency 6 MHz: high-speed through mode) Memory sizes ROM M3455AG8 8192 words × 10 bits M3455AGC 12288 words × 10 bits RAM 512 words × 4 bits (including LCD display RAM 32 words × 4 bits) I/O port D 0−D5 I/O (Input is examined by skip decision.) Six independent I/O ports. A pull-up function, a key-on wakeup function and output structure can be switched by software. Port D 5 is also used as INT pin. D6, D7 I/O (Input is examined by skip decision.) Two independent I/O ports; each pin is equipped with a pull-up function and a key-on wakeup function. Both functions can be switched by software. Ports D6 and D7 are also used as XCIN and XCOUT, respectively. P00−P03 I/O 4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched by software. Ports P00−P03 are also used as SEG16−SEG19, respectively. P10−P13 I/O 4-bit I/O port; A pull-up function, a key- on wakeup function and output structure can be switched by software. Ports P1 0−P13 are also used as SEG20−SEG23, respectively. P20−P23 I/O 4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched by software. Ports P20−P23 are also used as SEG24−SEG27, respectively. P30−P33 I/O 4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched by software. Ports P30−P33 are also used as SEG28−SEG31, respectively. C Output 1-bit output; Port C is also used as CNTR pin. Timer Timer 1 8-bit timer with a reload register and carrier wave output auto-control function, and has an event counter. Timer 2 8-bit timer with two reload regist ers and carrier wave generation function. Timer 3 16-bit timer, fixed dividi ng frequency (timer for clock count) Timer LC 4-bit programmable timer with a reload register (for LCD clock generating) Watchdog timer 16-bit timer, fixed di viding frequency (timer for monitor) LCD control circuit Selective bias value 1/2, 1/3 bias Selective duty value 2, 3, 4 duty Common output 4 Segment output 32 Internal resistor for power supply 2r × 3, 2r × 2, r × 3, r × 2 (r = 100 kΩ, (Ta = 25 °C, Typical value)) Voltage drop detection circuit Reset occurrence Typ. 1.7 V (Ta=25 °C) Reset release Typ. 1.8 V (Ta=25 °C) Skip occurrence Typ. 2.0 V (Ta=25 °C) Power-on reset circuit Built-in Interrupt Source 4 sources (one for external, three for timers) Nesting 1 level Subroutine nesting 8 levels Device structure CMOS silicon gate Operating temperature range -20 to 85 °C Power source voltage 1.8 to 5.5 V (It depends on op eration source cl ock, oscillation frequency and operation mode) Power dissipation (Typ. value) At active mode 0.3 mA (Ta = 25 °C, V DD = 3.0 V, f(XIN) = 4 MHz, f(X CIN) = stop, f(HSOCO) = stop, f(LSOCO)=stop, f(STCK) = f(XIN/8) At clock operating mode 5 µA (Ta = 25 °C, VDD = 3.0 V, f(XCIN) = 32 kHz) At RAM back-up 0.1 µA (Ta = 25 °C, output transistor is cut-off state)

Rev.1.01 Feb 15, 2008 Page 5 of 146 REJ03B0224-0101 455A Group PIN DESCRIPTION Table 3 Pin description Pin Name Input/Output Function VDD Power source − Connected to a plus power supply. VSS Power source − Connected to a 0 V power supply. CNVSS CNVSS − Connect this pin to VSS and always apply “L”(0 V) to it. VDCE Voltage drop detection circuit enable Input This pin is used to operate/stop the voltage drop detection circuit. When “H“ level is input to this pin, the circuit starts operating. When “L“ level is input to this pin, the circuit stops operating. XIN Main clock input Input I/O pins of the main clock generating circuit. When using a ceramic resonator, connect it between pins XIN and XOUT. A feedback resistor is built-in between them.XOUT Main clock output Output XCIN Sub clock input Input I/O pins of the sub-clock generating circuit. Connect a 32.768 kHz quartz-crystal oscillator between pins X CIN and X COUT. A feedback resistor is built-in between them. XCIN and XCOUT pins are also used as ports D6 and D7, respectively. XCOUT Sub clock output Output RESET Reset I/O I/O An N-channel open-drain I/O pin for a system reset. When the SRST instruction, watchdog timer, the built-in power-on reset or the voltage drop detection circuit causes the system to be reset, the RESET pin outputs “L” level. D0−D5 I/O port D (Input is examined by skip decision.) I/O Each pin of port D has an independent 1-bit wide I/O function. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Port D 0 to D5 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Port D 5 is also used as INT pin. D6, D7 I/O port D (Input is examined by skip decision.) I/O Each pin of port D has an independent 1-bit wide I/O function. The output structure is N-channel open -drain. Port D 6, D7 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Ports D 6 and D7 are also used as XCIN pin and XCOUT pin, respectively. P00−P03 I/O port P0 I/O Port P0 serves as a 4-bit I/O port. The output structure can be switched to N- channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N- channel open-drain. Port P0 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Ports P00-P03 are also used as SEG16-SEG19, respectively. P10−P13 I/O port P1 I/O Port P1 serves as a 4-bit I/O port. The output structure can be switched to N- channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N- channel open-drain. Port P1 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Ports P1 0-P13 are also used as SEG20-SEG23, respectively. P20−P23 I/O port P2 I/O Port P2 serves as a 4-bit I/O port. The output structure can be switched to N- channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N- channel open-drain. Port P2 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Ports P20–P23 are also used as SEG24–SEG27, respectively. P30−P33 I/O port P3 I/O Port P3 serves as a 4-bit I/O port. The output structure can be switched to N- channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N- channel open-drain. Port P3 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Ports P30–P33 are also used as SEG28–SEG31, respectively. C Output port C Output 1-bit output port. The output stru cture is CMOS. Port C is also used as CNTR pin. COM0− COM3 Common output Output LCD common output pins. Pins COM 0 and COM1 are used at 1/2 duty, pins COM0– COM2 are used at 1/3 duty and pins COM0–COM3 are used at 1/4 duty. SEG0− SEG31 Segment output Output LCD segment output pins. SEG 0– SEG 2 pins are used as V LC3– VLC1 pins, respectively. SEG 16-SEG31 pins are used as Ports P0 0-P03, Ports P1 0-P13, Ports P20-P23, and Ports P30-P33, respectively. CNTR Timer I/O I/O CNTR pin has the function to inpu t the clock for the timer 1 event counter and to output the PWM signal generated by timer 2. CNTR pin is also used as Port C. INT Interrupt input Input INT pin accepts external interrupts. They have the key-on wakeup function which can be switched by software. INT pin is also used as Port D5. VLC3− VLC1 LCD power source − These are the LCD power supply pins. If an internal resistor is used, connect the VLC3 pin to the VDD pin. (If brightness adjustment is required, connect via a resistor.) When using an external power supply, apply voltage such that V SS ≤ VLC1 ≤ VLC2 ≤ VLC3 ≤ VDD. Pins VLC3 to VLC1 also function as pins SEG0 to SEG2.

Rev.1.01 Feb 15, 2008 Page 6 of 146 REJ03B0224-0101 455A Group Note 1. Pins except above have just single function. Note 2. The input/output of D5 can be used even when INT is selected. Be careful when using inputs of both INT and D5 since the input threshold value of INT pin is different from that of port D5. Note 3. “H“ output function of port C can be used even when the CNTR (output) is used. PORT FUNCTION Table 4 Pin description Pin Multifunction Pin Multifunction Pin Multifunction Pin Multifunction P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 P31 P32 P33 C SEG0 SEG1 SEG2 SEG28 SEG29 SEG30 SEG31 INT X CIN XCOUT CNTR V LC3 VLC2 VLC1 SEG28 SEG29 SEG30 SEG31 INT X CIN XCOUT CNTR V LC3 VLC2 VLC1 P30 P31 P32 P33 C SEG SEG1 SEG2 Table 5 Port function Port Pin Input Output Output structure I/O unit Control instructions Control registers Remark Port D D 0−D4, D5/INT I/O (6) N-channel open-drain/ CMOS 1 bit SD, RD SZD, CLD FR1, FR2, I1, K3, PU3 Programmable pull-up, key- on wakeup and output structure selection function D6/XCIN, D7/XCOUT I/O (2) N-channel open-drain RG, K3, PU3 Programmable pull-up and key-on wakeup function Port P0 P0 0/SEG16, P01/SEG17, P02/SEG18, P03/SEG19 I/O (4) N-channel open-drain/ CMOS 4 bits OP0A IAP0 PU0, K0, FR0, C1 Programmable pull-up, key- on wakeup and output structure selection function Port P1 P1 0/SEG20, P11/SEG21, P12/SEG22, P13/SEG23 I/O (4) N-channel open-drain/ CMOS 4 bits OP1A IAP1 PU0, K0, FR0, C2 Programmable pull-up, key- on wakeup and output structure selection function Port P2 P2 0/SEG24, P21/SEG25, P22/SEG26, P23/SEG27, I/O (4) N-channel open-drain/ CMOS 4 bits OP2A IAP2 PU1, K1, FR3, L3 Programmable pull-up, key- on wakeup and output structure selection function Port P3 P3 0/SEG28, P31/SEG29, P32/SEG30, P33/SEG31 I/O (4) N-channel open-drain/ CMOS 4 bits OP3A IAP3 PU2, K2, K3, FR2, C3 Programmable pull-up, key- on wakeup and output structure selection function Port C C/CNTR Output (1) CMOS 1 bit RCP SCP W1, W2, W4 −

Rev.1.01 Feb 15, 2008 Page 7 of 146 REJ03B0224-0101 455A Group CONNECTIONS OF UNUSED PINS (Note when connecting to VSS or VDD) Connect the unused pins to VSS using the thickest wire at the shortest distance against noise. Table 6 Port function Pin Connection Usage condition XIN Connect to VSS. − XOUT Open. − XCIN/D6 Connect to VSS. Pull-up transistor is OFF. The key-on wakeup function is invalid. XCOUT/D7 Open. The key-on wakeup function is invalid. D0−D4 Open. The key-on wakeup function is invalid. Connect to VSS. N-channel open-drain is selected for the output structure. Pull-up transistor is OFF. The key-on wakeup function is invalid. D 5/INT Open. INT pin input is disabled. The key-on wakeup function is invalid. Connect to VSS. N-channel open-drain is selected for the output structure. Pull-up transistor is OFF. The key-on wakeup function is invalid. C/CNTR Open. CNTR input is not selected for timer 1 count source. 0/SEG16− P03/SEG19 Open. The key-on wakeup function is invalid. Connect to VSS. Segment output is not selected. N-channel open-drain is selected for the output structure. Pull-up transistor is OFF. The key-on wakeup function is invalid. 0/SEG20− P13/SEG23 Open. The key-on wakeup function is invalid. Connect to VSS. Segment output is not selected. N-channel open-drain is selected for the output structure. Pull-up transistor is OFF. The key-on wakeup function is invalid. P20/SEG24− P23/SEG27 Open. The key-on wakeup function is invalid. Connect to VSS. Segment output is not selected. N-channel open-drain is selected for the output structure. Pull-up transistor is OFF. The key-on wakeup function is invalid. P30/SEG28− P33/SEG31 Open. The key-on wakeup function is invalid. Connect to VSS. Segment output is not selected. N-channel open-drain is selected for the output structure. Pull-up transistor is OFF. The key-on wakeup function is invalid. COM0–COM3 Open. − SEG0/VLC3 Open. SEG 0 pin is selected. SEG1/VLC2 Open. SEG 1 pin is selected. SEG2/VLC1 Open. SEG 2 pin is selected. SEG3–SEG15 Open. −

Rev.1.01 Feb 15, 2008 Page 8 of 146 REJ03B0224-0101 455A Group DEFINITION OF CLOCK AND CYCLE

• Operation source clock The operation source clock is the source clock to operate this product. In this product, the following clocks are used.
• Clock (f(XIN)) by the external ceramic resonator
• Clock (f(XIN)) by the external input
• Clock (f(HSOCO)) of the high-speed on-chip oscillator which is the internal oscillator
• Clock (f(XCIN)) by the external quartz-crystal oscillation
• Clock (f(LSOCO)) by the low-speed on-chip oscillator
• System clock (STCK) The system clock is the basic clock for controlling this product. The system clock is selected by the clock control register MR shown as the table below.
• Machine cycle The machine cycle is the standard cycle required to execute the instruction.
• Instruction clock (INSTCK) The instruction clock is the basic clock for controlling CPU. The instruction clock (INSTCK) is a signal derived by dividing the system clock (STCK) by 3. The one instruction clock cycle generates the one machine cycle. Note 1. The f(HSOCO)/8 is selected after system is released from reset Table 7 Table Selection of system clock Register MR System clock Operation modeMR3 MR2 MR1 MR0 1 1 0 0 f(STCK) = f(HSOCO)/8 Internal frequency divided by 8 mode 1 0 0 0 f(STCK) = f(HSOCO)/4 Internal frequency divided by 4 mode 0 1 0 0 f(STCK) = f(HSOCO)/2 Internal frequency divided by 2 mode 0 0 0 0 f(STCK) = f(HSOCO) Internal frequency through mode 1 1 0 1 f(STCK) = f(X IN)/8 High-speed frequency divided by 8 mode 1 0 0 1 f(STCK) = f(X IN)/4 High-speed frequency divided by 4 mode 0 1 0 1 f(STCK) = f(X IN)/2 High-speed frequency divided by 2 mode 0 0 0 1 f(STCK) = f(X IN) High-speed through mode 1 1 1 0 f(STCK) = f(X CIN)/8 Low-speed frequency divided by 8 mode 1 0 1 0 f(STCK) = f(X CIN)/4 Low-speed frequency divided by 4 mode 0 1 1 0 f(STCK) = f(X CIN)/2 Low-speed frequency divided by 2 mode 0 0 1 0 f(STCK) = f(X CIN) Low-speed through mode 1 1 1 1 f(STCK) = f(LSOCO)/8 Internal Low-speed frequency divided by 8 mode 1 0 1 1 f(STCK) = f(LSOCO)/4 Internal Low-speed frequency divided by 4 mode 0 1 1 1 f(STCK) = f(LSOCO)/2 Internal Low-speed frequency divided by 2 mode 0 0 1 1 f(STCK) = f(LSOCO) Internal Low-speed through mode

Rev.1.01 Feb 15, 2008 Page 9 of 146 REJ03B0224-0101 455A Group PORT BLOCK DIAGRAM Fig 3. Port block diagram (1) Register Y Decoder Skip decision SZD instruction SD instruction RD instruction CLD instruction FR20 D4iNote2)S R Q Register Y Decoder Skip decision SZD instruction SD instruction RD instruction CLD instruction FR1iiNote3j iNote1j iNote1j D0\`D3iNote2jS R Q iNote1j iNote1j D5/INTiNote2j External 0 interrupt External 0 interrupt circuit Key-on wakeup input Timer 1 count start synchronous circuit input iNote5j Register Y Decoder Skip decision SZD instruction SD instruction RD instruction CLD instruction FR21 S R Q Edge detection circuit Key-on wakeup input K3j PU3j iNote4j Pull-up transistor PU32 Pull-up transistor Key-on wakeup input K32 PU32 Pull-up transistor Key-on wakeup input K32 iNote4j iNote1j iNote1j Edge detection circuit Edge detection circuit Notes 1. This symbol represents a parasitic diode on the port. 2. Applied potential to these ports must be VDD or less. 3. i represents bits 0 to 3. 4. j represents bits 0 to 1. 5. As for details, refer to the external interrupt structure.

Rev.1.01 Feb 15, 2008 Page 10 of 146 REJ03B0224-0101 455A Group Fig 4. Port block diagram (2) Register Y Decoder SD instruction RD instruction CLD instruction (Note 1) (Note 1) XCIN/D6 (Note 2) S R Q RG2 Register Y Decoder SD instruction RD instruction CLD instruction (Note 1) (Note 1) XCOUT/D7 (Note 2) S R Q RG2 Quartz-crystal oscillation circuitSub-clock input RG2 (Note 1) (Note 1) C/CNTR (Note 2) SCP instruction RCP instruction S R Q PWMOD D T Q R Timer 1 underflow signal W41 W12 W10 W11 Clock input for timer 1 event count Key-on wakeup input Pull-up transistor SZD instruction Skip decision Edge detection circuit PU33 K33 Pull-up transistor PU33 SZD instruction Skip decision Key-on wakeup input Edge detection circuit K33 Notes 1. This symbol represents a parasitic diode on the port. 2. Applied potential to these ports must be VDD or less.

Rev.1.01 Feb 15, 2008 Page 11 of 146 REJ03B0224-0101 455A Group Fig 5. Port block diagram (3) Edge detection circuit Key-on wakeup input IAP0 instruction OP0A instruction iNote1j iNote1j K01 Ak Register A Ak (Note 4) D T Q FR01 PU01 Pull-up transistor C1k (Note 4) LCD power supply LCD power supply LCD control signal C1k01 Edge detection circuit Key-on wakeup input IAP0 instruction OP0A instruction (Note 1) (Note 1) P00/SEG16, P01/SEG17 (Note 2) K00 Aj Register A Aj (Note 3) D T Q FR00 PU00 Pull-up transistor C1j (Note 3) LCD power supply LCD power supply LCD control signal C1j01 (Note 3) P02/SEG18, P03/SEG19 iNote2j (Note 4) Notes 1. This symbol represents a parasitic diode on the port. 2. Applied potential to these ports must be VDD or less. 3. j represents bits 0, 1. 4. k represents bits 2, 3.

Rev.1.01 Feb 15, 2008 Page 12 of 146 REJ03B0224-0101 455A Group Fig 6. Port block diagram (4) Edge detection circuit Key-on wakeup input IAP1 instruction OP1A instruction iNote 1j iNote 1j K03 Ak Register A Ak iNote4j D T Q FR03 PU03 Pull-up transistor C2k iNote 4j LCD power supply LCD power supply LCD control signal C2k01 Edge detection circuit Key-on wakeup input IAP1 instruction OP1A instruction (Note 1) (Note 1) P10/SEG20, P11/SEG21 (Note 2) K02 Aj Register A Aj i ’3j D T Q FR02 PU02 Pull-up transistor C2j (Note 3) LCD power supply LCD power supply LCD control signal C2j01 (Note 3) P12/SEG22, P13/SEG23 iNote 2j iNote 4j Notes 1. This symbol represents a parasitic diode on the port. 2. Applied potential to these ports must be VDD or less. 3. j represents bits 0, 1. 4. k represents bits 2, 3.

Rev.1.01 Feb 15, 2008 Page 13 of 146 REJ03B0224-0101 455A Group Fig 7. Port block diagram (5) K1k Ak Ak D T Q FR3k PU1k L3k L3k01 P20/SEG24, P21/SEG25 (Note 2) K1j Aj Aj D T Q FR3j PU1j L3j L3j01 P22/SEG26, P23/SEG27 (Note 2) Edge detection circuitKey-on wakeup input IAP2 instruction OP2A instruction Register A (Note 3) Pull-up transistor LCD power supply LCD control signal LCD power supply (Note 3) (Note 3) (Note 1) (Note 1) Edge detection circuit IAP2 instruction OP2A instruction Register A (Note 4) Pull-up transistor LCD power supply LCD control signal (Note 4) LCD power supply (Note 4) (Note 1) (Note 1) Notes 1. This symbol represents a parasitic diode on the port. 2. Applied potential to these ports must be VDD or less. 3. j represents bits 0, 1. 4. k represents bits 2, 3. (Note 3) (Note 4) Key-on wakeup input (Note 3) (Note 3) (Note 4) (Note 4)

Rev.1.01 Feb 15, 2008 Page 14 of 146 REJ03B0224-0101 455A Group Fig 8. Port block diagram (6) IAP3 instruction OP3A instruction iNote1j iNote1j K23 Ak Register A Ak iNote4j D T Q FR23 PU2k Pull-up transistor C3k iNote4j LCD power supply LCD power supply LCD control signal C3k01 IAP3 instruction OP3A instruction iNote1j iNote1j P30/SEG28, P31/SEG29 iNote2j K22 Aj Register A Aj iNote3j D T Q FR22 PU2j Pull-up transistor C3j iNote3j LCD power supply LCD power supply LCD control signal C3j01 iNote3j P32/SEG30, P33/SEG31 iNote2j iNote4j Edge detection circuit Key-on wakeup input Edge detection circuit Key-on wakeup input Notes 1. This symbol represents a parasitic diode on the port. 2. Applied potential to these ports must be VDD or less. 3. j represents bits 0, 1. 4. k represents bits 2, 3. iNote3j iNote4j

Rev.1.01 Feb 15, 2008 Page 15 of 146 REJ03B0224-0101 455A Group Fig 9. Port block diagram (7) SEG3 - SEG 15 LCD power supply LCD power supply LCD control signal LCD control signal COM0 - COM3 LCD power supply LCD power supply LCD control signal LCD control signal LCD power supply LCD control signal LCD control signal (Note 1) (Note 2) (Note 1) (Note 1) (Note 1) (Note 2) Notes 1. This symbol represents a parasitic diode on the port. 2. Applied potential to these ports must be VDD or less.

Rev.1.01 Feb 15, 2008 Page 16 of 146 REJ03B0224-0101 455A Group Fig 10. Port block diagram (8) 0 1 L20 L13 SEG0/VLC3

01 L23

01 L22

01 L21

(Note 2) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 2) (Note 2) LCD power supply LCD power supply LCD power supply LCD control signal LCD control signal LCD power supply LCD power supply (VLC1) LCD power supply (VLC2) Reset signal EPOF instruction POF2 instruction Notes 1. This symbol represents a parasitic diode on the port. 2. Applied potential to these ports must be VDD or less. LCD power supply (VLC3)

Rev.1.01 Feb 15, 2008 Page 17 of 146 REJ03B0224-0101 455A Group Fig 11. External interrupt circuit structure D9 /INT I13 or I11 Key-on wakeup inputK20 K21 EXF0 SNZI0 instruction Skip decision One-sided edge detection circuit Both edges detection circuit Level detection circuit Edge detection circuit (Note 3) (Note 2) External 0 interrupt Timer 1 count start synchronization circuit input Notes 1: This symbol represents a parasitic diode on the port. 2: When I1 2 is 0, “L” level is detected. When I12 is 1, “H” level is detected. 3: When I12 is 0, falling edge is detected. When I12 is 1, rising edge is detected. I12 Falling Rising (Note 1) (Note 1)

Rev.1.01 Feb 15, 2008 Page 18 of 146 REJ03B0224-0101 455A Group FUNCTION BLOCK OPERATIONS CPU (1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-bit data addition, comparison , AND operation, OR operation, and bit manipulation. (2) Register A and carry flag Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to “1” when there is a carry with the AMC instruction (Figure 12). It is unchanged with both A n instruction and AM instruction. The value of A 0 is stored in carry flag CY with the RAR instruction (Figure 13). Carry flag CY can be set to “1” with the SC instruction and cleared to “0” with the RC instruction. (3) Registers B and E Register B is a 4-bit register us ed for temporary storage of 4-bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 14). Register E is undefined after syst em is released from reset and returned from the power down mode. Accordingly, set the initial value. (4) Register D Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 15). Also, when the TABP p instruction is executed at UPTF flag = “1”, the high-order 2 bits of ROM reference data is stored to the low-order 2 bits of register D, the high-order 1 bit of register D is “0”. When the TABP p instruction is executed at UPTF flag = “0”, the contents of register D remains unchanged. The UPTF flag is set to “1” with the SUPT instruction and cleared to “0” with the RUPT instruction. The initial value of UPTF flag is “0”. Register D is undefined after syst em is released from reset and returned from the power down mode. Accordingly, set the initial value. Fig 12. AMC instruction execution example Fig 13. RAR instruction execution example Fig 14. Registers A, B and register E Fig 15. TABP p instruction execution example (CY) <Result> (M(DP)) (A) Addition ALU <Carry> <Clear> RC instruction <Set> SC instruction CY A3 A2 A1 A0 <Rotation> RAR instruction A0 CY A3 A2 A1 TABE instruction TEAB instruction A3 A2 A1 A0 Register ATAB instruction E3 E2 E1 E0E7 E6 E5 E4 B3 B2 B1 B0 Register B Register E A3 A2 A1 A0 Register ATBA instruction B3 B2 B1 B0 Register B A3 A2 A1 A0DR2 DR1 DR0 PCL Register A (4) Low-order 2 bits Register D (3) Register B (4)Middle-order 2 bits ROM Field value p The contents of register D Specifying address TABP p instruction p3 p2 p1 p0p6 p5 p4 PCH 840 The contents of register A High-order 2 bits Flag UPTF = 1; High-order 2 bits of reference data is transferred to the low-order 2 bits of register D. “0” is stored to the high-order 1 bit of register D. Flag UPTF = 0; Data is not transferred to register D.

Rev.1.01 Feb 15, 2008 Page 19 of 146 REJ03B0224-0101 455A Group (5) Stack registers (SKs) and stack pointer (SP) Stack registers are 14-bit registers. Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when;

• branching to an interrupt service routine (referred to as an interrupt service routine),
• performing a subroutine call, or
• executing the table reference instruction (TABP p). Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. The contents of registers SKs are destroyed when 8 levels are exceeded. The register SK nesting level is pointed automatically by 3-bit stack pointer (SP). The contents of the stack pointer (SP) can be transferred to register A with the TASP instruction. Figure 16 shows the stack registers (SKs) structure. Figure 17 shows the example of operation at subroutine call. (6) Interrupt stack register (SDP) Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (S DP) is used to temporarily store the contents of data pointer, carry flag, skip flag, register A, and register B just before an interr upt until returning to the original routine. Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table reference instruction. (7) Skip flag Skip flag controls skip deci sion for the conditional skip instructions and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained. Fig 16. Stack registers (SKs) structure Fig 17. Example of operation at subroutine call Program counter (PC) SK0 SK1 SK2 SK3 SK4 SK5 SK6 SK7 (SP) = 0 (SP) = 1 (SP) = 2 (SP) = 3 (SP) = 4 (SP) = 5 (SP) = 6 (SP) = 7 Stack pointer (SP) points “7” at reset or returning from power down mode. It points “0” by executing the first BM instruction, and the contents of program counter is stored in SK When the BM instruction is executed after eight stack registers are used ((SP) = 7), (SP) = 0 and the contents of SK 0 is destroyed. Executing BM instruction Executing RT instruction (SP) ← 0 (SK0) ← 000116 (PC) ← SUB1 (PC) ← (SK0) (SP) ← 7 Main program Address

000016 NOP

000116 BM SUB1

000216 NOP

SUB1: NOP RT Subroutine Note :Returning to the BM instruction execution address with the RT instruction, and the BM instruction becomes the NOP instruction. . . .

Rev.1.01 Feb 15, 2008 Page 20 of 146 REJ03B0224-0101 455A Group (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call inst ructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PC H (most significant bit to bit 7) which specifies to a ROM page and PC L (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 18). Make sure that the PC H does not specify after the last page of the built-in ROM. (9) Data pointer (DP) Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y . Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure 19). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD , or SZD instruction (Figure 20).

• N o t e Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the power down mode. After system is returned from the power down mode, set these registers. Fig 18. Program counter (PC) structure Fig 19. Data pointer (DP) structure Fig 20. SD instruction execution example a3 a2 a1 a0a6 a5 a4 PCH Specifying page Program counter (PC) p3 p2 p1 p0p6 p5 p4 PCL Specifying address Register Y (4) Data pointer (DP) X2 X1 X0 Y3Z1 Z0 X3 Y2 Y1 Y0 Register X (4) Register Z (2) Specifying RAM digit Specifying RAM file Specifying RAM file group Specifying bit position 0 0 0 1 Register Y (4) Set D3 D2 D1 D0 Port D output latch

Rev.1.01 Feb 15, 2008 Page 21 of 146 REJ03B0224-0101 455A Group PROGRAM MEMORY (ROM) The program memory is a mask ROM. 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 8 shows the ROM size and pages. Figure 21 shows the ROM map of M3455AGD. A part of page 1 (addresses 0080 16 to 00FF 16) is reserved for interrupt addresses (Figure 22). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and th e instruction at the interrupt address is executed. When usin g an interrupt service routine, write the instruction generating th e branch to that routine at an interrupt address. Page 2 (addresses 0100 16 to 017F 16) is the special page for subroutine calls. Subroutines writ ten in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern (bits 9 to 0) of al l addresses can be used as data areas with the TABP p instruction. Note1.In the initial state, data in pages 0 to 63 can be refered with the TABP inst ruction. Data in pages 64 to 95 can be refferd with the TABP p instruction after the SBK instruction is executed.Data in pages 0 to 63 can be referred with the TABP p instruction after the RBK instruction is executed. ROM Code Protect Address When selecting the protect bit write by using a serial programmer or selecting protect enabled for writing shipment by Renesas Technology corp., reading or writing from/to QzROM is disabled by a serial programmer. As for the QzROM product in blank, the ROM code is protected by selecting the protect bit wr ite at ROM writing with a serial programmer. As for the QzROM product shippe d after writing, whether the ROM code protect is used or not can be selected as ROM option setup (“MASK option” written in the mask file converter) when ordering. Fig 21. ROM map of M3455AGC Fig 22. Page 1 (addresses 0080 16 to 00FF16) structure Table 8 ROM size and pages Part number ROM (PROM) size (× 10 bits) Pages M3455AG8 8192 words 64 (0 to 63) M3455AGC (Note 1) 12288 words 96 (0 to 95) Interrupt address page Subroutine special page 000016 007F16 008016 00FF16 010016 017F16 018016 2FFF16 Page 95 Page 0 Page 1 Page 2 Page 3 9 876543210 00FF16 008C16 008A16 008816 Timer 2 interrupt address008616 Timer 1 interrupt address008416 008216 External 0 interrupt address008016 9876543210 Timer 3 interrupt address 008E16

Rev.1.01 Feb 15, 2008 Page 22 of 146 REJ03B0224-0101 455A Group DATA MEMORY (RAM) 1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM ad dress is specified by a data pointer. The data pointer consists of registers Z, X, and Y . Set a value to the data pointer certainly when executing an instruction to access RAM (also, set a value after system returns from power down mode). RAM includes the area for LCD. When writing “1” to a bit corresponding to displayed segment, the segment is turned on. Table 9 shows the RAM size. Figure 23 shows the RAM map.

• N o t e Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in power down mode. After system is returned from the power down mode, set these registers. Fig 23. RAM map Table 9 RAM size and pages Part number RAM size M3455AG8 512 words × 4 bits (2048 bits)M3455AGC Register Z Register Y Register X 0 1 2 3 c12 RAM 512 words~4 bits (2048 bits) 13 14 15 0 1 2 3 Note: The numbers in the shaded area indicate the corresponding segment output pin numbers. c12 13 14 15

Rev.1.01 Feb 15, 2008 Page 23 of 146 REJ03B0224-0101 455A Group INTERRUPT FUNCTION The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the foll owing 3 conditions are satisfied.

• An interrupt activated condition is satisfied (request flag = “1”)
• Interrupt enable bit is enabled (“1”)
• Interrupt enable flag is enabled (INTE = “1”) Table 10 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.) (1) Interrupt enable flag (INTE) The interrupt enable flag (IN TE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to “1” with the EI instruction and disabled when INTE flag is cleared to “0” with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to “0,” so that other interrupts are disabled until the EI instruction is executed. (2) Interrupt enable bit Use an interrupt enable bit of interrupt control registers V1 and V2 to select the corresponding interrupt or skip instruction. Table 11 shows the interrupt request flag, interrupt enable bit and skip instruction. Table 12 shows the interrupt enable bit function. (3) Interrupt request flag When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to “1.” Each interrupt request flag except the voltage dr op detection circuit interrupt request flag is cleared to “0” when either;
• an interrupt occurs, or
• a skip instruction is executed. The voltage drop detection circu it interrupt request flag cannot be cleared to “0” at the state that the activated condition is satisfied. Each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set until a clear condition is satisfied. Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. If more than one inte rrupt request flag is set when the interrupt disable state is released, the interru pt priority level is as follows shown in Table 10. Table 10 Interrupt sources Priority level Interrupt source Interrupt addressInterrupt name Activated condition

1 External 0

2 Timer 1 interrupt Timer 1

3 Timer 2 interrupt Timer 2

4 Timer 3 interrupt Timer 3

Table 11 Interrupt request flag, interrupt enable bit and skip instruction Interrupt name Interrupt request flag Skip instruction Interrupt enable bit External 0 interrupt EXF0 SNZ0 V1 0 Timer 1 interrupt T1F SNZT1 V1 2 Timer 2 interrupt T2F SNZT2 V1 3 Timer 3 interrupt T3F SNZT3 V2 0 Table 12 Interrupt en able bit function Interrupt enable bit Occurrence of interrupt Skip instruction

1 Enabled Invalid

0 Disabled Valid

Rev.1.01 Feb 15, 2008 Page 24 of 146 REJ03B0224-0101 455A Group (4) Internal state during an interrupt The internal state of the microcom puter during an interrupt is as follows (Figure 25).

• Program counter (PC) An interrupt address is set in program c ounter. The address to be executed when returnin g to the main routine is automatically stored in the stack register (SK).
• Interrupt enable flag (INTE) INTE flag is cleared to “0” so that interrupts are disabled.
• Interrupt request flag Only the request flag for the current interrupt source is cleared to “0”.
• Data pointer, carry flag, skip flag, registers A and B The contents of these registers and flags are stored automatically in the interrupt stack register (SDP). (5) Interrupt processing When an interrupt o ccurs, a program at an interrupt address is executed after branching a data store sequence to stack register. Write the branch instruction to an interrupt service routine at an interrupt address. Use the RTI instruction to return from an interrupt service routine. Interrupt enabled by executing th e EI instruction is performed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction, interr upts are enabled after returning the main routine. (Refer to Figure 24) Fig 24. Program example of interrupt processing Fig 25. Internal state when interrupt occurs Fig 26. Interrupt system diagram Main routine Interrupt occurs Interrupt is enabled Interrupt service routine EI RTI : Interrupt enabled state : Interrupt disabled state Each interrupt address
• Program counter (PC) The address of main routine to be executed when returning
• Stack register (SK) 0 (Interrupt disabled)
• Interrupt enable flag (INTE)
• Interrupt request flag (only the flag for the current interrupt source) Stored in the interrupt stack register (SDP) automatically
• Data pointer, carry flag, registers A and B, skip flag Request flag (state retained) Enable bit Enable flag Timer 2 underflow T1F V12 Address 4 in page 1 Timer 1 underflow T2F V13 Address 6 in page 1 T3F V20 Address 8 in page 1 Activated condition INTE Timer 3 underflow EXF0 V10 Address 0 in page 1 INT pin interrupt waveform input

Rev.1.01 Feb 15, 2008 Page 25 of 146 REJ03B0224-0101 455A Group (6) Interrupt control registers

• Interrupt control register V1 Interrupt enable bits of extern al 0, timer 1 and timer 2 are assigned to register V1. Set the co ntents of this register through register A with the TV1A instruction. The TA V1 instruction can be used to transfer the contents of register V1 to register A.
• Interrupt control register V2 The timer 3 interrupt enable bit are assigned to register V2. Set the contents of this register through register A with the TV2A instruction. The TA V2 instructi on can be used to transfer the contents of register V2 to register A. Note 1.“R” represents read enabled, and “W” represents write enabled. (7) Interrupt sequence Interrupts occur only when th e respective INTE flag, interrupt enable bits (V1 0, V12, V13, V30), and interrupt request flag are set to “1.” The interrupt occurs two or three cycles after the cycle where all the above three conditions are satisfied. The interrupt occurs after three machine cycles if instructions other than one-cycle instruction are executed when the conditions are satisfied (Refer to Figure 27). Table 13 Interrupt control registers Interrupt control register V1 at reset : 0000 2 at power down : 00002 R/W TAV1/TV1A V13 Timer 2 interrupt enable bit 0 Interrupt disabled (SNZT2 instruction is valid)

1 Interrupt enabled (SNZT2 instruction is invalid)

V12 Timer 1 interrupt enable bit 0 Interrupt disabled (SNZT1 instruction is valid)

1 Interrupt enabled (SNZT1 instruction is invalid)

V11 Not used 0 This bit has no function, but read/write is enabled.1 V10 External 0 interrupt enable bit 0 Interrupt disabled (SNZ0 instruction is valid)

1 Interrupt enabled (SNZ0 instruction is invalid)

Interrupt control register V2 at reset : 0000 2 at power down : 00002 R/W TAV2/TV2A V23 Not used 0 This bit has no function, but read/write is enabled.1 V22 Not used 0 This bit has no function, but read/write is enabled.1 V21 Not used 0 This bit has no function, but read/write is enabled.1 V20 Timer 3 interrupt enable bit 0 Interrupt disabled (SNZT3 instruction is valid)

1 Interrupt enabled (SNZT3 instruction is invalid)

Rev.1.01 Feb 15, 2008 Page 26 of 146 REJ03B0224-0101 455A Group Fig 27. Interrupt sequence T3T2T1 1 machine cycle System clock (STCK) Interrupt enable flag (INTE) INT T1F T2F T3F The program starts from the interrupt address. Interrupt activated condition is satisfied. Flag cleared 2 to 3 machine cycles (Notes 1, 2) EXF0 External 0 interrupt Timer 1 Timer 2 Timer 3 interrupt When an interrupt request flag is set after its interrupt is enabled EI instruction execution cycle Interrupt enabled state Interrupt disabled state Retaining level of system clock for 4 periods or more is necessary. Notes 1: The address is stacked to the last cycle. 2: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied. T3T2T1 T3T2T1 T3T2T1 T2T1

Rev.1.01 Feb 15, 2008 Page 27 of 146 REJ03B0224-0101 455A Group EXTERNAL INTERRUPTS The 455A Group has the external 0 interrupt. An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). The external interrupt can be controlled with the interrupt control register I1. Fig 28. External interrupt circuit structure Table 14 External interrupt activated conditions Name Input pin Activated condition Valid waveform selection bit External 0 interrupt D 5/INT When the next waveform is input to D 5/INT pin

• Falling waveform (“H” → “L”)
• Both rising and falling waveforms I11 I12 Key-on wakeup input SNZI0 instruction (Note 1) K21 1Edge detection circuit Level detection circuit D5/INT I13 I12 Falling Rising K20 I11 One-sided edge detection circuit Both edges detection circuit Skip EXF0 External 0 interrupt Timer 1 count start synchronization circuit input (Note 2) (Note 3) Note 1: This symbol represents a parasitic diode on the port. 2: When I12= 0(X=0 or 1) is 0, “L” level is detected. When I12 is 1, “H” level is detected. 3: When I12 is 0, falling edge is detected. When I12 is 1, rising edge is detected. (Note 1) or

Rev.1.01 Feb 15, 2008 Page 28 of 146 REJ03B0224-0101 455A Group (1) External 0 interrupt request flag (EXF0) External 0 interrupt request flag (EXF0) is set to “1” when a valid waveform is input to D5/INT pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 27). The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the interrupt contro l register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip instruction.

• External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to D 5/INT pin. The valid waveform can be sele cted from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 0 interrupt is as follows. (1) Set the bit 3 of register I1 to “1” for the INT pin to be in the input enabled state. (2) Select the valid waveform with the bits 1 and 2 of register I1. (3) Clear the EXF0 flag to “0” with the SNZ0 instruction. (4) Set the NOP instruction for the case when a skip is performed with the SNZ0 instruction. (5) Set both the external 0 interrupt enable bit (V1 0) and the INTE flag to “1.” The external 0 interrupt is now enabled. Now when a valid waveform is input to the D5/INT pin, the EXF0 flag is set to “1” and the external 0 interrupt occurs. (2) External interrupt control registers (1) Interrupt cont rol register I1 Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents of register I1 to register A. Note 1.“R” represents read enabled, and “W” represents write enabled. Note 2.When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Table 15 External interrupt control register Interrupt control register I1 at reset : 0000 2 at power down : state retained R/W TAI1/TI1A I13 INT pin input control bit (Note 2) 0 INT pin input disabled

1 INT pin input enabled

Interrupt valid waveform for INT pin/ return level selection bit (Note 2)

0 Falling waveform (“L” level of INT pin is recognized with the SNZI0

instruction)/“L” level

1 Rising waveform (“H” level of INT pin is recognized with the SNZI0

instruction)/“H” level I11 INT pin edge detection circuit control bit 0 One-sided edge detected

1 Both edges detected

INT pin timer 1 count start synchronous cir- cuit selection bit

0 Timer 1 count start synchronous circuit not selected

1 Timer 1 count start synchronous circuit selected

Rev.1.01 Feb 15, 2008 Page 29 of 146 REJ03B0224-0101 455A Group (3) Notes on interrupts (1) Bit 3 of register I1 When the input of the INT pin is controlled with the bit 3 of register I1 in software, be careful about the following notes.

• Depending on the input state of the D 5/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In or der to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to (1) in Figure 29.) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to (2) in Figure 29.). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instru ction (refer to (3) in Figure 29.). Fig 29. External 0 interrupt program example-1 (2) Bit 3 of register I1 When the bit 3 of register I1 is cleared to “0”, the power down mode is selected and the input of INT pin is disabled, be careful about the following notes.
• When the INT pin input is disabled (register I1 3 = “0”), set the key-on wakeup of INT pin to be invalid (register K2 0 = “0”) before system enters to power down mode. (refer to (1) in Figure 30.). Fig 30. External 0 interrupt program example-2 (3) Bit 2 of register I1 When the interrupt valid wa veform of the INT pin is changed with the bit 2 of regist er I1 in software, be careful about the following notes.
• Depending on the input state of the D 5/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In or der to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to (1) in Figure 31.) and then, cha nge the bit 2 of register I1 is changed. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to (2) in Figure 31.). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instru ction (refer to (3) in Figure 31.). Fig 31. External 0 interrupt program example-3 LA 4 ; ( ×××02) LA 8 ; (1 ×××2) TI1A ; Control of INT pin input is changed SNZ0 ; The SNZ0 instruction is executed (EXF0 flag cleared) ×: these bits are not used here.
• •• LA 0 ; ( ×××02) DI EPOF POF2 ; RAM back-up
• •• ×: these bits are not used here. LA 4 ; ( ×××02) LA 12 ; ( ×1××2) TI1A ; Interrupt valid waveform is changed SNZ0 ; The SNZ0 instruction is executed (EXF0 flag cleared)
• •• ×: these bits are not used here.

Rev.1.01 Feb 15, 2008 Page 30 of 146 REJ03B0224-0101 455A Group TIMERS The 455A Group has the following timers.

• Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be se t. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt request flag is set to “1,” new data is loaded from the reload register, and count continues (auto-reload function).
• Fixed dividing frequency timer The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to “1” after every n count of a count pulse. Fig 32. Auto-reload function n+1 count Reload n+1 count An interrupt occurs or a skip instruction is executed. 1st underflow Reload 2nd underflow FF16 Time n 0016 “1” “0” n : Counter initial value The contents of counter Timer interrupt request flag Count starts

Rev.1.01 Feb 15, 2008 Page 31 of 146 REJ03B0224-0101 455A Group The 455A Group timer consists of the following circuits.

• Prescaler : 8-bit programmable timer
• Timer 1 : 8-bit programmable timer
• Timer 2 : 8-bit programmable timer
• Timer 3 : 16-bit fixed frequency timer
• Timer LC : 4-bit programmable timer
• Watchdog timer: 16-bit fixed frequency timer (Timers 1, 2 and 3 have the interrupt function, respectively) Prescaler, timer 1, timer 2, timer 3 and timer LC can be controlled with the timer control registers PA and W1 to W5. The watchdog timer is a free counter which is not controlled with the control register. Each function is described below. Table 16 Function related timers Circuit Structure Count source Frequency dividing ratio Use of output signal Control register Prescaler 8-bit programmable binary down counter
• Instruction clock (INSTCK) 1 to 256 • Timer 1 count source
• Timer 2 count source
• Timer 3 count source PA Timer 1 8-bit programmable binary down counter (link to INT input) (carrier wave output auto- control function)
• PWM signal (PWMOUT)
• Prescaler output (ORCLK)
• Timer 3 underflow (T3UDF)
• CNTR input 1 to 256 • CNTR output control
• Timer 1 interrupt Timer 2 8-bit programmable binary down counter (with carrier wave generation function) IN input
• Prescaler output divided by 2 (ORCLK/2) 1 to 256 • Timer 1 count source
• CNTR output
• Timer 2 interrupt Timer 3 16-bit fixed dividing frequency
• X CIN input
• Prescaler output (ORCLK)
• High-speed on-chip oscillator (f(HSOCO))
• Low-speed on-chip oscillator (f(LSOCO)) 512 1024 2048 4096 8192 16384 32768 65536
• Timer 1 count source
• Timer LC count source
• Timer 3 interrupt Timer LC 4-bit programmable binary down counter
• Bit 4 of timer 3 (T3
• System clock (STCK) 1 to 16 • LCD clock W4 Watchdog timer 16-bit fixed dividing frequency
• Instruction clock (INSTCK) 65536 • System reset (counting twice)
• Decision of flag WDF1

Rev.1.01 Feb 15, 2008 Page 32 of 146 REJ03B0224-0101 455A Group Fig 33. Timers structure (1) XIN ORCLK ORCLK W21 Timer 2 (8) Reload register R2L (8) Register B (TAB2) (T2AB) Register A (T2AB)(T2AB) (TAB2) Timer 2 interrupt W11, W10 PWMOUT ORCLK W12 W40 Timer 1 (8) Reload register R1 (8) Register B (TAB1) (T1AB) Register A (T1AB) (T1AB) (TAB1) T1F Timer 1 interrupt Timer 1 underflow signal (T1UDF) T3UDF MR3, MR2Division circuit Divided by 8 Divided by 4 Divided by 2 Internal clock generating circuit (divided by 3) System clock (STCK) Instruction clock (INSTCK) Prescaler (8)PA0 Reload register RPS (8) Register B (TABPS) (TPSAB) Register A (TPSAB)(TPSAB) (TABPS) (TR1AB) D5/INT I13 I12 I11 One-sided edge detection circuit Both edges detection circuit S R Q I10 W13 T1UDF C/CNTR W11 W10 PWMOUT Q D R T W12 W41 T1UDF I10 Port C output W20 Reload register R2H (8) Register B Register A Reload control circuit “H” interval expansion W22 0(T2R2L) (T2HAB) T2F Q R T W23 PWMOD Data is set automatically from each reload register when timer underflows (auto-reload function). XIN MR1, MR0 High-speed on-chip oscillator Ceramic resonance X‚b‚hN Quartz-crystal oscillation Low-speed on-chip oscillator

Rev.1.01 Feb 15, 2008 Page 33 of 146 REJ03B0224-0101 455A Group Fig 34. Timers structure (2) Note 1: Flag WDF1 is cleared to “0” and the next instruction is skipped when the WRST instruction is executed while flag WDF1 = “1”. The WRST instruction is equivalent to the NOP instruction while flag WDF1 = “0”. 2: Flag WEF is cleared to “0” and watchdog timer reset does not occur when the DWDT instruction and WRST instruction are executed continuously. 3: The WEF flag is set to “1” at system reset or RAM back-up mode. Data is set automatically from each reload register when timer underflows (auto-reload function). 111 W32AW31AW30 Timer3 (16) 1 - - 4 - - - - - 9 10 11 12 13 14 15 16 W51, W50 W33 XCIN ORCLK Low-speed OCO High-speed OCO Watchdog reset signal reset signal (Note 2) D T Q R DWDT instruction WRST instruction Reset signal (Note 3) (Note 1) WRST instruction Watchdog timer (16) S R Q WDF1 S R Q WEF W42 W43 Timer LC (4) Reload register RLC (4) (TLCA) (TLCA) Register A STCK LCD clock1/2 100 110 101 011 010 000 001 Timer 3 interruptT3F Timer 3 underflow signal (T3UDF)

Rev.1.01 Feb 15, 2008 Page 34 of 146 REJ03B0224-0101 455A Group Note 1. “R” represents read enabled, and “W” represents write enabled. Note 2. This function is valid only when the timer 1 control start synchronous circuit is selected (I10 =“1”). Note 3. Port C output is invalid when CNTR input is selected for the timer 1 count source. Table 17 Timer control registers Timer control register PA at reset : 0 2 at power down : 02 W TPAA PA0 Prescaler control bit 0 Stop (state retained) 1O p e r a t i n g Timer control register W1 at reset : 0000 2 at power down : state retained R/W TAW1/TW1A W13 Timer 1 count auto-stop circuit selection bit (Note 2)

0 Timer 1 count auto-stop circuit not selected

1 Timer 1 count auto-stop circuit selected

W12 Timer 1 control bit 0 Stop (state retained) 1O p e r a t i n g Timer 1 count source selection bits (Note 3) W11 W10 Count source W11 0 0 PWM signal (PWMOUT) 0 1 Prescaler output (ORCLK) 1 0 Timer 3 underflow signal (T3UDF)W1 1 1 CNTR input Timer control register W2 at reset : 0000 2 at power down : 00002 R/W TAW2/TW2A W23 CNTR pin function control bit 0 CNTR pin output invalid

1 CNTR pin output valid

“H” interval expansion function control bit

0 PWM signal “H” interval expansion function invalid

1 PWM signal “H” interval expansion function valid

W21 Timer 2 control bit 0 Stop (state retained) 1O p e r a t i n g W20 Timer 2 count source selection bit 0X IN input

1 Prescaler output (ORCLK)/2

Timer control register W3 at reset : 0000 2 at power down : state retained R/W TAW3/TW3A W33 Timer 3 control bit 0 Stop (initial state)

1 Operating

Timer 3 count value selection bits W32 W31 W30 Count value

000 Underflow every 512 count

001 Underflow every 1024 count

010 Underflow every 2048 count

011 Underflow every 4096 count

100 Underflow every 8192 count

101 Underflow every 16384 count

110 Underflow every 32768 count

111 Underflow every 65536 count

Timer control register W4 at reset : 0000 2 at power down : state retained R/W TAW4/TW4A W43 Timer LC control bit 0 Stop (state retained) 1O p e r a t i n g W42 Timer LC count source selection bit 0B i t 4 ( T 34) of timer 3

1 System clock (STCK)

CNTR pin output auto-control circuit selection bit

0 CNTR output auto-control circuit not selected

1 CNTR output auto-control circuit selected

W40 CNTR pin input count edge selection bit 0 Falling edge

1 Rising edge

Rev.1.01 Feb 15, 2008 Page 35 of 146 REJ03B0224-0101 455A Group (1) Timer control registers

• Timer control register PA Register PA controls the count operation of prescaler. Set the contents of this register through register A with the TPAA instruction.
• Timer control register W1 Register W1 controls the coun t operation and count source of timer 1, and timer 1 count auto-stop circuit. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A.
• Timer control register W2 Register W2 controls the coun t operation and count source of timer 2, CNTR pin output, an d extension function of PWM signal “H” interval. Set the cont ents of this re gister through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the cont ents of register W2 to register
• Timer control register W3 Register W3 controls the coun t operation and count value of timer 3. Set the contents of this register through register A with the TW3A instruction. The TAW3 instruction can be used to transfer the contents of register W3 to register A.
• Timer control register W4 Register W4 controls the input count edge of CNTR pin, CNTR1 pin output auto-control circuit. Set the contents of this register through register A with the TW4A instruction. The TAW4 instruction can be used to transfer the contents of register W4 to register A.
• Timer control register W5 Register W5 controls the count source of timer 3. Set the contents of this register th rough register A with the TW5A instruction. The TAW5A instruction can be used to transfer the contents of register W5 to register A. (2) Prescaler Prescaler is an 8-bit binary down counter with the prescaler reload register PRS. Data can be set simultaneously in prescaler and the reload register RPS with the TPSAB instruction. Data can be read from reload re gister RPS with the TABPS instruction. Stop counting and then execute the TPSAB or TABPS instruction to read or set prescaler data. Prescaler starts counting after the following process; (1) set data in prescaler, and (2) set the bit 0 of register PA to “1.” When a value set in reload register RPS is n, prescaler divides the count source signal by n + 1 (n = 0 to 255). Count source for prescaler can be selected the instruction clock (INSTCK). Once count is started, when prescaler underflows (the next count pulse is input after the contents of prescaler becomes “0”), new data is loaded from reload regi ster RPS, and count continues (auto-reload function). The output signal (ORCLK) of prescaler can be used for timer 1, 2 and 3 count sources. Timer control register W5 at reset : 0000 2 at power down : state retained R/W TAW5/TW5A W53 Not used 0 This bit has no function, but read/write is enabled. 1 This bit has no function, but read/write is enabled. W52 Not used 0 This bit has no function, but read/write is enabled. 1 This bit has no function, but read/write is enabled. W51 Timer 3 count source selection bits W51W52 Count source

00 XCIN input

01 ORCLK input

10 Low-speed on-chip oscillator

11 High-speed on-chip oscillator

Rev.1.01 Feb 15, 2008 Page 36 of 146 REJ03B0224-0101 455A Group (3) Timer 1 (interrupt function) Timer 1 is an 8-bit binary down counter with a timer 1 reload register (R1). Data can be set simultaneously in timer 1 and the reload register R1 with the T1AB instruction. Data can be read from timer 1 with the TAB1 instruction. Stop counting and then execute the T1AB or TAB1 instruction to read or set timer 1 data. When executing the TR1AB instru ction to set data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows. Timer 1 starts counting after the following process; (1) set data in timer 1 (2) set count source by bit 0 and 1 of register W1, and (3) set the bit 2 of register W1 to “1.” When a value set in reload register R1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when time r 1 underflows (the next count pulse is input after the contents of timer 1 becomes “0”), the timer 1 interrupt request flag (T1F) is set to “1,” new data is loaded from reload register R1, and count continues (auto-reload function). The INT pin input can be used as the start trigger for timer 1 count operation by setting “1” in bit 0 of interrupt control register l1. Also, in this time, the auto-stop function by timer 1 underflow can be performed by setting the bit 3 of register W1 to “1.” (4) Timer 2 (interrupt function) Timer 2 is an 8-bit binary down counter with two timer 2 reload register (R2L, R2H). Data can be set simultaneously in timer 2 and the reload register R2L with the T2AB instruction. Data can be set in the reload register R2H with the T2HAB instruction. The contents of reload register R2L set with the T2AB instruction can be set to timer 2 again with the T2R2L instruction. Data can be read from timer 2 with the TAB2 instruction. Stop counting and then execute the T2AB or TAB2 instruction to read or set timer 2 data. When executing the T2 HAB instruction to set data to reload register R2H while timer 2 is operating, avoid a timing when timer 2 underflows. Timer 2 starts counting after the following process; (1) set data in timer 2 (2) set count source by bi t 0 of register W2, and (3) set the bit 1 of register W2 to “1.” When a value set in reload register R2L is n and R2H is m, timer 2 divides the count source signal by n + 1 or m + 1 (n = 0 to 255, m = 0 to 255). Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes “0”), the timer 2 interrupt request flag (T2F) is set to “1,” new data is loaded from reload register R2 L, and count continues (auto- reload function). When bit 3 of register W2 is set to “1”, timer 2 reloads data from reload register R2L and R2H alternately each underflow. Timer 2 generates the PWM si gnal (PWMOUT) of the “L” interval set as reload register R2L, and the “H” interval set as reload registerR2H. The PWM signal (PWMOUT) is output from CNTR pin. When bit 2 of regi ster W2 is set to “1” at this time, the interval (PWM signal “H” interval) set to reload register R2H for the counter of timer 2 is extended for a half period of count source. In this case, when a value set in reload register R2H is m, timer 2 divides the count source signal by n + 1.5 (m = 1 to 255). When this function is used, set “1” or more to reload register R2H. When bit 1 of register W4 is set to “1”, the PWM signal output to CNTR pin is switched to valid /invalid each timer 1 underflow. However, when timer 1 is stopped (bit 2 of register W1 is cleared to “0”), this function is canceled. Even when bit 1 of a register W2 is cleared to “0” in the “H” interval of PWM signal, timer 2 does not stop until it next timer 2 underflow. When clearing bit 1 of register W2 to “0” to stop timer 2, avoid a timing when timer 2 underflows.

Rev.1.01 Feb 15, 2008 Page 37 of 146 REJ03B0224-0101 455A Group (5) Timer 3 (interrupt function) Timer 3 is a 16-bit binary down counter. Timer 3 starts counting after the following process; (1) set count value by bits 0, 1 and 2 of register W3, (2) set count source by bit 0 and 1 of register W5, and (3) set the bit 3 of register W3 to “1.” Once count is starte d, when timer 3 underflows (the set count value is counted), the timer 3 interrupt request flag (T3F) is set to “1,” and count continues. Bit 4 of timer 3 can be used as the timer LC count source for the LCD clock generating. When bit 3 of register W3 is cleared to “0”, timer 3 is initialized to “FFFF 16” and count is stopped. Timer 3 can be used as the counter for clock because it can be operated at clock operating mode (POF instruction execution). When timer 3 underflow occurs at clock operating mode, system returns from the power down state. When operating timer 3 during clock operating mode, set 1 cycle or more of count source to th e following period; from setting bit 3 of register W3 to “1” till executing the POF instruction. (6) Timer LC Timer LC is a 4-bit binary do wn counter with the timer LC reload register (RLC). Data can be set simultaneously in timer LC and the reload register (R LC) with the TLCA instruction. Data cannot be read from timer LC. Stop counting and then execute the TLCA instruction to set timer LC data. Timer LC starts counting after the following process; (1) set data in timer LC, (2) select the count source with the bit 2 of register W4, and (3) set the bit 3 of register W4 to “1.” When a value set in reload register RLC is n, timer LC divides the count source signal by n + 1 (n = 0 to 15). Once count is started, when timer LC underflows (the next count pulse is input after the contents of timer LC becomes “0”), new data is loaded from reload regi ster RLC, and count continues (auto-reload function). Timer LC underflow signal divided by 2 can be used for the LCD clock. (7) Timer input/output pin (C/CNTR pin) CNTR pin is used to input the timer 1 count source and output the PWM signal generated by timer 2. The selection of CNTR output signal can be controlled by bit 3 of register W2. When the PWM signal is output from C/CNTR pin, set “0” to the output latch of port C. When the CNTR input is selected for timer 1 count source, timer 1 counts the waveform of CN TR input selected by bit 0 of register W4. Also, when the CN TR input is selected, the output of port C is invalid (high-impedance state). (8) Timer interrupt request flags (T1F, T2F, T3F) Each timer interrupt request flag is set to “1” when each timer underflows. The state of these flags can be examined with the skip instructions (SNZT1, SNZT2, SNZT3). Use the interrupt control register V1, V2 to select an interrupt or a skip instruction. An interrupt request flag is cl eared to “0” when an interrupt occurs or when the next instruction is skipped with a skip instruction. (9) Count start synchronization circuit (timer 1) Timer 1 has the count start synchronous circuit which synchronizes the input of INT pi n, and can start the timer count operation. Timer 1 count start synchronous ci rcuit function is selected by setting the bit 0 of register I1 to “1” and the control by INT pin input can be performed. When timer 1 count start synchronous circuit is used, the count start synchronous circuit is set, the count source is input to timer by inputting valid waveform to INT pin. The valid waveform of INT pin to set the count start synchronous circuit is the same as the external interrupt activated condition. Once set, the count start s ynchronous circuit is cleared by clearing the bit I1 0 to “0” or system reset. However, when the count auto-st op circuit is selected, the count start synchronous circuit is clea red (auto-stop) at the timer 1 underflow. (10)Count auto-stop circuit (timer 1) Timer 1 has the count auto-stop circuit which is used to stop timer 1 automatically by the timer 1 underflow when the count start synchronous circuit is used. The count auto-stop circuit is valid by setting the bit 3 of register W1 to “1”. It is cleared by the timer 1 underflow and the count source to timer 1 is stopped. This function is valid only when the timer 1 count start synchronous circuit is selected.

Rev.1.01 Feb 15, 2008 Page 39 of 146 REJ03B0224-0101 455A Group Fig 37. Timer 2 operation example Timer 2 count source Timer 2 start Timer 2 count value (Reload register) Timer 2 underflow signal PWM signal 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 00160316 (R2L) (R2L) (R2L) (R2L) (R2L) PWM1 signal “L” fixed - CNTR pin output invalid (W23=0) Timer 2 count source Timer 2 start Timer 2 count value (Reload register) Timer 2 underflow signal PWM signal 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 01160316 (R2L) (R2H) (R2L) (R2H) (R2L) (R2H) PWM period 7 clock PWM period 7 clock * : “0316” is set to reload register R3L and “0216” is set to reload register R3H. 4 clock 3 clock 4 clock 3 clock 4 clock Timer 2 count source Timer 2 start Timer 2 count value (Reload register) Timer 2 underflow signal PWM signal 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 02160316 (R2L) (R2H) (R2L) (R2H) (R2L) (R2H) PWM period 7.5 clock PWM period 7.5 clock 4 clock 3.5 clock 4 clock 3.5 clock 4 clock Note: When the PWM signal “H” interval expansion function is valid, set “1” or more to reload register R2H. - CNTR pin output valid (W23=1), PWM signal “H” interval expansion function invalid (W22=0) - CNTR pin output valid (W23=1), PWM signal “H” interval expansion function valid (W22=1) (Note)

Rev.1.01 Feb 15, 2008 Page 40 of 146 REJ03B0224-0101 455A Group Fig 38. CNTR output auto-con trol function by timer 1 Timer 1 start CNTR output start Timer 1 underflow signal PWM signal

• CNTR output auto-control circuit operation example 1 (W23 = “1”, W41 = “1”) CNTR output * When the CNTR1 output auto-control circuit is selected, valid/invalid of CNTR output is repeated every timer 1 underflows.
• CNTR output auto-control circuit operation example 2 (W23 = “1”, W41 = “1”) Timer 1 start CNTR output start Timer 1 underflow signal PWM signal Register W41 Timer 1 stop CNTR output stop CNTR output (1) When the CNTR output auto-control function is not selected while the CNTR output is invalid, CNTR output invalid state is retained. (2) When the CNTR output auto-control function is not selected while the CNTR output is valid, CNTR output valid state is retained. (3) When the timer 1 is stopped, the CNTR output auto-control function becomes invalid. (1) (2) (3)

Rev.1.01 Feb 15, 2008 Page 41 of 146 REJ03B0224-0101 455A Group Fig 39. Timer count start/stop timing (R2H) Timer 2 underflow signal Machine cycle Timer 2 count start timing (R2L = “0216”, R2H = “0216”, W23 = “1”) Register W21 Mi Mi + 1 Mi + 2 Mi + 3 0216001601160216001601160216 (R2L)(R2L) Timer 2 count start timing PWM signal Timer 2 count value (reload register) Timer 2 count source (XIN input) (R2H) Mi Mi + 1 Mi + 2 Mi + 3 001601160216001601160216 0216 Timer 2 count stop timing (R2L)(R2H) (Note 1) TW2A instruction execution (W21←1) TW2A instruction execution (W21←0) Timer 2 underflow signal Machine cycle Register W21 PWM signal Timer 2 count value (reload register) Timer 2 count source (XIN input) Timer 2 count stop timing (R2L = “0216”, R2H = “0216”, W23 = “1”) Notes 1: If the timer count stop timing and the timer underflow timing overlap while the CNTR pin output is valid (W23=“1”), a hazard may occur in the PWM signal waveform. 2: When timer count is stopped during “H” interval of the PWM signal, timer is stopped after the end of the “H” output interval.

Rev.1.01 Feb 15, 2008 Page 42 of 146 REJ03B0224-0101 455A Group WATCHDOG TIMER Watchdog timer provides a method to reset the system when a program run-away occurs. Watchdog timer consists of timer WDT(16-bit binary counter), watchdog timer enable flag (WEF), and watchdog timer flags (WDF1, WDF2). The timer WDT downcounts the instruction clocks (INSTCK) as the count source from “FFFF 16” after system is released from reset. After the count is started, when the timer WDT underflow occurs (after the count value of timer WDT reaches “0000 16,” the next count pulse is input), the WDF1 flag is set to “1.” If the WRST instruction is never executed until the timer WDT underflow occurs (until timer WDT counts 65534), WDF2 flag is set to “1,” and the RESET pin outputs “L” level to reset the microcomputer. Execute the WRST instruction at each period of 65534 machine cycle or less by software when using watchdog timer to keep the microcomputer operating normally. When the WEF flag is set to “1” after system is released from reset, the watchdog timer function is valid. When the DWDT instruction a nd the WRST instruction are executed continuously, the WEF fl ag is cleared to “0” and the watchdog timer function is invalid. The WEF flag is set to “1” at system reset or RAM back-up mode. The WRST instruction has the skip function. When the WRST instruction is executed while the WDF1 flag is “1”, the WDF1 flag is cleared to “0” and the next instruction is skipped. When the WRST instruction is executed while the WDF1 flag is “0”, the next instruction is not skipped. The skip function of the WRST instruction can be used even when the watchdog timer function is invalid. Fig 40. Watchdog timer function (1) Reset released 65534 count (Note) (4) (2)(2) (3) WRST instruction executed (skip occurrence) (5) System reset FFFF16 000016 Value of 16-bit timer (WDT) WDF1 flag WDF2 flag RESET pin output (1) After system is released from reset (= after program is started), timer WDT starts count down. (2) When timer WDT underflow occurs, WDF1 flag is set to “1.” (3) When the WRST instruction is executed while the WDF1 flag is “1”, WDF1 flag is cleared to “0,” the next instruction is skipped. (4) When timer WDT underflow occurs while WDF1 flag is “1,” WDF2 flag is set to “1” and the watchdog reset signal is output. (5) The output transistor of RESET pin is turned “ON” by the watchdog reset signal and system reset is executed. Note: The number of count is equal to the number of machine cycle because the count source of watchdog timer is the instruction clock.

Rev.1.01 Feb 15, 2008 Page 43 of 146 REJ03B0224-0101 455A Group When the watchdog timer is used, clear the WDF1 flag at the period of 65534 machine cycles or less with the WRST instruction. When the watchdog timer is not used, execute the DWDT instruction and the WRST instruction continuously (refer to Figure 41). The watchdog timer is not stopped with only the DWDT instruction. The contents of WDF1 flag and timer WDT are initialized at the power down mode. When using the watchdog timer and the power down mode, initialize the WDF1 flag with th e WRST instruction just before the microcomputer enters the power down mode. Also, set the NOP instruction after the WRST instruction, for the case when a skip is performed with the WRST instruction (refer to Figure 42). Fig 41. Program example to start/stop watchdog timer Fig 42. Program example when using the watchdog timer WRST ; WDF1 flag cleared

• •• DI DWDT ; Watchdog timer fu nction enabled/disabled WRST ; WEF and WDF1 flags cleared
• •• WRST ; WDF1 flag cleared NOP DI ; Interrupt disabled EPOF ; POF instruction enabled POF2 ; RAM back-up mode Oscillation stop

Rev.1.01 Feb 15, 2008 Page 44 of 146 REJ03B0224-0101 455A Group LCD FUNCTION The 455A Group has an LCD (Liquid Crystal Display) controller/ driver. When data are set in LCD RAM and timer LC, LCD control registers (L1, L2, L3, C1, C2, C3), and timer control registers (W3, W4), the LCD controller/driver automatically reads the display data and controls the LCD display by setting duty and bias. 4 common signal output pins and 32 segment signal output pins can be used to drive the LCD. By using these pins, up to 128 pixels (when internal power, 1/4 duty and 1/3 bias are selected) can be controlled to display. When using the external input, set necessary pins with the LCD co ntrol register 2 and apply the proper voltage to the pins . The LCD power input pins (V LC3–VLC1) are also used as pins SEG0–SEG2. When SEG0 is selected, the internal power (V DD) is used for the LCD power. (1) Duty and bias There are 3 combinations of duty and bias for displaying data on the LCD. Use bits 0 and 1 of LCD control register (L1) to select the proper display method for the LCD panel being used.

• 1/2 duty, 1/2 bias
• 1/3 duty, 1/3 bias
• 1/4 duty, 1/3 bias Table 18 Duty and maximum number of displayed pixels Note. Leave unused COM pins open. Fig 43. LCD controller/driver Duty Maximum number of displayed pixels Used COM pins 1/2 64 pixels COM 0, COM1 (Note) 1/3 96 pixels COM 0–COM2 (Note) 1/4 128 pixels COM 0–COM3 Common driver Bias control Segment driver Segment driver Segment driver Segment driver Segment driver Segment driver Selector LCD RAM Register A Selector Selector Selector Selector Selector L12 L20 L23 VDD L23 L22 L21 L13 L13 L13 L11 L10 Decoder LCD ON/OFF control 1/2, 1/3, 1/4 counter LCD clock (from timer LC) COM 3 COM 2 COM 1 COM 0 SEG0/VLC3 SEG1/VLC2 SEG2/VLC1 SEG3 P00/SEG 16 C10 to C1 3 L23 L22 L21 C20 to C2 3 L30 to L3 3 C30 to C3 3 P03/SEG 19 P10/SEG 20 P13/SEG 23 P20/SEG 24 P23/SEG 27 P30/SEG 28 P33/SEG 31 SEG15 r r r r r r to to to to to

Rev.1.01 Feb 15, 2008 Page 45 of 146 REJ03B0224-0101 455A Group (2) LCD clock control The LCD clock is determined by the timer LC setting value and timer LC count source. After setting data to timer LC, timer LC starts counting by setting count source with bit 2 of register W4 and setting bit 3 of register W4 to “1.” Accordingly, the frequency (F) of the LCD clock is obtained by the following formula. Number s ((1) to (3)) shown below the formula correspond to numbers in Figure 44, respectively.

• When using the system cloc k (STCK) as timer LC count source (W42=“1”)
• When using the bit 4 of timer 3 as timer LC count source (W42=“0”) The frame frequency and frame pe riod for each display method can be obtained by the following formula: Fig 44. LCD clock control circuit structure (3) LCD RAM RAM contains areas corresponding to the liquid crystal display. When “1” is written to this LCD RAM, the display pixel corresponding to the bit is automatically displayed. Fig 45. LCD RAM map F = STCK × × (1) (2) (3) [LC: 0 to 15] LC + 1 F = T34 × × (1) (2) (3) [LC: 0 to 15] LC + 1 Frame frequency = (Hz) Frame frequency = (Hz) F: LCD clock frequency 1/n: Duty n F F n Timer LC (4) Reload register RLC (4) (TLCA) Register A 1/2 LCD clock (TLCA) W42 W43 T34 STCK (3) (1) (2) Z X COM Y bit SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM1 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM2 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM3 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM0 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM1 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM2 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM3 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 COM0 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 COM1 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 COM2 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 COM3 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 COM0 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 COM1 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 COM2 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 COM3

Rev.1.01 Feb 15, 2008 Page 46 of 146 REJ03B0224-0101 455A Group (4) LCD drive waveform When “1” is written to a bit in the LCD RAM data, the voltage difference between common pin and segment pin which correspond to the bit au tomatically becomes lV LC3 l and the display pixel at the cross section turns on. When returning from reset, and in the RAM back-up mode, a display pixel turns off becaus e every segment output pin and common output pin becomes VLC3 level. Fig 46. LCD controller/driver structure 1/2 Duty, 1/2 Bias: When writing (XX10)2 to address M (1, 14, 8) in RAM. VLC3 VSS VLC1=VLC2 VLC3 VSS VLC1=VLC2 (2/F) 1 flame (3/F) (4/F) ON OFF Voltage level VLC3 VLC2 VSS VLC1 VLC3 VLC2 VSS VLC1 Voltage level VLC3 VLC2 VSS VLC1 VLC3 VLC2 VSS VLC1 Voltage level COM0 COM0 COM0 COM1 COM1 COM2 COM2 COM3 COM1 COM1 COM2 COM3 COM2 COM1 COM0 COM1 COM0 COM0 COM1SEG16 SEG16 SEG16 SEG16 SEG16 COM2 SEG16 COM3 SEG16 COM2 SEG16 COM1 SEG16 COM0 SEG16 COM1 SEG16 COM0 SEG16 COM0 SEG16 SEG16 SEG16 X X M ( 1 , 1 4 , 8 ) (bit 0) M ( 1 , 1 4 , 8 ) (bit 0) M ( 1 , 1 4 , 8 ) (bit 0) (bit 3) (bit 3) (bit 3) ON OFF ON X ON OFF ON OFF F : LCD clock frequency X: Set an arbitrary value. (These bits are not related to set the drive waveform at each duty.) 1/F 1/F 1/F 1/3 Duty, 1/3 Bias: When writing (X101)2 to address M (1, 14, 8) in RAM. 1/4 Duty, 1/3 Bias: When writing (1010)2 to address M (1, 14, 8) in RAM. 1 flame 1 flame

Rev.1.01 Feb 15, 2008 Page 47 of 146 REJ03B0224-0101 455A Group (5) LCD power supply circuit Select the LCD power supply circ uit suitable for the using LCD panel. The LCD power supply circuit is fixed by the followings;

• The internal dividing resistor is controlled by bit 0 of register L2.
• The internal dividing resistor is selected by bit 3 of register L1.
• The bias condition is selected by bits 0 and 1 of register L1.
• Internal dividing resistor The 4553 Group has the internal dividing resistor for LCD power supply. When bit 0 of register L2 is se t to ì0î, the internal dividing resistor is valid. However, when the LCD is turned off by setting bit 2 of register L1 to ì0î, the internal dividing resistor is turned off. The same six resistor (r) is prep ared for the internal dividing resistor. According to the setting value of bit 3 of register L1 and using bias condition, the resistor is prepared as follows;
• L 1 3 = “0”, 1/3 bias used: 2r × 3 = 6r
• L 13 = “0”, 1/2 bias used: 2r × 2 = 4r
• L 13 = “1”, 1/3 bias used: r × 3 = 3r
• L 13 = “1”, 1/2 bias used: r × 2 = 2r
• S E G0/VLC3 pin The selection of SEG 0/VLC3 pin function is controlled with the bit 3 of register L2. When the V LC3 pin function is selected, apply voltage of VLC3 < VDD to the pin externally. When the SEG 0 pin function is selected, V LC3 is connected to VDD internally.
• SEG1/VLC2, SEG2/VLC1 pin The selection of SEG 1/VLC2 pin function is controlled with the bit 2 of register L2. The selection of SEG 2/VLC1 pin function is controlled with the bit 1 of register L2. When the VLC2 pin and V LC1 pin functions are selected and the internal dividing resistor is not used, apply voltage of 0 < VLC1 < VLC2 < VLC3 to these pins. Short the V LC2 pin and V LC1 pin at 1/2 bias. When the V LC2 pin and V LC1 pin functions are selected and the internal dividing resistor is used, the dividing voltage value generated internally is output from the V LC1 pin and V LC2 pin. The VLC2 pin and V LC1 pin have the same electric potential at 1/2 bias. When SEG1 and SEG2 pin func tions are selected, use the internal dividing resistor (L2 0 = ”0”). In this time, V LC2 and VLC1 are connected to the generated dividing voltage. Fig 47. LCD power supply circuit example (1/3 bias condition selected) VSS VLC3 VLC2 VLC1 VLC3 SEG1 SEG2 (b) Register L2 = (1000)2 VSS VLC3 VLC2 VLC1 SEG1 SEG2 (a) Register L2 = (0000)2 VSS VLC3 VLC2 VLC1 VLC3 (d) Register L2 = (1111)2 VSS VLC3 VLC2 VLC1 VLC3 (c) Register L2 = (1110)2 External power supply SEG0 VLC2 VLC1 VLC2 VLC1 External power supply External power supply

Rev.1.01 Feb 15, 2008 Page 48 of 146 REJ03B0224-0101 455A Group (6) LCD control register

• LCD control register L1 Register L1 controls duty/bias selection, LCD operation, internal dividing resistor selection. Set the contents of this register through register A with the TL1A instruction. The TAL1 instruction can be used to transfer the contents of register L1.
• LCD control register L2 Register L2 controls internal dividing resistor operation, selection of pin functions; SEG0/VLC3, SEG1/VLC2, SEG2/VLC1. Set the contents of this register through register A with the TL2A instruction.
• LCD control register L3 Register L3 controls selection of pin functions; P2 0/SEG24 to P23/SEG27. Set the contents of this register through register A with the TL3A instruction.
• LCD control register C1 Register C1 controls selection of pin functions; P0 0/SEG16 to P03/SEG19. Set the contents of this register through register A with the TC1A instruction.
• LCD control register C2 Register C2 controls selection of pin functions; P1 0/SEG20 to P13/SEG23. Set the contents of this register through register A with the TC2A instruction.
• LCD control register C3 Register C3 controls selection of pin functions; P3 0/SEG28 to P33/SEG31. The contents of this register through register A with the TC3A instruction. Note 1.“R” represents read enabled, and “W” represents write enabled. Note 2.“r (resistor) multiplied by 3” is used at 1/3 bias, and “r multiplied by 2” is used at 1/2 bias. Note 3.VLC3 is connected to VDD internally when SEG0 pin is selected. Note 4.Use internal dividing resistor when SEG1 and SEG2 pins are selected. Table 19 LCD control registers (1) LCD control register L1 at reset : 0000 2 at power down : state retained R/W TAL1/TL1A L13 Internal dividing resistor for LCD power supply selection bit (Note 2) 0 2r × 3, 2r × 2 1 r × 3, r × 2 L12 LCD control bit 0S t o p ( O F F )

LCD duty and bias selection bits L11 L1 Duty Bias L11 0 0 Not available Not available 01 1 / 2 1 / 2 10 1 / 3 1 / 3 L10 11 1 / 4 1 / 3 LCD control register L2 at reset : 0000 2 at power down : state retained W TL2A L23 SEG0/VLC3 pin function switch bit (Note 3) 0 SEG 0 1V LC3 L22 SEG1/VLC2 pin function switch bit (Note 4) 0 SEG 1 1V LC2 L21 SEG2/VLC1 pin function switch bit (Note 4) 0 SEG 2 1V LC1 L20 Internal dividing resistor for LCD power supply control bit

0 Internal dividing resistor valid

1 Internal dividing resistor invalid

LCD control register L3 at reset : 1111 2 at power down : state retained W TL3A L33 P23/SEG27 pin function switch bit 0 SEG 27 1P 2 3 L32 P22/SEG26 pin function switch bit 0 SEG 26 1P 2 2 L31 P21/SEG25 pin function switch bit 0 SEG 25 1P 2 1 L30 P20/SEG24 pin function switch bit 0 SEG 24 1P 2 0

Rev.1.01 Feb 15, 2008 Page 49 of 146 REJ03B0224-0101 455A Group Table 20 LCD control registers (2) Note 1.“R” represents read enabled, and “W” represents write enabled. LCD control register C1 at reset : 1111 2 at power down : state retained W TC1A C13 P03/SEG19 pin function switch bit 0 SEG 19 1P 0 3 C12 P02/SEG18 pin function switch bit 0 SEG 18 1P 0 2 C11 P01/SEG17 pin function switch bit 0 SEG 17 1P 0 1 C10 P00/SEG16 pin function switch bit 0 SEG 16 1P 0 0 LCD control register C2 at reset : 1111 2 at power down : state retained W TC2A C23 P13/SEG23 pin function switch bit 0 SEG 23 1P 1 3 C22 P12/SEG22 pin function switch bit 0 SEG 22 1P 1 2 C21 P11/SEG21 pin function switch bit 0 SEG 21 1P 1 1 C20 P10/SEG20 pin function switch bit 0 SEG 20 1P 0 0 LCD control register C3 at reset : 1111 2 at power down : state retained W TC3A C33 P33/SEG31 pin function switch bit 0 SEG 31 1P 3 3 C32 P32/SEG30 pin function switch bit 0 SEG 30 1P 3 2 C31 P31/SEG29 pin function switch bit 0 SEG 29 1P 3 1 C30 P30/SEG28 pin function switch bit 0 SEG 28 1P 3 0

Rev.1.01 Feb 15, 2008 Page 50 of 146 REJ03B0224-0101 455A Group RESET FUNCTION System reset is performed by the followings:

• “L” level is applied to the RESET pin externally,
• System reset instruction (SRST) is executed,
• Reset occurs by watchdog timer,
• Reset occurs by built-in power-on reset
• Reset occurs by voltage drop detection circuit Then when “H” level is applied to RESET pin, software starts from address 0 in page 0. Fig 48. Structure of RESET pin and its peripherals Note 1. Output latch is set to “1.” Note 2. The output structure is N-channel open-drain. Note 3. Pull-up transistor is turned OFF. Notes 1: This symbol represents a parasitic diode. 2: Applied potential to RESET pin must be VDD or less. Power-on reset circuit Watchdog reset signal WEF SRST instruction Internal reset signal (Note 1) RESET pin (Note 2) Pull-up transistor Voltage drop detection circuit (Note 1) Table 21 Port state at reset Name Function State D0−D4 D0−D4 High-impedance (Notes 1, 2) D5/INT D 5 High-impedance (Notes 1, 2) XCIN/D6, XCOUT/D7 XCIN, XCOUT Sub-clock input P00/SEG16−P03/SEG19 P00−P03 High-impedance (Notes 1, 2, 3) P10/SEG20−P13/SEG23 P10−P13 High-impedance (Notes 1, 2, 3) P20/SEG24−P23/SEG27 P20−P23 High-impedance (Notes 1, 2, 3) P30/SEG28−P33/SEG31 P30−P33 High-impedance (Notes 1, 2, 3) SEG0/VLC3−SEG2/VLC1 SEG0−SEG2 VLC3 (VDD) level SEG3−SEG15 SEG3−SEG15 VLC3 (VDD) level COM0−COM3 COM0−COM3 VLC3 (VDD) level C/CNTR C/CNTR “L” (VSS) level

Rev.1.01 Feb 15, 2008 Page 51 of 146 REJ03B0224-0101 455A Group (1) RESET pin input System reset is performed ce rtainly by applying “L” level to RESET pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions. Fig 49. RESET pin input waveform and reset release timing (2) Power-on reset Reset can be automatically performed at power on (power-on reset) by the built-in power-on reset circuit. When the built-in power-on reset circuit is used, set the time for the supply voltage to rise from 0 V to the minimum voltage of recommended operating conditions to 100 µs or less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and Vss at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage. (3) System reset instruction (SRST) By executing the SRST instruction, “L” level is output to RESET pin and system reset is performed. Fig 50. Power-on reset operation 0.3VDD 0.85VDD (Note 1) Program starts (address 0 in page 0) Reset input 1 machine cycle or more RESET f(HSOCO) Notes 1: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. 2: It depends on the internal state at reset. High-speed on-chip oscillator (internal oscillator) is counted 1376 times (Note 2). 100µs or less VDD (Note) Power-on reset circuit output Internal reset signal Note: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. Reset released Reset state Power-on

Rev.1.01 Feb 15, 2008 Page 52 of 146 REJ03B0224-0101 455A Group (4) Internal state at reset Figure 51 and 52 shows internal state at reset (they are the same after system is released from reset). The contents of timers, registers, flags and RAM excep t shown in Figure 51 and 52 are undefined, so set the initial value to them. Fig 51. Internal state at reset (1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0• Program counter (PC) Address 0 in page 0 is set to program counter.

• Interrupt enable flag (INTE)
• Power down flag (P)
• External 0 interrupt request flag (EXF0)
• Interrupt control register V1
• Interrupt control register V2
• Interrupt control register I1
• Timer 1 interrupt request flag (T1F)
• Timer 2 interrupt request flag (T2F)
• Timer 3 interrupt request flag (T3F)
• Watchdog timer flags (WDF1, WDF2)
• Watchdog timer enable flag (WEF)
• Timer control register PA
• Timer control register W1
• Timer control register W2
• Timer control register W3
• Timer control register W4
• Timer control register W5
• Clock control register MR
• Clock control register RG
• LCD control register L1
• LCD control register L2
• LCD control register L3
• LCD control register C1
• LCD control register C2
• LCD control register C3 0 (Interrupt disabled) 0 (Interrupt disabled)0 0 0 0 (Interrupt disabled)0 0 0 00 0 0 0 (Prescaler stopped) 0 (Timer 1 stopped)0 0 0 0 (Timer 2 stopped)0 0 0 00 0 0 01 1 0 (Timer 3 stopped) (Timer LC stopped) 00 0 00 0 0 00 0 0 11 1 1 11 1 1 11 1 1 11 1 1 00 0 0 00 0 0

Rev.1.01 Feb 15, 2008 Page 53 of 146 REJ03B0224-0101 455A Group Fig 52. Internal state at reset (2)

• Key-on wakeup control register K0
• Key-on wakeup control register K1
• Key-on wakeup control register K2
• Key-on wakeup control register K3
• Pull-up control register PU0
• Pull-up control register PU1
• Pull-up control register PU2
• Pull-up control register PU3
• Port output structure control register FR0
• Port output structure control register FR1
• Port output structure control register FR2
• Port output structure control register FR3
• High-order bit reference enable flag (UPTF)
• Carry flag (CY)
• Register A
• Register B
• Register D
• Register E
• Register X
• Register Y
• Register Z
• Stack pointer (SP)
• Operation source clock
• Ceramic resonator circuit
• Low-speed on-chip oscillator
• Quartz-crystal oscillator 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 ×× × ×× × × 11 1 “X” represents undefined. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 00 0 ×× × × 00 0 0 00 0 0 High-speed on-chip oscillator (operating) Operating Stop Operating 00 0 0

Rev.1.01 Feb 15, 2008 Page 54 of 146 REJ03B0224-0101 455A Group VOLTAGE DROP DETECTION CIRCUIT (WITH SKIP JUDGMENT) The built-in voltage drop detectio n circuit is used to set the voltage drop detection circuit flag (VDF) or to perform system reset. Fig 53. Voltage drop detection reset circuit (1) Operating state of voltage drop detection circuit The voltage drop detection circ uit becomes valid by inputting “H” to the VDCE pin and it becomes invalid by inputting “L.” When not executing the SVDE instruction under “H” level of the VDCE pin, the voltage drop detection circui t become invalid in power down state (RAM back-up, clock operating mode). As for this, the voltage drop detection circuit becomes valid at returning from power down, again. When executing the SVDE instru ction under “H” level of the VDCE pin, the voltage drop de tection circuit becomes valid in power down state (RAM back-up, clock operating mode). The state of executing SVDE instruction can be cleared by system reset. Note. “O” indicates valid, “×” indicates invalid. Notes 1: This symbol represents a parasitic diode. 2: Applied potential to RESET pin must be VDD or less. (Note 1) (Note 1) VDCE (Note 2) Internal reset signal T3UDF Key-on wakeup signal S R Q S R Q SVDE instruction Internal reset signal Q VSKIP Voltage drop detection circuit VRST−/VRST+ Reset occurrence Flag occurrence VDF Skip judgement VDD VDD Voltage drop detection circuit reset signal Voltage drop detection circuit flag EPOF instruction + POF instruction EPOF instruction + POF2 instruction Oscillation stop signal Table 22 Operating state of voltage drop detection circuit VDCE pin SVDE instruction at CPU operating at power down “L” No execute × × Execute × × “H” No execute O × Execute O O

Rev.1.01 Feb 15, 2008 Page 55 of 146 REJ03B0224-0101 455A Group (2) Voltage drop detection circuit flag (VDF) V oltage drop detection circuit flag (VDF) is set to “1” when the supply voltage goes the skip occurrence voltage (V SKIP) or less. Moreover, voltage drop detection circuit flag (VDF) is cleared to “0” when the supply voltage go es the skip occurrence voltage (VSKIP) or more. The state of the voltage drop detection circuit flag (VDF) can be examined with the skip instruction (SNZVD). Even when the skip instructio n is executed, the voltage drop detection circuit flag is not cleared to “0”. Refer to the electrical characteristics for skip occurrence voltage value. (3) Voltage drop detection circuit reset System reset is performed when the supply voltage goes the reset occurrence voltage (V RST-) or less. When the supply voltage goes reset releas e voltage (V RST+) or more, the oscillation circuit goes to be in the operating enabled state and system reset is released . Refer to the electrical characte ristics for reset occurrence value and reset release voltage value. Fig 54. Voltage drop detection circuit operation waveform Fig 55. V DD and VRST- (4) Note on voltage drop detection circuit The voltage drop detection circ uit detection voltage of this product is set up lower than th e minimum value of the supply voltage of the recommended operating conditions. When the supply voltage of a mic rocomputer falls below to the minimum value of recommende d operating conditions and regoes up, depending on the capacity value of the bypass capacitor added to the power supply pin, the following case may cause program failure (Figure 55); supply voltage does not fall below to V RST-, and its voltage re- goes up with no reset. In such a case, please design a system which supply voltage is once reduced below to VRST- and re-goes up after that. VDD Voltage drop detection circuit flag (VDF) VRST+(reset release voltage) VRST-(reset occurrence voltage) Voltage drop detection circuit reset signal Note 1: Microcomputer starts operation after high-speed on-chip oscillator clock is counted 1376 times. (Note 1) VSKIP (skip occurrence voltage) VDD VRST+ VRST- VDD VRST+ VRST- Recommended operating condition min.value Normal operation Reset No reset Program failure may occur. Recommended operating condition min.value

Rev.1.01 Feb 15, 2008 Page 56 of 146 REJ03B0224-0101 455A Group POWER DOWN FUNCTION The 455A Group has 2-type power down functions. System enters into each power down state by executing the following instructions. When the EPOF instru ction is not executed before the POF or POF2 instruction is executed, these instructions are equivalent to the NOP instruction. (1) Clock operating mode The following functions and states are retained.

• R A M
• Reset circuit
• X CIN–XCOUT oscillation
• L C D d i s p l a y
• T i m e r 3
• Low-speed on-chip oscillator (2) RAM back-up mode The following functions and states are retained.
• R A M
• Reset circuit (3) Warm start condition The system returns from the power down state when;
• External wakeup signal is input
• Timer 3 underflow occurs in the power down mode. In either case, the CPU starts executing the software from address 0 in page 0. In this case, the P flag is “1.” (4) Cold start condition The CPU starts executing the softwa re from address 0 in page 0 when;
• external “L” level is input to RESET pin,
• execute system reset instruction (SRST instruction)
• reset by watchdog timer is performed
• reset by internal power-on reset, or
• reset by the voltage drop detection circuit is performed. In this case, the P flag is “0.” (5) Identification of the start condition Warm start or cold start can be identified by examining the state of the power down flag (P) with the SNZP instruction. (6) Identification of the return condition using the timer 3 interrupt request flag When the system returns fro m the power down mode, the following conditions can be iden tified by examining the state of the timer 3 interrupt request flag (T3F):
• When T3F = “1”, return by timer 3 underflow (time elapse)
• When T3F = “0”, return by key-on wakeup (key input) Note 1. “O” represents that the function can be retained, and “ ×” represents that the function is initialized. Registers and flags other than the above are undefined at power down mode, and set an initial value after returning. Note 2. The stack pointer (SP) points the level of the stack register and is initialized to “7” at power down mode. Note 3. The state of the timer is undefined. Note 4. Initialize the WDF1 flag with the WRST instruction, and then go into the power down state. Note 5. LCD is turned off. Note 6. When the SVDE instruction is executed, this function is valid at power down. Note 7. In the power down mode, C/CNTR pin outputs “L” level. However, when the CNTR input is selected (W1 W10=“11”), C/CNTR pin is in an input enabled state (output = high-impedance). Other ports retain their respective output levels. Table 23 Functions and states retained at power down mode Function Power down mode Clock operating RAM back-up Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note Contents of RAM O O Interrupt control registers V1, V2 ×× Interrupt control registers I1, V2 O O Selected oscillation circuit O O Clock control register MR, RG O O Timer 1, Timer 2 functions (Note 3) (Note 3) Timer 3 function O O Timer LC function O (Note 3) Watchdog timer function × (Note × (Note Timer control registers PA, W2 ×× Timer control registers W1, W3, W4, W5 O O LCD display function O (Note 5) LCD control registers L1 to L3, C1 to C3 O O Voltage drop detection circuit (Note 6) (Note 6) Port level (Note 7) (Note 7) Key-on wakeup control registers K0 to K3 O O Pull-up control registers PU0 to PU3 O O Port output structure control registers FR0 to FR3 OO External interrupt request flags (EXF0) Timer interrupt request flags (T1F, T2F) (Note 3) (Note 3) Timer interrupt request flag (T3F) O O Interrupt enable flag (INTE) Voltage drop detection circuit flag (VDF) ×× Watchdog timer flags (WDF1, WDF2) × (Note × (Note Watchdog timer enable flag (WEF) × (Note × (Note

Rev.1.01 Feb 15, 2008 Page 57 of 146 REJ03B0224-0101 455A Group (7) Return signal An external wakeup signal or timer 3 interrupt request flag (T3F) is used to return from the clock operating mode. An external wakeup signal is used to return from the RAM back- up mode because the oscillation is stopped. Table 24 shows the return condition for each return source. (8) Control registers

• Key-on wakeup control register K0 Register K0 controls the por ts P0 and P1 key-on wakeup function. Set the contents of th is register through register A with the TK0A instruction. In addition, the TAK0 instruction can be used to transfer the contents of register K0 to register A.
• Key-on wakeup control register K1 Register K1 controls the port P2 key-on wakeup function. Set the contents of this register through register A with the TK1A instruction. In addition,the TA K1 instruction can be used to transfer the contents of register K1 to register A.
• Key-on wakeup control register K2 Register K2 controls the port P3 and INT pin key-on wakeup function and the selection of retu rn condition of INT pin. Set the contents of this register through register A with the TK2A instruction. In addition, the T AK2 instruction can be used to transfer the contents of register K2 to register A.
• Key-on wakeup control register K3 Register K3 controls the port D 0 to D 7 pin key-on wakeup function. Set the contents of th is register through register A with the TK3A instruction. In addition, the TAK3 instruction can be used to transfer the contents of register K3 to register A.
• Pull-up control register PU0 Register PU0 controls the ON/OFF of the port P0 and P1 pull- up transistor. Set the contents of this register through register A with the TPU0A instructio n. In addition, the TAPU0 instruction can be used to transfer the contents of register PU0 to register A.
• Pull-up control register PU1 Register PU1 controls the ON/OFF of the port P2 pull-up transistor. Set the contents of th is register through register A with the TPU1A instruction. In addition, the TAPU1 instruction can be used to transfer the contents of register PU1 to register A.
• Pull-up control register PU2 Register PU2 controls the ON/ OFF of the ports P3 pull-up transistor. Set the contents of th is register through register A with the TPU2A instruction. In addition, the TAPU2 instruction can be used to transfer the contents of register PU2 to register A.
• Pull-up control register PU3 Register PU3 controls the ON/OFF of the ports D 0 to D7 pull- up transistor. Set the contents of this register through register A with the TPU3A instructio n. In addition, the TAPU3 instruction can be used to transfer the contents of register PU3 to register A.
• External interrupt control register I1 Register I1 controls the input control and the selection of valid waveform/level of INT pin. Set the contents of this register through register A with the TI1A instruction. In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A. Table 24 Return source and return condition Return source Return condition Remarks External wakeup signal Ports P00−P03 Ports P10−P13 Ports P20−P23 Ports P30−P33 Ports D0−D7 Return by an external falling edge (“H” → “L”). For ports P0, P1, P3 and D 0 to D7 the key-on wakeup function can be selected by two port unit, for port P2, it can be selected by a unit. INT pin Return by an external “H” level or “L” level input, or rising edge (“L” → “H”) or falling edge When the return level is input, the interrupt request flag (EXF0) is not set. Select the return level (“L” level or “H” level) with register I1 and return condition (return by level or edge) with register K2 according to the external state before going into the power down state. Timer 3 interrupt request flag (T3F) Return by timer 3 underflow or by setting T3F to “1”. It can be used in the clock operating mode. Clear T3F with the SNZT3 instruction before system enters into the power down state. When system enters into the power down state while T3F is “1”, system returns from the state immediately because it is recognized as return condition.

Rev.1.01 Feb 15, 2008 Page 58 of 146 REJ03B0224-0101 455A Group Fig 56. State transition Fig 57. Set source and clear source of the P flag Fig 58. Start condition identified example using the SNZP instruction Key-on wakeup (Stabilizing time [d] ) F RAM back-up mode f(HSOCO): stop f(XIN): stop f(XCIN): stop f(LSOCO): stop EPOF + POF2 instruction execution Key-on wakeup (Stabilizing time [c] ) B Operation state O p e r a t i o ns o u r c ec l o c k :f ( XIN) Ceramic resonator D Operation state Operation source clock: f(LSOCO) Low-spped on-chip oscillator High-speed mode EPOF + POF2 instruction execution Key-on wakeup (Stabilizing time [e] ) E Clock operating mode f(HSOCO): stop f(XIN): stop f(XCIN), f(LSOCO)F by RG register EPOF + POF instruction execution Key-on wakeup Timer 3 underflow (Stabilizing time [c] ) EPOF + POF instruction execution Key-on wakeup Timer 3 underflow (Stabilizing time [e] ) MR1, MR0©11MR1, MR0©10 C Operation state O p e r a t i o ns o u r c ec l o c k :f ( XCIN) Quartz-crystal oscillation EPOF + POF2 instruction execution EPOF + POF instruction execution Key-on wakeup Timer 3 underflow (Stabilizing time [d] ) MR1, MR0©10MR1, MR0©00 A Operation state Operation source clock: f(HSOCO) High-speedon-chiposcillator EPOF + POF2 instruction execution Key-on wakeup (Stabilizing time [b] ) EPOF + POF instruction execution Key-on wakeup Timer 3 underflow (Stabilizing time [b] ) (Stabilizing time [a] ) MR1, MR0©00MR1, MR0©01 MR1,MR0 ©11 MR1,MR0 ©01 MR1,MR0 ©11 MR1,MR0 ©00 Internal mode Low-speed mode MR1,MR0 ©10 MR1,MR0 ©01 Internal low-speed mode Reset 1. The system clock selected by the clock control registers MR and RG is retained at power down. The oscillation stability time at return can be adjusted by setting the clock control registers MR and RG before transiting to the power down state. 2. To transmit to the clock operating mode, the EPOF and POF instructions must be executed continuously. 3. To transmit to the RAM back-up mode, the EPOF and POF2 instructions must beexecuted continuously. 4. After reset release, the main clock (f(XIN)), the sub-clock, and the internal clock (f(HSOCO)) are enabled. 5. To select a stopped clock as the system clock, first start the clock selected by the clock control register RG and generate the oscillation stability time by software. Then switch the system clock. Stabilizing time [a] : Microcomputer starts its operation after countingthe f(HSOCO) to 1376 times. Stabilizing time [b] : Microcomputer starts its operation after counting the f(HSOCO) to (system clock division ratio X 15) times. Stabilizing time [c] : Microcomputer starts its operation after countingthe f(XIN) to (system clock division ratio X 171) times. Stabilizing time [d] : Microcomputer starts its operation after countingthe f(XCIN) to (system clock division ratio X 171) times. Stabilizing time [e] : Microcomputer starts its operation after countingthe f(LSOCO) to (system clock division ratio X 15) times. Notes S R Q P o w e rd o w nf l a gPPOF or POF2 instruction Reset input Set source Clear source System reset EPOF instruction + POF or POF2 instruction EPOF instruction + P Program start P= “1” Warm start Cold start No T3F = Return from timer 3 underflow Return from external wakeup signal “1” Yes Yes No SNZT3 instruction SNZP instruction

Rev.1.01 Feb 15, 2008 Page 59 of 146 REJ03B0224-0101 455A Group Note 1. “R” represents read enabled, and “W” represents write enabled. Table 25 Key-on wakeup control register Key-on wakeup control register K0 at reset : 0000 2 at power down : state retained R/W TAK0/TK0A K03 Ports P12 and P13 key-on wakeup control bit

0 Key-on wakeup not used

1 Key-on wakeup used

Ports P10 and P11 key-on wakeup control bit Ports P02 and P03 key-on wakeup control bit Ports P00 and P01 key-on wakeup control bit Key-on wakeup control register K1 at reset : 0000 2 at power down : state retained R/W TAK1/TK1A K13 Port P23 key-on wakeup control bit 0 Key-on wakeup not used K12 Port P22 key-on wakeup control bit 0 Key-on wakeup not used K11 Port P21 key-on wakeup control bit 0 Key-on wakeup not used K10 Port P20 key-on wakeup control bit 0 Key-on wakeup not used Key-on wakeup control register K2 at reset : 0000 2 at power down : state retained R/W TAK2/TK2A K23 Ports P32 and P33 key-on wakeup control bit Ports P30 and P31 key-on wakeup control bit K21 INT pin return condition selection bit 0 Return by level

1 Return by edge

K20 INT pin key-on wakeup control bit 0 Key-on wakeup invalid

1 Key-on wakeup valid

Key-on wakeup control register K3 at reset : 0000 2 at power down : state retained R/W TAK3/TK3A K33 Ports D6 and D7 key-on wakeup control bit 0 Key-on wakeup not used K32 Ports D4 and D5 key-on wakeup control bit 0 Key-on wakeup not used K31 Ports D2 and D3 key-on wakeup control bit 0 Key-on wakeup not used K30 Ports D0 and D1 key-on wakeup control bit 0 Key-on wakeup not used

Rev.1.01 Feb 15, 2008 Page 60 of 146 REJ03B0224-0101 455A Group Note 1.“R” represents read enabled, and “W” represents write enabled. Table 26 Pull-up control register Pull-up control register PU0 at reset : 0000 2 at power down : state retained R/W TAPU0/TPU0A PU03 Port P12 and P13 pull-up transistor control bit

0 Pull-up transistor OFF

1 Pull-up transistor ON

Port P10 and P11 pull-up transistor control bit Port P02 and P03 pull-up transistor control bit Port P00 and P01 pull-up transistor control bit Pull-up control register PU1 at reset : 0000 2 at power down : state retained R/W TAPU1/TPU1A PU13 Port P23 pull-up transistor control bit 0 Pull-up transistor OFF PU12 Port P22 pull-up transistor control bit 0 Pull-up transistor OFF PU11 Port P21 pull-up transistor control bit 0 Pull-up transistor OFF PU10 Port P20 pull-up transistor control bit 0 Pull-up transistor OFF Pull-up control register PU2 at reset : 0000 2 at power down : state retained R/W TAPU2/TPU2A PU23 Port P33 pull-up transistor control bit 0 Pull-up transistor OFF PU22 Port P32 pull-up transistor control bit 0 Pull-up transistor OFF PU21 Port P31 pull-up transistor control bit 0 Pull-up transistor OFF PU20 Port P30 pull-up transistor control bit 0 Pull-up transistor OFF Pull-up control register PU3 at reset : 0000 2 at power down : state retained R/W TAPU3/TPU3A PU33 Port D6 and D7 pull-up transistor control bit 0 Pull-up transistor OFF PU32 Port D4 and D5 pull-up transistor control bit 0 Pull-up transistor OFF PU31 Port D2 and D3 pull-up transistor control bit 0 Pull-up transistor OFF PU30 Port D0 and D1 pull-up transistor control bit 0 Pull-up transistor OFF

Rev.1.01 Feb 15, 2008 Page 61 of 146 REJ03B0224-0101 455A Group Table 27 Interrupt control register Note 1. “R” represents read enabled, and “W” represents write enabled. Note 2. When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Interrupt control register I1 at reset : 0000 2 at power down : state retained R/W TAI1/TI1A I13 INT pin input control bit (Note 2) 0 INT pin input disabled Interrupt valid waveform for INT pin/ return level selection bit (Note 2)

0 Falling waveform (“L” level of INT pi n is recognized with the SNZI0

instruction)/“L” level instruction)/“H” level I11 INT pin edge detection circuit control bit 0 One-sided edge detected INT pin timer 1 count start synchronous circuit selection bit

Rev.1.01 Feb 15, 2008 Page 62 of 146 REJ03B0224-0101 455A Group CLOCK CONTROL The clock control circuit consists of the following circuits.

• High-speed on-chip oscillator
• Ceramic resonator
• Low-speed on-chip oscillator
• Quartz-crystal oscillation circuit
• Frequency divider
• Internal clock generating circuit The system clock and the instruct ion clock are generated as the source clock for operation by these circuits. Figure 59 shows the structure of the clock control circuit. The 455A Group operates by the high-speed on-chip oscillator clock (f(HSOCO)) which is the internal oscillator after system is released from reset. The quartz-crystal oscillator can be used for sub-clock (f(X CIN)). Fig 59. Clock control circuit structure High-speed on-chip oscillator (internal oscillator) MR3, MR2Division circuit Divided by 8 Divided by 4 Divided by 2 Internal clock generating circuit (divided by 3) System clock (STCK) Instruction clock (INSTCK) XIN XOUT Ceramic resonance EPOF instruction + POF instruction Key-on wakeup signal Internal reset signal RG0 RG1 QS R MR1, MR0 XCIN XCOUT Quartz-crystal oscillation RG2 EPOF instruction + POF2 instruction Low-speed on-chip oscillator (Low-speed internal oscillator) RG3 QS R T3F signal

Rev.1.01 Feb 15, 2008 Page 63 of 146 REJ03B0224-0101 455A Group (1) High-speed on-chip oscillator operation After system is released from reset, the MCU starts operation by the clock output from the high-s peed on-chip oscillator which is the internal oscillator. The clock frequency of the high-speed on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. (2) Main clock generating circuit (f(X IN)) After reset release, the ceramic oscillation is valid for the main clock. Connect the ceramic oscill ator and the external circuit to pins X IN and X OUT at the shortest distance (Figure 61). A feedback resistor is built in between pins XIN and XOUT. If the main clock is not used, connect the X IN pin to V SS and leave the XOUT pin open. (3) Low-speed on-chip oscillator operation After system is released from reset, the low-speed on-chip oscillator turns invalid which is the internal oscillator. Oscillator operation/stopping and the control of system clock selection are operated by the register RG and MR. The clock frequency of the low-speed on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. Fig 60. Handling of X IN and XOUT when operating on- chip oscillator Fig 61. Ceramic resonator external circuit 455A XIN XOUT 455A XIN XOUT Rd CIN COUT Note: Externally connect a damping resistor Rd depending on the oscillation frequency. (A feedback resistor is built-in.) Use the resonator manufacturer’s recommended value because constants such as capacitance depend on the resonator.

Rev.1.01 Feb 15, 2008 Page 64 of 146 REJ03B0224-0101 455A Group (4) External clock When the external clock signal is used as the main clock (f(XIN)), connect the XIN pin to the clock source and leave XOUT pin open (Figure 62). Be careful that the maximum value of the oscillation frequency when using the external clock differs from the value when using the ceramic resonator (refer to the recommended operating condition). Also, note that th e power down mode (POF and POF2 instructions) cannot be used when using the external clock. (5) Sub-clock generating circuit f(X CIN) Sub-clock signal f(X CIN) is obtained by exte rnally connecting a quartz-crystal oscillator. Connec t this external circuit and a quartz-crystal oscillator to pins X CIN and XCOUT at the shortest distance. A feedback resistor is built in between pins X CIN and XCOUT (Figure 63). X CIN pin and X COUT pin are also used as ports D6 and D7, respectively. The sub-clock oscillation circuit is invalid and the function of ports D 6 and D7 are valid by setting bit 2 of register RG to “1”. When sub-clock, ports D6 and D7 are not used, connect XCIN/D6 to VSS and leave XCOUT/D7 open. Fig 62. External clock input circuit Fig 63. External quarts-crystal circuit 455A XIN XOUT External oscillation circuit VDD VSS 455A XCIN XCOUT Rd CIN COUT Note: Externally connect a damping resistor Rd depending on the oscillation frequency. (A feedback resistor is built-in.) Use the quartz-crystal manufacturer’s recommended value because constants such as capacitance depend on the resonator.

Rev.1.01 Feb 15, 2008 Page 65 of 146 REJ03B0224-0101 455A Group (6) Clock control register MR Register MR controls syst em clock and operation mode (frequency division of system cl ock). Set the contents of this register through register A wi th the TMRA in struction. In addition, the TAMR instruction can be used to transfer the contents of register MR to register A. (7) Clock control register RG Register RG controls the start/stop of each oscillation circuit. Set the contents of this register through register A with the TRGA instruction. Note 1. R” represents read enabled, and “W” represents write enabled. Note 2. The stopped clock cannot be selected for system clock. Note 3. The oscillation circuit selected for system clock cannot be stopped. Table 28 Clock control registers Clock control register MR at reset : 1100 2 at power down : state retained R/W TAMR/TMRA MR3 Operation mode selection bits MR3 MR2 Operation mode 0 0 Through mode 0 1 Frequency divided by 2 mode MR 2 1 0 Frequency divided by 4 mode 1 1 Frequency divided by 8 mode MR System clock selection bits (Note 2) MR1 MR0 System clock 0 0 f(HSOCO) MR0 0 1 f(XIN) 10 f ( X CIN) 1 1 f(LSOCO) Clock control register RG at reset : 1000 2 at power down : state retained W TRGA RG3 Low-speed on-chip oscillator (f(LSOCO)) control bit (Note 3)

0 Low-speed on-chip oscillator (f(L SOCO)) oscillation available

1 Low-speed on-chip oscillator (f(LSOCO)) oscillation stop

RG2 Sub-clock (f(XCIN)) control bit (Note 3) 0 Sub-clock (f(X CIN)) oscillation available, ports D6 and D7 not selected

1 Sub-clock (f(X CIN)) oscillation stop, ports D6 and D7 selected

RG1 Main-clock (f(XIN)) control bit (Note 3) 0 Main clock (f(X IN)) oscillation available

1 Main clock (f(X IN)) oscillation stop

High-speed on-chip oscillator (f(HSOCO)) control bit (Note 3)

0 High-speed on-chip oscillator (f (HSOCO)) oscillation available

1 High-speed on-chip oscillator (f(HSOCO)) oscillation stop

Rev.1.01 Feb 15, 2008 Page 66 of 146 REJ03B0224-0101 455A Group QzROM Writing Mode In the QzROM writing mode , the user ROM area can be rewritten while the microcomputer is mounted on-board by using a serial pro-grammer which is applicable for this microcomputer. Table 29 lists the pin descript ion (QzROM writing mode) and Figure 64 shows the pin connections. Refer to Figure 65 for examples of a connection with a serial pro- grammer. Contact the manufacturer of y our serial programmer for serial pro-grammer. Refer to the user’s manual of your serial programmer for details on how to use it. Note 1. Note that the P2 0/SEG24 pin is pulled down internally by the MCU during the transition period (the period when VPP is approximately 0.5 VDD to 1.3 VDD) when the programming power supply (VPP) is applied to the CNVSS pin. In addition, the P20/SEG24 pin is high inpedance when VPP is approximately 1.3 VDD or grater. Table 29 Pin description (QzROM writing mode) Pin Name I/O Function VDD, VSS Power source, GND Apply 2.7 to 4.7V to V CC, and 0V to VSS. RESET Reset input input Reset input pin for active “L”. Reset occurs when RESET pin is hold at an “L” level for 16 cycles or more of XIN. XIN, XCIN Clock input input Either connect an oscillator circuit or connect XIN and XCIN to VSS and leave XOUT and XCOUT open.XOUT, XCOUT Clock output output D0 − D5 P00/SEG16 − P03/SEG19 P10/SEG20 − P13/SEG23 P20/SEG24 (Note 1) − P23/SEG27 P30/SEG28 − P33/SEG31 I/O port I/O Input “H” or “L” level signal or leave the pin open. CNVSS VPP input input QzROM programmable power source pin. D4 SDA input/output I/O Serial data I/O pin. D3 SCLK input input Serial clock input pin. D2 PGM input input Read/program pulse input pin. VDCE Voltage drop detection circuit enable input Input “H” or “L” level signal SEG0/VLC3 − SEG2/VLC1 SEG3 − SEG15 COM0 − COM3 Segment output/ LCD power source/ Common output output Either connect to an LCD panel or leave open. C/CNTR Output port C/ Timer I/O output C/CNTR pin outputs “L” level.

Rev.1.01 Feb 15, 2008 Page 67 of 146 REJ03B0224-0101 455A Group Fig 64. Pin connection diagram OUTLINE PLQP0052JA-A (52P6A-A) D5/INT CNVss XCIN/D6 XCOUT /D7 RESET XOUT Vss XIN VDD C/CNTR P10/SEG20 P03/SEG19 P02/SEG18 P01/SEG17 P00/SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2/VLC1 SEG1/VLC2 SEG0/VLC3 COM3 COM2 COM1 COM0 VDCE P11/SEG21 P12/SEG22 P13/SEG23 (Note) P20/SEG24 P21/SEG25 P22/SEG26 P23/SEG27 P30/SEG28 P31/SEG29 P32/SEG30 P33/SEG31 M3455AG8FP M3455AG8-XXXFP M3455AGCFP M3455AGC-XXXFP Pin configuration (top view) –PGM 1KΩ *: Connect an oscillation circuit : QzROM pin SCLK SDA VPP VDD VSS Note: Note that the P20/SEG24 pin is pulled down internally by the MCU during the transition period (that period when VPP is approximately 0.5 VDD to 1.3 VDD) when the programming power supply (VPP) is applied to the CNVSS pin. In addition, the P20/SEG24 pin is high impedance when VPP is approximately 1.3 VDD or greater.

Rev.1.01 Feb 15, 2008 Page 68 of 146 REJ03B0224-0101 455A Group Fig 65. When using programmer of Suisei Electronics System Co., LTD, connection example 455A Group T_VDD T_VPP T_SCLK T_PGM/OE /MD T_RESET GND RESET circuit Vcc CNVSS D4 (SDA) RESET Vss XIN XOUT 4.7 kΩ T_RXD T_TXD 1k Ω T_ BUSY D3 (SCLK) D2 (PGM) N.C. Set the same termination as the single-chip mode. Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF.

Rev.1.01 Feb 15, 2008 Page 69 of 146 REJ03B0224-0101 455A Group LIST OF PRECAUTIONS (1) Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up;

• connect a bypass capacitor (approx. 0.1 µF) between pins VDD and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use relatively thick wire. CNVSS is also used as VPP pin. Accordingly, when using this pin, connect this pin to V SS through a resistor about 5k Ω (connect this resistor to CNVSS/VPP pin as close as possible). (2) Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicat ed as the recommended operating conditions, the microc omputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the s upply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. (3) Register initial values 1 The initial value of the following registers are undefined after system is released from reset. After system is released from reset, set initial values.
• Register Z (2 bits)
• Register D (3 bits)
• Register E (8 bits) (4) Register initial values 2 The initial value of the following registers are undefined at RAM back-up. After system is returned from RAM back-up, set initial values.
• Register Z (2 bits)
• Register X (4 bits)
• Register Y (4 bits)
• Register D (3 bits)
• Register E (8 bits) (5) Program counter Make sure that the PC H does not specify after the last page of the built-in ROM. (6) Stack registers (SKS) Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. (7) Multifunction
• The input/output of D5 can be used even when INT is used. Be careful when using inputs of both INT and D 5 since the input threshold value of INT pin is different from that of port D5.
• “H“ output function of port C can be used even when the CNTR (output) is used. (8) Power-on reset When the built-in power-on reset circuit is used, set the time for the supply voltage to rise from 0 V to the minimum voltage of recommended operating conditions to 100 µs or less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and Vss at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage. (9) POF, POF2 instruction When the POF or POF2 instru ction is executed continuously after the EPOF instruction, system enters the RAM back-up state. Note that system cannot enter the RAM back-up state when executing only the POF or POF2 instruction. Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction and the POF/POF2 instruction continuously.

Rev.1.01 Feb 15, 2008 Page 70 of 146 REJ03B0224-0101 455A Group (10)D5/INT pin (1) Bit 3 of register I1 When the input of the D5/INT pin is controlled with the bit 3 of register I1 in software, be careful about the following notes.

• Depending on the input state of the D 5/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In or der to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to (1) in Figure 66.) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to (2) in Figure 66.). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instru ction (refer to (3) in Figure 66.). Fig 66. External 0 interrupt program example-1 (2) Bit 3 of register I1 When the bit 3 of register I1 is cleared to “0”, the power down mode is selected and the input of INT pin is disabled, be careful about the following notes.
• When the INT pin input is disabled (register I1 3 = “0”), set the key-on wakeup of INT pin to be invalid (register K2 0 = “0”) before system enters to the power down mode. (refer to (1) in Figure 67.). Fig 67. External 0 interrupt program example-2 (3) Bit 2 of register I1 When the interrupt valid waveform of the D 5/INT pin is changed with the bit 2 of regist er I1 in software, be careful about the following notes.
• Depending on the input state of the D 5/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In or der to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to (1) in Figure 68.) and then, cha nge the bit 2 of register I1 is changed. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to (2) in Figure 68.). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instru ction (refer to (3) in Figure 68.). Fig 68. External 0 interrupt program example-3
• •• LA 4 ; ( ×××02) LA 8 ; (1 ×××2) TI1A ; Control of INT pin input is changed SNZ0 ; The SNZ0 instruction is executed (EXF0 flag cleared)
• •• ×: these bits are not used here. LA 0 ; ( ×××02) DI EPOF POF2 ; RAM back-up
• •• ×: these bits are not used here. LA 4 ; ( ×××02) LA 12 ; ( ×1××2) TI1A ; Interrupt valid waveform is changed SNZ0 ; The SNZ0 instruction is executed (EXF0 flag cleared)
• •• ×: these bits are not used here.

Rev.1.01 Feb 15, 2008 Page 71 of 146 REJ03B0224-0101 455A Group (11)Prescaler Stop prescaler counting and then execute the TABPS instruction to read its data. Stop prescaler counting and then execute the TPSAB instruction to write data to prescaler. (12)Timer count source Stop timer 1, 2 or LC counting to change its count source. (13)Reading the count value Stop timer 1 or 2 counting and then execute the TAB1 or TAB2 instruction to read its data. (14)Writing to the timer Stop timer 1, 2 or LC counting and then execute the T1AB, T2AB, T2R2L or TLCA instruction to write data to timer. (15)Writing to reload register In order to write a data to the reload register R1 while the timer 1 is operating, execute the TR 1AB instruction except a timing of the timer 1 underflow. In order to write a data to the reload register R2H while the timer 2 is operating, execute the T3HAB instruction except a timing of the timer 2 underflow. (16)PWM signal If the timer 2 count stop timing and the timer 2 underflow timing overlap during output of the PWM signal, a hazard may occur in the PWM output waveform. When “H” interval expansion function of the PWM signal is used, set “1” or more to reload register R2H. Set the port C output latch to “0” to output the PWM signal from C/CNTR pin. (17)Timer 3 Stop timer 3 counting to change its count source. When operating timer 3 during clock operating mode, set 1 cycle or more of count source to th e following period; from setting bit 3 of register W3 to “1” till executing the POF instruction. (18)Prescaler, timer 1 count start timing and count time when operation starts Count starts from the first rising edge of the count source (2) in Figure 69 after prescaler and ti mer operations start (1) in Figure 69. Time to first underflow (3) in Figu re 69 is shorter (for up to 1 period of the count source) than time among next underflow (4) in Figure 69 by the timing to start the timer and count source operations after count starts. When selecting CNTR input as the count source of timer 1, timer 1 operates synchronizing with th e count edge (falling edge or rising edge) of CNTR input selected by software. Fig 69. Timer count start timing and count time when operation starts (1) (19)Timer 2, LC count start timing and count time when operation starts Count starts from the first edge of the count source (2) in Figure 70 after timer 2 and LC operation start (1) in Figure 70. Time to first underflow (3) in Figur e 70 is different (for up to 1 period of the count source) fro m time among next underflow (4) in Figure 70 by the timing to start the timer and count source operations after count starts. Fig 70. Timer count start timing and count time when operation starts (2) Count source (3) (4) (1) Timer start (2) Count source (When falling edge of CNTR input is selected) Timer 1 value Timer 1 underflow signal 32 1 0 3 2 1 0 3 2 Count source (3) (4) (1) Timer start (2) Timer value Timer underflow signal 32 1 0 3 2 1 0 3 2

Rev.1.01 Feb 15, 2008 Page 72 of 146 REJ03B0224-0101 455A Group (20)Watchdog timer

• The watchdog timer function is valid after system is released from reset. When not usi ng the watchdog timer function, execute the DWDT instructio n and the WRST instruction continuously, and clear the WEF flag to “0” to stop the watchdog timer function.
• The contents of WDF1 flag and timer WDT are initialized at the power down.
• When using the watchdog timer and the power down, initialize the WDF1 flag with the WRST instruction just before the microcomputer enters the power down mode. Also, set the NOP instruction after the WRST instruction, for the case when a skip is performed with the WRST instruction. (21)Voltage drop detection circuit The voltage drop detection circ uit detection voltage of this product is set up lower than th e minimum value of the supply voltage of the recommended operating conditions. When the supply voltage of a mic rocomputer falls below to the minimum value of recommende d operating conditions and regoes up (ex. battery exchange of an application product), depending on the capacity value of the bypass capacitor added to the power supply pin, the fo llowing case may cause program failure (Figure 71); supply voltage does not fall below to V RST-, and its voltage re- goes up with no reset. In such a case, please design a system which supply voltage is once reduced below to V RST- and re-goes up after that. Fig 71. V DD and VRST- (22)On-chip oscillator The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. Also, the oscillation stabilize wait time after system is released from reset is generated by the on-chip oscillator clock. When considering the oscillation stabilize wait time after system is released from reset, be careful that the variable frequency of the on-chip oscillator clock. (23)External clock Be careful that the maximum value of the oscillation frequency when using the external clock differs from the value when using the ceramic resonator (refer to the recommended operating condition). Also, note that the power-down mode (POF or POF2 instruction) cannot be used when using the external clock. (24)QzROM (1) Be careful not to apply overvoltage to MCU. The contents of QzROM may be overwritte n because of overvoltage. Take care especially at turning on the power. (2) As for the product shippe d in blank, Renesas does not perform the writing test to user ROM area after the assembly process though the QzROM writing test is performed enough before the assembly process. Therefore, a writing error of approx. 0.1 % may occur. Moreover, please note the contact of cables and foreign bodies on a socket, etc. because a writing environment may cause some writing errors. (25)Notes On ROM Code Protect (QzROM product shipped after writing) As for the QzROM product shipped after writing, the ROM code protect is specified according to the ROM option setup data in the mask file which is submitted at ordering. The ROM option setup data in the mask file is “00 16” for protect enabled or “FF16” for protect disabled. Note that the mask file which has nothing at the ROM option data or has the data other than “00 16” and “FF 16” can not be accepted. (26)Data Required for QzROM Writing Orders The following are necessary when ordering a QzROM product shipped after writing: 1. QzROM Writing Confirmation Form* 2. Mark Specification Form* * For the QzROM writing confirmation form and the mark specification form, refer to th e “Renesas Technology Corp.” Homepage (http://www.renesas.com/homepage.jsp). Note that we cannot de al with special font marking (customer’s trademark etc.) in QzROM microcomputer. VDD VRST+ VRST- Recommended operating condition min. value VDD VRST+ VRST- Normal operation Reset No reset Program failure may occur. Recommended operating condition min. value

Rev.1.01 Feb 15, 2008 Page 73 of 146 REJ03B0224-0101 455A Group NOTES ON NOISE Countermeasures against noise are described below. The following counte rmeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. (1) Shortest wiring length The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer. The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer. (1) Wiring for RESET input pin Make the length of wiring which is connected to the RESET input pin as short as possible. Especially, connect a capacitor across the RESET input pin and the VSS pin with the shortest possible wiring.

• R e a s o n In order to reset a microcomputer correctly, 1 machine cycle or more of the width of a pulse input into the RESET pin is required. If noise having a shorter pulse wi dth than this is input to the RESET input pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Fig 72. Wiring for the RESET input pin (2) Wiring for cloc k input/output pins
• Make the length of wiring which is connected to clock I/O pins as short as possible.
• Make the length of wiring across the grounding lead of a capacitor which is connected to an oscillator and the V SS pin of a microcomputer as short as possible.
• Separate the V SS pattern only for osc illation from other VSS patterns. Fig 73. Wiring for clock I/O pins
• R e a s o n If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the V SS level of a microcomputer and the V SS level of an oscillator, the correct clock will not be input in the microcomputer. (3) Wiring to CNV SS pin Connect an approximately 5 k Ω resistor to the V PP pin and also to the GND pattern supplied to the V SS pin with shortest possible wiring.
• R e a s o n The CNVSS pin is the power source input pin for the built-in QzROM. When programming in the built-in QzROM, the impedance of the CNV SS pin is low to allow the electric current for writing flow into the QzROM. Because of this, noise can enter easily. If noise enters the CNVSS pin, abnormal instruction codes or data ar e read from the built-in QzROM, which may cause a program runaway. Fig 74. Wiring for CNV SS pin RESETReset circuit Noise VSSVSS N.G. Reset circuit VSS RESET VSS O.K. Noise XIN XOUT VSS N.G. XIN XOUT VSS O.K. CNVss VSS The shortest The shortest about 5k Ω Note: This indicates pin. (Note) (Note)

Rev.1.01 Feb 15, 2008 Page 74 of 146 REJ03B0224-0101 455A Group (2) Connection of bypass capacitor across V SS line and VDD line Connect an approximately 0.1 µF bypass capacitor across the VSS line and the VDD line as follows:

• Connect a bypass capacitor across the VSS pin and the VDD pin at equal length.
• Connect a bypass capacitor across the VSS pin and the VDD pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS line and VDD line.
• Connect the power source wiring via a bypass capacitor to the VSS pin and the VDD pin. Fig 75. Bypass capacitor across the V SS line and the VDD line (3) Oscillator concerns Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping oscillator away from large current signal lines Install a microcomputer (and es pecially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows.
• R e a s o n In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and th ermal heads or others. When a large current flows through t hose signal lines, strong noise occurs because of mutual inductance. Fig 76. Wiring for a large current signal line (2) Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines wher e potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise.
• R e a s o n Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be de formed, which causes a microcomputer failure or a program runaway. Fig 77. Wiring to a signal line where potential levels change frequently VSS VDD VSS VDD N.G. O.K. XIN XOUT VSS M Microcomputer Mutual inductance Large current GND XIN XOUT VSS CNTRDo not cross N.G.

Rev.1.01 Feb 15, 2008 Page 75 of 146 REJ03B0224-0101 455A Group (3) Oscillator protection using V SS pattern As for a two-sided printed circuit board, print a V SS pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. Connect the VSS pattern to the microcomputer VSS pin with the shortest possible wiring. Besides, separate this VSS pattern from other VSS patterns. Fig 78. V SS pattern on the underside of an oscillator (4) Setup for I/O ports Setup I/O ports using hardware and software as follows: <Hardware>

• Connect a resistor of 100 Ω or more to an I/O port in series. <Software>
• As for an input port, read data several times by a program for checking whether input levels are equal or not.
• As for an output port or an I/O port, since the output data may reverse because of noise, rewrite data to its output latch at fixed periods.
• Rewrite data to pull-up control registers at fixed periods. (5) Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a so ftware watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective th an program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main rout ine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that in terrupt processing is repeated multiple times in a single main routine processing. <The main routine>
• Assigns a single word of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition: N + 1 As the main routine execution cycle may change because of an interrupt processing or ot hers, the initial value N should have a margin.
• Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing after the initial value N has been set.
• Detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents do not change after interrupt processing. <The interrupt processing routine>
• Decrements the SWDT conten ts by 1 at each interrupt processing.
• Determines that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to branch to the program initia lization routine for recovery processing in the following case: If the SWDT contents are not in itialized to the initial value N but continued to decrement and if they reach 0 or less. Fig 79. Watchdog timer by software Oscillator wiring pattern example An example of VSS patterns on the underside of a printed circuit board Separate the VSS line for oscillation from other VSS lines XIN XOUT VSS Main routine Interrupt processing routine errors (SWDT) ← N EI Main processing (SWDT) = N? ≠ N N Interrupt processing routine (SWDT) ← (SWDT)−1 Interrupt processing (SWDT) ≤ 0? ≤ 0 > 0 RTI Return Main routine errors

Rev.1.01 Feb 15, 2008 Page 76 of 146 REJ03B0224-0101 455A Group CONTROL REGISTERS Note 1. “R” represents read enabled, and “W” represents write enabled. Note 2. When the contents of I1 2 and I13 are changed, the external interrupt request flag (EXF0) may be set. Interrupt control register V1 at reset : 0000 2 at power down : 00002 R/W (Note 1) TAV1/TV1A V13 Timer 2 interrupt enable bit 0 Interrupt disabled (SNZT2 instruction is valid) V12 Timer 1 interrupt enable bit 0 Interrupt disabled (SNZT1 instruction is valid) V11 Not used 0 This bit has no function, but read/write is enabled.1 V10 External 0 interrupt enable bit 0 Interrupt disabled (SNZ0 instruction is valid) Interrupt control register V2 at reset : 0000 2 at power down : 00002 R/W TAV2/TV2A V23 Not used 0 This bit has no function, but read/write is enabled.1 V22 Not used 0 This bit has no function, but read/write is enabled.1 V21 Not used 0 This bit has no function, but read/write is enabled.1 V20 Timer 3 interrupt enable bit 0 Interrupt disabled (SNZT3 instruction is valid) Interrupt control register I1 at reset : 0000 2 at power down : state retained R/W TAI1/TI1A I13 INT pin input control bit (Note 2) 0 INT pin input disabled Interrupt valid waveform for INT pin/ return level selection bit (Note 2)

0 Falling waveform (“L” leve l of INT pin is recogn ized with the SNZI0

instruction)/“L” level instruction)/“H” level I11 INT pin edge detection circuit control bit 0 One-sided edge detected INT pin timer 1 count start synchronous circuit selection bit

Rev.1.01 Feb 15, 2008 Page 77 of 146 REJ03B0224-0101 455A Group Note 1. R” represents read enabled, and “W” represents write enabled. Note 2. The stopped clock cannot be selected for system clock. Note 3. The oscillation circuit selected for system clock cannot be stopped. Clock control register MR at reset : 1100 2 at power down : state retained R/W TAMR/TMRA MR3 Operation mode selection bits MR3 MR2 Operation mode 0 0 Through mode 0 1 Frequency divided by 2 mode MR 2 1 0 Frequency divided by 4 mode 1 1 Frequency divided by 8 mode MR System clock selection bits (Note 2) MR1 MR0 System clock 0 0 f(HSOCO) MR0 0 1 f(XIN) 10 f ( X CIN) 1 1 f(LSOCO) Clock control register RG at reset : 1000 2 at power down : state retained W TRGA RG3 Low-speed on-chip oscillator (f(LSOCO)) control bit (Note 3)

0 Low-speed on-chip oscillator (f (LSOCO)) oscillation available

RG2 Sub-clock (f(XCIN)) control bit (Note 3) 0 Sub-clock (f(X CIN)) oscillation available, ports D6 and D7 not selected RG1 Main-clock (f(XIN)) control bit (Note 3) 0 Main clock (f(X IN)) oscillation available High-speed on-chip oscillator (f(HSOCO)) control bit (Note 3)

Rev.1.01 Feb 15, 2008 Page 78 of 146 REJ03B0224-0101 455A Group Note 1. “R” represents read enabled, and “W” represents write enabled. Note 2. This function is valid only when the timer 1 count start synchronous circuit is selected (I10 =“1”). Note 3. Port C output is invalid when CNTR input is selected for the timer 1 count source. Timer control register PA at reset : 0 2 at power down : 02 W TAPP PA0 Prescaler control bit 0 Stop (state retained) 1O p e r a t i n g Timer control register W1 at reset : 0000 2 at power down : state retained R/W (Note 1) TAW1/TW1A W13 Timer 1 count auto-stop circuit selection bit (Note 2) W12 Timer 1 control bit 0 Stop (state retained) 1O p e r a t i n g Timer 1 count source selection bits (Note 3) W11 W10 Count source W11 0 0 PWM signal (PWMOUT) 0 1 Prescaler output (ORCLK) 1 0 Timer 3 underflow signal (T3UDF)W10 1 1 CNTR input Timer control register W2 at reset : 0000 2 at power down : 00002 R/W TAW2/TW2A W23 CNTR pin function control bit 0 CNTR pin output invalid “H” interval expansion function control bit W21 Timer 2 control bit 0 Stop (state retained) W20 Timer 2 count source selection bit 0X IN input Timer control register W3 at reset : 0000 2 at power down : state retained R/W TAW3/TW3A W33 Timer 3 control bit 0 Stop (initial state) Timer 3 count value selection bits W32 W31 W30 Count value Timer control register W4 at reset : 0000 2 at power down : state retained R/W TAW4/TW4A W43 Timer LC control bit 0 Stop (state retained) W42 Timer LC count source selection bit 0B i t 4 ( T 34) of timer 3 CNTR pin output auto-control circuit selection bit W40 CNTR pin input count edge selection bit 0 Falling edge

Rev.1.01 Feb 15, 2008 Page 79 of 146 REJ03B0224-0101 455A Group Note 1. ”R” represents read enabled, and “W” represents write enabled. Note 2. “r (resistor) multiplied by 3” is used at 1/3 bias, and “r multiplied by 2” is used at 1/2 bias. Note 3. V LC3 is connected to VDD internally when SEG0 pin is selected. Note 4. Use internal di viding resistor when SEG1 and SEG2 pins are selected. Timer control register W5 at reset : 0000 2 at power down : state retained R/W TAW5/TW5A W53 Not used 0 This bit has no function, but read/write is enabled. 1 This bit has no function, but read/write is enabled. W52 Not used 0 This bit has no function, but read/write is enabled. 1 This bit has no function, but read/write is enabled. W51 Timer 3 count source selection bits W51 W52 Count source

00 X CIN input

LCD control register L1 at reset : 0000 2 at power down : state retained R/W TAL1/TL1A L13 Internal dividing resistor for LCD power supply selection bit (Note 2) 0 2r × 3, 2r × 2 1 r × 3, r × 2 L12 LCD control bit 0 Stop (OFF) LCD duty and bias selection bits L11 L1 Duty Bias L11 0 0 Not available N ot available 01 1 / 2 1 / 2 10 1 / 3 1 / 3 L10 11 1 / 4 1 / 3 LCD control register L2 at reset : 0000 2 at power down : state retained W TL2A L23 SEG0/VLC3 pin function switch bit (Note 3) 0 SEG 0 1V LC3 L22 SEG1/VLC2 pin function switch bit (Note 4) 0 SEG 1 1V LC2 L21 SEG2/VLC1 pin function switch bit (Note 4) 0 SEG 2 1V LC1 L20 Internal dividing resistor for LCD power supply control bit LCD control register L3 at reset : 1111 2 at power down : state retained W TL3A L33 P23/SEG27 pin function switch bit 0 SEG 27 1P 2 3 L32 P22/SEG26 pin function switch bit 0 SEG 26 1P 2 2 L31 P21/SEG25 pin function switch bit 0 SEG 25 1P 2 1 L30 P20/SEG24 pin function switch bit 0 SEG 24 1P 2 0

Rev.1.01 Feb 15, 2008 Page 80 of 146 REJ03B0224-0101 455A Group Note 1.“R” represents read enabled, and “W” represents write enabled. . LCD control register C1 at reset : 1111 2 at power down : state retained W TC1A C13 P03/SEG19 pin function switch bit 0 SEG 19 1P 0 3 C12 P02/SEG18 pin function switch bit 0 SEG 18 1P 0 2 C11 P01/SEG17 pin function switch bit 0 SEG 17 1P 0 1 C10 P00/SEG16 pin function switch bit 0 SEG 16 1P 0 0 LCD control register C2 at reset : 1111 2 at power down : state retained W TC2A C23 P13/SEG23 pin function switch bit 0 SEG 23 1P 1 3 C22 P12/SEG22 pin function switch bit 0 SEG 22 1P 1 2 C21 P11/SEG21 pin function switch bit 0 SEG 21 1P 1 1 C20 P10/SEG20 pin function switch bit 0 SEG 20 1P 1 0 LCD control register C3 at reset : 1111 2 at power down : state retained W TC3A C33 P33/SEG31 pin function switch bit 0 SEG 31 1P 3 3 C32 P32/SEG30 pin function switch bit 0 SEG 30 1P 3 2 C31 P31/SEG29 pin function switch bit 0 SEG 29 1P 3 1 C30 P30/SEG28 pin function switch bit 0 SEG 28 1P 3 0

Rev.1.01 Feb 15, 2008 Page 81 of 146 REJ03B0224-0101 455A Group Note 1. “R” represents read enabled, and “W” represents write enabled. Note 2. To be invalid (K2 2 = “0”) key-on wakeup of ports P30 and P31, set the registers K30 and K31 to “0.” Note 3. To be invalid (K2 3 = “0”) key-on wakeup of ports P32 and P33, set the registers K32 and K33 to “0.” Key-on wakeup control register K0 at reset : 0000 2 at power down : state retained R/W TAK0/TK0A K03 Ports P12 and P13 key-on wakeup control bit Ports P10 and P11 key-on wakeup control bit Ports P02 and P03 key-on wakeup control bit Ports P00 and P01 key-on wakeup control bit Key-on wakeup control register K1 at reset : 0000 2 at power down : state retained R/W TAK1/TK1A K13 Port P23 key-on wakeup control bit 0 Key-on wakeup not used K12 Port P22 key-on wakeup control bit 0 Key-on wakeup not used K11 Port P21 key-on wakeup control bit 0 Key-on wakeup not used K10 Port P20 key-on wakeup control bit 0 Key-on wakeup not used Key-on wakeup control register K2 at reset : 0000 2 at power down : state retained R/W TAK2/TK2A K23 Ports P32 and P33 key-on wakeup control bit (Note 3) Ports P30 and P31 key-on wakeup control bit (Note 2) K21 INT pin return condition selection bit 0 Return by level K20 INT pin key-on wakeup control bit 0 Key-on wakeup invalid Key-on wakeup control register K3 at reset : 0000 2 at power down : state retained R/W TAK3/TK3A K33 Ports D6 and D7 key-on wakeup control bit 0 Key-on wakeup not used K32 Ports D4 and D5 key-on wakeup control bit 0 Key-on wakeup not used K31 Ports D2 and D3 key-on wakeup control bit 0 Key-on wakeup not used K30 Ports D0 and D1 key-on wakeup control bit 0 Key-on wakeup not used

Rev.1.01 Feb 15, 2008 Page 82 of 146 REJ03B0224-0101 455A Group Note 1. “R” represents read enabled, and “W” represents write enabled. Pull-up control register PU0 at reset : 0000 2 at power down : state retained R/W TAPU0/TPU0A PU03 Port P12 and P13 pull-up transistor control bit Port P10 and P11 pull-up transistor control bit Port P02 and P03 pull-up transistor control bit Port P00 and P01 pull-up transistor control bit Pull-up control register PU1 at reset : 0000 2 at power down : state retained R/W TAPU1/TPU1A PU13 Port P23 pull-up transistor control bit 0 Pull-up transistor OFF PU12 Port P22 pull-up transistor control bit 0 Pull-up transistor OFF PU11 Port P21 pull-up transistor control bit 0 Pull-up transistor OFF PU10 Port P20 pull-up transistor control bit 0 Pull-up transistor OFF Pull-up control register PU2 at reset : 0000 2 at power down : state retained R/W TAPU2/TPU2A PU23 Port P33 pull-up transistor control bit 0 Pull-up transistor OFF PU22 Port P32 pull-up transistor control bit 0 Pull-up transistor OFF PU21 Port P31 pull-up transistor control bit 0 Pull-up transistor OFF PU20 Port P30 pull-up transistor control bit 0 Pull-up transistor OFF Pull-up control register PU3 at reset : 0000 2 at power down : state retained R/W TAPU3/TPU3A PU33 Port D6 and D7 pull-up transistor control bit 0 Pull-up transistor OFF PU32 Port D4 and D5 pull-up transistor control bit 0 Pull-up transistor OFF PU31 Port D2 and D3 pull-up transistor control bit 0 Pull-up transistor OFF PU30 Port D0 and D1 pull-up transistor control bit 0 Pull-up transistor OFF

Rev.1.01 Feb 15, 2008 Page 83 of 146 REJ03B0224-0101 455A Group Note 1. “W” represents write enabled. Port output structure control register FR0 at reset : 0000 2 at power down : state retained W TFR0A FR03 Ports P12 and P13 output structure selection bit

0 N-channel open-drain output

1 CMOS output

Ports P10 and P11 output structure selection bit Ports P02 and P03 output structure selection bit Ports P00 and P01 output structure selection bit Port output structure control register FR1 at reset : 0000 2 at power down : state retained W (Note 1) TFR1A FR13 Ports D3 output structure selection bit 0 N-channel open-drain output FR12 Ports D2 output structure selection bit 0 N-channel open-drain output FR11 Ports D1 output structure selection bit 0 N-channel open-drain output FR10 Ports D0 output structure selection bit 0 N-channel open-drain output Port output structure control register FR2 at reset : 0000 2 at power down : state retained W TFR2A FR23 Ports P32 and P33 output structure selection bit Ports P30 and P31 output structure selection bit FR21 Ports D5 output structure selection bit 0 N-channel open-drain output FR20 Ports D4 output structure selection bit 0 N-channel open-drain output Port output structure control register FR3 at reset : 0000 2 at power down : state retained W TFR3A FR33 Ports P23 output structure selection bit 0 N-channel open-drain output FR32 Ports P22 output structure selection bit 0 N-channel open-drain output FR31 Ports P21 output structure selection bit 0 N-channel open-drain output FR30 Ports P20 output structure selection bit 0 N-channel open-drain output

Rev.1.01 Feb 15, 2008 Page 84 of 146 REJ03B0224-0101 455A Group INSTRUCTIONS Each instruction is described as follows; 1. Index list of instruction function 2. Machine instructions (index by alphabet) 3. Machine instructions (index by function) 4. Instruction code table The symbols shown below are used in the following list of instruction function and the machine instructions. Note 1. The 455A Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped. SYMBOL Symbol Contents Symbol Contents A Register A (4 bits) R2H Timer 2 reload register (8 bits) B Register B (4 bits) RLC Timer LC reload register (4 bits) DR Register DR (3 bits) PS Prescaler E Register E (8 bits) T1 Timer 1 V1 Interrupt control register V1 (4 bits) T2 Timer 2 V2 Interrupt control register V2 (4 bits) TLC Timer LC I1 Interrupt control register I1 (4 bits) T1F Timer 1 interrupt request flag PA Timer control register PA (1 bit) T2F Timer 2 interrupt request flag W1 Timer control register W1 (4 bits) T3F Timer 3 interrupt request flag W2 Timer control register W2 (4 bits) WDF1 Watchdog timer flag W3 Timer control register W3 (4 bits) WEF Watchdog timer enable flag W4 Timer control register W4 (4 bits) INTE Interrupt enable flag W5 Timer control register W5 (5 bits) EXF0 External 0 interrupt request flag MR Clock control register MR (4 bits) VDF Voltage drop detection circuit flag RG Clock control register RG (3 bits) P Power down flag L1 LCD control register L1 (4 bits) D Port D (8 bits) L2 LCD control register L2 (4 bits) P0 Port P0 (4 bits) L3 LCD control register L3 (4 bits) P1 Port P1 (4 bits) C1 LCD control register C1 (4 bits) P2 Port P2 (4 bits) C2 LCD control register C2 (4 bits) P3 Port P3 (4 bits) C3 LCD control register C3 (4 bits) C Port C (1 bit) K0 Key-on wakeup control register K0 (4 bits) INT INT pin (1 bit) K1 Key-on wakeup control register K1 (4 bits) K2 Key-on wakeup control register K2 (4 bits) x Hexadecimal variable K3 Key-on wakeup control register K3 (4 bits) y Hexadecimal variable PU0 Pull-up control register PU0 (4 bits) z Hexadecimal variable PU1 Pull-up control register PU1 (4 bits) p Hexadecimal variable PU2 Pull-up control register PU2 (4 bits) n Hexadecimal constant PU3 Pull-up control register PU3 (4 bits) i Hexadecimal constant FR0 Port output structure control regist er FR0 (4 bits) j H exadecimal constant FR1 Port output structure control register FR1 (4 bits) A

3 A2 A1 A0 Binary notation of hexadecimal variable A

(same for others)FR2 Port output structure control register FR2 (4 bits) FR3 Port output structure control register FR3 (4 bits) ← Direction of data movement X Register X (4 bits) ( ) Contents of registers and memories Y Register Y (4 bits) − Negate, Flag unchanged after executing instruction Z Register Z (2 bits) M (DP) RAM address pointed by the data pointer DP Data pointer (10 bits) (It consists of registers X, Y, and Z) a Label indicating address a 6 a5 a4 a3 a2 a1 a0 p, a Label indicating address a 6 a5 a4 a3 a2 a1 a0 in page p6 p5 p4 p3 p2 p1 p0PC Program counter (14 bits) PCH High-order 7 bits of program counter PCL Low-order 7 bits of program counter C+x Hex . C + Hex. number x (also same for others) SK Stack register (14 bits × 8) ? Decision of state shown before “?” SP Stack pointer (3 bits) ← → Data exchange between a register and memory CY Carry flag UPTF High-order bit reference enable flag RPS Prescaler reload register (8 bits) R1 Timer 1 reload register (8 bits) R2L Timer 2 reload register (8 bits)

Rev.1.01 Feb 15, 2008 Page 85 of 146 REJ03B0224-0101 455A Group Note 1. M3455AG8: p=0 to 63 and M3455AGC: p=0 to 95. INDEX LIST OF INSTRUCTION FUNCTION Group- ing Mnemonic Function Page Register to register transfer TAB (A) ← (B) 103 122 TBA (B) ← (A) 110 122 TAY (A) ← (Y) 110 122 TYA (Y) ← (A) 119 122 TEAB (E 7−E4) ← (B) (E3−E0) ← (A) 112 122 TABE (B) ← (E7−E4) (A) ← (E3−E0) 104 122 TDA (DR 2−DR0) ← (A2−A0) 111 122 TAD (A 2−A0) ← (DR2−DR0) (A3) ← 0 105 122 TAZ (A 1, A0) ← (Z1, Z0) (A3, A2) ← 0 110 122 TAX (A) ← (X) 110 122 TASP (A 2−A0) ← (SP2−SP0) (A3) ← 0 108 122 RAM addresses LXY x, y (X) ← x, x = 0 to 15 (Y) ← y, y = 0 to 15 93 122 LZ z (Z) ← z, z = 0 to 3 93 122 INY (Y) ← (Y) + 1 92 122 DEY (Y) ← (Y) − 1 90 122 RAM to register transfer TAM j (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 106 122 XAM j (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 120 122 XAMD j (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) − 1 120 122 XAMI j (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 120 122 TMA j (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 115 122 Group- ing Mnemonic Function Page Arithmetic operation LA n (A) ← n n = 0 to 15 92 124 TABP p (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← (DR2−DR0, A3−A0) (UPTF) = 1, (DR2) ← 0 (DR1, DR0) ← (ROM(PC))9, 8 (B) ← (ROM(PC))7−4 (A) ← (ROM(PC))3−0 (PC) ← (SK(SP)) (SP) ← (SP) − 1 104 124 AMC (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry 87 124 A n (A) ← (A) + n n = 0 to 15 87 124 AND (A) ← (A)AND(M(DP)) 87 124 OR (A) ← (A)OR(M(DP)) 94 124 SC (CY) ← 1 98 124 RC (CY) ← 0 96 124 SZC (CY) = 0 ? 102 124 CMA (A) ← (A) 89 124 RAR 95 124 Bit operation SB j (Mj(DP)) ← 1 j = 0 to 3 97 124 RB j (Mj(DP)) ← 0 j = 0 to 3 95 124 SZB j (Mj(DP)) = 0 ? j = 0 to 3 101 124 Comparison operation SEAM (A) = (M(DP)) ? 99 126 SEA n (A) = n ? n = 0 to 15 98 126 Branch operation B a (PC L) ← a6−a0 88 126 BL p, a (PC H) ← p (PCL) ← a6−a0 88 126 BLA p (PC H) ← p (PCL) ← (DR2−DR0, A3−A0) 88 126 CY A3A2A1A0

Rev.1.01 Feb 15, 2008 Page 86 of 146 REJ03B0224-0101 455A Group Note 1. M3455AG8: p=0 to 63 and M3455AGC: p=0 to 95. INDEX LIST OF INSTRUCTION FUNCTION (continued) Group- ing Mnemonic Function Page Subroutine operation BM a (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← 2 (PCL) ← a6−a0 88 126 BML p, a (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← a6−a0 89 126 BMLA p (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← (DR2−DR0, A3−A0) 89 126 Return operation RTI (PC) ← (SK(SP)) (SP) ← (SP) − 1 97 126 RT (PC) ← (SK(SP)) (SP) ← (SP) − 1 96 126 RTS (PC) ← (SK(SP)) (SP) ← (SP) − 1 97 126 Interrupt operation DI (INTE) ← 0 90 128 EI (INTE) ← 1 91 128 SNZ0 V1 0 = 0 : (EXF0) = 1 ? (EXF0) ← 0 V10 = 1 : SNZ0 = NOP 99 128 SNZI0 I1 2 = 0 : (INT) = “L” ? 99 128 TAV1 (A) ← (V1) 108 128 TV1A (V1) ← (A) 118 128 TAV2 (A) ← (V2) 108 128 TV2A (V2) ← (A) 118 128 TAI1 (A) ← (I1) 105 128 TI1A (I1) ← (A) 113 128 Group- ing Mnemonic Function Page Timer operation TPAA (PA) ← (A) 116 128 TAW1 (A) ← (W1) 109 128 TW1A (W1) ← (A) 118 128 TAW2 (A) ← (W2) 109 128 TW2A (W2) ← (A) 118 128 TAW3 (A) ← (W3) 109 128 TW3A (W3) ← (A) 119 128 TAW4 (A) ← (W4) 109 128 TW4A (W4) ← (A) 119 128 TAW5 (A) ← (W5) 119 128 TW5A (W5) ← (A) 119 128 TABPS (B) ← (TPS7−TPS4) (A) ← (TPS3−TPS0) 104 130 TPSAB (RPS 7−RPS4) ← (B) (TPS7−TPS4) ← (B) (RPS3−RPS0) ← (A) (TPS3−TPS0) ← (A) 116 130 TAB1 (B) ← (T17−T14) (A) ← (T13−T10) 103 130 T1AB (R1 7−R14) ← (B) (T17−T14) ← (B) (R13−R10) ← (A) (T13−T10) ← (A) 102 130 TR1AB (R1 7−R14) ← (B) (R13−R10) ← (A) 117 130 TAB2 (B) ← (T27−T24) (A) ← (T23−T20) 104 130 T2AB (R2L 7−R2L4) ← (B) (T27−T24) ← (B) (R2L3−R2L0) ← (A) (T23−T20) ← (A) 102 130 T2R2L (T2 7−T20) ← (R2L7−R2L0) 103 130 T2HAB (R2H 7−R2H4) ← (B) (R2H3−R2H0) ← (A) 103 130

Rev.1.01 Feb 15, 2008 Page 87 of 146 REJ03B0224-0101 455A Group Note 1. (SBK, RBK) cannot be used in the M3455AG8. INDEX LIST OF INSTRUCTION FUNCTION (continued) Group- ing Mnemonic Function Page Timer operation TLCA (RLC) ← (A) (TLC) ← (A) 115 130 SNZT1 V1 2 = 0 : (T1F) = 1 ? (T1F) ← 0 V12 = 1 : SNZT1=NOP 100 130 SNZT2 V1 3 = 0 : (T2F) = 1 ? (T2F) ← 0 V13 = 1 : SNZT2=NOP 100 130 SNZT3 V2 0 = 0 : (T3F) = 1 ? (T3F) ← 0 V20 = 1 : SNZT3=NOP 100 130 Input/Output operation IAP0 (A) ← (P0) 91 132 OP0A (P0) ← (A) 93 132 IAP1 (A) ←(P1) 91 132 OP1A (P1) ← (A) 94 132 IAP2 (A) ← (P2) 92 132 OP2A (P2) ← (A) 94 132 IAP3 (A) ← (P3) 92 132 OP3A (P3) ← (A) 94 132 CLD (D) ← 1 89 132 RCP (C) ← 0 96 132 SCP (C) ← 1 98 132 TFR0A (FR0) ← (A) 112 132 TFR1A (FR1) ← (A) 112 132 TFR2A (FR2) ← (A) 112 132 TFR3A (FR3) ← (A) 113 132 TAPU0 (A) ← (PU0) 107 132 TPU0A (PU0) ← (A) 116 132 TAPU1 (A) ← (PU1) 107 132 TPU1A (PU1) ← (A) 116 132 TAPU2 (A) ← (PU2) 107 132 TPU2A (PU2) ← (A) 117 132 TAPU3 (A) ← (PU3) 108 132 Group- ing Mnemonic Function Page Input/Output operation TPU3A (PU3) ← (A) 117 132 TAK0 (A) ← (K0) 105 134 TK0A (K0) ← (A) 113 134 TAK1 (A) ← (K1) 105 134 TK1A (K1) ← (A) 113 134 TAK2 (A) ← (K2) 106 134 TK2A (K2) ← (A) 114 134 TAK3 (A) ← (K3) 106 134 TK3A (K3) ← (A) 114 134 LCD operation TAL1 (A) ← (L1) 106 134 TL1A (L1) ← (A) 114 134 TL2A (L2) ← (A) 114 134 TL3A (L3) ← (A) 115 134 TC1A (C1) ← (A) 111 134 TC2A (C2) ← (A) 111 134 TC3A (C3) ← (A) 111 134 Clock operation TAMR (A) ← (MR) 107 134 TMRA (MR) ← (A) 115 134 TRGA (RG 2−RG0) ← (A2−A0 117 134 Other operation NOP (PC) ← (PC)+1 93 136 POF Transition to clock operating 95 136 POF2 Transition to RAM back-up 95 136 EPOF POF instruction valid 91 136 SNZP (P) = 1 ? 99 136 SNZVD (VDF) = 1? 100 136 WRST (WDF1) = 1 ? (WDF1) ← 0 119 136 DWDT Stop of watchdog timer func- tion enabled 90 136 SRST System reset 101 136 RUPT (UPTF) ←0 97 136 SUPT (UPTF) ←1 101 136 SVDE At power down mode, volt- age drop detection circuit valid 101 136 RBK (Note 1) When TABPp instruction is executed, p6©0 81 117 SBK (Note 1) When TABPp instruction is executed, p6©1 84 117

Rev.1.01 Feb 15, 2008 Page 88 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) A n (Add n and accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 000110nnnn 2 06n 16 11- O v e r f l o w = 0 Opera- tion: (A) ← (A) + n n = 0 to 15 Grouping: Arithmetic operation Description: Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation. AM (Add accumulator and Memory) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000001010 2 00A 16 11- - Opera- tion: (A) ← (A)Å{(M(DP)) Grouping: Arithmetic operation Description: Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged. AMC (Add accumulator, Memory and Carry) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000001011 2 00B 16 11 0 / 1 - Opera- tion: (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry Grouping: Arithmetic operation Description: Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. AND (logical AND between accumulator and memory) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000011000 2 018 16 11- - Opera- tion: (A) ← (A) AND (M(DP)) Grouping: Arithmetic operation Description: Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in regis- ter A.

Rev.1.01 Feb 15, 2008 Page 89 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) B a (Branch to address a) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 011 a 6 a5 a4 a3 a2 a1 a0 2 1 8 +a a 16 11- - Opera- tion: (PCL) ← a6 to a0 Grouping: Branch operation Description: Branch within a page : Branches to address a in the identi- cal page. Note: Specify the branch address with in the page including this instruction. BL p,a (Branch Long to address a in page p) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 00111 p 4 p3 p2 p1 p0 2 0 E +p p 16 2 2 - - 1p 6 p5 a6 a5 a4 a3 a2 a1 a0 2 2aa 16 Grouping: Branch operation Description: Branch out of a page : Branches to address a in page p. Note: M3455AG8: p=0 to 63 p6=0 M3455AGC: p=0 to 95 Opera- tion: (PCH) ← p (PCL) ← a6 to a0 BLA p (Branch Long to address (D)+(A) in page p) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000010000 2 010 16 22- - 1p 6 p5 p4 00 p 3 p2 p1 p0 2 2pp 16 Grouping: Branch operation Description: Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. Note: M3455AG8: p=0 to 63 p6=0 M3455AGC: p=0 to 95 Opera- tion: (PCH) ← p (PCL) ← (DR2−R0, A3−A0) BM a (Branch and Mark to address a in page 2) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 010 a 6 a5 a4 a3 a2 a1 a0 2 1aa 16 11- - Opera- tion: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← 2 (PCL) ← a6−a0 Grouping: Subroutine call operation Description: Call the subroutine in page 2 : Calls the subroutine at address a in page 2. Note: Subroutine extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. Be careful not to over the stack because the maximum level of subroutine nesting is 8.

Rev.1.01 Feb 15, 2008 Page 90 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) BML p,a (Branch and Mark Long to address a in page p) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 00110 p 4 p3 p2 p1 p0 2 0 c +p p 16 22- - 1p 6 p5 a6 a5 a4 a3 a2 a1 a0 2 2aa 16 Grouping: Subroutine call operation Description: Call the subroutine : Calls the subroutine at address a in page p. Note: M3455AG8: p=0 to 63 p6=0 M3455AGC: p=0 to 95 Be careful not to over the stack because the maximum level of subroutine nesting is 8. Opera- tion: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← a6−a0 BMLA p (Branch and Mark Long to address (D)+(A) in page p) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000110000 2 030 16 22- - 1p 6 p5 p4 00 p 3 p2 p1 p0 2 2pp 16 Grouping: Subroutine call operation Description: Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. Note: M3455AG8: p=0 to 63 p6=0 M3455AGC: p=0 to 95 Be careful not to over the stack because the maximum level of subroutine nesting is 8. Opera- tion: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← (DR2−DR0, A3−A0) CLD (CLear port D) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000010001 2 011 16 11- - Opera- tion: (D) ← 1 Grouping: Input/Output operation Description: Sets (1) to port D. CMA (CoMplement of Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000011100 2 01C 16 11- - Opera- tion: (A) ←(A) Grouping: Arithmetic operation Description: Stores the one’s complement for register A’s contents in register A.

Rev.1.01 Feb 15, 2008 Page 91 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) DEY (DEcrement register Y) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000010111 2 017 16 11- ( Y ) = 1 5 Opera- tion: (Y) ← (Y) −1 Grouping: RAM addresses Description: Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.DI (Disable Interrupt) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000000100 2 004 16 11- - Opera- tion: (INTE) ← 0 Grouping: Interrupt control operation Description: Clears (0) to interrupt enable flag INTE, and disables the interrupt. Note: Interrupt is disabled by ex ecuting the DI instruction after executing 1 machine cycle. DWDT (Disable WatchDog Timer) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1010011100 2 29C 16 11- - Opera- tion: Stop of watchdog timer function enabled Grouping: Other operation Description: Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction.

Rev.1.01 Feb 15, 2008 Page 92 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) EI (Enable Interrupt) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000000101 2 005 16 11- - Opera- tion: (INTE) ← 1 Grouping: Interrupt control operation Description: Sets (1) to interrupt enable flag INTE, and enables the interrupt. Note: Interrupt is enabled by exec uting the EI instruction after executing 1 machine cycle. EPOF (Enable POF instruction) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001011011 2 05B 16 11- - Opera- tion: POF instruction or POF2 instruction valid Grouping: Other operation Description: Makes the immediate after POF instruction or POF2 instruction valid by executing the EPOF instruction. IAP0 (Input Accumulator from port P0) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001100000 2 260 16 11- - Opera- tion: (A) ← (P0) Grouping: Input/Output operation Description: Transfers the input of port P0 to register A. IAP1 (Input Accumulator from port P1) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001100001 2 261 16 11- - Opera- tion: (A) ← (P1) Grouping: Input/Output operation Description: Transfers the input of port P1 to register A.

Rev.1.01 Feb 15, 2008 Page 93 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) IAP2 (Input Accumulator from port P2) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001100010 2 262 16 11- - Opera- tion: (A) ← (P2) Grouping: Input/Output operation Description: Transfers the input of port P2 to the register A. IAP3 (Input Accumulator from port P3) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001100011 2 263 16 11- - Opera- tion: (A) ← (P3) Grouping: Input/Output operation Description: Transfers the input of port P3 to the register A. INY (INcrement register Y) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000010011 2 013 16 11- ( Y ) = 0 Opera- tion: (Y) ← (Y) + 1 Grouping: RAM addresses Description: Adds 1 to the contents of register Y . As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. LA n (Load n in Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 000111nnnn 2 07n 16 11- Continuous tion: (A) ← n n = 0 to 15 Grouping: Arithmetic operation Description: Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and exe- cuted, only the first LA instruction is executed and other LA instructions coded continuously are skipped.

Rev.1.01 Feb 15, 2008 Page 94 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) LXY x,y (Load register X and Y with x and y) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 11 x 3 x2 x1 x0 y3 y2 y1 y0 2 3xy 16 11- Continuous tion: (X) ← x x = 0 to 15 (Y) ← y y = 0 to 15 Grouping: RAM addresses Description: Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. LZ z (Load register Z with z) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition

00010010 Z 1 Z0 2 04 8

+z 16 1 1 - - Opera- tion: (Z) ← z z = 0 to 3 Grouping: RAM addresses Description: Loads the value z in the immediate field to register Z. NOP (No OPeration) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000000000 2 000 16 11- - Opera- tion: (PC) ← (PC) + 1 Grouping: Other operation Description: No operation; Adds 1 to program counter value, and others remain unchanged. OP0A (Output port P0 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000100000 2 220 16 11- - Opera- tion: (P0) ← (A) Grouping: Input/Output operation Description: Outputs the contents of register A to port P0.

Rev.1.01 Feb 15, 2008 Page 95 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) OP1A (Output port P1 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000100001 2 221 16 11- - Opera- tion: (P1) ← (A) Grouping: Input/Output operation Description: Outputs the contents of register A to port P1. OP2A (Output port P2 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000100010 2 222 16 11- - Opera- tion: (P2) ← (A) Grouping: Input/Output operation Description: Outputs the contents of the register A to port P2. OP3A (Output port P3 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000100011 2 223 16 11- - Opera- tion: (P3) ← (A) Grouping: Input/Output operation Description: Outputs the contents of the register A to port P3. OR (logical OR between accumulator and memory) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000011001 2 019 16 11- - Opera- tion: (A) ← (A) OR (M(DP)) Grouping: Arithmetic operation Description: Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register

Rev.1.01 Feb 15, 2008 Page 96 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) POF (Power OFf) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000000010 2 002 16 11- - Opera- tion: Transition to clock operating mode Grouping: Other operation Description: Puts the system in clock operating mode by executing the POF2 instruction after executing the EPOF instruction. Note: If the EPOF instruction is not executed just before this instruction, this instruction is equivalent to the NOP instruc- tion. POF2 (Power OFf2) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000001000 2 008 16 11- - Opera- tion: Transition to RAM back-up mode Grouping: Other operation Description: Puts the system in RAM back-up state by executing the POF2 instruction after executing the EPOF instruction. Note: If the EPOF instruction is not executed before executing this instruction, this instruction is equivalent to the NOP instruction. RAR (Rotate Accumulator Right) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000011101 2 01D 16 11 0 / 1 - Opera- tion: Grouping: Arithmetic operation Description: Rotates 1 bit of the contents of register A including the con- tents of carry flag CY to the right. RB j (Reset Bit) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 00010011 j j 2 04 C +j 16 11- - Opera- tion: (Mj(DP)) ← 0 j = 0 to 3 Grouping: Bit operation Description: Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). CY A3A2A1A0

Rev.1.01 Feb 15, 2008 Page 97 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) RBK (Reset Bank flag) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 00010 0 0000 2 040 16 11- - Opera- tion: When TABPp instruction is executed, p6©0 Grouping: Other operation Description: Sets referring data area to pages 0 to 63 when the TABPp instruction is executed. This instruction is valid only for the TABPp instruction. Note: This instruction cannot be used in M3455AG8. RC (Reset Carry flag) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000000110 2 006 16 110 - Opera- tion: (CY) ← 0 Grouping: Arithmetic operation Description: Clears (0) to carry flag CY. RCP (Reset Port C) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1010001100 2 28C 16 11- - Opera- tion: (C) ← 0 Grouping: Input/Output operation Description: Clears (0) to port C. RD (Reset port D specified by register Y) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000010100 2 014 16 11- - Opera- tion: (D(Y)) ← 0 (Y) = 0 to 7 Grouping: Input/Output operation Description: Clears (0) to a bit of port D specified by register Y. Note: (Y) = 0 to 7. Do not execute this instruction if values except above are set to register Y.

Rev.1.01 Feb 15, 2008 Page 98 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) RT (ReTurn from subroutine) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001000100 2 044 16 12- - Opera- tion: (PC) ← (SK(SP)) (SP) ← (SP) −1 Grouping: Return operation Description: Returns from subroutine to the routine called the subrou- tine. RTI (ReTurn from Interrupt) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001000110 2 046 16 11- - Opera- tion: (PC) ← (SK(SP)) (SP) ← (SP) − 1 Grouping: Return operation Description: Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt. RTS (ReTurn from subroutine and Skip) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001000101 2 045 16 1 2 - Skip at uncondition Operation: (PC) ← (SK(SP)) (SP) ← (SP) − 1 Grouping: Return operation Description: Returns from subroutine to the routine called the subrou- tine, and skips the next instruction at uncondition. RUPT (Reset UPT flag) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001011000 2 058 16 11- - Opera- tion: (UPTF) ←0 Grouping: Other operation Description: Clears (0) to the high-order bit reference enable flag UPTF. Note: Even when the table reference instruction (TABP p) is exe- cuted, the high-order 2 bits of ROM reference data is not transferred to register D. SB j (Set Bit) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 00010111 j j 2 05 C +j 16 1 1 - - Opera- tion: (Mj(DP)) ← 1 j = 0 to 3 Grouping: Bit operation Description: Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).

Rev.1.01 Feb 15, 2008 Page 99 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SBK (Set BanK flag) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001000001 2 041 16 11- - Opera- tion: When TABPp instruction is executed, p6©1 Grouping: Arithmetic operation Description: Sets referring data area to pages 64 to 127 when the TABPp instruction is executed. This instruction is valid only for the TABPp instruction. Note: This instruction cannot be used in M3455AG8. SC (Set Carry flag) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000000111 2 007 16 111 - Opera- tion: (CY) ← 1 Grouping: Arithmetic operation Description: Sets (1) to carry flag CY. SCP (Set Port C) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1010001101 2 28D 16 11- - Opera- tion: (C) ← 1 Grouping: Input/Output operation Description: Sets (1) to port C. SD (Set port D specified by register Y) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000010101 2 015 16 11- - Opera- tion: (D(Y)) ← 1 (Y) = 0 to 7 Grouping: Input/Output operation Description: Sets (1) to a bit of port D specified by register Y . Note: (Y) = 0 to 7. Do not execute this instruction if values except above are set to register Y. SEA n (Skip Equal, Accumulator with immediate data n) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000100101 2 025 16 22- (A) = n n = 0 to 15 000111nnnn 2 07n 16 Grouping: Comparison operation Description: Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Executes the next instruction when the contents of register A is not equal to the value n in the immediate field. Opera- tion: (A) = n ? n = 0 to 15

Rev.1.01 Feb 15, 2008 Page 100 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SEAM (Skip Equal, Accumulator with Memory) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000100110 2 026 16 1 1 - (A) = (M(DP)) Opera- tion: (A) = (M(DP)) ? Grouping: Comparison operation Description: Skips the next instruction when the contents of register A is equal to the contents of M(DP). Executes the next instruction when the contents of register A is not equal to the contents of M(DP).SNZ0 (Skip if Non Zero condition of external interrupt 0 request flag) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000111000 2 038 16 11- V 1 0 = 0 : (EXF0) = 1 Opera- tion: (EXF0) ← 0 V10 = 1 : SNZ0 = NOP (V10 : bit 0 of the interrupt control register V1) Grouping: Interrupt operation Description: When V10 = 0 : Clears (0) to the EXF0 flag and skips the next instruction when external 0 interrupt request flag EXF0 is “1”. When the EXF0 flag is “0”, executes the next instruction. When V1 0 = 1 : This instruction is equivalent to the NOP instruction. SNZI0 (Skip if Non Zero condition of external Interrupt 0 input pin) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000111010 2 03A 16 11- I12 = 0 : (INT0) = “L” Opera- tion: (I12 : bit 2 of the interrupt control register I1) Grouping: Interrupt operation Description: When I12 = 0 : Skips the next instruction when the level of INT pin is “L”. Executes the next instruction when the level of INT pin is “H”. When I12 = 1 : Skips the next instruction when the level of INT pin is “H.” Executes the next instruction when the level of INT pin is “L”. SNZP (Skip if Non Zero condition of Power down flag) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000000011 2 003 16 11- ( P ) = 1 Opera- tion: (P) = 1 ? Grouping: Other operation Description: Skips the next instruction when the P flag is “1”. After skipping, the P flag remains unchanged. Executes the next instruction when the P flag is “0”.

Rev.1.01 Feb 15, 2008 Page 101 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SNZT1 (Skip if Non Zero condition of Timer 1 interrupt request flag) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1010000000 2 280 16 11- V 1 2 = 0 : (T1F) = 1 Opera- tion: (T1F) ← 0 V12 = 1 : SNZT1 = NOP (V12 = bit 2 of interrupt control register V1) Grouping: Timer operation Description: When V12 = 0 : Clears (0) to the T1F flag and skips the next instruction when timer 1 interrupt request flag T1F is “1”. When the T1F flag is “0,” executes the next instruction. When V1 2 = 1 : This instruction is equivalent to the NOP instruction. SNZT2 (Skip if Non Zero condition of Timer 2 interrupt request flag) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1010000001 2 281 16 11- V 1 3 = 0 : (T2F) = 1 Opera- tion: (T2F) ← 0 V13 = 1 : SNZT2 = NOP (V13 = bit 3 of interrupt control register V1) Grouping: Timer operation Description: When V13 = 0 : Clears (0) to the T2F flag and skips the next instruction when timer 2 interrupt request flag T2F is “1”. When the T2F flag is “0”, executes the next instruction. When V13 = 1 : This instruction is equivalent to the NOP instruction. SNZT3 (Skip if Non Zero condition of Timer 3 interrupt request flag) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1010000010 2 282 16 11- V 2 0 = 0 : (T3F) = 1 Opera- tion: (T3F) ← 0 V20 = 1 : SNZT3 = NOP Grouping: Timer operation Description: When V20 = 0 : Clears (0) to the T3F flag and skips the next instruction when timer 3 interrupt request flag T3F is “1”. When the T3F flag is “0”, executes the next instruction. When V20 = 1 : This instruction is equivalent to the NOP instruction. SNZVD (Skip if Non Zero condition of Voltage Detector flag) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1010001010 2 28A 16 11- V 2 3 = 0 : (VDF) = 1 Opera- tion: (VDF) = 1? Grouping: Other operation Description: Skips the next instruction when voltage drop detection cir- cuit flag VDF is “1”. Execute instruction when VDF is “0”. After skipping, the contents of VDF remains unchanged.

Rev.1.01 Feb 15, 2008 Page 102 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SRST (System ReSet) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000000001 2 001 16 11- - Opera- tion: System reset Grouping: Other operation Description: System reset occurs. SUPT (Set UPT flag) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001011001 2 059 16 11- - Opera- tion: (UPTF) ←1 Grouping: Other operation Description: Sets (1) to the high-order bit reference enable flag UPTF. When the table reference instruction (TABP p) is executed, the high-order 2 bits of ROM reference data is transferred to the low-order 2 bits of register D.SVDE (Set Voltage Detector Enable flag) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1010010011 2 293 16 11- - Opera- tion: Voltage drop detection circuit valid at powerdown mode. Grouping: Other operation Description: Voltage drop detection circuit is valid at powerdown mode (clock operating mode, RAM back-up mode) Note: This instruction can be used only for H version. SZB j (Skip if Zero, Bit) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 00001000 j j 2 02 j 16 11- (Mj(DP)) = 0 j = 0 to 3 Opera- tion: (Mj(DP)) = 0 ? j = 0 to 3 Grouping: Bit operation Description: Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0”. Executes the next instruction when the contents of bit j of M(DP) is “1”.

Rev.1.01 Feb 15, 2008 Page 103 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SZC (Skip if Zero, Carry flag ) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000101111 2 02F 16 11- ( C Y ) = 0 Opera- tion: (CY) = 0 ? Grouping: Arithmetic operation Description: Skips the next instruction when the contents of carry flag CY is “0”. After skipping, the CY flag remains unchanged. Executes the next instruction when the contents of the CY flag is “1”. SZD (Skip if Zero, port D specified by register Y) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000100100 2 024 16 2 2 - (D(Y)) = 0 0000101011 2 02B 16 Grouping: Input/Output operation Description: Skips the next instruction when a bit of port D specified by register Y is “0”. Executes the next instruction when the bit is “1”. Note: (Y) = 0 to 5. Do not execute this instruction if values except above are set to register Y. Opera- tion: (D(Y)) = 0 ? (Y) = 0 to 5 T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000110000 2 230 16 11- - Opera- tion: (T17−T14) ← (B) (R17−R14) ← (B) (T13−T10) ← (A) (R13−R10) ← (A) Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1. Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1.T2AB (Transfer data to timer 2 and register R2L from Accumulator and register B) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000110001 2 231 16 11- - Opera- tion: (T27−T24) ← (B) (R2L7−R2L4) ← (B) (T23−T20) ← (A) (R2L3−R2L0) ← (A) Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits (T27−T24) of timer 2 and the high-order 4 bits (R2L7−R2L4) of timer 2 reload register R2L. Transfers the contents of register A to the low-order 4 bits (T23−T20) of timer 2 and the low-order 4 bits (R2L3−R2L0) of timer 2 reload register R2.

Rev.1.01 Feb 15, 2008 Page 104 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) T2HAB (Transfer data to register R2H from Accumulator and register B) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1010010100 2 294 16 11- - Opera- tion: (R2H7−R2H4) ← (B) (R2H3−R2H0) ← (A) Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2H. Transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2H.T2R2L (Transfer data to timer 2 from register R2L) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1010010101 2 295 16 11- - Opera- tion: (T27−T20) ← (R2L7−R2L0) Grouping: Timer operation Description: Transfers the contents of reload register R2L to timer 2. TAB (Transfer data to Accumulator from register B) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000011110 2 01E 16 11- - Opera- tion: (A) ← (B) Grouping: Register to register transfer Description: Transfers the contents of register B to register A. TAB1 (Transfer data to Accumulator and register B from timer 1) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001110000 2 270 16 11- - Opera- tion: (B) ← (T17−T14) (A) ← (T13−T10) Grouping: Timer operation Description: Transfers the high-order 4 bits (T17−T14) of timer 1 to reg- ister B. Transfers the low-order 4 bits (T1 3−T10) of timer 1 to regis- ter A.

Rev.1.01 Feb 15, 2008 Page 105 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAB2 (Transfer data to Accumulator and register B from timer 2) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001110001 2 271 16 11- - Opera- tion: (B) ← (T27−T24) (A) ← (T23−T20) Grouping: Timer operation Description: Transfers the high-order 4 bits (T27−T24) of timer 2 to reg- ister B. Transfers the low-order 4 bits (T2 3−T20) of timer 2 to regis- ter A. TABE (Transfer data to Accumulator and register B from register E) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000101010 2 02A 16 11- - Opera- tion: (B) ← (E7−E4) (A) ← (E3−E0) Grouping: Register to register transfer Description: Transfers the high-order 4 bits (E7−E4) of register E to reg- ister B, and low-order 4 bits of register E to register A. TABP p (Transfer data to Accumulator and register B from Program memory in page p) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0010 p 5 p4 p3 p2 p1 p0 2 0 8 +p p 16 1 3 - - Opera- tion: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← (DR2−DR0, A3−A0) (B) ← (ROM(PC))7−4 (A) ← (ROM(PC))3−0 (UPTF) ← 1 (DR1, DR0) ← (ROM(PC))9, 8 (DR2) ← 0 (PC) ← (SK(SP)) (SP) ← (SP) − 1 Grouping: Arithmetic operation Description: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When UPTF is 1, Transfers bits 9, 8 to the low- order 2 bits (DR 1, DR0) of register D, and “0” is stored to the least significant bit (DR2) of register D. When this instruction is executed, 1 stage of stack register (SK) is used. Note: p is 0 to 63 for M3455AG8, and p is 0 to 95 for M3455AGC. When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. TABPS (Transfer data to Accumulator and register B from Pre-Scaler) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001110101 2 275 16 11- - Opera- tion: (B) ← (TPS7−TPS4) (A) ← (TPS3−TPS0) Grouping: Timer operation Description: Transfers the high-order 4 bits of prescaler to register B. Transfers the low-order 4 bits of prescaler to register A.

Rev.1.01 Feb 15, 2008 Page 106 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAD (Transfer data to Accumulator from register D) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001010001 2 051 16 11- - Opera- tion: (A2−A0) ← (DR2−DR0) (A3) ← 0 Grouping: Register to register transfer Description: Transfers the contents of register D to the low-order 3 bits (A2−A0) of register A. “0” is stored to the bit 3 (A3) of register A. TAI1 (Transfer data to Accumulator from register I1) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001010011 2 253 16 11- - Opera- tion: (A) ← (I1) Grouping: Interrupt operation Description: Transfers the contents of interrupt control register I1 to reg- ister A. TAK0 (Transfer data to Accumulator from register K0) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001010110 2 256 16 11- - Opera- tion: (A) ← (K0) Grouping: Input/Output operation Description: Transfers the contents of key-on wakeup control register K0 to register A. TAK1 (Transfer data to Accumulator from register K1) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001011001 2 259 16 11- - Opera- tion: (A) ← (K1) Grouping: Input/Output operation Description: Transfers the contents of key-on wakeup control register K1 to register A.

Rev.1.01 Feb 15, 2008 Page 107 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAK2 (Transfer data to Accumulator from register K2) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001011010 2 25A 16 11- - Opera- tion: (A) ← (K2) Grouping: Input/Output operation Description: Transfers the contents of key-on wakeup control register K2 to register A. TAK3 (Transfer data to Accumulator from register K3) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001011011 2 25B 16 11- - Opera- tion: (A) ← (K3) Grouping: Input/Output operation Description: Transfers the contents of key-on wakeup control register K3 to register A. TAL1 (Transfer data to Accumulator from register L1) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001001010 2 24A 16 11- - Opera- tion: (A) ← (L1) Grouping: LCD operation Description: Transfers the contents of LCD control register L1 to regis- ter A. TAM j (Transfer data to Accumulator from Memory) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 101100 j j j j 2 2C j 16 11- - Opera- tion: (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 Grouping: RAM to register transfer Description: After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.

Rev.1.01 Feb 15, 2008 Page 108 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAMR (Transfer data to Accumulator from register MR) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001010010 2 252 16 11- - Opera- tion: (A) ← (MR) Grouping: Clock operation Description: Transfers the contents of clock control register MR to reg- ister A. TAPU0 (Transfer data to Accumulator from register PU0) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001010111 2 257 16 11- - Opera- tion: (A) ← (PU0) Grouping: Input/Output operation Description: Transfers the contents of pull-up control register PU0 to register A. TAPU1 (Transfer data to Accumulator from register PU1) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001011110 2 25E 16 11- - Opera- tion: (A) ← (PU1) Grouping: Input/Output operation Description: Transfers the contents of pull-up control register PU1 to register A. TAPU2 (Transfer data to Accumulator from register PU2) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001011111 2 25F 16 11- - Opera- tion: (A) ← (PU2) Grouping: Input/Output operation Description: Transfers the contents of pull-up control register PU2 to register A.

Rev.1.01 Feb 15, 2008 Page 109 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAPU3 (Transfer data to Accumulator from register PU3) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001011101 2 25D 16 11- - Opera- tion: (A) ← (PU3) Grouping: Input/Output operation Description: Transfers the contents of pull-up control register PU3 to register A. TASP (Transfer data to Accumulator from Stack Pointer) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001010000 2 050 16 11- - Opera- tion: (A2−A0) ← (SP2−SP0) (A3) ← 0 Grouping: Register to register transfer Description: Transfers the contents of stack pointer (SP) to the low- order 3 bits (A2−A0) of register A. “0” is stored to the bit 3 (A3) of register A. TAV1 (Transfer data to Accumulator from register V1) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001010100 2 054 16 11- - Opera- tion: (A) ← (V1) Grouping: Interrupt operation Description: Transfers the contents of interrupt control register V1 to register A. TAV2 (Transfer data to Accumulator from register V2) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001010101 2 055 16 11- - Opera- tion: (A) ← (V2) Grouping: Interrupt operation Description: Transfers the contents of interrupt control register V2 to register A.

Rev.1.01 Feb 15, 2008 Page 110 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAW1 (Transfer data to Accumulator from register W1) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001001011 2 24B 16 11- - Opera- tion: (A) ← (W1) Grouping: Timer operation Description: Transfers the contents of timer control register W1 to regis- ter A. TAW2 (Transfer data to Accumulator from register W2) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001001100 2 24C 16 11- - Opera- tion: (A) ← (W2) Grouping: Timer operation Description: Transfers the contents of timer control register W2 to regis- ter A. TAW3 (Transfer data to Accumulator from register W3) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001001101 2 24D 16 11- - Opera- tion: (A) ← (W3) Grouping: Timer operation Description: Transfers the contents of timer control register W3 to regis- ter A. TAW4 (Transfer data to Accumulator from register W4) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001001110 2 24E 16 11- - Opera- tion: (A) ← (W4) Grouping: Timer operation Description: Transfers the contents of timer control register W4 to regis- ter A. TAW5 (Transfer data to Accumulator from register W5) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001001111 2 24F 16 11- - Opera- tion: (A) ← (W5) Grouping: Timer operation Description: Transfers the contents of timer control register W5 to regis- ter A.

Rev.1.01 Feb 15, 2008 Page 111 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAX (Transfer data to Accumulator from register X) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001010010 2 052 16 11- - Opera- tion: (A) ← (X) Grouping: Register to register transfer Description: Transfers the contents of register X to register A. TAY (Transfer data to Accumulator from register Y) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000011111 2 01F 16 11- - Opera- tion: (A) ← (Y) Grouping: Register to register transfer Description: Transfers the contents of register Y to register A. TAZ (Transfer data to Accumulator from register Z) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001010011 2 053 16 11- - Opera- tion: (A3, A2) ← 0 Grouping: Register to register transfer Description: Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. “0” is stored to the high-order 2 bits (A3, A2) of register A. TBA (Transfer data to register B from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000001110 2 00E 16 11- - Opera- tion: (B) ← (A) Grouping: Register to register transfer Description: Transfers the contents of register A to register B.

Rev.1.01 Feb 15, 2008 Page 112 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TC1A (Transfer data to register C1 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1010101000 2 2A8 16 11- - Opera- tion: (C1) ← (A) Grouping: LCD control operation Description: Transfers the contents of register A to the LCD control reg- ister C1. TC2A (Transfer data to register C2 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1010101001 2 2A9 16 11- - Opera- tion: (C2) ← (A) Grouping: LCD control operation Description: Transfers the contents of register A to the LCD control reg- ister C2. TC3A (Transfer data to register C3 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000100110 2 226 16 11- - Opera- tion: (C3) ← (A) Grouping: LCD control operation Description: Transfers the contents of register A to the LCD control reg- ister C3. TDA (Transfer data to register D from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000101001 2 029 16 11- - Opera- tion: (DR2−DR0) ← (A2−A0) Grouping: Register to register transfer Description: Transfers the contents of the low-order 3 bits (A2−A0) of register A to register D.

Rev.1.01 Feb 15, 2008 Page 113 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TEAB (Transfer data to register E from Accumulator and register B) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000011010 2 01A 16 11- - Opera- tion: (E7−E4) ← (B) (E3−E0) ← (A) Grouping: Register to register transfer Description: Transfers the contents of register B to the high-order 4 bits (E3−E0) of register E, and the contents of register A to the low-order 4 bits (E3−E0) of register E. TFR0A (Transfer data to register FR0 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000101000 2 228 16 11- - Opera- tion: (FR0) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to port output structure control register FR0. TFR1A (Transfer data to register FR1 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000101001 2 229 16 11- - Opera- tion: (FR1) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to port output structure control register FR1. TFR2A (Transfer data to register FR2 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000101010 2 22A 16 11- - Opera- tion: (FR2) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to port output structure control register FR2.

Rev.1.01 Feb 15, 2008 Page 114 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TFR3A (Transfer data to register FR3 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000101011 2 22B 16 11- - Opera- tion: (FR3) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to port output structure control register FR3. TI1A (Transfer data to register I1 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000010111 2 217 16 11- - Opera- tion: (I1) ← (A) Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control reg- ister I1. TK0A (Transfer data to register K0 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000011011 2 21B 16 11- - Opera- tion: (K0) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to key-on wakeup con- trol register K0. TK1A (Transfer data to register K1 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000010100 2 214 16 11- - Opera- tion: (K1) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to key-on wakeup con- trol register K1.

Rev.1.01 Feb 15, 2008 Page 115 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TK2A (Transfer data to register K2 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000010101 2 215 16 11- - Opera- tion: (K2) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to key-on wakeup con- trol register K2. TK3A (Transfer data to register K3 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000101100 2 22C 16 11- - Opera- tion: (K3) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to key-on wakeup con- trol register K3. TL1A (Transfer data to register L1 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000001010 2 20A 16 11- - Opera- tion: (L1) ← (A) Grouping: LCD control operation Description: Transfers the contents of register A to the LCD control reg- ister L1. TL2A (Transfer data to register L2 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000001011 2 20B 16 11- - Opera- tion: (L2) ← (A) Grouping: LCD control operation Description: Transfers the contents of register A to the LCD control reg- ister L2.

Rev.1.01 Feb 15, 2008 Page 116 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TL3A (Transfer data to register L3 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000001100 2 20C 16 11- - Opera- tion: (L3) ← (A) Grouping: LCD control operation Description: Transfers the contents of register A to the LCD control reg- ister L3. TLCA (Transfer data to timer LC and register RLC from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000001101 2 20D 16 11- - Opera- tion: (LC) ← (A) (RLC) ← (A) Grouping: Timer control operation Description: Transfers the contents of register A to timer LC and reload register RLC. TMA j (Transfer data to Memory from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 101011 j j j j 2 2B j 16 11- - Opera- tion: (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 Grouping: RAM to register transfer Description: After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. TMRA (Transfer data to register MR from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000010110 2 216 16 11- - Opera- tion: (MR) ← (A) Grouping: Clock operation Description: Transfers the contents of register A to clock control register MR.

Rev.1.01 Feb 15, 2008 Page 117 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TPAA (Transfer data to register PA from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1010101010 2 2AA 16 11- - Opera- tion: (PA0) ← (A0) Grouping: Timer operation Description: Transfers the least significant bit of register A (A0) to timer control register PA. TPSAB (Transfer data to Pre-Scaler and register RPS from Accumulator and register B) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000110101 2 235 16 11- - Opera- tion: (RPS7−RPS4) ← (B) (TPS7−TPS4) ← (B) (RPS3−RPS0) ← (A) (TPS3−TPS0) ← (A) Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS. Transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS.TPU0A (Transfer data to register PU0 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000101101 2 22D 16 11- - Opera- tion: (PU0) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to pull-up control regis- ter PU0. TPU1A (Transfer data to register PU1 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000101110 2 22E 16 11- - Opera- tion: (PU1) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to pull-up control regis- ter PU1.

Rev.1.01 Feb 15, 2008 Page 118 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TPU2A (Transfer data to register PU2 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000101111 2 22F 16 11- - Opera- tion: (PU2) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to pull-up control regis- ter PU2. TPU3A (Transfer data to register PU3 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000001000 2 208 16 11- - Opera- tion: (PU3) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to pull-up control regis- ter PU3. TR1AB (Transfer data to register R1 from Accumulator and register B) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000111111 2 23F 16 11- - Opera- tion: (R17−R14) ← (B) (R13−R10) ← (A) Grouping: Timer control operation Description: Transfers the contents of register B to the high-order 4 bits (R17−R14) of timer 1 reload register R1, and the contents of register A to the low-order 4 bits (R13−R10) of timer 1 reload register R1. TRGA (Transfer data to register RG from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000001001 2 209 16 11- - Opera- tion: (RG2−RG0) ← (A2−A0) Grouping: Clock control operation Description: Transfers the contents of register A to register RG.

Rev.1.01 Feb 15, 2008 Page 119 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TV1A (Transfer data to register V1 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000111111 2 03F 16 11- - Opera- tion: (V1) ← (A) Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control reg- ister V1. TV2A (Transfer data to register V2 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000111110 2 03E 16 11- - Opera- tion: (V2) ← (A) Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control reg- ister V2. TW1A (Transfer data to register W1 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000001110 2 20E 16 11- - Opera- tion: (W1) ← (A) Grouping: Timer operation Description: Transfers the contents of register A to timer control register W1. TW2A (Transfer data to register W2 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000001111 2 20F 16 11- - Opera- tion: (W2) ← (A) Grouping: Timer operation Description: Transfers the contents of register A to timer control register W2.

Rev.1.01 Feb 15, 2008 Page 120 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TW3A (Transfer data to register W3 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000010000 2 210 16 11- - Opera- tion: (W3) ← (A) Grouping: Timer operation Description: Transfers the contents of register A to timer control register W3. TW4A (Transfer data to register W4 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000010001 2 211 16 11- - Opera- tion: (W4) ← (A) Grouping: Timer operation Description: Transfers the contents of register A to timer control register W4. TW5A (Transfer data to register W5 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000010010 2 212 16 11- - Opera- tion: (W5) ← (A) Grouping: Timer operation Description: Transfers the contents of register A to timer control register W5. TYA (Transfer data to register Y from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000001100 2 00C 16 11- - Opera- tion: (Y) ← (A) Grouping: Register to register transfer Description: Transfers the contents of register A to register Y. WRST (Watchdog timer ReSeT) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1010100000 2 2A0 16 11- ( W D F 1 ) = 1 Opera- tion: (WDF1) = 1 ? (WDF1) ← 0 Grouping: Other operation Description: Clears (0) to the WDF1 flag and skips the next instruction when watchdog timer flag WDF1 is “1”. When the WDF1 flag is “0”, executes the next instruction. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction.

Rev.1.01 Feb 15, 2008 Page 121 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) XAM j (eXchange Accumulator and Memory data) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 101101 j j j j 2 2D j 16 11- - Opera- tion: (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 101111 j j j j 2 2F j 16 11- ( Y ) = 1 5 Opera- tion: (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) −1 Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 101110 j j j j 2 2E j 16 11- ( Y ) = 0 Opera- tion: (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y . As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed.

Rev.1.01 Feb 15, 2008 Page 122 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY TYPES) Mnemonic Instruction code Number of words Number of cycles Function D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hexadecim al notation Register to register transfer T A B 000001111001E 1 1( A ) ← (B) T B A 000000111000E 1 1( B ) ← (A) T A Y 000001111101F 1 1( A ) ← (Y) T Y A 000000110000C 1 1( Y ) ← (A) T E A B 000001101001A 1 1( E 7−E4) ← (B) (E3−E0) ← (A) T A B E 000010101002A 1 1( B ) ← (E7−E4) (A) ← (E3−E0) T D A 0000101001029 1 1( D R 2−DR0) ← (A2−A0) T A D 0001010001051 1 1( A 2−A0) ← (DR2−DR0) (A3) ← 0 T A Z 0001010011053 1 1( A 1, A0) ← (Z1, Z0) (A3, A2) ← 0 T A X 0001010010052 1 1( A ) ← (X) T A S P 0001010000050 1 1( A 2−A0) ← (SP2−SP0) (A3) ← 0 RAM addresses LXY x, y 1 1 x 3 x2 x1 x0 y3 y2 y1 y0 3xy 1 1( X ) ← x x = 0 to 15 (Y) ← y y = 0 to 15 L Z z 00010010 z 1 z0 048 1 1 (Z) ← z z = 0 to 3 I N Y 0000010011013 1 1( Y ) ← (Y) + 1 D E Y 0000010111017 1 1( Y ) ← (Y) − 1 RAM to register transfer T A M j 101100 j j j j 2Cj 1 1( A ) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 X A M j 101101 j j j j 2Dj 1 1( A ) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 X A M D j 101111 j j j j 2F j 1 1( A ) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) − 1 X A M I j 101110 j j j j 2Ej 1 1( A ) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 T M A j 101011 j j j j 2Bj 1 1( M ( D P ) ) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 Para meter Type of instructi ons

Rev.1.01 Feb 15, 2008 Page 123 of 146 REJ03B0224-0101 455A Group Skip condition Carry flag CY Detailed description −− Transfers the contents of register B to register A. −− Transfers the contents of register A to register B. −− Transfers the contents of register Y to register A. −− Transfers the contents of register A to register Y . −− Transfers the contents of register B to the high-order 4 bits (E3−E0) of register E, and the contents of register A to the low-order 4 bits (E3−E0) of register E. −− Transfers the high-order 4 bits (E7−E4) of register E to register B, and low-order 4 bits of register E to register −− Transfers the contents of the low-order 3 bits (A2−A0) of register A to register D. −− Transfers the contents of register D to the low-order 3 bits (A2−A0) of register A. “0” is stored to the bit 3 (A3) of register A. −− Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. “0” is stored to the high-order 2 bits (A3, A2) of register A. −− Transfers the contents of register X to register A. −− Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2−A0) of register A. “0” is stored to the bit 3 (A3) of register A. Continuous − Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. −− Loads the value z in the immediate field to register Z. (Y) = 0 − Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. (Y) = 15 − Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. −− After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. −− After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. (Y) = 15 − After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. (Y) = 0 − After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. when the contents of register Y is not 0, the next instruction is executed. −− After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.

Rev.1.01 Feb 15, 2008 Page 124 of 146 REJ03B0224-0101 455A Group Note 1. M3455AG8: p=0 to 63 and M3455AGC: p=0 to 95. MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Mnemonic Instruction code Number of words Number of cycles Function D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hexadecim al notation Arithmetic operation L A n 000111nnnn07n 1 1( A ) ← n n = 0 to 15 TABP p 0010 p 5 p4 p3 p2 p1 p0 08 (SK(SP)) ← (PC) (PCH) ← p (Note 1) (PCL) ← (DR2−DR0, A3−A0) (B) ← (ROM(PC))7-4 (A) ← (ROM(PC))3-0 (UPTF) = 1 (DR 1, DR0) ← (ROM(PC))9, 8 (DR2) ← 0 (PC) ← (SK(SP)) (SP) ← (SP) − 1 A M 000000101000A 1 1( A ) ← (A) + (M(DP)) (CY) ← Carry A n 000110nnnn06n 1 1( A ) ← (A) + n n = 0 to 15 A N D 0000011000018 1 1( A ) ← (A) AND (M(DP)) O R 0000011001019 1 1( A ) ← (A) OR (M(DP)) S C 0000000111007 1 1( C Y ) ← 1 R C 0000000110006 1 1( C Y ) ← 0 S Z C 000010111102F 1 1( C Y ) = 0 ? C M A 000001110001C 1 1( A ) ← (A) R A R 000001110101D 1 1 Bit operation S B j 00010111 j j 05C 1 1 (Mj(DP)) ← 1 j = 0 to 3 R B j 00010011 j j 04C 1 1 (Mj(DP)) ← 0 j = 0 to 3 S Z B j 00001000 j j 02 j 1 1( M j ( D P ) ) = 0 ? j = 0 to 3 Para meter Type of instructi ons CY A3A2A1A0

Rev.1.01 Feb 15, 2008 Page 125 of 146 REJ03B0224-0101 455A Group Skip condition Carry flag CY Detailed description Continuous − Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. −− Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When UPTF is 1, Transfers bits 9, 8 to the low-order 2 bits (DR1, DR0) of register D, and “0” is stored to the least significant bit (DR2) of register D. When this instruction is executed, 1 stage of stack register (SK) is used. −− Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged. − 0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. Overflow = 0 − Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation. −− Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A. −− Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A. − 1 Sets (1) to carry flag CY . − 0 Clears (0) to carry flag CY. (CY) = 0 − Skips the next instruction when the contents of carry flag CY is “0”. Executes the next instruction when the contents of carry flag CY is “1”. The contents of carry flag CY remains unchanged. −− Stores the one’s complement for register A’s contents in register A. − 0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. −− Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). −− Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). (Mj(DP)) = 0 j = 0 to 3 − Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0”. Executes the next instruction when the contents of bit j of M(DP) is “1”.

Rev.1.01 Feb 15, 2008 Page 126 of 146 REJ03B0224-0101 455A Group Note 1. M3455AG8: p=0 to 63 and p 6=0, and M3455AGC: p=0 to 95. MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Mnemonic Instruction code Number of words Number of cycles Function D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hexadecim al notation Comparison operation SEAM 0000100110026 1 1( A ) = ( M ( D P ) ) ? SEA n 0000100101025 2 2( A ) = n ? n = 0 to 15 000111nnnn07n Branch operation B a 011 a 6 a5 a4 a3 a2 a1 a0 18 a1 1 ( P C L) ← a6−a0 B L p , a 00111 p 4 p3 p2 p1 p0 0E p2 2 ( P C H) ←p (Note 1) (PCL) ← a6−a0 1p 6 p5 a6 a5 a4 a3 a2 a1 a0 2aa B L A p 0000010000 0 10 2 2( P C H) ← p (Note 1) (PCL) ← (DR2−DR0, A3−A0) 1p 6 p5 p4 00 p 3 p2 p1 p0 2pp Subroutine operation B M a 010 a 6 a5 a4 a3 a2 a1 a0 1aa 1 1( S P ) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← 2 (PCL) ← a6−a0 B M L p , a 00110 p 4 p3 p2 p1 p0 0C (SK(SP)) ← (PC) (PCH) ← p (Note 1) (PCL) ← a6−a01p 6 p5 a6 a5 a4 a3 a2 a1 a0 2aa B M L A p 0000110000 030 2 2( S P ) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (Note 1) (PCL) ← (DR2−DR0, A3−A0)1p 6 p5 p4 00 p 3 p2 p1 p0 2pp Return operation R T I 0001000110046 1 1( P C ) ← (SK(SP)) (SP) ← (SP) − 1 R T 0001000100044 1 2( P C ) ← (SK(SP)) (SP) ← (SP) − 1 R T S 0001000101045 1 2( P C ) ← (SK(SP)) (SP) ← (SP) − 1 Para meter Type of instructi ons

Rev.1.01 Feb 15, 2008 Page 127 of 146 REJ03B0224-0101 455A Group Skip condition Carry flag CY Detailed description (A) = (M(DP)) − Skips the next instruction when the contents of register A is equal to the contents of M(DP). Executes the next instruction when the contents of register A is not equal to the contents of M(DP). (A) = n n = 0 to 15 − Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Executes the next instruction when the contents of register A is not equal to the value n in the immediate field. −− Branch within a page : Branches to address a in the identical page. −− Branch out of a page : Branches to address a in page p. −− Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. −− Call the subroutine in page 2 : Calls the subroutine at address a in page 2. −− Call the subroutine : Calls the subroutine at address a in page p. −− Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. −− Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt. −− Returns from subroutine to the routine called the subroutine. Skip at uncondition − Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.

Rev.1.01 Feb 15, 2008 Page 128 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Mnemonic Instruction code Number of words Number of cycles Function D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hexadecim al notation Interrupt operation D I 0000000100004 1 1( I N T E ) ← 0 E I 0000000101005 1 1( I N T E ) ← 1 S N Z 0 0 000111000038 1 1V 1 0 = 0 : (EXF0) = 1 ? (EXF0) ← 0 V10 = 1 : SNZ0 = NOP S N Z I 0 000011101003A 1 1I 1 2 = 0 : (INT) = “L”? T A V 1 0001010100054 1 1( A ) ← (V1) T V 1 A 000011111103F 1 1( V 1 ) ← (A) T A V 2 0001010101055 1 1( A ) ← (V2) T V 2 A 000011111003E 1 1( V 2 ) ← (A) T A I 1 1001010011253 1 1( A ) ← (I1) T I 1 A 1000010111217 1 1( I 1 ) ← (A) Timer operation T P A A 10101010102AA 1 1( P A ) ← (A) T A W 1 100100101124B 1 1( A ) ← (W1) T W 1 A 100000111020E 1 1( W 1 ) ← (A) T A W 2 100100110024C 1 1( A ) ← (W2) T W 2 A 100000111120F 1 1( W 2 ) ← (A) T A W 3 100100110124D 1 1( A ) ← (W3) T W 3 A 1000010000210 1 1( W 3 ) ← (A) T A W 4 100100111024E 1 1( A ) ← (W4) T W 4 A 1000010001211 1 1( W 4 ) ← (A) T A W 5 100100111124F 1 1( A ) ← (W5) T W 5 A 1000010010212 1 1( W 5 ) ← (A) Para meter Type of instructi ons

Rev.1.01 Feb 15, 2008 Page 129 of 146 REJ03B0224-0101 455A Group Skip condition Carry flag CY Detailed description −− Clears (0) to interrupt enable flag INTE, and disables the interrupt. −− Sets (1) to interrupt enable flag INTE, and enables the interrupt. V10 = 0 : (EXF0) = 1 − When V10 = 0 : Clears (0) to the EXF0 flag and skips the next instruction when external 0 interrupt request flag EXF0 is “1”. When the EXF0 flag is “0”, executes the next instruction. When V10 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register V1) (INT) = “L” However, I12 = 0 − When I12 = 0 : Skips the next instruction when the level of INT pin is “L”. Executes the next instruction when the level of INT0 pin is “H”. (INT) = “H” However, I12 = 1 When I12 = 1 : Skips the next instruction when the level of INT pin is “H”. Executes the next instruction when the level of INT0 pin is “L”. (I12: bit 2 of interrupt control register I1) −− Transfers the contents of interrupt control register V1 to register A. −− Transfers the contents of register A to interrupt control register V1. −− Transfers the contents of interrupt control register V2 to register A. −− Transfers the contents of register A to interrupt control register V2. −− Transfers the contents of interrupt control register I1 to register A. −− Transfers the contents of register A to interrupt control register I1. −− Transfers the contents of register A (A0) to timer control register PA. −− Transfers the contents of timer control register W1 to register A. −− Transfers the contents of register A to timer control register W1. −− Transfers the contents of timer control register W2 to register A. −− Transfers the contents of register A to timer control register W2. −− Transfers the contents of timer control register W3 to register A. −− Transfers the contents of register A to timer control register W3. −− Transfers the contents of timer control register W4 to register A. −− Transfers the contents of register A to timer control register W4. −− Transfers the contents of timer control register W5 to register A. −− Transfers the contents of register A to timer control register W5.

Rev.1.01 Feb 15, 2008 Page 130 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Mnemonic Instruction code Number of words Number of cycles Function D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hexadecim al notation Timer operation TABPS 1001110101275 1 1( B ) ← (TPS7−TPS4) (A) ← (TPS3−TPS0) TPSAB 1000110101235 1 1( R P S 7−RPS4) ← (B) (TPS7−TPS4) ← (B) (RPS3−RPS0) ← (A) (TPS3−TPS0) ← (A) T A B 1 1001110000270 1 1( B ) ← (T17−T14) (A) ← (T13−T10) T 1 A B 1000110000230 1 1( R 1 7−R14) ← (B) (T17−T14) ← (B) (R13−R10) ← (A) (T13−T10) ← (A) T R 1 A B 100011111123F 1 1( R 1 7−R14) ← (B) (R13−R10) ← (A) T A B 2 1001110001271 1 1( B ) ← (T27−T24) (A) ← (T23−T20) T 2 A B 1000110001231 1 1( R 2 L 7−R2L4) ← (B) (T27−T24) ← (B) (R2L3−R2L0) ← (A) (T23−T20) ← (A) T 2 H A B 1010010100294 1 1( R 2 H 7−R2H4) ← (B) (R2H3−R2H0) ← (A) T 2 R 2 L 1010010101295 1 1( T 2 7) ← (R2L) T L C A 100000110120D 1 1( R L C ) ← (A) (TLC) ← (A) S N Z T 1 1010000000280 1 1V 1 2 = 0 : (T1F) = 1 ? After skipping, (T1F) ← 0 V12 = 1 : SNZT1=NOP S N Z T 2 1010000001281 1 1V 1 3 = 0 : (T2F) = 1 ? After skipping, (T2F) ← 0 V13 = 1 : SNZT2=NOP S N Z T 3 1010000010282 1 1V 2 0 = 0 : (T3F) = 1 ? After skipping, (T3F) ← 0 V20 = 1 : SNZT3=NOP Para meter Type of instructi ons

Rev.1.01 Feb 15, 2008 Page 131 of 146 REJ03B0224-0101 455A Group Skip condition Carry flag CY Detailed description −− Transfers the high-order 4 bits of prescaler to register B. Transfers the low-order 4 bits of prescaler to register A. −− Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS. Transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS. −− Transfers the high-order 4 bits (T17−T14) of timer 1 to register B. Transfers the low-order 4 bits (T13−T10) of timer 1 to register A. −− Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1L. Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1L. −− Transfers the contents of register B to the high-order 4 bits (R17−R14) of reload register R1, and the contents of register A to the low-order 4 bits (R13−R10) of reload register R1. −− Transfers the high-order 4 bits (T27−T24) of timer 2 to register B. Transfers the low-order 4 bits (T23−T20) of timer 2 to register A. −− Transfers the contents of register B to the high-order 4 bits (R2L7−R2L4) of timer 2 and timer 2 reload register R2L. Transfers the contents of register A to the low-order 4 bits (R2L3−R2L0) of timer 2 and timer 2 reload register R2L. −− Transfers the contents of register B to the high-order 4 bits (R2H7−R2H4) of timer 2 and timer 2 reload register R2H. Transfers the contents of register A to the low-order 4 bits (R2H3−R2H0) of timer 2 and timer 2 reload register R2H. −− Transfers the contents of timer 2 reload register R2L to timer 2. −− Transfers the contents of register A to timer LC and reload register RLC. V12 = 0 : (T1F) = 1 − When V12 = 0 : Clears (0) to the T1F flag and skips the next instruction when timer 1 interrupt request flag T1F is “1”. When the T1F flag is “0”, executes the next instruction. When V12 = 1 : This instruction is equivalent to the NOP instruction. (V12: bit 2 of interrupt control register V1) V13 = 0 : (T2F) = 1 − When V13 = 0 : Clears (0) to the T2F flag and skips the next instruction when timer 2 interrupt request flag T2F is “1”. When the T2F flag is “0”, executes the next instruction. When V13 = 1 : This instruction is equivalent to the NOP instruction. (V13: bit 3 of interrupt control register V1) V20 = 0 : (T3F) = 1 − When V20 = 0 : Clears (0) to the T3F flag and skips the next instruction when timer 3 interrupt request flag T3F is “1”. When the T3F flag is “0”, executes the next instruction. When V20 = 1 : This instruction is equivalent to the NOP instruction. (V20: bit 0 of interrupt control register V2)

Rev.1.01 Feb 15, 2008 Page 132 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Mnemonic Instruction code Number of words Number of cycles Function D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hexadecim al notation Input/Output operation I A P 0 1001100000260 1 1( A ) ← (P0) O P 0 A 1000100000220 1 1( P 0 ) ← (A) I A P 1 1001100001261 1 1( A ) ← (P1) O P 1 A 1000100001221 1 1( P 1 ) ← (A) I A P 2 1001100010262 1 1( A ) ← (P2) O P 2 A 1000100010222 1 1( P 2 ) ← (A) I A P 3 1001100011263 1 1( A ) ← (P3) O P 3 A 1000100011223 1 1( P 3 ) ← (A) C L D 0000010001011 1 1( D ) ← 1 R D 0000010100014 1 1( D ( Y ) ) ← 0 (Y) = 0 to 7 S D 0000010101015 1 1( D ( Y ) ) ← 1 (Y) = 0 to 7 S Z D 0000100100024 2 2( D ( Y ) ) = 0 ? (Y) = 0 to 5 000010101102B R C P 101000110028C 1 1( C ) ← 0 S C P 101000110128D 1 1( C ) ← 1 T F R 0 A 1000101000228 1 1( F R 0 ) ← (A) T F R 1 A 1000101001229 1 1( F R 1 ) ← (A) T F R 2 A 100010101022A 1 1( F R 2 ) ← (A) T F R 3 A 100010101122B 1 1( F R 3 ) ← (A) T A P U 0 1001010111257 1 1( A ) ← (PU0) T P U 0 A 100010110122D 1 1( P U 0 ) ← (A) T A P U 1 100101111025E 1 1( A ) ← (PU1) T P U 1 A 100010111022E 1 1( P U 1 ) ← (A) T A P U 2 100101111125F 1 1( A ) ← (PU2) T P U 2 A 100010111122F 1 1( P U 2 ) ← (A) T A P U 3 100101110125D 1 1( A ) ← (PU3) T P U 3 A 1000001000208 1 1( P U 3 ) ← (A) Para meter Type of instructi ons

Rev.1.01 Feb 15, 2008 Page 133 of 146 REJ03B0224-0101 455A Group Skip condition Carry flag CY Detailed description −− Transfers the input of port P0 to register A. −− Outputs the contents of register A to port P0. −− Transfers the input of port P1 to register A. −− Outputs the contents of register A to port P1. −− Transfers the input of port P2 to the register A. −− Outputs the contents of the register A to port P2. −− Transfers the input of port P3 to the register A. −− Outputs the contents of the register A to port P3. −− Sets (1) to port D. −− Clears (0) to a bit of port D specified by register Y . −− Sets (1) to a bit of port D specified by register Y . (D(Y)) = 0 Y = 0 to 4 − Skips the next instruction when a bit of port D specified by register Y is “0”. Executes the next instruction when a bit of port D specified by register Y is “1”. −− Clears (0) to port C. −− Sets (1) to port C. −− Transfers the contents of register A to port output structure control register FR0. −− Transfers the contents of register A to port output structure control register FR1. −− Transfers the contents of register A to port output structure control register FR2. −− Transfers the contents of register A to port output structure control register FR3. −− Transfers the contents of pull-up control register PU0 to register A. −− Transfers the contents of register A to pull-up control register PU0. −− Transfers the contents of pull-up control register PU1 to register A. −− Transfers the contents of register A to pull-up control register PU1. −− Transfers the contents of pull-up control register PU2 to register A. −− Transfers the contents of register A to pull-up control register PU2. −− Transfers the contents of pull-up control register PU3 to register A. −− Transfers the contents of register A to pull-up control register PU3.

Rev.1.01 Feb 15, 2008 Page 134 of 146 REJ03B0224-0101 455A Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Mnemonic Instruction code Number of words Number of cycles Function D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hexadecim al notation Input/Output operation T A K 0 1001010110256 1 1( A ) ← (K0) T K 0 A 100001101121B 1 1( K 0 ) ← (A) T A K 1 1001011001259 1 1( A ) ← (K1) T K 1 A 1000010100214 1 1( K 1 ) ← (A) T A K 2 100101101025A 1 1( A ) ← (K2) T K 2 A 1000010101215 1 1( K 2 ) ← (A) T A K 3 100101101125B 1 1( A ) ← (K3) T K 3 A 100010110022C 1 1( K 3 ) ← (A) LCD operation T A L 1 100100101024A 1 1( A ) ← (L1) T L 1 A 100000101020A 1 1( L 1 ) ← (A) T L 2 A 100000101120B 1 1( L 2 ) ← (A) T L 3 A 100000110020C 1 1( L 3 ) ← (A) T C 1 A 10101010002A8 1 1( C 1 ) ← (A) T C 2 A 10101010012A9 1 1( C 2 ) ← (A) T C 3 A 1000100110226 1 1( C 3 ) ← (A) Clock operation T A M R 1001010010252 1 1( A ) ← (MR) T M R A 1000010110216 1 1( M R ) ← (A) T R G A 1000001001209 1 1( R G 2−RG0) ← (A2−A0) Para meter Type of instructi ons

Rev.1.01 Feb 15, 2008 Page 135 of 146 REJ03B0224-0101 455A Group Skip condition Carry flag CY Detailed description −− Transfers the contents of key-on wakeup control register K0 to register A. −− Transfers the contents of register A to key-on wakeup control register K0. −− Transfers the contents of key-on wakeup control register K1 to register A. −− Transfers the contents of register A to key-on wakeup control register K1. −− Transfers the contents of key-on wakeup control register K2 to register A. −− Transfers the contents of register A to key-on wakeup control register K2. −− Transfers the contents of key-on wakeup control register K3 to register A. −− Transfers the contents of register A to key-on wakeup control register K3. −− Transfers the contents of the LCD control register L1 to register A. −− Transfers the contents of register A to the LCD control register L1. −− Transfers the contents of register A to the LCD control register L2. −− Transfers the contents of register A to the LCD control register L3. −− Transfers the contents of register A to the LCD control register C1. −− Transfers the contents of register A to the LCD control register C2. −− Transfers the contents of register A to the LCD control register C3. −− Transfers the contents of clock control regiser MR to register A. −− Transfers the contents of register A to clock control register MR. −− Transfers the contents of register A to clock control register RG.

Rev.1.01 Feb 15, 2008 Page 136 of 146 REJ03B0224-0101 455A Group Note 1. (SBK, RBK) cannot be used int the M3455AG8. The pages which can be referred by the TABP instruction after the SBK instruction is executed are 64 to 95 in the M3455AGC. MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Mnemonic Instruction code Number of words Number of cycles Function D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hexadecim al notation Other operation N O P 0000000000000 1 1( P C ) ← (PC) + 1 P O F 0000000010002 1 1T r a n s i t i o n t o c l o c k operating mode P O F 2 0000001000008 1 1T r a n s i t i o n t o R A M b a c k - u p mode E P O F 000101101105B 1 1P O F o r P O F 2 i n s t r u c t i o n v a l i d S N Z P 0000000011003 1 1( P ) = 1 ? W R S T 10101000002A0 1 1( W D F 1 ) = 1 ? (WDF1) ← 0 D W D T 101001110029C 1 1S t o p o f w a t c hdog timer function enabled S R S T 0000000001001 1 1S y s t e m r e s e t R U P T 0001011000058 1 1( U P T F ) ← 0 S U P T 0001011001059 1 1( U P T F ) ← 1 S V D E 1010010011293 1 1A t p o w e r d o w n mode, voltage drop detection circuit valid S N Z V D 101000101028A 1 1( V D F ) = 1 ? RBK (Note 1) 0001000000040 1 1 When TABPp instruction is executed, p6©0 SBK (Note 1) 0001000001041 1 1 When TABPp instruction is executed, p6©1 Para meter Type of instructi ons

Rev.1.01 Feb 15, 2008 Page 137 of 146 REJ03B0224-0101 455A Group Skip condition Carry flag CY Detailed description −− No operation; Adds 1 to program counter value, and others remain unchanged. −− Puts the system in clock operating mode by executing the POF instruction after executing the EPOF instruction. −− Puts the system in RAM back-up state by executing the POF2 instruction after executing the EPOF instruction. −− Makes the immediate after POF or POF2 instruction valid by executing the EPOF instruction. (P) = 1 − Skips the next instruction when the P flag is “1”. After skipping, the P flag remains unchanged. Executes the next instruction when the P flag is “0”. (WDF1) = 1 Clears (0) to the WDF1 flag and skips the next inst ruction when watchdog timer flag WDF1 is “1”. When the WDF1 flag is “0”, executes the next instruction. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction. −− Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction. −− System reset occurs. −− Clears (0) to the high-order bit reference enable flag UPTF. −− Sets (1) to the high-order bit reference enable flag UPTF. (VDF) = 1 − Skips the next instruction when voltage drop detection circuit flag VDF is “1”. Execute instruction when VPF is “0”. After skipping, the contents of VDF remains unchanged. −− Validates the voltage drop detection circuit at power down (clock operating mode and RAM back-up mode). || Sets referring data area to pages 0 to 63 when the TABP p instruction is executed. This instruction is valid only for the TABP p instruction. || Sets referring data area to pages 64 to 127 when the TABP p instruction is executed. This instruction is valid only for the TABP p instruction.

Rev.1.01 Feb 15, 2008 Page 138 of 146 REJ03B0224-0101 455A Group The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order 4 bits of the machine language code, and D 9– D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is al so provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below. INSTRUCTION CODE TABLE D9− 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 00 1111 010000 to 010111 011000 to 011111 D3− Hex, notation 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 −17 18 −F 0000 0 NOP BLA SZB

0 BMLA RBK** TASP A

32* TABP 48* BML BML BL BL BM B 0001 1 SRST CLD SZB 1 − SBK** TAD A LA TABP TABP TABP 33* TABP 49* BML BML BL BL BM B 0010 2 POF − SZB 2 −− TAX A LA TABP TABP TABP 34* TABP 50* BML BML BL BL BM B 0011 3 SNZP INY SZB 3 −− TAZ A LA TABP TABP TABP 35* TABP 51* BML BML BL BL BM B 0100 4 DI RD SZD − RT TAV1 A LA TABP TABP TABP 36* TABP 52* BML BML BL BL BM B 0101 5 EI SD SEAn − RTS TAV2 A LA TABP TABP TABP 37* TABP 53* BML BML BL BL BM B 0110 6 RC − SEAM − RTI − A LA TABP TABP TABP 38* TABP 54* BML BML BL BL BM B 0111 7 SC DEY −−−− A LA TABP TABP TABP 39* TABP 55* BML BML BL BL BM B 1000 8 POF2 AND − SNZ0 LZ

0 RUPT A

40* TABP 56* BML BML BL BL BM B 1001 9 − OR TDA − LZ

1 SUPT A

41* TABP 57* BML BML BL BL BM B

1010 A AM TEAB TABE SNZI

2 − A LA TABP TABP TABP 42* TABP 58* BML BML BL BL BM B

1011 B AMC −−− LZ

3 EPOF A

43* TABP 59* BML BML BL BL BM B

1100 C TYA CMA −− RB

A LA TABP TABP TABP 44* TABP 60* BML BML BL BL BM B

1101 D − RAR −− RB

A LA TABP TABP TABP 45* TABP 61* BML BML BL BL BM B

1110 E TBA TAB − TV2A RB

A LA TABP TABP TABP 46* TABP 62* BML BML BL BL BM B

1111 F − TAY SZC TV1A RB

A LA TABP TABP TABP 47* TABP 63* BML BML BL BL BM B The second word BL 10 paaa aaaa BML 10 paaa aaaa BLA 10 pp00 pppp BMLA 10 pp00 pppp SEA 00 0111 nnnn SZD 00 0010 1011

• **(SBK and RBK instructions) cannot be used in the M3455AG8.
• * cannot be used after the SBK instruction executed in the M3455AGC.
• A page referred by the TABP instruction can be switched by the SBK and RBK instructions in the M3455AGC.
• The pages which can be referred by the TABP instruction after the SBK instruction is executed are 64 to 95 in the M3455AGC.
• The pages which can be referred by the TABP instruction after the RBK instruction is executed are 0 to 63.
• When the SBK instruction is not used, the pages which can be referred by the TABP instruction are 0 to 63.

Rev.1.01 Feb 15, 2008 Page 139 of 146 REJ03B0224-0101 455A Group The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order 4 bits of the machine language code, and D 9– D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is al so provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below. INSTRUCTION CODE TABLE D9− 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 10 1111 110000 to 111111 D3− Hex, notation 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 −3F 0000 0 − TW3A OP0A T1AB −− IAP0 TAB1 SNZT 1 − WRST TMA TAM XAM XAMI XAMD

0 LXY

0001 1 − TW4A OP1A T2AB −− IAP1 TAB2 SNZT 2 −− TMA TAM XAM XAMI XAMD

1 LXY

0010 2 − TW5A OP2A −− TAMR IAP2 − SNZT 3 −− TMA TAM XAM XAMI XAMD

2 LXY

0011 3 −− OP3A −− TAI1 IAP3 −− SVDE − TMA TAM XAM XAMI XAMD

3 LXY

B − TMA TAM XAM XAMI XAMD

4 LXY

0101 5 − TK2A − TPSAB −−− TABPS − T2R2 L − TMA TAM XAM XAMI XAMD

5 LXY

6 LXY

7 LXY

8 LXY

1001 9 TRGA − TFR1A −− TAK1 −−−− TC2A TMA TAM XAM XAMI XAMD

9 LXY

1010 A TL1A − TFR2A − TAL1 TAK2 −− SNZV

D − TPAA TMA TAM XAM XAMI XAMD

10 LXY

1011 B TL2A TK0A TFR3A − TAW1 TAK3 −−−−− TMA

11 LXY

1100 C TL3A − TK3A − TAW2 −−− RCP DWDT − TMA

12 LXY

1101 D TLCA − TPU0A − TAW3 TAPU3 −− SCP −− TMA

13 LXY

1110 E TW1A − TPU1A − TAW4 TAPU1 −−−−− TMA

14 LXY

1111 F TW2A − TPU2A TR1AB TAW5 TAPU2 −−−−− TMA

15 LXY

Rev.1.01 Feb 15, 2008 Page 140 of 146 REJ03B0224-0101 455A Group

Electrical characteristics

Table 30 Absolute maximum ratings Symbol Parameter Conditions Ratings Unit VDD Supply voltage - −0.3 to 6.5 V VI Input voltage P0, P1, P2, P3, D 0-D7, RESET, XIN, XCIN, INT, CNTR - −0.3 to VDD+0.3 V VO Output voltage P0, P1, P2, P3, D 0–D7, RESET Output transistors in cut-off state −0.3 to VDD+0.3 V VO Output voltage C/CNTR, X OUT, XCOUT - −0.3 to VDD+0.3 V VO Output voltage SEG 0 to SEG31, COM0 to COM3 - −0.3 to VDD+0.3 V Pd Power dissipation Ta = 25 °C 300 mW Topr Operating temperature range - −20 to 85 °C Tstg Storage temperature range - −40 to 125 °C

Rev.1.01 Feb 15, 2008 Page 141 of 146 REJ03B0224-0101 455A Group Recommended operating conditions Note 1. At 1/2 bias: VLC1 = VLC2 = (1/2)•VLC3 At 1/3 bias: VLC1 = (1/3)•VLC3, VLC2 = (2/3)•VLC3 Note 2. The average output current is the average value during 100ms. Table 31 Recommended operating conditions 1 (Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) Symbol Parameter Conditions Limits UnitMin. Typ. Max. VDD Supply voltage (with a ceramic resonator) f(STCK) ≤ 6MHz 4 5.5 V f(STCK) ≤ 4.4MHz 2.7 5.5 f(STCK) ≤ 2.2MHz 2 5.5 f(STCK) ≤ 1.1MHz 1.8 5.5 VDD Supply voltage (when an external clock is used) f(STCK) ≤ 4.8MHz 4 5.5 V f(STCK) ≤ 3.2MHz 2.7 5.5 f(STCK) ≤ 1.6MHz 2 5.5 f(STCK) ≤ 0.8MHz 1.8 5.5 VDD Supply voltage (when quartz-crystal oscillation is used) f(STCK) ≤ 50 kHz 1.8 5.5 V VDD Supply voltage (Low-speed/High-speed on- chip oscillator is used) 1.8 5.5 V VRAM RAM back-up voltage (at RAM back-up) 1.6 5.5 V VSS Supply voltage 0V VLC3 LCD power supply (Note 1) 1.8 V DD V VIH “H” level input voltage P0, P1, P2, P3, D 0–D7 0.8VDD VDD V XIN, XCIN 0.7VDD VDD RESET 0.85VDD VDD INT 0.85VDD VDD CNTR 0.8V DD VDD VIL “L” level input voltage P0, P1, P2, P3, D 0–D7 00 . 2 V DD V XIN, XCIN 00 . 3 V DD RESET 00 . 3 V DD INT 00 . 1 5 V DD CNTR 0 0.15V DD IOH(peak) “H” level peak output current P0, P1, P2, P3, D 0–D5 VDD = 5V −20 mA VDD = 3V −10 C/CNTR V DD = 5V −30 VDD = 3V −15 IOH(avg) “H” level average output current (Note 2) P0, P1, P2, P3, D0–D5 VDD = 5V −10 mA VDD = 3V −5 C/CNTR V DD = 5V −20 VDD = 3V −10 IOL(peak) “L” level peak output current P0, P1, P2, P3, D0–D7, C/CNTR VDD = 5V 24 mA VDD = 3V 12 RESET VDD = 5V 10 VDD = 3V 4 IOL(avg) “L” level average output current (Note 2) P0, P1, P2, P3, D0–D7, C/CNTR VDD = 5V 15 mA VDD = 3V 7 RESET VDD = 5V 5 VDD = 3V 2 ΣIOH(avg) “H” level total average current P0, C/CNTR −40 mA P1, P2, P3, D0−D5 −40 ΣIOL(avg) “L” level total average current P0, C/CNTR 40 mA P1, P2, P3, D0−D7, RESET 40

Rev.1.01 Feb 15, 2008 Page 142 of 146 REJ03B0224-0101 455A Group Note 1. If the rising time exceeds the maximum rati ng value, connect a capacitor between the RESET pin and Vss at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage. Fig 80. System clock (STCK) operating condition map Table 32 Recommended operating conditions 2 (Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) Symbol Parameter Conditions Limits UnitMin. Typ. Max. f(XIN) Oscillation frequency (with a ceramic resonator) f(STCK) = f(XIN)V DD = 4.0 V to 5.5 V 6 MHz VDD = 2.7 V to 5.5 V 4.4 VDD = 2 V to 5.5 V 2.2 VDD = 1.8 V to 5.5 V 1.1 f(STCK) = f(XIN)/2 V DD = 2.7 V to 5.5 V 6 VDD = 2 V to 5.5 V 4.4 VDD = 1.8 V to 5.5 V 2.2 f(STCK) = f(XIN)/4, f(XIN)/8 V DD = 2 V to 5.5 V 6 VDD = 1.8 V to 5.5 V 4.4 f(XIN) Oscillation frequency (with an external clock input) f(STCK) = f(XIN)V DD = 4 V to 5.5 V 4.8 MHz VDD = 2.7 V to 5.5 V 3.2 VDD = 2 V to 5.5 V 1.6 VDD = 1.8 V to 5.5 V 0.8 f(STCK) = f(XIN)/2 V DD = 2.7 V to 5.5 V 4.8 VDD = 2 V to 5.5 V 3.2 VDD = 1.8 V to 5.5 V 1.6 f(STCK) = f(XIN)/4, f(XIN)/8 V DD = 2 V to 5.5 V 4.8 VDD = 1.8 V to 5.5 V 3.2 f(XCIN) Oscillation frequency (at quarts-crystal oscillation) Quartz-crystal oscillator 50 kHz f(CNTR) Timer external input frequency CNTR f(STCK)/6 Hz tw(CNTR) Timer external input period (“H” and “L” pulse width) CNTR 3/f(STCK) s TPON Power-on reset circuit valid supply voltage rising time (Note 1) VDD = 0 → 1.8V 100 µs 1.1 2.2 4.4 1.8 2 2.7 4 5.5 Recommended operating conditions with a ceramic resonator f(STCK) [MHz] VDD [V] 0.8 1.6 3.2 4.8 1.8 2 2.7 4 5.5 Recommended operating conditions at external clock oscillation f(STCK) [MHz] VDD [V] 1.8 5.5 Recommended operating conditions at quartz-crystal oscillation f(STCK) [kHz] VDD [V]

Rev.1.01 Feb 15, 2008 Page 143 of 146 REJ03B0224-0101 455A Group Note 1. The impedance state is the resistor value of the output voltage. at VLC3 level output: VO = 0.8 VLC3 at VLC2 level output: VO = 0.8 VLC2 at VLC1 level output: VO = 0.2 VLC2 + VLC1 at VSS level output: VO = 0.2 VLC1 Table 33 Electrical charac teristics 1 (Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) Symbol Parameter Test conditions Limits UnitMin. Typ. Max. VOH “H” level output voltage P0, P1, P2, P3, D 0–D5 VDD = 5V I OH = −10mA 3 V IOH = −3mA 4.1 VDD = 3V I OH = −5mA 2.1 IOH = −1mA 2.4 VOH “H” level output voltage C/CNTR V DD = 5V I OH = −20mA 3 V IOH = −6mA 4.1 VDD = 3V I OH =−10mA 2.1 IOH = −3mA 2.4 VOL “L” level output voltage P0, P1, P2, P3, D 0–D7 C/CNTR VDD = 5V I OL = 15mA 2 V IOL = 5mA 0.9 VDD = 3V I OL = 9mA 1.4 IOL = 3mA 0.9 VOL “L” level output voltage RESET VDD = 5V I OL = 5mA 2 V IOL = 1mA 0.6 VDD = 3V I OL = 2mA 0.9 IIH “H” level input current P0, P1, P2, P3, D 0–D7 RESET, XIN, XCIN, INT CNTR VI = VDD 2 µA IIL “L” level input current P0, P1, P2, P3, D 0–D7 RESET, XIN, XCIN, INT CNTR VI = 0V P0, P1, P2, P3, D0 to D7 No pull-up −2 µA RPU Pull-up resistor value P0, P1, P2, P3, D 0 to D7 RESET VI = 0V V DD = 5V 30 60 125 k Ω VDD = 3V 50 120 250 VT+ −VT− Hysteresis RESET VDD = 5V 1 V VDD = 3V 0.4 VT+ −VT− Hysteresis INT V DD = 5V 0.6 V VDD = 3V 0.3 VT+ −VT− Hysteresis CNTR V DD = 5V 0.2 V VDD = 3V 0.2 f(HSOCO) High-speed on-chip oscillator clock frequency V DD = 5V 400 1000 1600 kHz VDD = 3V 200 500 700 f(LSOCO) Low-speed on-chip oscillator clock frequency V DD = 5V 40 100 160 kHz VDD = 3V 20 50 70 RCOM COM output impedance (Note 1) VDD = 5V 1.5 7.5 k Ω VDD = 3V 2 10 RSEG SEG output impedance (Note 1) VDD = 5V 1.5 7.5 k Ω VDD = 3V 2 10 RVLC Internal resistor for LCD power supply When dividing resistor 2r × 3 selected 300 600 1200 k Ω When dividing resistor 2r × 2 selected 200 400 800 When dividing resistor r × 3 selected 150 300 600 When dividing resistor r × 2 selected 100 200 400

Rev.1.01 Feb 15, 2008 Page 144 of 146 REJ03B0224-0101 455A Group Note 1. The voltage drop detection circuit operation current (I RST) is added. Note 2. When the internal dividing resistors for LCD power are used , the current values according to using resistor values are added. Table 34 Electrical charac teristics 2 (Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) Symbol Parameter Test conditions Limits UnitMin. Typ. Max. IDD Supply current at active mode (with a ceramic oscillator) (1, 2) VDD = 5V f(XIN) = 6MHz f(HSOCO) = stop f(XCIN) = stop f(LSOCO) = stop f(STCK) = f(XIN)/8 1.2 2.4 mA f(STCK) = f(XIN)/4 1.3 2.6 f(STCK) = f(XIN)/2 1.6 3.2 f(STCK) = f(XIN)2 . 2 4 . 4 VDD = 5V f(XIN) = 4MHz f(HSOCO) = stop f(XCIN) = stop f(LSOCO) = stop f(STCK) = f(XIN)/8 0.9 1.8 mA f(STCK) = f(XIN)/4 1 2 f(STCK) = f(XIN)/2 1.2 2.4 f(STCK) = f(XIN)1 . 6 3 . 2 VDD = 3V f(XIN) = 4MHz f(HSOCO) = stop f(XCIN) = stop f(LSOCO) = stop f(STCK) = f(XIN)/8 0.3 0.6 mA f(STCK) = f(XIN)/4 0.4 0.8 f(STCK) = f(XIN)/2 0.5 1 f(STCK) = f(XIN)0 . 7 1 . 4 at active mode (with a quartz-crystal oscillator)(1, 2) VDD = 5V f(XIN) = stop f(HSOCO) = stop f(X CIN) = 32 kHz f(LSOCO) = stop f(STCK) = f(XCIN)/8 7 14 µA f(STCK) = f(XCIN)/4 8 16 f(STCK) = f(XCIN)/2 10 20 f(STCK) = f(XCIN)1 4 2 8 VDD = 3V f(XIN) = stop f(HSOCO) = stop f(XCIN) = 32 kHz f(LSOCO) = stop f(STCK) = f(XCIN)/8 5 10 µA f(STCK) = f(XCIN)/4 6 12 f(STCK) = f(XCIN)/2 7 14 f(STCK) = f(XCIN)8 1 6 at active mode (with a high-speed on-chip oscillator f(HSOCO))(1, 2) VDD = 5V f(XIN) = stop f(HSOCO) = active f(XCIN) = stop f(LSOCO) = stop f(STCK) = f(HSOCO)/8 50 100 µA f(STCK) = f(HSOCO)/4 70 140 f(STCK) = f(HSOCO)/2 110 220 f(STCK) = f(HSOCO) 190 380 V DD = 3V f(XIN) = stop f(HSOCO) = active f(X CIN) = stop f(LSOCO) = stop f(STCK) = f(HSOCO)/8 12 24 µA f(STCK) = f(HSOCO)/4 18 36 f(STCK) = f(HSOCO)/2 30 60 f(STCK) = f(HSOCO) 54 108 at active mode (with a low-speed on-chip oscillator f(LSOCO)) (1, 2) VDD = 5V f(XIN) = stop f(HSOCO) = stop f(XCIN) = stop f(LSOCO) = active f(STCK) = f(LSOCO)/8 10 20 µA f(STCK) = f(LSOCO)/4 12 24 f(STCK) = f(LSOCO/2 16 32 f(STCK) = f(LSOCO) 24 48 V DD = 3V f(XIN) = stop f(HSOCO) = stop f(XCIN) = stop f(LSOCO) = active f(STCK) = f(LSOCO)/8 3 6 µA f(STCK) = f(LSOCO)/4 4 8 f(STCK) = f(LSOCO)/2 5 10 f(STCK) = f(LSOCO) 7 14 at clock operation mode (POF instruction execution) (1, 2) f(XCIN) = 32 kHz VDD = 5V 6 12 µA VDD = 3V 5 10 f(LSOCO) = active VDD = 5V 20 40 VDD = 3V 5 10 at RAM back-up mode (POF2 instruction execution)(1) Ta = 25°C0 . 1 3 µA VDD = 5V 10 VDD = 3V 6

Rev.1.01 Feb 15, 2008 Page 145 of 146 REJ03B0224-0101 455A Group Voltage drop detection circuit characteristics Note 1. The detection voltage (V RST−) is defined as the voltage when reset occurs when the supply voltage (VDD) is falling. Note 2. The detection voltage (V RST+) is defined as the voltage when reset is released when the supply voltage (VDD) is rising from reset occurs. Note 3. When the supply voltage goes lower than the detection voltage (V SKIP), the voltage drop detection circuit interrupt request flag (VDF) is set to “1“. Note 4. Voltage drop detection circuit operation current (IRST) is added to IDD (power current) when voltage drop detection circuit is used. Note 5. The detection time (T RST) is defined as the time until reset occurs when the supply voltage (VDD) is falling to [VRST- −0.1V]. Basic timing diagram Table 35 Voltage drop detection circuit characteristics (Ta = –20 °C to 85 °C, unless otherwise noted) Symbol Parameter Test conditions Limits UnitMin. Typ. Max. VRST- Detection voltage (reset occurs) (Note 1) Ta = 25°C1 . 7 V 0°C≤ Ta < 50°C1 . 3 2 . 1 50°C≤ Ta ≤ 85°C1 . 1 1 . 8 VRST+ Detection voltage (reset release) (Note 2) Ta = 25°C1 . 8 V 0°C≤ Ta < 50°C1 . 4 2 . 2 50°C≤ Ta ≤ 85°C1 . 2 1 . 9 VSKIP Detection voltage (skip occurs) (Note 3) Ta = 25°C2 V 0°C≤ Ta < 50°C1 . 6 2 . 4 50°C≤ Ta ≤ 85°C1 . 4 2 . 1 VRST+ −VRST- Detection voltage hysteresis 0.1 V IRST Operation current (Note 4) V DD = 5V 30 60 µA VDD = 3V 15 30 VDD = 1.8V 6 12 TRST Detection time (Note 5) V DD → (VRST- −0.1V) 0.2 1.2 ms System clock STCK Port output D 0 to D7 P00 to P03 P10 to P13 P20 to P23 P30 to P33, C Port input D 0 to D7 P00 to P03 P10 to P13 P20 to P23 P30 to P33 Interrupt input INT Parameter Pin name Machine cycle Mi Mi + 1

Rev.1.01 Feb 15, 2008 Page 146 of 146 REJ03B0224-0101 455A Group PACKAGE OUTLINE INCLUDE TRIM OFFSET. DIMENSION "*3" DOES NOT NOTE) DO NOT INCLUDE MOLD FLASH. Detail F c A L A2A1 Index mark x y *3 F 39 27 131 ZD ZE D HD E HE bp Terminal cross section c bp Previous CodeJEITA Package Code RENESAS Code PLQP0052JA-A 52P6A-A MASS[Typ.] 0.3gP-LQFP52-10x10-0.65 1.0 0.125 0.30 1.1 1.1 0.13 0.200.1450.09 0.370.320.27 MaxNomMin Dimension in Millimeters Symbol Reference 10.110.09.9D 10.110.09.9E 1.4A2 12.212.011.8 12.212.011.8 1.7A 0.150.10.05 0.650.50.35L x 8°0° c 0.65e 0.10y HD HE bp ZD ZE e Under development

(1/1) REVISION HISTORY 455A Group Datasheet Rev. Date Description Page Summary

1.00 Oct 18, 2007 - First edition issued

1.01 Feb 15, 2008 - Delete the “PRELIMINARY” note

7 Table 6: "The key-on wakeup function is invalid." is added to “Usage Condition” column of “X

28 Table 15: Revised

50 Figure 48: Revised

58 Figure 56: Revised whole

76 Interrupt control register I1:

At the “INT pin timer 1 count start synchronous circuit selection bit” value is “0” “Timer 1 disabled” → “Timer 1 count start synchronous circuit not selected” At the “INT pin timer 1 count start synchronous circuit selection bit” value is “1” “Timer 1 enabled” → “Timer 1 count start synchronous circuit selected”

89 The second word “D 8” value of “BL p, a” instruction: “0” → “p6”

Note: “p=0 to 47” → ”M3455AG8: p=0 to 63 p6=0 M3455AGC: p=0 to 95” The second word “D8” value of “BLA p” instruction: “0” → “p6” Note: “p=0 to 47” → ”M3455AG8: p=0 to 63 p6=0 M3455AGC: p=0 to 95”

90 The second word “D 8” value of “BML p, a” instruction: “0” → “p6”

Note: “p=0 to 47” → ”M3455AG8: p=0 to 63 p6=0 M3455AGC: p=0 to 95” The second word “D8” value of “BMLA p” instruction: “0” → “p6” Note: “p=0 to 47” → ”M3455AG8: p=0 to 63 p6=0 M3455AGC: p=0 to 95”

98 The “RBK” instruction order is chan ged to next of the ”RBj” instruction

126 The second word “D 8” value of “BL p, a” instruction: “0” → “p6”

The second word “D8” value of “BLA p” instruction: “0” → “p6” The second word “D8” value of “BML p, a” instruction: “0” → “p6” The second word “D8” value of “BMLA p” instruction: “0” → “p6” Note: ”M3455AG8: p6=0” is added

144 Table 34: All “f(STCK)=f(X IN)“ are changed to “f(STCK)=f(LSOCO)” at active mode

(with a low-speed on-chip oscillator f(LSOCO))“

REVISION HISTORY

Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2377-3473 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Renesas Technology Singapore Pte. Ltd.

1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632

Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 RENESAS SALES OFFICES © 2008. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .7.2