4556

4556 RENESAS | Alldatasheet

Document overview

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Technical content

DESCRIPTION

The 4556 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with two 8-bit timers (each timer has one or two reload registers), a 16- bit timer for clock count, interrupts, and oscillation circuit switch function. The various microcomputers in the 4556 Group include variations of the built-in memory size as shown in the table below.

FEATURES

G Minimum instruction execution time (at 6 MHz oscillation frequency, in high-speed through-mode) µs (at 4.4 MHz oscillation frequency, in high-speed through-mode) G Supply voltage (It depends on operation source clock, oscillation frequency and op- eration mode) Part number ROM type Mask ROM Mask ROM One Time PROM Mask ROM Mask ROM One Time PROM Package 42P2R-A 42P2R-A 42P2R-A 42P2R-A 42P2R-A 42P2R-A RAM size (✕ 4 bits) 288 words 288 words 288 words 288 words 288 words 288 words ROM (PROM) size (✕ 10 bits) 4096 words 8192 words 8192 words 4096 words 8192 words 8192 words G Timers G LCD control circuit G Voltage drop detection circuit (only H version) G Watchdog timer G Clock generating circuit Built-in clock (on-chip oscillator) Main clock (ceramic resonator/RC oscillation) Sub-clock (quartz-crystal oscillation) G LED drive directly enabled (port D) APPLICATION Remote control transmitter Note: Shipped in blank. M34556M4-XXXFP M34556M8-XXXFP M34556G8FP ( Note) M34556M4H-XXXFP M34556M8H-XXXFP M34556G8HFP ( Note)

4556 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER REJ03B0025-0302 Rev.3.02 2006.12.22 Rev.3.02 Dec 22, 2006 page 1 of 142 REJ03B0025-0302

Rev.3.02 Dec 22, 2006 page 2 of 142 REJ03B0025-0302 Pin configuration (top view) (4556 Group) M34556Mx-XXXFP M34556G8FP M34556MxH-XXXFP M34556G8HFP XIN XOUT CNV SS XCIN/D6 XCOUT /D7 RESET COM 0 COM 1 COM 2 COM 3 SEG 0/VLC3 SEG 1/VLC2 SEG 2/VLC1 SEG 3 SEG 4 SEG 5 SEG 6 SEG 7 SEG 8 SEG 9 SEG 10 VSS VDD C/CNTR D 5/INT D 4 D 3 D 2 D 1 D 0 P13/SEG 28 P12/SEG 27 P11/SEG 26 P10/SEG 25 P03/SEG 24 P02/SEG 23 P01/SEG 22 P00/SEG 21 P23/SEG 20 P22/SEG 19 P21/SEG 18 P20/SEG 17

Rev.3.02 Dec 22, 2006 page 3 of 142 REJ03B0025-0302 Block diagram (4556 Group) RAMRO M Memory I/O portInternal peripheral function s Timer Timer 1(8 bits) System clock generation circuit Timer 2(8 bits) 288 words ✕ 4 bits 4096, 8192 words ✕ 10 bits 4500 seriesCPU core Register B (4 bits) Register A (4 bits)Register D (3 bits) Register E (8 bits) Stack register SK (8 levels) Interrupt stack register SDP (1 level) ALU(4 bits) Watchdog timer (16 bits) Port P0 Port P1 Port P2 Voltage drop detection circuit Timer 3(16 bits) LCD drive control circuit (Max.23 segments ✕ 4 common) X IN OUT Segment outpu t Common outpu t Port D Port C Note: The voltage drop detection circuit is equipped with only H version including 23 words ✕ 4 bits LCD display RAMOn-chip oscillator(Quartz-crystal) X CIN COUT (Ceramic/RC)

Rev.3.02 Dec 22, 2006 page 4 of 142 REJ03B0025-0302 4096 words ✕ 10 bits 8192 words ✕ 10 bits 288 words ✕ 4 bits (including LCD display RAM 23 words ✕ 4 bits) Six independent I/O ports. Input is examined by skip decision. The output structure can be switched by software. Port D 5 is also used as INT pin. Two independent output ports. Ports D6 and D7 are also used as XCIN and XCOUT , respectively. 4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched by software. Ports P00–P03 are also used as SEG21–SEG 24, respectively. 4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched by software. Ports P10–P13 are also used as SEG25–SEG 28, respectively. 4-bit I/O port; The output structure can be switched by software. Ports P20–P23 are also used as SEG 17–SEG 20, respectively. 1-bit output; Port C is also used as CNTR pin. 8-bit programmable timer with a reload register and has an event counter. 8-bit programmable timer with two reload registers and PWM output function. 16-bit timer, fixed dividing frequency (timer for clock count) 4-bit timer with a reload register (for LCD clock) 16-bit timer (fixed dividing frequency) (for watchdog) 1/2, 1/3 bias 2, 3, 4 duty 2r ✕ 3, 2r ✕ 2, r ✕ 3, r ✕ 2 (r = 80 kΩ, (Ta = 25 °C, Typical value)) 4 (one for external, three for timer ) 1 level 8 levels CMOS silicon gate 42-pin plastic molded SSOP (42P2R-A) –20 °C to 85 °C 1.8 to 5.5 V (It depends on operation source clock, oscillation frequency and operation mode) 1.8 to 3.6 V (It depends on operation source clock, oscillation frequency and operation mode) 2.2 mA (at room temperature, VDD = 5 V, f(XIN) = 6 MHz, f(XCIN ) = stop, f(RING) = stop, f(STCK) = f(XIN)/1) 6 µA (at room temperature, VDD = 5 V, f(XCIN) = 32 kHz) 0.1 µA (at room temperature, VDD = 5 V, output transistor is cut-off state) Parameter Number of basic instructions Minimum instruction execution time Memory sizes Input/Output ports Timers LCD control circuit Interrupt Subroutine nesting Device structure Package Operating temperature range Supply voltage Power dissipation (Typ.value) M34556M4/M8/G8 M34556M4H/M8H/G8H ROM RAM D 0–D 5 D 6, D7 P00–P03 P10–P13 P20–P23 C Timer 1 Timer 2 Timer 3 Timer LC Watchdog timer Selective bias value Selective duty value Common output Segment output Internal resistor for power supply Sources Nesting Mask ROM version One Time PROM version Active mode (Mask ROM version) At clock operating mode (Mask ROM version) At RAM back-up (Mask ROM version) I/O Output I/O I/O I/O Output M34556M4 M34556M4H M34556M8/G8 M34556M8H/G8H M34556M4/M8/G8 M34556M4H/M8H/G8H Mask ROM version One Time PROM version 0.5 µs (at 6 MHz oscillation frequency, in through mode) 0.68 µs (at 4.4 MHz oscillation frequency, in through mode)

Rev.3.02 Dec 22, 2006 page 5 of 142 REJ03B0025-0302 Connected to a plus power supply. Connected to a 0 V power supply. Connect CNV SS to VSS and apply “L” (0V) to CNVSS certainly. An N-channel open-drain I/O pin for a system reset. When the SRST instruction, watchdog timer, the built-in power-on reset or the voltage drop detection circuit causes the system to be reset, the RESET pin outputs “L” level. I/O pins of the main clock generating circuit. When using a ceramic resonator, con- nect it between pins X IN and XOUT . A feedback resistor is built-in between them. When using the RC oscillation, connect a resistor and a capacitor to XIN, and leave XOUT pin open. I/O pins of the sub-clock generating circuit. Connect a 32.768 kHz quartz-crystal oscilla- tor between pins XCIN and XCOUT . A feedback resistor is built-in between them. XCIN and XCOUT pins are also used as ports D6 and D7, respectively. XOUT Main clock output Output D 0–D 5 D 6, D7 P00–P03 P10–P13 P20–P23 Port C COM 0– COM 3 SEG 0–SEG 10 SEG 17–SEG 28 (Note) CNTR INT I/O port D Input is examined by skip decision. Output port D I/O port P0 I/O port P1 I/O port P2 Output port C Common output Segment output Timer input/output Interrupt input I/O Output I/O I/O I/O Output Output Output I/O Input Each pin of port D has an independent 1-bit wide I/O function. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Port D 5 is also used as INT pin. Each pin of port D has an independent 1-bit wide output function. The output struc- ture is N-channel open-drain. Ports D6 and D7 are also used as XCIN pin and XCOUT pin, respectively. Port P0 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Port P0 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Ports P0 0–P0 3 are also used as SEG21–SEG 24, respectively. Port P1 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Port P1 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Ports P1 0–P1 3 are also used as SEG25–SEG 28, respectively. Port P2 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Ports P2 0–P23 are also used as SEG17–SEG 20, respectively. 1-bit output port. The output structure is CMOS. Port C is also used as CNTR pin. LCD common output pins. Pins COM0 and COM 1 are used at 1/2 duty, pins COM0– COM 2 are used at 1/3 duty and pins COM0–COM 3 are used at 1/4 duty. LCD segment output pins. SEG0–SEG 2 pins are used as VLC3 –VLC1 pins, respec- tively. SEG17–SEG 28 pins are used as Ports P20–P2 3, Ports P00–P0 3 and Ports P10–P13, respectively. CNTR pin has the function to input the clock for the timer 1 event counter and to out- put the PWM signal generated by timer 2.CNTR pin is also used as Port C. INT pin accepts external interrupts. They have the key-on wakeup function which can be switched by software. INT pin is also used as Port D5. Notes 1: Pins except above have just single function. 2: The input/output of D5 can be used even when INT is selected. The threshold value is different between port D5 and INT. Accordingly, be careful when the input of both is used. 3: The port C “H ” output function can be used even when CNTR (output) is selected. Pin XCIN XCOUT P00 P01 P02 P03 P10 P11 P12 P13 Multifunction D 6 D 7 SEG 21 SEG 22 SEG 23 SEG 24 SEG 25 SEG 26 SEG 27 SEG 28 MULTIFUNCTION Pin D 6 D 7 SEG 21 SEG 22 SEG 23 SEG 24 SEG 25 SEG 26 SEG 27 SEG 28 Multifunction XCIN XCOUT P00 P01 P02 P03 P10 P11 P12 P13 Pin P20 P21 P22 P23 D 5 C SEG SEG 1 SEG 2 Multifunction SEG 17 SEG 18 SEG 19 SEG 20 INT CNTR V LC3 VLC2 VLC1 Pin SEG 17 SEG 18 SEG 19 SEG 20 INT CNTR V LC3 VLC2 VLC1 Multifunction P20 P21 P22 P23 D 5 C SEG SEG 1 SEG 2 XCOUT Sub-clock output Output Note: SEG11 to SEG16 pins are not existed in the 4556 Group.

Rev.3.02 Dec 22, 2006 page 6 of 142 REJ03B0025-0302 DEFINITION OF CLOCK AND CYCLE G Operation source clock The operation source clock is the source clock to operate this product. In this product, the following clocks are used.

• Clock (f(X IN)) by the external ceramic resonator
• Clock (f(XIN)) by the external RC oscillation
• Clock (f(XIN)) by the external input
• Clock (f(RING)) of the on-chip oscillator which is the internal oscillator
• Clock (f(XCIN)) by the external quartz-crystal resonator Register MR System clock f(STCK) = f(RING)/8 f(STCK) = f(RING)/4 f(STCK) = f(RING)/2 f(STCK) = f(RING) f(STCK) = f(X IN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XCIN)/8 f(STCK) = f(XCIN)/4 f(STCK) = f(XCIN)/2 f(STCK) = f(XCIN) Table Selection of system clock Note: The f(RING)/8 is selected after system is released from reset. MR 2 MR Operation mode Internal frequency divided by 8 mode Internal frequency divided by 4 mode Internal frequency divided by 2 mode Internal frequency through mode High-speed frequency divided by 8 mode High-speed frequency divided by 4 mode High-speed frequency divided by 2 mode High-speed through mode Low-speed frequency divided by 8 mode Low-speed frequency divided by 4 mode Low-speed frequency divided by 2 mode Low-speed through mode G System clock (STCK) The system clock is the basic clock for controlling this product. The system clock is selected by the clock control register MR shown as the table below. G Instruction clock (INSTCK) The instruction clock is the basic clock for controlling CPU. The instruction clock (INSTCK) is a signal derived by dividing the system clock (STCK) by 3. The one instruction clock cycle gen- erates the one machine cycle. G Machine cycle The machine cycle is the standard cycle required to execute the instruction. MR 0 MR PORT FUNCTION Port Port D Port P0 Port P1 Port P2 Port C I/O unit Control instructions SD, RD SZD CLD OP0A IAP0 OP1A IAP1 OP2A IAP2 RCP SCP Control registers FR1, FR2 I1, K2 RG FR0, PU0 FR0, PU1 K0, K1 FR2 Output structure N-channel open-drain/ CMOS N-channel open-drain N-channel open-drain/ CMOS N-channel open-drain/ CMOS N-channel open-drain/ CMOS CMOS Input Output I/O (6) Output (2) I/O (4) I/O (4) I/O (4) Output (1) RemarkPin D 0–D 4, D5/INT XCIN/D6, XCOUT /D7 P00/SEG 21–P03/SEG 24 P10/SEG 25–P13/SEG 28 P20/SEG 17–P23/SEG 20 C/CNTR Output structure selection function (programmable) Built-in pull-up functions, key-on wakeup functions and output structure selection function (programmable) Built-in pull-up functions, key-on wakeup functions and output structure selection function (programmable) Output structure selection func tion (programmable)

Rev.3.02 Dec 22, 2006 page 7 of 142 REJ03B0025-0302 CONNECTIONS OF UNUSED PINS Connection Connect to VSS . Open. Connect to V SS . Open. Open. Connect to V SS . Open. Connect to V SS . Open. Open. Connect to V SS . Open. Connect to Vss. Open. Connect to Vss. Open. Open. Open. Open. Open. Pin X IN XOUT XCIN/D6 XCOUT /D7 D 0–D 4 D 5/INT C/CNTR P00/SEG 21– P03/SEG 24 P10/SEG 25– P13/SEG 28 P20/SEG 17– P23/SEG 20 COM 0–COM 3 SEG 0/VLC3 SEG 1/VLC2 SEG 2/VLC1 SEG 3–SEG 10 (Note) Usage condition RC oscillator is not selected N-channel open-drain is selected for the output structure. INT pin input is disabled. N-channel open-drain is selected for the output structure. CNTR input is not selected for timer 1 count source. The key-on wakeup function is invalid. Segment output is not selected. N-channel open-drain is selected for the output structure. Pull-up transistor is OFF. The key-on wakeup function is invalid. The key-on wakeup function is invalid. Segment output is not selected. N-channel open-drain is selected for the output structure. Pull-up transistor is OFF. The key-on wakeup function is invalid. Segment output is not selected. N-channel open-drain is selected for the output structure. SEG 0 pin is selected. SEG 1 pin is selected. SEG 2 pin is selected. Note: SEG11 to SEG16 pins are not existed in the 4556 Group. (Note when connecting to VSS and VDD ) G Connect the unused pins to VSS and VDD using the thickest wire at the shortest distance against noise.

Rev.3.02 Dec 22, 2006 page 8 of 142 REJ03B0025-0302 Port block diagram (1) D 0 — D 3S RQ FR1 i T h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e o n t h e p o r t A p p l i e d p o t e n t i a l t o t h e s e p o r t s m u s t b e VD D o r l e s s i r e p r e s e n t s b i t s t o A s f o r d e t a i l s r e f e r t o t h e e x t e r n a l i n t e r r u p t s t r u c t u r e N o t e s Register Y Decoder S D i n s t r u c t i o n R D i n s t r u c t i o n Skip decision C L D i n s t r u c t i o n (Note 1) (Note 2) (Note 1) (Note 3) S Z D i n s t r u c t i o n D 4S RQ FR2 0 Register Y Decoder SD instruction RD instruction Skip decision CLD instruction (Note 1) (Note 2) (Note 1) SZD instruction D 5/ I N TS RQ FR2 1 Register Y Decoder SD instruction R D i n s t r u c t i o n Skip decision CLD instruction (Note 1) (Note 2) (Note 1) S Z D i n s t r u c t i o n E x t e r n a l i n t e r r u p t c i r c u i t (Note 4) E x t e r n a l i n t e r r u p t K e y o n w a k e u p i n p u t Timer 1 count start synchronous circuit input

Rev.3.02 Dec 22, 2006 page 9 of 142 REJ03B0025-0302 Port block diagram (2) C/CNTR SCP instruction RCP instruction S R W1 0 W1 1 Q PWMOD D T QR W1 2 W4 1 Clock input for timer 1 event count This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. Notes 1: (Note 1) (Note 2) XCIN/D6S RQ Register Y Decoder SD instruction RD instruction CLD instruction (Note 1) (Note 2) (Note 1) XCOUT /D7S RQ Register Y Decoder SD instruction RD instruction CLD instruction (Note 1) (Note 2) (Note 1) RG 2 Quartz-crystal oscillation circuit RG 2 RG 2 Timer 1 underflow signal (Note 1) Sub-clock input

Rev.3.02 Dec 22, 2006 page 10 of 142 REJ03B0025-0302 Port block diagram (3) P00/SEG 21, P01/SEG 22 C1 j (Note 1) LCD control signal LCD power supply LCD power supply Notes 1: (Note 1) FR0 0 OP0A instruction Register A Aj Aj D IAP0 instruction TQ C1 j This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: j represents bits 0 and 1. 4: k represents bits 2 and 3. K00 Edge detection circuit key-on wakeup input PU0 j Pull-up transistor P02/SEG 23, P03/SEG 24 C1 k (Note 1) LCD control signal LCD power supply LCD power supply (Note 1) FR0 1 OP0A instruction Register A Ak Ak D IAP0 instruction TQ C1 k K01 Edge detection circuit key-on wakeup input PU0 K Pull-up transistor

Rev.3.02 Dec 22, 2006 page 11 of 142 REJ03B0025-0302 Port block diagram (4) P10/SEG 25, P11/SEG 26 C2 j (Note 1) LCD control signal LCD power supply LCD power supply Notes 1: (Note 1) FR0 2 OP1A instruction Register A Aj Aj D IAP1 instruction TQ C2 j This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: j represents bits 0 and 1. 4: k represents bits 2 and 3. K02Edge detection circuitkey-on wakeup input PU1 j Pull-up transistor Level detection circuit K11 K10 P12/SEG 27, P13/SEG 28 C2 k (Note 1) LCD control signal LCD power supply LCD power supply (Note 1) FR0 3 OP1A instruction Register A Ak Ak D IAP1 instruction TQ C2 k K03Edge detection circuitkey-on wakeup input PU1 k Pull-up transistor Level detection circuit K13 K12

Rev.3.02 Dec 22, 2006 page 12 of 142 REJ03B0025-0302 Port block diagram (5) P20/SEG 17, P21/SEG 18 L3j (Note 1) LCD control signal LCD power supply LCD power supply (Note 2) Notes 1: (Note 1) FR2 2 OP2A instruction Register A Aj Aj D IAP2 instruction TQ L3j (Note 3) This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: j represents bits 0 and 1. 4: k represents bits 2 and 3. (Note 3) P22/SEG 19, P23/SEG 20 L3k (Note 1) LCD control signal LCD power supply LCD power supply (Note 2)(Note 1) FR2 3 OP2A instruction Register A Ak Ak D IAP2 instruction TQ L3k (Note 4) (Note 4) (Note 3) (Note 4)

Rev.3.02 Dec 22, 2006 page 13 of 142 REJ03B0025-0302 Port block diagram (6) COM 0–COM 3 SEG 3–SEG 10 LCD control signal LCD power supply LCD control signal LCD power supply LCD control signal LCD power supply LCD control signal LCD power supply LCD control signal LCD power supply LCD control signal (Note 1) (Note 2) (Note 2) (Note 1) (Note 1) (Note 1) Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less.

Rev.3.02 Dec 22, 2006 page 14 of 142 REJ03B0025-0302 (VLC3 ) SEG 0/VLC3 L23 (VLC2 ) SEG 1/VLC2 L22 (VLC1 ) SEG 2/VLC1 L21 L13 L20 L12 L21 Reset signal EPOF+POF2 instruction (Note 1) LCD control signal LCD power supply LCD power supply (Note 2) LCD power supply (Note 1) LCD control signal LCD power supply LCD power supply (Note 2) LCD power supply LCD power supply LCD power supply LCD power supply LCD control signal (Note 1) (Note 2) Notes 1: L23 (Note 1) (Note 1) (Note 1) L22 L21 This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. Port block diagram (7)

Rev.3.02 Dec 22, 2006 page 15 of 142 REJ03B0025-0302 Block diagram of external interrupt I12 EXF0 I11 D 5/INT I13 (Note 1) Skip decision One-sided edge detection circuit Both edges detection circuit External 0 interrupt This symbol represents a parasitic diode on the port.• Timer 1 count start synchronization circuit input (Note 1) SNZI0 instruction K20 Level detection circuit Edge detection circuit K21 Key-on wakeup input

Rev.3.02 Dec 22, 2006 page 16 of 142 REJ03B0025-0302 (1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4- bit data addition, comparison, AND operation, OR operation, and bit manipulation. (2) Register A and carry flag Register A is a 4-bit register used for arithmetic, transfer, ex- change, and I/O operation. Carry flag CY is a 1-bit flag that is set to “1” when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A 0 is stored in carry flag CY with the RAR instruction (Figure 2). Carry flag CY can be set to “1” with the SC instruction and cleared to “0” with the RC instruction. (3) Registers B and E Register B is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3). Register E is undefined after system is released from reset and re- turned from the power down mode. Accordingly, set the initial value. (4) Register D Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 4). Also, when the TABP p instruction is executed at UPTF flag = “1”, the high-order 2 bits of ROM reference data is stored to the low-or- der 2 bits of register D, the high-order 1 bit of register D is “0”. When the TABP p instruction is executed at UPTF flag = “0”, the contents of register D remains unchanged. The UPTF flag is set to “1” with the SUPT instruction and cleared to “0” with the RUPT in- struction. The initial value of UPTF flag is “0”. Register D is undefined after system is released from reset and re- turned from the power down mode. Accordingly, set the initial value. Fig. 1 AMC instruction execution example Fig. 2 RAR instruction execution example Fig. 3 Registers A, B and register E Fig. 4 TABP p instruction execution example ( C Y ) ( M ( D P ) ) ( A ) Addition A L U <Carry> < R e s u l t > CY A 3 A2 A1 A0 A0 C YA 3 A2 A1 < R o t a t i o n > R A R i n s t r u c t i o n <Set> SC instruction <Clear> RC instruction A3 A2 A1 A0B3 B2 B1 B0 E7 E6 E5 E4 E3 E2 E1 E0 A3 A2 A1 A0B3 B2 B1 B0 TAB instruction T E A B i n s t r u c t i o n TABE instruction TBA instruction R e g i s t e r BR e g i s t e r A Register B Register A Register E Specifying address TABP p instruction p6 p5 p4 p3 p2 p1 p0 PC H DR 2 DR 1DR 0 A3 A2 A1 A0 PC L Immediate field value p The contents of register D RO M 84 0 Middle-order 4 bits Low-order 4bits Register A (4) Register B (4) The contents of register A High-order 2 bits Register D (3) * UPTF=1, high-order 1 bit of register D is “0”. UPTF=0, data is not transferred to register D.

Rev.3.02 Dec 22, 2006 page 17 of 142 REJ03B0025-0302 (5) Stack registers (SKS) and stack pointer (SP) Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when;

• branching to an interrupt service routine (referred to as an inter- rupt service routine),
• performing a subroutine call, or
• executing the table reference instruction (TABP p). Stack registers (SKs) are eight identical registers, so that subrou- tines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be care- ful not to over the stack when performing these operations together. The contents of registers SKs are destroyed when 8 lev- els are exceeded. The register SK nesting level is pointed automatically by 3-bit stack pointer (SP). The contents of the stack pointer (SP) can be transferred to register A with the TASP instruction. Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call. (6) Interrupt stack register (SDP) Interrupt stack register (SDP) is a 1-stage register. When an inter- rupt occurs, this register (SDP) is used to temporarily store the contents of data pointer, carry flag, skip flag, register A, and regis- ter B just before an interrupt until returning to the original routine. Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table refer- ence instruction. (7) Skip flag Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. When an interrupt oc- curs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained. Fig. 5 Stack registers (SKs) structure Fig. 6 Example of operation at subroutine call S K0 S K1 S K2 S K3 S K4 S K5 S K6 S K7 ( S P ) = 0 ( S P ) = 1 ( S P ) = 2 ( S P ) = 3 ( S P ) = 4 ( S P ) = 5 ( S P ) = 6 ( S P ) = 7 Program counter (PC) E x e c u t i n g R T i n s t r u c t i o n Executing BM instruction Stack pointer (SP) points “7” at reset or returning from power down mode. It points “0” by executing the first BM instruction, and the contents of program counter is stored in SK0. When the BM instruction is executed after eight stack registers are used ((SP) = 7), (SP) = 0 and the contents of SK0 is destroyed. Returning to the BM instruction execution address with the RT instruction, and the BM instruction becomes the NOP instruction. (SP) ← 0 (SK0) ← 000116 (PC) ← SUB1 Main program

000216 NOP

6 N O P

000116 BM SUB1

S U B 1 : NOP RT ( P C ) ← ( S K0) S P Note :

Rev.3.02 Dec 22, 2006 page 18 of 142 REJ03B0025-0302 (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table refer- ence instruction (TABP p) is executed. Program counter consists of PC H (most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which speci- fies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PC H does not specify after the last page of the built-in ROM. (9) Data pointer (DP) Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y . Register Z specifies a RAM file group, reg- ister X specifies a file, and register Y specifies a RAM digit (Figure 8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 9).

• Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the power down mode. After system is returned from the power down mode, set these reg- isters. Fig. 7 Program counter (PC) structure Fig. 8 Data pointer (DP) structure Fig. 9 SD instruction execution example p5 p4 p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0 P r o g r a m c o u n t e r P C H S p e c i f y i n g p a g e P C L S p e c i f y i n g a d d r e s s Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0 D a t a p o i n t e r ( D P ) Register Z (2) R e g i s t e r X ( 4 ) Register Y (4)S p e c i f y i n g R A M d i g i t S p e c i f y i n g R A M f i l e Specifying RAM file group 0 01 1 Set S p e c i f y i n g b i t p o s i t i o n Port D output latchRegister Y (4) D 2D 3 D 1 D 0

Rev.3.02 Dec 22, 2006 page 19 of 142 REJ03B0025-0302 PROGRAM MEMORY (ROM) The program memory is a mask ROM. 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Fig- ure 10 shows the ROM map of M34556ED. Table 1 ROM size and pages Part number M34556M4 M34556M4H M34556M8 M34556M8H M34556G8 M34556G8H ROM (PROM) size (✕ 10 bits) 4096 words 8192 words Pages 32 (0 to 31) 64 (0 to 63) A part of page 1 (addresses 008016 to 00FF16) is reserved for in- terrupt addresses (Figure 11). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is executed. When using an interrupt service routine, write the in- struction generating the branch to that routine at an interrupt address. Page 2 (addresses 0100 16 to 017F16) is the special page for sub- routine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM in- struction when it starts on page 2. ROM pattern (bits 7 to 0) of all addresses can be used as data ar- eas with the TABP p instruction. Fig. 10 ROM map of M34556M8/M8H/G8/G8H Fig. 11 Page 1 (addresses 008016 to 00FF16) structure 9876543210 Interrupt address page 0000 008016 017F16 Subroutine special page 007F 00FF16 010016 1FFF 16 018016 Page 1 Page 2 Page 0 Page 3 Page 63 90 87654321 External 0 interrupt address008016 008216

008416 Timer 1 interrupt address

Timer 2 interrupt address008616 008816 008A16 008C 16 008E16 00FF16 Timer 3 interrupt address

Rev.3.02 Dec 22, 2006 page 20 of 142 REJ03B0025-0302 DATA MEMORY (RAM) 1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers Z, X, and Y. Set a value to the data pointer certainly when executing an instruction to access RAM (also, set a value after system returns from power down mode). RAM includes the area for LCD. When writing “1” to a bit corresponding to displayed segment, the segment is turned on. Table 2 shows the RAM size. Figure 12 shows the RAM map.

• Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the power down mode, set these registers. Fig. 12 RAM map Table 2 RAM size Part number M34556M4/M4H M34556M8/M8H M34556G8/G8H RAM size 288 words ✕ 4 bits (1152 bits) Register Y Register Z Register X 0 1 13 RAM 288 words ✕ 4 bits (1152 bits) 23 1 2... 1514 0 1 2 Note: The numbers in the shaded area indicate the corresponding segment output pin numbers.

Rev.3.02 Dec 22, 2006 page 21 of 142 REJ03B0025-0302 The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the following 3 conditions are satisfied.

• An interrupt activated condition is satisfied (request flag = “1”)
• Interrupt enable bit is enabled (“1”)
• Interrupt enable flag is enabled (INTE = “1”) Table 3 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.) (1) Interrupt enable flag (INTE) The interrupt enable flag (INTE) controls whether the every inter- rupt enable/disable. Interrupts are enabled when INTE flag is set to “1” with the EI instruction and disabled when INTE flag is cleared to “0” with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to “0,” so that other interrupts are disabled until the EI instruction is executed. (2) Interrupt enable bit Use an interrupt enable bit of interrupt control registers V1 and V2 to select the corresponding interrupt or skip instruction. Table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. Table 5 shows the interrupt enable bit function. (3) Interrupt request flag When the activated condition for each interrupt is satisfied, the cor- responding interrupt request flag is set to “1.” Each interrupt request flag is cleared to “0” when either;
• an interrupt occurs, or
• the next instruction is skipped with a skip instruction. Each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its in- terrupt enable bit. Once set, the interrupt request flag retains set until a clear condition is satisfied. Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. If more than one interrupt request flag is set when the interrupt dis- able state is released, the interrupt priority level is as follows shown in Table 3. Table 3 Interrupt sources Activated condition Level change of INT pin Timer 1 underflow Timer 2 underflow Timer 3 underflow Priority level Interrupt name External 0 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Request flag EXF0 T1F T2F T3F Interrupt name External 0 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Table 5 Interrupt enable bit function Occurrence of interrupt Enabled Disabled Skip instruction Invalid Valid Interrupt enable bit Interrupt address Address 0 in page 1 Address 4 in page 1 Address 6 in page 1 Address 8 in page 1 Table 4 Interrupt request flag, interrupt enable bit and skip in- struction Skip instruction SNZ0 SNZT1 SNZT2 SNZT3 Enable bit V10 V12 V13 V20

Rev.3.02 Dec 22, 2006 page 22 of 142 REJ03B0025-0302 (4) Internal state during an interrupt The internal state of the microcomputer during an interrupt is as fol- lows (Figure 14).

• Program counter (PC) An interrupt address is set in program counter. The address to be executed when returning to the main routine is automatically stored in the stack register (SK).
• Interrupt enable flag (INTE) INTE flag is cleared to “0” so that interrupts are disabled.
• Interrupt request flag Only the request flag for the current interrupt source is cleared to “0.”
• Data pointer, carry flag, skip flag, registers A and B The contents of these registers and flags are stored automatically in the interrupt stack register (SDP). (5) Interrupt processing When an interrupt occurs, a program at an interrupt address is ex- ecuted after branching a data store sequence to stack register. Write the branch instruction to an interrupt service routine at an in- terrupt address. Use the RTI instruction to return from an interrupt service routine. Interrupt enabled by executing the EI instruction is performed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction, interrupts are enabled after returning the main routine. (Refer to Figure 13) Fig. 13 Program example of interrupt processing
• Program counter (PC)
• Stack register (SK)
• Interrupt enable flag (INTE)
• Interrupt request flag (only the flag for the current interrupt
• Data pointer, carry flag, registers A and B, skip flag The address of main routine to be executed when returning Fig. 15 Interrupt system diagram Fig. 14 Internal state when interrupt occurs E I R T I I n t e r r u p t s e r v i c e r o u t i n e Interrupt occurs Interrupt is enabled M a i n r o u t i n e : I n t e r r u p t e n a b l e d s t a t e : I n t e r r u p t d i s a b l e d s t a t e EXF0 V10 Address 4 in page 1 Address 0 in page 1 Timer 1 underflow Timer 2 underflow T1F V1 2 Request flag (state retained) Enable bit Enable flagActivated condition V13 Address 6 in page 1 INTE T2F V20T3F INT pin interrupt waveform input Timer 3 underflow Address 8 in page 1

Rev.3.02 Dec 22, 2006 page 23 of 142 REJ03B0025-0302 (6) Interrupt control registers

• Interrupt control register V1 Interrupt enable bits of external 0, timer 1 and timer 2 are as- signed to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A. Table 6 Interrupt control registers Note: “R ” represents read enabled, and “W ” represents write enabled.
• Interrupt control register V2 The timer 3 interrupt enable bit is assigned to register V2. Set the contents of this register through register A with the TV2A instruc- tion. The TAV2 instruction can be used to transfer the contents of register V2 to register A. This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) V13 V12 V11 V10 V23 V22 V21 V20 Not used Not used Not used Timer 3 interrupt enable bit Interrupt control register V2 at power down : 00002at reset : 00002 Interrupt control register V1 Timer 2 interrupt enable bit Timer 1 interrupt enable bit Not used External 0 interrupt enable bit Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) This bit has no function, but read/write is enabled. Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) at power down : 0000 2at reset : 00002 R/W TAV1/TV1A R/W TAV2/TV2A

Rev.3.02 Dec 22, 2006 page 24 of 142 REJ03B0025-0302 Fig. 16 Interrupt sequence T1F,T2F,T3F INT EXF0 T1 T2 T3 T1 T2 T3 T2 T3T1 T1 T2 T3 T1 T2 G When an interrupt request flag is set after its interrupt is enabled (Note 1) System clock (STCK) The program starts from the interrupt address. Interrupt enabled state 1 machine cycle EI instruction execution cycle Interrupt enable flag (INTE) Retaining level of system clock for 4 periods or more is necessary. Interrupt disabled state External interrupt Timer 1, Timer 2, Timer 3 interrupts Interrupt activated condition is satisfied. Notes 1: The address is stacked to the last cycle. 2: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied. Flag cleared 2 to 3 machine cycles (Notes 1, 2) (7) Interrupt sequence Interrupts only occur when the respective INTE flag, interrupt en- able bits (V10, V12, V13, V20), and interrupt request flag are “1.” The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. The interrupt occurs after 3 machine cycles only when the three interrupt conditions are sat- isfied on execution of other than one-cycle instructions (Refer to Figure 16).

Rev.3.02 Dec 22, 2006 page 25 of 142 REJ03B0025-0302 Table 7 External interrupt activated conditions Name External 0 interrupt Input pin D 5/INT Activated condition When the next waveform is input to D5/INT pin

• Both rising and falling waveforms Valid waveform selection bit I11 I12 Fig. 17 External interrupt circuit structure EXTERNAL INTERRUPTS The 4556 Group has the external 0 interrupt. An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). The external interrupt can be controlled with the interrupt control register I1. Rising Falling I12 One-sided edge detection circuit Key-on wakeup EXF0 External 0 interrupt I11 D 5/INT K20 Timer 1 count start synchronous circuitI13 (Note 1) Level detection circuit Edge detection circuit K21 Skip decision (SNZI0 instruction) Both edges detection circuit This symbol represents a parasitic diode on the port.Notes 1: (Note 2) (Note 3) 2: I12 (I22) = 0: “L” level detected I12 (I22) = 1: “H ” level detected 3: I12 (I22) = 0: Falling edge detected I12 (I22) = 1: Rising edge detected

Rev.3.02 Dec 22, 2006 page 26 of 142 REJ03B0025-0302 Table 8 External interrupt control register Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: When the contents of these bits (I12 , I13) are changed, the external interrupt request flag (EXF0) may be set. I13 I12 I11 I10 INT pin input control bit (Note 2) Interrupt valid waveform for INT pin/ return level selection bit (Note 2) INT pin edge detection circuit control bit INT pin Timer 1 count start synchronous circuit selection bit Interrupt control register I1 R/W TAI1/TI1Aat power down : state retainedat reset : 00002 INT pin input disabled INT pin input enabled Falling waveform/“L” level (“L” level is recognized with the SNZI0 instruction) Rising waveform/“H ” level (“H ” level is recognized with the SNZI0 instruction) One-sided edge detected Both edges detected Timer 1 count start synchronous circuit not selected Timer 1 count start synchronous circuit selected (1) External 0 interrupt request flag (EXF0) External 0 interrupt request flag (EXF0) is set to “1” when a valid waveform is input to D5/INT pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to “0” when an in- terrupt occurs or when the next instruction is skipped with the skip instruction.

• External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to D 5/INT pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 0 interrupt is as follows. ➀ Set the bit 3 of register I1 to “1” for the INT pin to be in the input enabled state. ➁ Select the valid waveform with the bits 1 and 2 of register I1. ➂ Clear the EXF0 flag to “0” with the SNZ0 instruction. ➃ Set the NOP instruction for the case when a skip is performed with the SNZ0 instruction. ➄ Set both the external 0 interrupt enable bit (V1 0) and the INTE flag to “1.” The external 0 interrupt is now enabled. Now when a valid wave- form is input to the D5/INT pin, the EXF0 flag is set to “1” and the external 0 interrupt occurs. (2) External interrupt control registers
• Interrupt control register I1 Register I1 controls the valid waveform for the external 0 inter- rupt. Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents of register I1 to register A.

Rev.3.02 Dec 22, 2006 page 27 of 142 REJ03B0025-0302 (3) Notes on External 0 interrupts ➀ Note [1] on bit 3 of register I1 When the input of the INT pin is controlled with the bit 3 of regis- ter I1 in software, be careful about the following notes.

• Depending on the input state of the D5/INT pin, the external 0 in- terrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 18➀ ) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to Figure 18➁ ). Also, set the NOP instruction for the case when a skip is per- formed with the SNZ0 instruction (refer to Figure 18➂ ). LA 4 ; ( ✕✕✕ 02) LA 8 ; (1 ✕✕✕ 2) TI1A ; Control of INT pin input is changed SNZ0 ; The SNZ0 instruction is executed (EXF0 flag cleared) ✕ : these bits are not used here. Fig. 18 External 0 interrupt program example-1 ➁ Note [2] on bit 3 of register I1 When the bit 3 of register I1 is cleared to “0”, the RAM back-up mode is selected and the input of INT pin is disabled, be careful about the following notes.
• When the key-on wakeup function of INT pin is not used (register 0 = “0”), clear bits 2 and 3 of register I1 before system enters to the power down mode. (refer to Figure 19➀ ).
• ••
• •• LA 0 ; (00 ✕✕ 2) DI EPOF POF2 ; power down mode ✕ : these bits are not used here. Fig. 19 External 0 interrupt program example-2
• ••
• •• ➂ Note on bit 2 of register I1 When the interrupt valid waveform of the D5/INT pin is changed with the bit 2 of register I1 in software, be careful about the fol- lowing notes.
• Depending on the input state of the D5/INT pin, the external 0 in- terrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 20➀ ) and then, change the bit 2 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to Figure 20➁ ). Also, set the NOP instruction for the case when a skip is per- formed with the SNZ0 instruction (refer to Figure 20➂ ). LA 4 ; ( ✕✕✕ 02) LA 12 TI1A ; Interrupt valid waveform is changed SNZ0 ; The SNZ0 instruction is executed (EXF0 flag cleared) ✕ : these bits are not used here. Fig. 20 External 0 interrupt program example-3
• ••
• ••

Rev.3.02 Dec 22, 2006 page 28 of 142 REJ03B0025-0302 The 4556 Group has the following timers.

• Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a set- ting value n. When it underflows (count to n + 1), a timer interrupt request flag is set to “1,” new data is loaded from the reload reg- ister, and count continues (auto-reload function).
• Fixed dividing frequency timer The fixed dividing frequency timer has the fixed frequency divid- ing ratio (n). An interrupt request flag is set to “1” after every n count of a count pulse. Fig. 21 Auto-reload function The 4556 Group timer consists of the following circuits.
• Prescaler : 8-bit programmable timer
• Timer 1 : 8-bit programmable timer
• Timer 2 : 8-bit programmable timer
• Timer 3 : 16-bit fixed dividing frequency timer
• Timer LC : 4-bit programmable timer
• Watchdog timer : 16-bit fixed dividing frequency timer (Timers 1, 2, and 3 have the interrupt function, respectively) Prescaler and timers 1, 2, 3 and LC can be controlled with the timer control registers PA, W1 to W4. The watchdog timer is a free counter which is not controlled with the control register. Each function is described below. F F1 n 0 01 n : C o u n t e r i n i t i a l v a l u e C o u n t s t a r t s Reload R e l o a d 1st underflow 2nd underflow n + 1 c o u n t n + 1 c o u n t Time A n i n t e r r u p t o c c u r s o r a s k i p i n s t r u c t i o n i s e x e c u t e d Timer interrupt request flag T h e c o n t e n t s o f c o u n t e r “1” “0”

Rev.3.02 Dec 22, 2006 page 29 of 142 REJ03B0025-0302

• Instruction clock (INSTCK)
• PWM output (PWMOUT)
• Prescaler output (ORCLK)
• Timer 3 underflow (T3UDF)
• CNTR input
• X IN input
• Prescaler output (ORCLK) divided by 2
• XCIN input
• ORCLK
• Bit 4 of timer 3
• System clock (STCK)
• Instruction clock (INSTCK) Structure 8-bit programmable binary down counter 8-bit programmable binary down counter (link to INT input) 8-bit programmable binary down counter (PWM output function) 16-bit fixed dividing frequency 4-bit programmable binary down counter 16-bit fixed dividing frequency Circuit Prescaler Timer 1 Timer 2 Timer 3 Timer LC Watchdog timer Use of output signal
• Timer 1, 2, and 3 count sources
• CNTR output control
• Timer 1 interrupt
• Timer 1 count source
• CNTR output
• Timer 2 interrupt
• Timer 1 count source
• Timer 3 interrupt
• Timer LC count source
• LCD clock
• System reset (count twice)
• WDF flag decision Frequency dividing ratio 1 to 256 1 to 256 1 to 256 8192 16384 32768 65536 1 to 16 65534 Control register PA Table 9 Function related timers

Rev.3.02 Dec 22, 2006 page 30 of 142 REJ03B0025-0302 Fig. 22 Timer structure (1) D i v i s i o n c i r c u i t S y s t e m c l o c k S T C K XC I N I n s t r u c t i o n c l o c k I N S T C K M u l t i p l e x e r C R C K M R 1, M R 0 O R C L K R e l o a d r e g i s t e r R P S P r e s c a l e r Register B Register A T A B P S T A B P S T P S A B P M R 3, M R 2 P W M O U T R S I 12 D 5/ I N T W1 3 T U D F I10 I 13 I 11 I10 W1 1, W10 O R C L K T3UDF C/CNTR T1F T A B T A B ) ( T A B T A B T A B T P S A B T P S A B W 21 W T F On-chip oscillator XI N C e r a m i c r e s o n a n c e R C o s c i l l a t i o n T i m e r 1 ( 8 ) T i m e r 1 i n t e r r u p t Reload register R1 (8) Register BR e g i s t e r A Timer 1 underflow signal O n e - s i d e d e d g e d e t e c t i o n c i r c u i t B o t h e d g e s d e t e c t i o n c i r c u i t T A B T A B )(T2AB)( T A B ) ( T A B T i m e r 2 ( 8 ) R e l o a d r e g i s t e r R 2 L ( 8 ) R e g i s t e r B R e g i s t e r A T i m e r 2 i n t e r r u p t I n t e r n a l c l o c k g e n e r a t i n g c i r c u i t d i v i d e d b y Q u a r t z c r y s t a l o s c i l l a t i o n W1 2 W4 0 P W M O U T Q R D TW 12 T U D F W 41 P o r t C o u t p u t XI N O R C L K Reload register R2H (8) T H A B R e g i s t e r B R e g i s t e r A R e l o a d c o n t r o l c i r c u i t “ H ” i n t e r v a l e x p a n s i o n W Q R T P W M O D W2 3 T R L D i v i d e d b y D i v i d e d b y D i v i d e d b y W 10 W 11 T U D F Data is set automatically from each reload register when timer underflows (auto-reload function).

Rev.3.02 Dec 22, 2006 page 31 of 142 REJ03B0025-0302 Fig. 23 Timer structure (2) W W3 1, W30 T F T L C A (TLCA) Timer 3 interrupt Timer 3 underflow signal (T3UDF) Timer LC (4) R e l o a d r e g i s t e r R L C ( 4 ) Register A L C D c l o c k W 43 STCK T i m e r W 32 XC I N W a t c h d o g t i m e rI N T S N C Q R S WDF1 WRST instruction Q R S WEF DWDT instruction WRST instruction RESET signal Q T D R RESET signal W a t c h d o g r e s e t s i g n a l W O R C L K (Note) Notes: The WEF flag is set to “1” at system reset or RAM back-up mode. D a t a i s s e t a u t o m a t i c a l l y f r o m e a c h r e l o a d r e g i s t e r w h e n t i m e r u n d e r f l o w s a u t o r e l o a d f u n c t i o n

Rev.3.02 Dec 22, 2006 page 32 of 142 REJ03B0025-0302 Table 10 Timer related registers CNTR pin output invalid CNTR pin output valid PWM signal “H ” interval expansion function invalid PWM signal “H ” interval expansion function valid Stop (state retained) Operating X IN input Prescaler output (ORCLK)/2 signal output CNTR pin output control bit PWM signal interrupt valid waveform/ return level selection bit Timer 2 control bit Timer 2 count soruce selection bit Timer control register W2 at power down : 0000 2at reset : 00002 Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”). 3: Port C output is invalid when CNTR input is selected for the timer 1 count source. W2 3 W2 2 W2 1 W2 0 W1 1 Timer 1 count auto-stop circuit not selected Timer 1 count auto-stop circuit selected Stop (state retained) Operating Count source PWM signal (PWMOUT) Prescaler output (ORCLK) Timer 3 underflow signal (T3UDF) CNTR input Timer 1 count auto-stop circuit selection bit (Note 2) Timer 1 control bit Timer 1 count source selection bits (Note 3) Timer control register W1 R/W TAW1/TW1Aat power down : state retainedat reset : 00002 W1 3 W1 2 W1 1 W1 0 W3 1 X CIN input Prescaler output (ORCLK) Stop (Initial state) Operating Count value Underflow occurs every 8192 counts Underflow occurs every 16384 counts Underflow occurs every 32768 counts Underflow occurs every 65536 counts Timer 3 count auto-stop circuit selection bit Timer 3 control bit Timer 3 count value selection bits Timer control register W3 at power down : state retainedat reset : 00002 W3 3 W3 2 W3 1 W3 0 R/W TAW2/TW2A R/W TAW3/TW3A Stop (state retained) Operating Prescaler control bit Timer control register PA W TPAAat power down : 02at reset : 02 PA 0 Stop (state retained) Operating Bit 4 (T3 4) of timer 3 System clock (STCK) CNTR output auto-control circuit not selected CNTR output auto-control circuit selected Falling edge Rising edge Timer LC control bit Timer LC count source selection bit CNTR output auto-control circuit selection bit CNTR pin input count edge selection bit Timer control register W4 at power down : state retainedat reset : 00002 W4 3 W4 2 W4 1 W4 0 R/W TAW4/TW4A

Rev.3.02 Dec 22, 2006 page 33 of 142 REJ03B0025-0302 (1) Timer control registers

• Timer control register PA Register PA controls the count operation of prescaler. Set the contents of this register through register A with the TPAA instruc- tion.
• Timer control register W1 Register W1 controls the selection of timer 1 count auto-stop cir- cuit, and the count operation and count source of timer 1. Set the contents of this register through register A with the TW1A instruc- tion. The TAW1 instruction can be used to transfer the contents of register W1 to register A.
• Timer control register W2 Register W2 controls the CNTR output, the expansion of “H ” in- terval of PWM output, and the count operation and count source of timer 2. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to trans- fer the contents of register W2 to register A.
• Timer control register W3 Register W3 controls the count operation and count source of timer 3. Set the contents of this register through register A with the TW5A instruction. The TAW3 instruction can be used to trans- fer the contents of register W3 to register A.
• Timer control register W4 Register W4 controls the operation and count source of timer LC, the selection of CNTR output auto-control circuit and the count edge of CNTR input. Set the contents of this register through reg- ister A with the TW4A instruction. The TAW4 instruction can be used to transfer the contents of register W4 to register A.. (2) Prescaler (interrupt function) Prescaler is an 8-bit binary down counter with the prescaler reload register RPS. Data can be set simultaneously in prescaler and the reload register RPS with the TPSAB instruction. Data can be read from reload register RPS with the TABPS instruction. Stop counting and then execute the TPSAB or TABPS instruction to read or set prescaler data. Prescaler starts counting after the following process; ➀ set data in prescaler, and ➁ set the bit 0 of register PA to “1.” When a value set in reload register RPS is n, prescaler divides the count source signal by n + 1 (n = 0 to 255). Count source for prescaler is the instruction clock (INSTCK). Once count is started, when prescaler underflows (the next count pulse is input after the contents of prescaler becomes “0”), new data is loaded from reload register RPS, and count continues (auto-reload function). The output signal (ORCLK) of prescaler can be used for timer 1, 2, and 3 count sources. (3) Timer 1 (interrupt function) Timer 1 is an 8-bit binary down counter with the timer 1 reload reg- ister (R1). Data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. Data can be written to re- load register (R1) with the TR1AB instruction. Data can be read from timer 1 with the TAB1 instruction. Stop counting and then execute the T1AB or TAB1 instruction to read or set timer 1 data. When executing the TR1AB instruction to set data to reload regis- ter R1 while timer 1 is operating, avoid a timing when timer 1 underflows. Timer 1 starts counting after the following process; ➀ set data in timer 1 ➁ set count source by bits 0 and 1 of register W1, and ➂ set the bit 2 of register W1 to “1.” When a value set in reload register R1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes “0”), the timer 1 interrupt request flag (T1F) is set to “1,” new data is loaded from reload register R1, and count continues (auto-reload function). INT pin input can be used as the start trigger for timer 1 count op- eration by setting the bit 0 of register I1 to “1.” Also, in this time, the auto-stop function by timer 1 underflow can be performed by setting the bit 3 of register W1 to “1.”

Rev.3.02 Dec 22, 2006 page 34 of 142 REJ03B0025-0302 (4) Timer 2 (interrupt function) Timer 2 is an 8-bit binary down counter with two timer 2 reload reg- isters (R2L, R2H). Data can be set simultaneously in timer 2 and the reload register R2L with the T2AB instruction. Data can be set in the reload register R2H with the T2HAB instruction. The contents of reload register R2L set with the T2AB instruction can be set to timer 2 again with the T2R2L instruction. Data can be read from timer 2 with the TAB2 instruction. Stop counting and then execute the T2AB or TAB2 instruction to read or set timer 2 data. When executing the T2HAB instruction to set data to reload regis- ter R2H while timer 2 is operating, avoid a timing when timer 2 underflows. Timer 2 starts counting after the following process; ➀ set data in timer 2 ➁ set count source by bit 0 of register W2, and ➂ set the bit 1 of register W2 to “1.” When a value set in reload register R2L is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes “0”), the timer 2 interrupt request flag (T2F) is set to “1,” new data is loaded from reload register R2L, and count continues (auto-reload function). When bit 3 of register W2 is set to “1”, timer 2 reloads data from re- load register R2L and R2H alternately each underflow. Timer 2 generates the PWM signal (PWMOUT) of the “L” interval set as reload register R2L, and the “H ” interval set as reload regis- ter R2H. The PWM signal (PWMOUT) is output from CNTR pin. When bit 2 of register W2 is set to “1” at this time, the interval (PWM signal “H ” interval) set to reload register R2H for the counter of timer 2 is extended for a half period of count source. In this case, when a value set in reload register R2H is n, timer 2 divides the count source signal by n + 1.5 (n = 1 to 255). When this function is used, set “1” or more to reload register R2H. When bit 1 of register W4 is set to “1”, the PWM signal output to CNTR pin is switched to valid/invalid each timer 1 underflow. How- ever, when timer 1 is stopped (bit 2 of register W1 is cleared to “0”), this function is canceled. Even when bit 1 of a register W2 is cleared to “0” in the “H ” interval of PWM signal, timer 2 does not stop until it next timer 2 underflow. When clearing bit 1 of register W2 to “0” to stop timer 2, avoid a timing when timer 2 underflows. (5) Timer 3 (interrupt function) Timer 3 is a 16-bit binary down counter. Timer 3 starts counting after the following process; ➀ set count value by bits 0 and 1 of register W3, ➁ set count source by bit 3 of register W3, and ➂ set the bit 2 of register W3 to “1.” Once count is started, when timer 3 underflows (the set count value is counted), the timer 3 interrupt request flag (T3F) is set to “1,” and count continues. Bit 4 of timer 3 can be used as the timer LC count source for the LCD clock generating. When bit 2 of register W3 is cleared to “0”, timer 3 is initialized to “FFFF 16” and count is stopped. Timer 3 can be used as the counter for clock because it can be op- erated at clock operating mode (POF instruction execution). When timer 3 underflow occurs at clock operating mode, system returns from the power down state. When operating timer 3 during clock operating mode, set 1 cycle or more of count source to the following period; from setting bit 2 of register W3 to “1” till executing the POF instruction. (6) Timer LC Timer LC is a 4-bit binary down counter with the timer LC reload register (RLC). Data can be set simultaneously in timer LC and the reload register (RLC) with the TLCA instruction. Data cannot be read from timer LC. Stop counting and then execute the TLCA in- struction to set timer LC data. Timer LC starts counting after the following process; ➀ set data in timer LC, ➁ select the count source with the bit 2 of register W4, and ➂ set the bit 3 of register W4 to “1.” When a value set in reload register RLC is n, timer LC divides the count source signal by n + 1 (n = 0 to 15). Once count is started, when timer LC underflows (the next count pulse is input after the contents of timer LC becomes “0”), new data is loaded from reload register RLC, and count continues (auto-re- load function). Timer LC underflow signal divided by 2 can be used for the LCD clock.

Rev.3.02 Dec 22, 2006 page 35 of 142 REJ03B0025-0302 (7) Timer input/output pin (C/CNTR pin) CNTR pin is used to input the timer 1 count source and output the PWM signal generated by timer 2. When the PWM signal is output from C/CNTR pin, set “0” to the output latch of port C. The selection of CNTR output signal can be controlled by bit 3 of register W2. When the CNTR input is selected for timer 1 count source, timer 1 counts the waveform of CNTR input selected by bit 0 of register W4. Also, when the CNTR input is selected, the output of port C is invalid (high-impedance state). (8) Timer interrupt request flags (T1F, T2F, T3F) Each timer interrupt request flag is set to “1” when each timer underflows. The state of these flags can be examined with the skip instructions (SNZT1, SNZT2, SNZT3). Use the interrupt control register V1, V2 to select an interrupt or a skip instruction. An interrupt request flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with a skip instruction. (9) Count start synchronization circuit (timer 1) Timer 1 has the count start synchronous circuit which synchronizes the input of INT pin, and can start the timer count operation. Timer 1 count start synchronous circuit function is selected by set- ting the bit 0 of register I1 to “1” and the control by INT pin input can be performed. When timer 1 count start synchronous circuit is used, the count start synchronous circuit is set, the count source is input to each timer by inputting valid waveform to INT pin. The valid waveform of INT pin to set the count start synchronous circuit is the same as the external interrupt activated condition. Once set, the count start synchronous circuit is cleared by clearing the bit I1 0 to “0” or reset. However, when the count auto-stop circuit is selected, the count start synchronous circuit is cleared (auto-stop) at the timer 1 under- flow. (10) Count auto-stop circuit (timer 1) Timer 1 has the count auto-stop circuit which is used to stop timer 1 automatically by the timer 1 underflow when the count start syn- chronous circuit is used. The count auto-stop cicuit is valid by setting the bit 3 of register W1 to “1”. It is cleared by the timer 1 underflow and the count source to timer 1 is stopped. This function is valid only when the timer 1 count start synchronous circuit is selected. (11) Precautions Note the following for the use of timers.

• Prescaler Stop counting and then execute the TABPS instruction to read from prescaler data. Stop counting and then execute the TPSAB instruction to set prescaler data.
• Timer count source Stop timer 1, 2, and LC counting to change its count source.
• Reading the count value Stop timer 1 or 2 counting and then execute the data read in- struction (TAB1, TAB2) to read its data.
• Writing to the timer Stop timer 1, 2 or LC counting and then execute the data write in- struction (T1AB, T2AB, TLCA) to write its data.
• Writing to reload register R1, R2H When writing data to reload register R1 or reload regiser R2H while timer 1 or timer 2 is operating, avoid a timing when timer 1 or timer 2 underflows.
• Timer 2 Avoid a timing when timer 2 underflows to stop timer 2 at PWM output function used. When “H ” interval extension function of the PWM signal is set to be “valid”, set “1” or more to reload register R2H.
• Timer 3 Stop timer 3 counting to change its count source.
• Timer input/output pin Set the port C output latch to “0” to output the PWM signal from C/CNTR pin.

Rev.3.02 Dec 22, 2006 page 36 of 142 REJ03B0025-0302

• Prescaler and Timer 1 count start timing and count time when op- eration starts Count starts from the first rising edge of the count source (2) af- ter Prescaler and Timer 1 operations start (1). Time to first underflow (3) is shorter (for up to 1 period of the count source) than time among next underflow (4) by the timing to start the timer and count source operations after count starts. When selecting CNTR input as the count source of Timer 1, Timer 1 operates synchronizing with the falling edge of CNTR in- put. Fig. 24 Timer count start timing and count time when opera- tion starts (Prescaler and Timer 1)
• Timer 2 and Timer LC count start timing and count time when op- eration starts Count starts from the rising edge (2) after the first falling edge of the count source, after Timer 2 and Timer LC operations start (1). Time to first underflow (3) is different from time among next un- derflow (4) by the timing to start the timer and count source operations after count starts. Fig. 25 Timer count start timing and count time when opera- tion starts (Timer 2 and Timer LC) (1) Timer Start Count Source Timer Value Timer Underflow signal 3 21032103 (4)(3) (2) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Count Source Selecting CNTR input falling edge (1) Timer Start Count Source Timer Value Timer Underflow Signal 3 21032103 (4)(3) (2) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

Rev.3.02 Dec 22, 2006 page 37 of 142 REJ03B0025-0302 Fig. 26 Timer 2 operation (reload register R2L: “0316”, R2H: “0216”) G CNTR output: invalid (W23 = “0”) Timer 2 count source Timer 2 count value (Reload register) 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 00160316 (R2L) Timer 2 underflow signal PWM signal (output invalid) Timer 2 start PWM signal “L” fixed 02160316 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 (R2H) PWM period 7 clock PWM period 7 clock 0316 0116 00160216 0216 0116 0016 0216 0116 00160316 0216 0116 0016 0216 0116 00160316 0216 (R2L) (R2H) (R2L) (R2H) (R2L) (R2H) PWM period 7.5 clock PWM period 7.5 clock G CNTR output: valid (W23 = “1”) PWM signal “H ” interval extension function: invalid (W22 = “0”) Timer 2 count source Timer 2 count value (Reload register) Timer 2 underflow signal PWM signal Timer 2 count source Timer 2 count value (Reload register) Timer 2 underflow signal PWM signal Timer 2 start Timer 2 start G CNTR output: valid (W23 = “1”) PWM signal “H ” interval extension function: valid (W22 = “1”) (Note) Note: At PWM signal “H ” interval extension function: valid, set “0116” or more to reload register R2H. (R2L) (R2H) (R2L) (R2H) (R2L) (R2L) (R2L) (R2L)(R2L) 3 clock 3 clock 3.5 clock3.5 clock

Rev.3.02 Dec 22, 2006 page 38 of 142 REJ03B0025-0302 Fig. 27 CNTR output auto-control function by timer 1 CNTR output auto-control circuit by timer 1 is selected. CNTR output Register W41 When the CNTR output auto-control function is set to be invalid while the CNTR output is invalid, the CNTR output invalid state is retained. When the CNTR output auto-control function is set to be invalid while the CNTR output is valid, the CNTR output valid state is retained. When timer 1 is stopped, the CNTR output auto-control function becomes invalid. Note: When the PWM signal is output from C/CNTR pin, set the output latch of port C to “0”. G CNTR output: valid (W2 3 = “1”) CNTR output auto-control circuit selected (W41 = “1”) Timer 1 underflow signal PWM signal Timer 1 start CNTR output start G CNTR output auto-control function CNTR output Timer 1 underflow signal PWM signal Timer 1 start CNTR output start Timer 1 stop CNTR output stop ➀ ➁

Rev.3.02 Dec 22, 2006 page 39 of 142 REJ03B0025-0302 Fig. 28 Timer 2 count start/stop timing (R2L) (R2H) (R2L) Timer 2 count start timing Waveform extension function of CNTR output “H ” interval: Invalid (W22 = “0”), CNTR output: valid (W23 = “1”), Count source: XIN input selected (W20 = “0”), Reload register R2L: “0316” Reload register R2H: “0216” Timer 2 count start timing TW2A instruction execution cycle (W21) ← 1 0216 0116 0016 021603160216 0116 00160316 021600160016 0216 0116 0016 0316 0216 01160216 (R2H)(R2L) 0116 (R2H) (Note 1) Notes 1: In order to stop timer 2 at CNTR output valid (W23 = “1”), avoid a timing when timer 2 underflows. If these timings overlap, a hazard may occur in a CNTR output waveform. 2: At CNTR output valid, timer 2 stops after “H ” interval of PWM signal set by reload register R2H is output. Mi Mi+1 Mi+2 Mi Mi+1 Mi+2 0116Timer 2 count value (Reload register) Timer 2 underflow signal PWM signal Machine cycle XIN input (count source selected) System clock f(STCK)=f(XIN)/4 Register W21 G Timer 2 count stop timing TW2A instruction execution cycle (W21) ← 0 Timer 2 count stop timing Timer 2 count value (Reload register) Timer 2 underflow signal PWM signal Machine cycle XIN input (count source selected) System clock f(STCK)=f(XIN)/4 Register W21

Rev.3.02 Dec 22, 2006 page 40 of 142 REJ03B0025-0302 Watchdog timer provides a method to reset the system when a pro- gram run-away occurs. Watchdog timer consists of timer WDT(16-bit binary counter), watchdog timer enable flag (WEF), and watchdog timer flags (WDF1, WDF2). The timer WDT downcounts the instruction clocks as the count source from “FFFF 16” after system is released from reset. After the count is started, when the timer WDT underflow occurs (after the count value of timer WDT reaches “0000 16,” the next count pulse is input), the WDF1 flag is set to “1.” If the WRST instruction is never executed until the timer WDT un- derflow occurs (until timer WDT counts 65534), WDF2 flag is set to “1,” and the RESET pin outputs “L” level to reset the microcom- puter. Execute the WRST instruction at each period of 65534 machine cycle or less by software when using watchdog timer to keep the microcomputer operating normally. When the WEF flag is set to “1” after system is released from reset, the watchdog timer function is valid. When the DWDT instruction and the WRST instruction are ex- ecuted continuously, the WEF flag is cleared to “0” and the watchdog timer function is invalid. The WEF flag is set to "1" at system reset or RAM back-up mode. The WRST instruction has the skip function. When the WRST in- struction is executed while the WDF1 flag is “1”, the WDF1 flag is cleared to “0” and the next instruction is skipped. When the WRST instruction is executed while the WDF1 flag is “0”, the next instruction is not skipped. The skip function of the WRST instruction can be used even when the watchdog timer function is invalid. Fig. 29 Watchdog timer function c o u n t N o t e V a l u e o f b i t t i m e r W D T W D F f l a g W R S T i n s t r u c t i o n e x e c u t e d s k i p e x e c u t e d R E S E T p i n o u t p u t WDF2 flag ➄ System reset➀ Reset released A f t e r s y s t e m i s r e l e a s e d f r o m r e s e t a f t e r p r o g r a m i s s t a r t e d t i m e r W D T s t a r t s c o u n t d o w n W h e n t i m e r W D T u n d e r f l o w o c c u r s W D F f l a g i s s e t t o W h e n t h e W R S T i n s t r u c t i o n i s e x e c u t e d W D F f l a g i s c l e a r e d t o t h e n e x t i n s t r u c t i o n i s s k i p p e d W h e n t i m e r W D T u n d e r f l o w o c c u r s w h i l e W D F f l a g i s W D F f l a g i s s e t t o a n d t h e w a t c h d o g r e s e t s i g n a l i s o u t p u t T h e o u t p u t t r a n s i s t o r o f R E S E T p i n i s t u r n e d O N b y t h e w a t c h d o g r e s e t s i g n a l a n d s y s t e m r e s e t i s e x e c u t e d N o t e T h e n u m b e r o f c o u n t i s e q u a l t o t h e n u m b e r o f c y c l e b e c a u s e t h e c o u n t s o u r c e o f w a t c h d o g t i m e r i s t h e i n s t r u c t i o n c l o c k F F F 000016 ➁ ➁

Rev.3.02 Dec 22, 2006 page 41 of 142 REJ03B0025-0302 Fig. 30 Program example to start/stop watchdog timer Fig. 31 Program example to enter the mode when using the watchdog timer WRST ; WDF1 flag cleared NOP DI ; Interrupt disabled EPOF ; POF instruction enabled POF Oscillation stop

• ••
• •• When the watchdog timer is used, clear the WDF1 flag at the pe- riod of 65534 machine cycles or less with the WRST instruction. When the watchdog timer is not used, execute the DWDT instruc- tion and the WRST instruction continuously (refer to Figure 30). The watchdog timer is not stopped with only the DWDT instruction. The contents of WDF1 flag and timer WDT are initialized at the power down mode. When using the watchdog timer and the power down mode, initial- ize the WDF1 flag with the WRST instruction just before the microcomputer enters the power down state (refer to Figure 31). The watchdog timer function is valid after system is returned from the power down. When not using the watchdog timer function, ex- ecute the DWDT instruction and the WRST instruction continuously every system is returned from the power down, and stop the watch- dog timer function. WRST ; WDF1 flag cleared DI DWDT ; Wat chdog timer function enabled/disabled WRST ; WEF and WDF1 flags cleared
• ••

Rev.3.02 Dec 22, 2006 page 42 of 142 REJ03B0025-0302 The 4556 Group has an LCD (Liquid Crystal Display) controller/ driver. When the proper voltage is applied to LCD power supply in- put pins (VLC1 –V LC3 ) and data are set in timer control register (W4), timer LC, LCD control registers (L1, L2, L3, C1, C2), and LCD RAM, the LCD controller/driver automatically reads the dis- play data and controls the LCD display by setting duty and bias. 4 common signal output pins and 23 segment signal output pins can be used to drive the LCD. By using these pins, up to 92 seg- ments (when 1/4 duty and 1/3 bias are selected) can be controlled to display. The LCD power input pins (V LC1 –VLC3 ) are also used as pins SEG0–SEG 2. When SEG 0–SEG 2 are selected, the internal power (VDD ) is used for the LCD power. (1) Duty and bias There are 3 combinations of duty and bias for displaying data on the LCD. Use bits 0 and 1 of LCD control register (L1) to select the proper display method for the LCD panel being used.

• 1/2 duty, 1/2 bias
• 1/3 duty, 1/3 bias
• 1/4 duty, 1/3 bias Table 11 Duty and maximum number of displayed pixels (2) LCD clock control The LCD clock is determined by the timer LC count source selec- tion bit (W42), timer LC control bit (W43), and timer LC. Accordingly, the frequency (F) of the LCD clock is obtained by the following formula. Numbers (➀ to ➂ ) shown below the formula cor- respond to numbers in Figure 32, respectively.
• When using the prescaler output (ORCLK) as timer LC count source (W42=“1”) F = ORCLK ✕✕
• When using the bit 4 of timer 3 as timer LC count source (W42=“0”) F = T3 4 ✕✕ [LC: 0 to 15] The frame frequency and frame period for each display method can be obtained by the following formula: Frame frequency = (Hz) Frame period = (s) F: LCD clock frequency 1/n: Duty Fig. 32 LCD clock control circuit structure Duty Used COM pins COM 0, COM 1 (Note) COM 0–COM 2 (Note) COM 0–COM 3 Maximum number of displayed pixels 46 segments 69 segments 92 segments Note: Leave unused COM pins open. LC + 1 ➀➁ ➂ LC + 1 ➀➁ ➂ F n n F Note: Count source is stopped by setting “0” to this bit. Timer LC 1/2 W4 3 (Note) T34 W4 2 1STCK LCD clock(4) Reload register RLC (4) Register A (TLCA ) (TLCA ) ➁ ➂

Rev.3.02 Dec 22, 2006 page 43 of 142 REJ03B0025-0302 Fig. 33 LCD controller/driver Common driver Bias control Multiplexer Selector RA M Segment driver Selector RAM COM 3 COM 2 COM 1 COM 0 Decoder SEG 28 1/2,1/3,1/4 counter LCD clock (from timer block) L10L11L12L13 Register A LCD ON/ OFF control Control signal SEG 0/VLC 3 SEG 17 ... ... Segment driver ... SEG 1 /VLC2 SEG 2/VLC1 SEG 0 to SEG2 output L20L21L22L23 r r r r r r to SEG 10SEG 3 to (3) LCD RAM RAM contains areas corresponding to the liquid crystal display. When “1” is written to this LCD RAM, the display pixel correspond- ing to the bit is automatically displayed. (4) LCD drive waveform When “1” is written to a bit in the LCD RAM data, the voltage differ- ence between common pin and segment pin which correspond to the bit automatically becomes lVLC3 l and the display pixel at the cross section turns on. When returning from reset, and in the RAM back-up mode, a dis- play pixel turns off because every segment output pin and common output pin becomes V LC3 level. Fig. 34 LCD RAM map Z X Y Bits CO M 3 210 3 210 3 210 SEG 1 SEG 2 SEG 3 SEG 4 SEG 5 SEG 6 SEG 7 COM 3 SEG 1 SEG 2 SEG 3 SEG 4 SEG 5 SEG 6 SEG 7 COM 2 SEG 1 SEG 2 SEG 3 SEG 4 SEG 5 SEG 6 SEG 7 COM 1 SEG 1 SEG 2 SEG 3 SEG 4 SEG 5 SEG 6 SEG 7 COM 0 SEG 9 SEG 10 COM 3 COM 2 COM 1 COM 0 COM 3 COM 2 COM 1 COM 0 SEG 9 SEG 10 SEG 9 SEG 10 SEG 0 SEG 0 SEG 0 SEG 0 SEG 8 SEG 17 SEG 18 SEG 19 SEG 8 SEG 8 SEG 8 SEG 9 SEG 10 SEG 17 SEG 18 SEG 19 SEG 17 SEG 18 SEG 19 SEG 17 SEG 18 SEG 19 0 1 Note: The area marked “ ” is not the LCD display RAM. SEG 21 SEG 22 SEG 23 SEG 20 3 210 COM 3 COM 2 COM 1 COM 0 SEG 25 SEG 26 SEG 27 SEG 24 SEG 28 SEG 21 SEG 22 SEG 23 SEG 20 SEG 21 SEG 22 SEG 23 SEG 20 SEG 21 SEG 22 SEG 23 SEG 20 SEG 25 SEG 26 SEG 27 SEG 24 SEG 28 SEG 25 SEG 26 SEG 27 SEG 24 SEG 28 SEG 25 SEG 26 SEG 27 SEG 24 SEG 28

Rev.3.02 Dec 22, 2006 page 44 of 142 REJ03B0025-0302 Table 12 LCD control registers (1) Internal dividing resistor for LCD power supply selection bit (Note 2) LCD control bit LCD control register L1 L13 L12 L11 L10 at reset : 00002 at power down : state retained Duty Bias LCD control register L2 at reset : 0000 2 at power down : state retained W TL2A SEG VLC3 SEG 1 VLC2 SEG 2 VLC1 Internal dividing resistor valid Internal dividing resistor invalid L23 L22 L21 L20 SEG 0/VLC3 pin function switch bit (Note 3) SEG 1/VLC2 pin function switch bit (Note 4) SEG 2/VLC1 pin function switch bit (Note 4) Internal dividing resistor for LCD power supply control bit 2r ✕ 3, 2r ✕ 2 r ✕ 3, r ✕ 2 Stop Operating Not available LCD control register L3 at reset : 1111 2 at power down : state retained W TL3A SEG P23 SEG 19 P22 SEG 18 P21 SEG 17 P20 L33 L32 L31 L30 P23/SEG 20 pin function switch bit P22/SEG 19 pin function switch bit P21/SEG 18 pin function switch bit P20/SEG 17 pin function switch bit R/W TAL1/TL1A LCD duty and bias selection bits Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: “r (resistor) multiplied by 3” is used at 1/3 bias, and “r multiplied by 2” is used at 1/2 bias. 3: VLC3 is connected to VDD internally when SEG0 pin is selected. 4: Use internal dividing resistor when SEG1 and SEG2 pins are selected.

Rev.3.02 Dec 22, 2006 page 45 of 142 REJ03B0025-0302 Note: “R ” represents read enabled, and “W ” represents write enabled. LCD control register C1 at reset : 11112 at power down : state retained W TC1A SEG P03 SEG 23 P02 SEG 22 P01 SEG 21 P00 C1 3 C1 2 C11 C1 0 P03/SEG 24 pin function switch bit P02/SEG 23 pin function switch bit P01/SEG 22 pin function switch bit P00/SEG 21 pin function switch bit LCD control register C2 at reset : 11112 at power down : state retained W TC2A SEG P13 SEG 27 P12 SEG 26 P11 SEG 25 P10 C2 3 C2 2 C2 1 C2 0 P13/SEG 28 pin function switch bit P12/SEG 27 pin function switch bit P11/SEG 26 pin function switch bit P10/SEG 25 pin function switch bit Table 12 LCD control registers (2)

Rev.3.02 Dec 22, 2006 page 46 of 142 REJ03B0025-0302 Fig. 35 LCD controller/driver structure COM 1 COM 0 SEG 17 VLC 3 VLC 1=VLC 2 VSS VLC 3 VLC 1=VLC 2 VSS 1 flame (2/F) 1/F ON OFF Voltage level (bit 0)COM 0 COM 1 SEG 17 X X (bit 3) M (1, 2, 9) COM 1 SEG 17 COM 0 SEG 17 1 flame (3/F) 1/F ON OFF ON COM 2 VLC 3 VLC 2 VLC 1 VSS COM 1 COM 0 SEG 17 VLC 3 VLC 2 VLC 1 VSS Voltage level (bit 0)COM 0 COM 1 COM 2 SEG 17 X (bit 3) M (1, 2, 9) COM 2 SEG 17 COM 1 SEG 17 COM 0 SEG 17 1 flame (4/F) 1/F ON OFF COM 3 COM 2 COM 1 COM 0 SEG 17 VLC 3 VLC 2 VLC 1 VSS VLC 3 VLC 2 VLC 1 VSS Voltage level (bit 0)COM 0 COM 1 COM 2 COM 3 SEG 17 1 (bit 3) M (1, 2, 9) COM 3 SEG 17 COM 2 SEG 17 COM 1 SEG 17 COM 0 SEG 17 F : LCD clock frequency X: Set an arbitrary value. (These bits are not related to set the drive waveform at each duty.) ON OFF 1/2 Duty, 1/2 Bias: When writing (XX10)2 to address M (1, 2, 9) in RAM. 1/3 Duty, 1/3 Bias: When writing (X101)2 to address M (1, 2, 9) in RAM. 1/4 Duty, 1/3 Bias: When writing (1010)2 to address M (1, 2, 9) in RAM.

Rev.3.02 Dec 22, 2006 page 47 of 142 REJ03B0025-0302 (5) LCD power supply circuit Select the LCD power supply circuit suitable for the using LCD panel. The LCD power supply circuit is fixed by the followings;

• The internal dividing resistor is controlled by bit 0 of register L2.
• The internal dividing resistor is selected by bit 3 of register L1.
• The bias condition is selected by bits 0 and 1 of register L1. G Internal dividing resistor The 4556 Group has the internal dividing resistor for LCD power supply. When bit 0 of register L2 is set to “0”, the internal dividing resis- tor is valid. However, when the LCD is turned off by setting bit 2 of register L1 to “0”, the internal dividing resistor is turned off. The same six resistor (r) is prepared for the internal dividing re- sistor. According to the setting value of bit 3 of register L1 and using bias condition, the resistor is prepared as follows;
• L1 3 = “0”, 1/3 bias used: 2r ✕ 3 = 6r
• L13 = “0”, 1/2 bias used: 2r ✕ 2 = 4r
• L13 = “1”, 1/3 bias used: r ✕ 3 = 3r
• L13 = “1”, 1/2 bias used: r ✕ 2 = 2r G VLC3 /SEG 0 pin The selection of VLC3 /SEG 0 pin function is controlled with the bit 3 of register L2. When the VLC3 pin function is selected, apply voltage of VLC3 < VDD to the pin externally. When the SEG 0 pin function is selected, VLC3 is connected to VDD internally. G VLC2 /SEG 1, VLC1 /SEG 2 pin The selection of VLC2 /SEG 1 pin function is controlled with the bit 2 of register L2. The selection of V LC1 /SEG 2 pin function is controlled with the bit 1 of register L2. When the V LC2 pin and VLC1 pin functions are selected and the internal dividing resistor is not used, apply voltage of 0<V LC1 <V LC2 <V LC3 to these pins. Short the VLC2 pin and VLC1 pin at 1/2 bias. When the VLC2 pin and VLC1 pin functions are selected and the internal dividing resistor is used, the dividing voltage value gen- erated internally is output from the V LC1 pin and VLC2 pin. The VLC2 pin and VLC1 pin have the same electric potential at 1/2 bias. When SEG 1 and SEG2 pin functions are selected, use the inter- nal dividing resistor. In this time, VLC2 and VLC1 are connected to the generated dividingg voltage. Fig. 36 LCD power supply circuit example (1/3 bias condition selected) VLC3 VLC2 VLC1 SEG 0 SEG 1 SEG 2 VLC3 VLC2 VLC1 VLC3 SEG 1 SEG 2 a) Register L2=(0000)2 b) Register L2=(1000)2 VLC3 VLC2 VLC1 VLC3 VLC2 VLC1 VLC3 VLC2 VLC1 c) Register L2=(1110)2 d) Register L2=(1111)2 VLC3 VLC2 VLC1

Rev.3.02 Dec 22, 2006 page 48 of 142 REJ03B0025-0302 System reset is performed by applying “L” level to RESET pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions. Then when “H ” level is applied to RESET pin, software starts from address 0 in page 0. Fig. 37 Reset release timing Fig. 38 RESET pin input waveform and reset operation R E S E T VD D 0.85VDD (Note) N o t e K e e p t h e v a l u e o f s u p p l y v o l t a g e t o t h e m i n i m u m v a l u e o r m o r e o f t h e r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s R e s e t i n p u t m a c h i n e c y c l e o r m o r e Program starts (address 0 in page 0) On-chip oscillator (internal oscillator) is counted 1376 times. RESET Program starts (address 0 in page 0) On-chip oscillator (internal oscillator) is counted 1376 times. f(RING) Note: The number of clock cycles depends on the internal state of the microcomputer when reset is performed.

Rev.3.02 Dec 22, 2006 page 49 of 142 REJ03B0025-0302 Fig. 39 Structure of reset pin and its peripherals,, and power-on reset operation Name D 0–D 4 D 5/INT XCIN/D6, XCOUT /D7 P00/SEG 21–P03/SEG 24 P10/SEG 25–P13/SEG 28 P20/SEG 17–P23/SEG 20 SEG 0/VLC3 –SEG 2/VLC1 SEG 3–SEG 10 COM 0–COM 3 C/CNTR Notes 1: Output latch is set to “1.” 2: Output structure is N-channel open-drain. 3: Pull-up transistor is turned OFF. Function D 0–D 4 D 5 XCIN, XCOUT P00–P03 P10–P13 P20–P23 SEG 0–SEG 2 SEG 3–SEG 10 COM 0–COM 3 C State High-impedance (Notes 1, 2) High-impedance (Notes 1, 2) Sub-clock input High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2, 3) V LC3 (VDD ) level VLC3 (VDD ) level VLC3 (VDD ) level “L” (VSS ) level (1) Power-on reset Reset can be automatically performed at power on (power-on re- set) by the built-in power-on reset circuit. When the built-in power-on reset circuit is used, set the time for the supply voltage to rise from 0 V to the minimum voltage of recommended operating conditions to 100 µs or less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and V SS at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage. Table 13 Port state at reset R E S E T p i n W SRST instruction Voltage drop detection circuit (only for H version) E F (Note 1) P u l l u p t r a n s i s t o r N o t e Power-on reset circuit VDD (Note 3)100 µs or less N o t e I n t e r n a l r e s e t s i g n a l Power-on Reset released Internal reset signal Reset state Notes 1: This symbol represents a parasitic diode. A p p l i e d p o t e n t i a l t o R E S E T p i n m u s t b e VD D o r l e s s K e e p t h e v a l u e o f s u p p l y v o l t a g e t o t h e m i n i m u m v a l u e o r m o r e o f t h e r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s Po circuit output wer-on reset Watchdog reset signal

Rev.3.02 Dec 22, 2006 page 50 of 142 REJ03B0025-0302 Address 0 in page 0 is set to program counter. Fig. 40 Internal state at reset (2) Internal state at reset Figure 40 shows internal state at reset (they are the same after sys- tem is released from reset). The contents of timers, registers, flags and RAM except shown in Figure 40 are undefined, so set the ini- tial value to them. “✕ ” represents undefined. 00000000000000 0 (Interrupt disabled) 0 0 0 0 (Interrupt disabled) 0 0 0 0 (Interrupt disabled) 0000 0 (Prescaler stopped) 0 0 0 0 (Timer 1 stopped) 0 0 0 0 (Timer 2 stopped) 0 0 0 0 (Timer 3 stopped) 0 0 0 0 (Timer LC stopped) 1100 000 0000 0000 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ✕✕✕ 0000 0000 111

Rev.3.02 Dec 22, 2006 page 51 of 142 REJ03B0025-0302 VRST (reset release voltage)+ VDD Voltage drop detection circuit Reset signal Microcomputer starts operation after on-chip oscillator (internal oscillator) clock is counted 1376 times. V RST (reset occurrence voltage) RESET pin Note: Detection voltage hysteresis of voltage drop detection circuit is 0.1 V (Typ). VOLTAGE DROP DETECTION CIRCUIT (only for H version) The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value. Fig. 41 Voltage drop detection reset circuit Fig. 42 Voltage drop detection circuit operation waveform EPOF instruction +POF instruction EPOF instruction +POF2 instruction Q S R SVDE instruction Internal reset signal Voltage drop detection circuit Reset signal VRS T Voltage drop detection circuit Internal reset signal T3F flag Key-on wakeup signa l QS R (1) SVDE instruction When the SVDE instruction is executed, the voltage drop deteciton circuit is valid even after system enters into the power down mode. The SVDE instruction can be executed only once. In order to release the execution of the SVDE instruction, the sys- tem reset is required. VDD Recommended operatng condition min.value No reset Program failure may occur. V RST + VRST – VDD Recommended operatng condition min.value V RST + VRST – → Normal operation Reset (2) Note on voltage drop detection circuit The voltage drop detection circuit detection voltage of this prod- uct is set up lower than the minimum value of the supply voltage of the recommended operating conditions. When the supply voltage of a microcomputer falls below to the minimum value of recommended operating conditions and re- goes up (ex. battery exchange of an application product), depending on the capacity value of the bypass capacitor added to the power supply pin, the following case may cause program failure (Figure 43); supply voltage does not fall below to V RST -, and its voltage re-goes up with no reset. In such a case, please design a system which supply voltage is once reduced below to V RST - and re-goes up after that. Fig. 43 VDD and VRST –

Rev.3.02 Dec 22, 2006 page 52 of 142 REJ03B0025-0302 Table 15 Functions and states retained at power down mode Function Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2) Contents of RAM Interrupt control registers V1, V2 Interrupt control register I1 Selected oscillation circuit Clock control register MR, RG Timer 1 to timer 2 functions Timer 3 function Timer LC function Watchdog timer function Timer control registers PA Timer control registers W1 to W4 LCD display function LCD control registers L1 to L3, C1, C2 Voltage drop detection circuit Port level Pull-up control registers PU0, PU1 Key-on wakeup control registers K0 to K2 Port output structure control registers FR0 to FR2 External interrupt request flag (EXF0) Timer interrupt request flags (T1F, T2F) Timer interrupt request flag (T3F) Interrupt enable flag (INTE) Watchdog timer flags (WDF1, WDF2) Watchdog timer enable flag (WEF) O O O O (Note 3) (Note 3) (Note 3) ✕ (Note 4) O (Note 5) O (Note 6) (Note 7) O O O (Note 3) (Note 3) ✕ (Note 4) ✕ (Note 4) Notes 1:“O ” represents that the function can be retained, and “✕ ” repre- sents that the function is initialized. Registers and flags other than the above are undefined at RAM back-up, and set an initial value after returning. 2: The stack pointer (SP) points the level of the stack register and is initialized to “7” at RAM back-up. 3: The state of the timer is undefined. 4: Initialize the watchdog timer with the WRST instruction, and then go into the power down state. 5: LCD is turned off. 6: When the SVDE instruction is executed, this function is valid at power down. 7: In the RAM back-up mode, C/CNTR pin outputs “L” level. However, when the CNTR input is selected (W1 1, W10=“11”), C/ CNTR pin is in an input enabled state (output = high-impedance). Other ports retain their respective output levels. Power down mode O O O O (Note 3) O O ✕ (Note 4) O O O (Note 6) (Note 7) O O O (Note 3) O ✕ (Note 4) ✕ (Note 4) POWER DOWN FUNCTION The 4556 Group has 2-type power down functions. System enters into each power down state by executing the follow- ing instructions. When the EPOF instruction is not executed before the POF or POF2 instruction is executed, these instructions are equivalent to the NOP instruction. (1) Clock operating mode The following functions and states are retained.

• RAM
• Reset circuit
• X CIN–XCOUT oscillation
• LCD display
• Timer 3 (2) RAM back-up mode The following functions and states are retained.
• RAM
• Reset circuit (3) Warm start condition The system returns from the power down state when;
• External wakeup signal is input
• Timer 3 underflow occurs in the power down mode. In either case, the CPU starts executing the software from address 0 in page 0. In this case, the P flag is “1.” (4) Cold start condition The CPU starts executing the software from address 0 in page 0 when;
• reset pulse is input to RESET pin,
• reset by watchdog timer is performed, or
• reset by the voltage drop detection circuit is performed. In this case, the P flag is “0.” (5) Identification of the start condition Warm start or cold start can be identified by examining the state of the power down flag (P) with the SNZP instruction. The warm start condition from the clock operating mode can be identified by exam- ining the state of T3F flag. Clock operating RAM back-up

Rev.3.02 Dec 22, 2006 page 53 of 142 REJ03B0025-0302 (6) Return signal An external wakeup signal or timer 3 interrupt request flag (T3F) is used to return from the clock operating mode. An external wakeup signal is used to return from the RAM back-up mode because the oscillation is stopped. Table 16 shows the return condition for each return source. (7) Control registers

• Key-on wakeup control register K0 Register K0 controls the ports P0 and P1 key-on wakeup func- tion. Set the contents of this register through register A with the TK0A instruction. In addition, the TAK0 instruction can be used to transfer the contents of register K0 to register A.
• Key-on wakeup control register K1 Register K1 controls the return condition and the selection of valid waveform/level of port P1. Set the contents of this register through register A with the TK1A instruction. In addition, the TAK1 instruction can be used to transfer the contents of register K0 to register A.
• Key-on wakeup control register K2 Register K2 controls the INT pin key-on wakeup function and the selection of return codition. Set the contents of this register through register A with the TK2A instruction. In addition, the TAK2 instruction can be used to transfer the contents of register K2 to register A. Table 16 Return source and return condition RemarksReturn condition External wakeup signal Return source Ports P00–P03 Ports P10–P13 INT pin
• Pull-up control register PU0 Register PU0 controls the ON/OFF of the port P0 pull-up transis- tor. Set the contents of this register through register A with the TPU0A instruction. In addition, the TAPU0 instruction can be used to transfer the contents of register PU0 to register A.
• Pull-up control register PU1 Register PU1 controls the ON/OFF of the port P1 pull-up transis- tor. Set the contents of this register through register A with the TPU1A instruction. In addition, the TAPU1 instruction can be used to transfer the contents of register PU1 to register A.
• External interrupt control register I1 Register I1 controls the valid waveform of the external 0 inter- rupt, the input control of INT pin and the return input level. Set the contents of this register through register A with the TI1A in- struction. In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A. Return by an external falling edge Return by an external “H ” level or “L” level input, or rising edge (“L”→“H ”) or falling edge (“H ”→“L”). Return by an external “L” level input. Return by an external “H ” level or “L” level input, or rising edge (“L”→“H ”) or falling edge (“H ”→“L”). When the return level is input, the in- terrupt request flag (EXF0) is not set. Return by timer 3 underflow or by setting T3F to “1”. It can be used in the clock operating mode. The key-on wakeup function can be selected by two port unit. The key-on wakeup function can be selected by two port unit. Select the re- turn level (“L” level or “H ” level) and return condition (return by level or edge) with register K1 according to the external state before going into the power down state. Select the return level (“L” level or “H ” level) with register I1 and return con- dition (return by level or edge) with register K2 according to the external state before going into the power down state. Clear T3F with the SNZT3 instruction before system enters into the power down state. When system enters into the power down state while T3F is “1”, system re- turns from the state immediately because it is recognized as return condition. Timer 3 interrupt request flag (T3F)

Rev.3.02 Dec 22, 2006 page 54 of 142 REJ03B0025-0302 Fig. 44 State transition Fig. 45 Set source and clear source of the P flag Fig. 46 Start condition identified example using the SNZP instruction B Operation state

• Operation source clock: f(XIN)
• Oscillation circuit: Ceramic resonator E Clock operating mode f(RING): stop f(XIN): stop f(XCIN): operating Key-on wakeup (Stabilizing time c ) POF2 instruction execution F Power down mode High-speed mode D
• Operation source clock: f(XCIN)
• Oscillation circuit: Quartz-crystal oscillation MR 1, MR0←00MR 1, MR0←10 Low-speed mode POF2 instruction execution Key-on wakeup (Stabilizing time e ) POF instruction execution Key-on wakeup (Stabilizing time e ) POF instruction execution Key-on wakeup (Stabilizing time c ) CRCK instruction no execution Operation state Stabilizing time a : Microcomputer starts its operation after counting the f(RING) to 1376 times. Stabilizing time b : Microcomputer starts its operation after counting the f(RING) to (system clock division ratio ✕ 15) times. Stabilizing time c : Microcomputer starts its operation after counting the f(XIN) to (system clock division ratio ✕ 171) times. Stabilizing time d : Microcomputer starts its operation after counting the f(XIN) to (system clock division ratio ✕ 15) times. Stabilizing time e : Microcomputer starts its operation after counting the f(XCIN) to (system clock division ratio ✕ 171) times. Reset A POF2 instruction execution Key-on wakeup (Stabilizing time b ) POF instruction execution Key-on wakeup (Stabilizing time b ) (Stabilizing time a ) Operation state
• Operation source clock: f(RING)
• Oscillation circuit: On-chip oscillator C POF2 instruction execution Key-on wakeup (Stabilizing time d ) POF instruction execution Key-on wakeup (Stabilizing time d ) Operation state
• Operation source clock: f(XIN)
• Oscillation circuit: RC oscillation f(RING): stop f(XIN): stop f(XCIN): stop CRCK instruction execution MR 1, MR0←00MR 1, MR0←01 Internal mode MR 1, MR MR 1, MR and generate the wait time until the oscillation is stabilized, and then, switch the system clock. 6: When the unoperating clock is selected as the system clock, turn it on by the clock control register RG, If the CRCK instruction is not executed, the ceramic oscillation is selected as the main clock f(XIN). 5: When the RC oscillation circuit is used, executing the CRCK instruction is required.
• Main clock (f(XIN)) and Suc-clock (f(XCIN)) are valid.
• A ceramic oscillation is selected as the main clock (f(XIN)). 4: The state after system is released from reset; 3: Continuous execution of the EPOF instruction and the POF2 instruction is required to go into the RAM back-up state. 2: Continuous execution of the EPOF instruction and the POF instruction is required to go into the clock operating state. Notes 1: Selection of the system clock by the clock control registers MR and RG is state retained at power down. The waiting time to stabilize oscillation at return can be adjustment by setting the clock control registers MR and RG before transition to the power down state. S R Q P o w e r d o w n f l a g PP O F o r P O F i n s t r u c t i o n Reset inpu t G Set source G Clear source Reset input E P O F i n s t r u c t i o n + POF or POF2 instruction E P O F i n s t r u c t i o n + Program start P = “1” Yes Warm start Cold start No T3F = “1” ?Yes No Return from timer 3 underflow Return from external wakeup signal

Rev.3.02 Dec 22, 2006 page 55 of 142 REJ03B0025-0302 Table 17 Key-on wakeup control register, pull-up control register and interrupt control register K03 K02 K01 K00 Key-on wakeup control register K0 Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Port P12, P13 key-on wakeup control bit (Note 3) Port P1 0, P11 key-on wakeup control bit (Note 2) Port P02, P03 key-on wakeup control bit Port P0 0, P01 key-on wakeup control bit at reset : 00002 at power down : state retained R/W TAK0/ TK0A Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: To be invalid (K02 = “0”) key-on wakeup of ports P10 and P11, set the registers K10 and K11 to “0”. 3: To be invalid (K03 = “0”) key-on wakeup of ports P12 and P13, set the registers K12 and K13 to “0”. K13 K12 K11 K10 Key-on wakeup control register K1 Returned by edge Returned by level Falling waveform/“L” level Rising waveform/“H ” level Returned by edge Returned by level Falling waveform/“L” level Rising waveform/“H ” level Ports P12, P13 return condition selection bit (Note 3) Ports P12, P13 valid waveform/level selection bit (Note 3) Ports P10, P11 return condition selection bit (Note 2) Ports P10, P11 valid waveform/level selection bit (Note 2) at reset : 00002 at power down : state retained K23 K22 K21 K20 Key-on wakeup control register K2 This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Returned by level Returned by edge Key-on wakeup invalid Key-on wakeup valid Not used Not used INT pin return condition selection bit INT pin key-on wakeup control bit at reset : 00002 at power down : state retained R/W TAK1/ TK1A R/W TAK2/ TK2A

Rev.3.02 Dec 22, 2006 page 56 of 142 REJ03B0025-0302 Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: When the contents of I12 and I13 are changed, the external interrupt request flag (EXF0) may be set. PU0 3 PU0 2 PU0 1 PU0 0 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Port P0 3 pull-up transistor control bit Port P0 2 pull-up transistor control bit Port P01 pull-up transistor control bit Port P0 0 pull-up transistor control bit Pull-up control register PU0 at reset : 00002 at power down : state retained R/W TAPU0/ TPU0A PU1 3 PU1 2 PU1 1 PU1 0 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Port P1 3 pull-up transistor control bit Port P1 2 pull-up transistor control bit Port P1 1 pull-up transistor control bit Port P10 pull-up transistor control bit Pull-up control register PU1 at reset : 00002 at power down : state retained R/W TAPU1/ TPU1A I13 I12 I11 I10 INT pin input control bit (Note 2) Interrupt valid waveform for INT pin/ return level selection bit (Note 2) INT pin edge detection circuit control bit INT pin Timer 1 count start synchronous circuit selection bit Interrupt control register I1 R/W TAI1/TI1Aat power down : state retainedat reset : 00002 INT pin input disabled INT pin input enabled Falling waveform/“L” level (“L” level is recognized with the SNZI0 instruction) Rising waveform/“H ” level (“H ” level is recognized with the SNZI0 instruction) One-sided edge detected Both edges detected Timer 1 count start synchronous circuit not selected Timer 1 count start synchronous circuit selected

Rev.3.02 Dec 22, 2006 page 57 of 142 REJ03B0025-0302 The clock control circuit consists of the following circuits.

• On-chip oscillator (internal oscillator)
• Ceramic resonator
• RC oscillation circuit
• Quartz-crystal oscillation circuit
• Multi-plexer (clock selection circuit)
• Frequency divider
• Internal clock generating circuit Fig. 47 Clock control circuit structure The system clock and the instruction clock are generated as the source clock for operation by these circuits. Figure 47 shows the structure of the clock control circuit. The 4556 Group operates by the on-chip oscillator clock (f(RING)) which is the internal oscillator after system is released from reset. Also, the ceramic resonator or the RC oscillation can be used for the main clock (f(X IN)) of the 4556 Group. The quartz-crystal oscillator can be used for sub-clock (f(XCIN)). MR 3, MR 2 CRCK instructionQ S R QS R Internal reset signal Key-on wakeup signal EPOF instruction POF2 instruction+ XCOUT XCIN QS R EPOF instruction POF instruction+ T3F signal MR 1, MR0 System clock (STCK) Instruction clock (INSTCK) Multi- plexer Quartz-crystal oscillation On-chip oscillator (internal oscillator) XOUT XIN Ceramic resonance RC oscillation Internal clock generating circuit (divided by 3) QRG 1 RG 0 RG 2 Divided by 2 Divided by 4 Divided by 8 Division circuit

Rev.3.02 Dec 22, 2006 page 58 of 142 REJ03B0025-0302 Fig. 48 Switch to ceramic oscillation/RC oscillation Fig. 49 Handling of XIN and XOUT when operating on-chip oscillator Fig. 50 Ceramic resonator external circuit Fig. 51 External RC circuit Do not execute the CRCK in- struction in program. Note: Externally connect a damping resistor Rd depending on the oscillation frequency. (A feedback resistor is built-in.) Use the resonator manu- facturer’s recommended value because constants such as ca- pacitance depend on the resonator. (1) On-chip oscillator operation After system is released from reset, the MCU starts operation by the clock output from the on-chip oscillator which is the internal os- cillator. The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. (2) Main clock generating circuit (f(XIN)) When the MCU operates by the ceramic resonator or the RC oscil- lator as the main clock (f(XIN)). After system is released from reset, the ceramic oscillation is valid for main clock. The ceramic oscillation is invalid and the RC oscillation circuit is valid with the CRCK instruction. The CRCK instruction can be executed only once. Execute the CRCK instruction in the initial setting routine (execut- ing it in address 0 in page 0 is recommended). When the main clock (f(X IN)) is not used, connect XIN pin to VSS and leave XOUT pin open, and do not execute the CRCK instruction (Figure 49). (3) Ceramic resonator When the ceramic resonator is used as the main clock (f(XIN)), con- nect the ceramic resonator and the external circuit to pins XIN and X OUT at the shortest distance. A feedback resistor is built in be- tween pins XIN and XOUT (Figure 50). Do not execute the CRCK instruction in program. (4) RC oscillation When the RC oscillation is used as the main clock (f(XIN)), connect the XIN pin to the external circuit of resistor R and the capacitor C at the shortest distance and leave XOUT pin open. Then, execute the CRCK instruction (Figure 51). The frequency is affected by a capacitor, a resistor and a micro- computer. So, set the constants within the range of the frequency limits. Reset CRCK

• Ceramic oscillation circuit valid
• RC oscillation circuit invalid Main clock (f(XIN))
• Ceramic oscillation circuit invalid
• RC oscillation circuit valid M34556 XIN XOU T Do not use the CRCK instruction in program. M34556 XIN XOU T Rd C IN C OUT M34556 XIN XOUTR C Execute the CRCK instruction in program.

Rev.3.02 Dec 22, 2006 page 59 of 142 REJ03B0025-0302 (5) External clock When the external clock signal is used as the main clock (f(XIN)), connect the XIN pin to the clock source and leave XOUT pin open. (Figure 52). Do not execute the CRCK instruction. Be careful that the maximum value of the oscillation frequency when using the external clock differs from the value when using the ceramic resonator (refer to the recommended operating condition). Also, note that the power down mode (POF and POF2 instructions) cannot be used when using the external clock. (6) Sub-clock generating circuit f(XCIN) Sub-clock signal f(XCIN ) is obtained by externally connecting a quartz-crystal oscillator. Connect this external circuit and a quartz- crystal oscillator to pins X CIN and XCOUT at the shortest distance. A feedback resistor is built in between pins XCIN and XCOUT (Figure 53). XCIN pin and XCOUT pin are also used as ports D6 and D7, respec- tively. The sub-clock oscillation circuit is invalid and the function of ports D6 and D7 are valid by setting bit 2 of register RG to “1”. When sub-clock, ports D6 and D7 are not used, connect XCIN/D6 to VSS and leave XCOUT /D7 open. (7) Clock control register MR Register MR controls system clock. Set the contents of this register through register A with the TMRA instruction. In addition, the TAMR instruction can be used to transfer the contents of register MR to register A. (8) Clock control register RG Register RG controls the start/stop of each oscillation circuit. Set the contents of this register through register A with the TRGA in- struction. Table 18 Clock control registers Fig. 52 External clock input circuit Fig. 53 External quartz-crystal circuit ROM ORDERING METHOD 1.Mask ROM Order Confirmation Form* 2.Mark Specification Form* * For the mask ROM confirmation and the mark specifications, re- fer to the “Renesas Technology Corp.” Homepage (http://www.renesas.com/homepage.jsp). Note: Externally connect a damping resistor Rd depending on the oscillation frequency. (A feedback resistor is built-in.) Use the quartz-crystal manu- facturer’s recommended value because constants such as ca- pacitance depend on the resonator. MR 3 Clock control register MR Operation mode Through mode Frequency divided by 2 mode Frequency divided by 4 mode Frequency divided by 8 mode System clock f(RING) f(X IN) f(XCIN) Not available (Note 2) at reset : 11002 at power down : state retained MR 3 MR R/W TAMR/ TMRA Operation mode selection bits MR 2 MR MR 2 MR 3 System clock selection bits (Note 3) MR 2 Sub-clock (f(XCIN)) oscillation available, ports D6 and D7 not selected Sub-clock (f(XCIN)) oscillation stop, ports D6 and D7 selected Main clock (f(XIN)) oscillation available Main clock (f(XIN)) oscillation stop On-chip oscillator (f(RING)) oscillation available On-chip oscillator (f(RING)) oscillation stop Sub-clock (f(X CIN)) control bit (Note 2) Main-clock (f(XIN)) control bit (Note 2) On-chip oscillator (f(RING)) control bit (Note 2) Clock control register RG W TRGAat power down : state retainedat reset : 0002 RG 2 RG 1 RG 0 Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: “11” cannot be set to the low-order 2 bits (MR1, MR0) of register MR. M34556 XIN XOU T External oscillation circuit VDD VSS *Do not use the CRCK instruction in program. M34556 XCIN XCOUT Rd C IN C OUT

Rev.3.02 Dec 22, 2006 page 60 of 142 REJ03B0025-0302 Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as fol- lows but to evaluate before actual use. 1. Shortest wiring length (1) Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the V SS pin with the shortest possible wiring. <Reason> In order to reset a microcomputer correctly, 1 machine cycle or more of the width of a pulse input into the RESET pin is required. If noise having a shorter pulse width than this is input to the RESET input pin, the reset is released before the internal state of the mi- crocomputer is completely initialized. This may cause a program runaway. Fig. 54 Wiring for the RESET pin (2) Wiring for clock input/output pins

• Make the length of wiring which is connected to clock I/O pins as short as possible.
• Make the length of wiring across the grounding lead of a capaci- tor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS pat- terns. <Reason> If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer. RESETReset circuit Noise VSSVSS Reset circuit VSS RESET VSS N.G. O.K. Noise XIN XOUT VSS XIN XOUT VSS N.G. O.K. Fig. 55 Wiring for clock I/O pins

Rev.3.02 Dec 22, 2006 page 61 of 142 REJ03B0025-0302 Fig. 57 Bypass capacitor across the VSS line and the VDD line 2. Connection of bypass capacitor across VSS line and VDD line Connect an approximately 0.1 µF bypass capacitor across the VSS line and the VDD line as follows:

• Connect a bypass capacitor across the VSS pin and the VDD pin at equal length.
• Connect a bypass capacitor across the VSS pin and the VDD pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS line and VDD line.
• Connect the power source wiring via a bypass capacitor to the VSS pin and the VDD pin. VSS VDD /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines VSS VDD /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines N.G. O.K. (3) Wiring to CNVSS pin Connect CNVSS pin to a GND pattern at the shortest distance. The GND pattern is required to be as close as possible to the GND supplied to V SS . In order to improve the noise reduction, to connect a 5 kΩ resistor serially to the CNVSS pin - GND line may be valid. As well as the above-mentioned, in this case, connect to a GND pattern at the shortest distance. The GND pattern is required to be as close as possible to the GND supplied to V SS . <Reason> The CNV SS pin of the One Time PROM is the power source input pin for the built-in One Time PROM. When programming in the built-in One Time PROM, the impedance of the CNV SS pin is low to allow the electric current for writing flow into the One Time PROM. Because of this, noise can enter easily. If noise enters the CNV SS pin, abnormal instruction codes or data are read from the built-in One Time PROM, which may cause a program runaway. Fig. 56 Wiring for the CNVSS pin of the One Time PROM About 5kΩ VSS The shortest The shortest CNV SS (Note) (Note) Note: This indicates pin.

Rev.3.02 Dec 22, 2006 page 62 of 142 REJ03B0025-0302

1. Oscillator concerns Take care to prevent an oscillator that generates clocks for a micro- computer operation from being affected by other signals. (1) Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as pos- sible from signal lines where a current larger than the tolerance of current value flows. <Reason> In the system using a microcomputer, there are signal lines for con- trolling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs be- cause of mutual inductance. (2) Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. <Reason> Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a pro- gram runaway. Fig. 58 Wiring for a large current signal line XIN XOUT VS S M Microcomputer Mutual inductance Large current G N D (3) Oscillator protection using Vss pattern As for a two-sided printed circuit board, print a Vss pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. Connect the Vss pattern to the microcomputer Vss pin with the shortest possible wiring. Besides, separate this Vss pattern from other Vss patterns. Fig. 60 Vss pattern on the underside of an oscillator /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines XIN XOUT VSS An example of VSS patterns on the underside of a printed circuit board Oscillator wiring pattern example Separate the V SS line for oscillation from other VSS lines XI N XO U T VS S C N T RD o n o t c r o s s N . G . Fig. 59 Wiring to a signal line where potential levels change frequently

Rev.3.02 Dec 22, 2006 page 63 of 142 REJ03B0025-0302 Fig. 61 Watchdog timer by software <The main routine>

• Assigns a single word of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition: N+1 ≥ (Counts of interrupt processing executed in each main rou- tine) As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin.
• Watches the operation of the interrupt processing routine by com- paring the SWDT contents with counts of interrupt processing after the initial value N has been set.
• Detects that the interrupt processing routine has failed and deter- mines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents do not change after interrupt processing. <The interrupt processing routine>
• Decrements the SWDT contents by 1 at each interrupt process- ing.
• Determines that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents are not initialized to the initial value N but continued to decrement and if they reach 0 or less. M a i n r o u t i n e (SWDT) ← N EI M a i n p r o c e s s i n g (SWDT) I n t e r r u p t p r o c e s s i n g r o u t i n e e r r o r s N I n t e r r u p t p r o c e s s i n g r o u t i n e ( S W D T ) ← ( S W D T ) — 1 I n t e r r u p t p r o c e s s i n g ( S W D T ) M a i n r o u t i n e e r r o r s ≤0 R T I R e t u r n = N ? ≤0? 4. Setup for I/O ports Setup I/O ports using hardware and software as follows: <Hardware>
• Connect a resistor of 100 Ω or more to an I/O port in series. <Software>
• As for an input port, read data several times by a program for checking whether input levels are equal or not.
• As for an output port or an I/O port, since the output data may re- verse because of noise, rewrite data to its port latch at fixed periods.
• Rewrite data to pull-up control registers at fixed periods. 5. Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The fol- lowing shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal op- eration, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated mul- tiple times in a single main routine processing.

Rev.3.02 Dec 22, 2006 page 64 of 142 REJ03B0025-0302 ➅ Timer count source Stop timer 1, 2 and LC counting to change its count source. ➆ Reading the count value Stop timer 1 or 2 counting and then execute the data read in- struction (TAB1, TAB2) to read its data. ➇ Writing to the timer Stop timer 1, 2 or LC counting and then execute the data write in- struction (T1AB, T2AB, TLCA) to write its data. ➈ Writing to reload register R1, R2H When writing data to reload register R1, reload register R2H while timer 1 or timer 2 is operating, avoid a timing when timer 1 or timer 2 underflows. Timer 2 Avoid a timing when timer 2 underflows to stop timer 2 at PWM output function used. When “H ” interval extension function of the PWM signal is set to be “valid”, set “1” or more to reload register R2H. Timer 3 Stop timer 3 counting to change its count source. Timer input/output pin Set the port C output latch to “0” to output the PWM signal from C/CNTR pin. LIST OF PRECAUTIONS ➀ Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up;

• connect a bypass capacitor (approx. 0.1 µF) between pins VDD and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use relatively thick wire. In the One Time PROM version, CNVSS pin is also used as VPP pin. Accordingly, when using this pin, connect this pin to VSS through a resistor about 5 kΩ (connect this resistor to CNVSS / VPP pin as close as possible). In addtion, the MCU may be replaced with mask ROM version without the need to remove the resistor from the circuit and with- out any adverse effect on operation. ➁ Register initial values 1 The initial value of the following registers are undefined after sys- tem is released from reset. After system is released from reset, set initial values.
• Register Z (2 bits)
• Register D (3 bits)
• Register E (8 bits) ➂ Register initial values 2 The initial value of the following registers are undefined at RAM back- up. After system is returned from RAM back-up, set initial values.
• Register Z (2 bits)
• Register X (4 bits)
• Register Y (4 bits)
• Register D (3 bits)
• Register E (8 bits) ➃ Stack registers (SKS) Stack registers (SKs) are eight identical registers, so that subrou- tines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accord- ingly, be careful not to over the stack when performing these operations together. ➄ Prescaler Stop counting and then execute the TABPS instruction to read from prescaler data. Stop counting and then execute the TPSAB instruction to set prescaler data.

Rev.3.02 Dec 22, 2006 page 65 of 142 REJ03B0025-0302

• The watchdog timer function is valid after system is released from reset. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously, and clear the WEF flag to “0” to stop the watchdog timer function.
• The watchdog timer function is valid after system is returned from the power down state. When not using the watchdog timer func- tion, execute the DWDT instruction and the WRST instruction continuously every system is returned from the power down state, and stop the watchdog timer function.
• When the watchdog timer function and power down function are used at the same time, execute the WRST instruction before sys- tem enters into the power down state and initialize the flag WDF1. Multifunction
• Be careful that the output of port D 5 can be used even when INT pin is selected. The threshold value is different between port D5 and INT. Accord- ingly, be careful when the input of both is used.
• Be careful that the “H ” output of port C can be used even when output of CNTR pin are selected. Program counter Make sure that the PCH does not specify after the last page of the built-in ROM. Timer 2 and Timer LC count start timing and count time when operation starts Count starts from the rising edge (2) after the first falling edge of the count source, after Timer 2 and Timer LC operations start (1). Time to first underflow (3) is different from time among next un- derflow (4) by the timing to start the timer and count source operations after count starts. Fig. 63 Timer count start timing and count time when opera- tion starts (Timer 2 and Timer LC) Fig. 62 Timer count start timing and count time when opera- tion starts (Prescaler and Timer 1) Prescaler and Timer 1 count start timing and count time when operation starts Count starts from the first rising edge of the count source (2) af- ter Prescaler and Timer 1 operations start (1). Time to first underflow (3) is shorter (for up to 1 period of the count source) than time among next underflow (4) by the timing to start the timer and count source operations after count starts. When selecting CNTR input as the count source of Timer 1, Timer 1 operates synchronizing with the falling edge of CNTR in- put. (1) Timer Start Count Source Timer Value Timer Underflow signal 3 21032103 (4)(3) (2) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Count Source Selecting CNTR input falling edge (1) Timer Start Count Source Timer Value Timer Underflow Signal 3 21032103 (4)(3) (2) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

Rev.3.02 Dec 22, 2006 page 66 of 142 REJ03B0025-0302 ❶ Note [1] on bit 3 of register I1 When the input of the INT pin is controlled with the bit 3 of regis- ter I1 in software, be careful about the following notes.

• Depending on the input state of the D 5/INT pin, the external 0 in- terrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 64➀ ) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to Figure 64➁ ). Also, set the NOP instruction for the case when a skip is per- formed with the SNZ0 instruction (refer to Figure 64➂ ). LA 4 ; ( ✕✕✕ 02) LA 8 ; (1 ✕✕✕ 2) TI1A ; Control of INT pin input is changed SNZ0 ; The SNZ0 instruction is executed (EXF0 flag cleared) ✕ : these bits are not used here. Fig. 64 External 0 interrupt program example-1 ❷ Note [2] on bit 3 of register I1 When the bit 3 of register I1 is cleared to “0”, the RAM back-up mode is selected and the input of INT pin is disabled, be careful about the following notes.
• When the key-on wakeup function of INT pin is not used (register K2 0 = “0”), clear bits 2 and 3 of register I1 before system enters to the power down mode. (refer to Figure 65➀ ).
• ••
• •• LA 0 ; (00 ✕✕ 2) DI EPOF POF2 ; Power down mode ✕ : these bits are not used here. Fig. 65 External 0 interrupt program example-2
• ••
• •• ❸ Note on bit 2 of register I1 When the interrupt valid waveform of the D5/INT pin is changed with the bit 2 of register I1 in software, be careful about the fol- lowing notes.
• Depending on the input state of the D 5/INT pin, the external 0 in- terrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 66➀ ) and then, change the bit 2 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to Figure 66➁ ). Also, set the NOP instruction for the case when a skip is per- formed with the SNZ0 instruction (refer to Figure 66➂ ). LA 4 ; ( ✕✕✕ 02) LA 12 TI1A ; Interrupt valid waveform is changed SNZ0 ; The SNZ0 instruction is executed (EXF0 flag cleared) ✕ : these bits are not used here. Fig. 66 External 0 interrupt program example-3
• ••
• ••

Rev.3.02 Dec 22, 2006 page 67 of 142 REJ03B0025-0302 When the POF or POF2 instruction is executed continuously af- ter the EPOF instruction, system enters the power down state. Note that system cannot enter the power down state when ex- ecuting only the POF or POF2 instruction. Be sure to disable interrupts by executing the DI instruction be- fore executing the EPOF instruction and the POF or POF2 instruction continuously. Power-on reset When the built-in power-on reset circuit is used, set the time for the supply voltage to rise from 0 V to the minimum voltage of rec- ommended operating conditions to 100 µs or less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and V SS at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage. Voltage drop detection circuit (only in H version) The voltage drop detection circuit detection voltage of this prod- uct is set up lower than the minimum value of the supply voltage of the recommended operating conditions. When the supply voltage of a microcomputer falls below to the minimum value of recommended operating conditions and re- goes up (ex. battery exchange of an application product), depending on the capacity value of the bypass capacitor added to the power supply pin, the following case may cause program failure (Figure 67); supply voltage does not fall below to V RST -, and its voltage re-goes up with no reset. In such a case, please design a system which supply voltage is once reduced below to V RST - and re-goes up after that. Clock control Execute the CRCK instruction in the initial setting routine of pro- gram (executing it in address 0 in page 0 is recommended). The oscillation circuit by the CRCK instruction can be selected only once. On-chip oscillator The clock frequency of the on-chip oscillator depends on the sup- ply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. Also, the oscillation stabilize wait time after system is released from reset is generated by the on-chip oscillator clock. When considering the oscillation stabilize wait time after system is re- leased from reset, be careful that the variable frequency of the on-chip oscillator clock. External clock When the external signal clock is used as the source oscillation (f(X IN)), note that the power down mode (POF and POF2 instruc- tions) cannot be used. Difference between Mask ROM version and One Time PROM version Mask ROM version and One Time PROM version have some dif- ference of the following characteristics within the limits of an electrical property by difference of a manufacture process, built- in ROM, and a layout pattern.

• a characteristic value
• a margin of operation
• the amount of noise-proof
• noise radiation, etc., Accordingly, be careful of them when swithcing.

26 Note on Power Source Voltage

When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. VDD Recommended operatng condition min.value No reset Program failure may occur. V RST + VRST – VDD Recommended operatng condition min.value V RST + VRST – → Normal operation Reset Fig. 67 VDD and VRST –

Rev.3.02 Dec 22, 2006 page 68 of 142 REJ03B0025-0302 INT pin input control bit (Note 2) Interrupt valid waveform for INT pin/ return level selection bit (Note 3) INT pin edge detection circuit control bit INT pin Timer 1 count start synchronous circuit selection bit Interrupt control register I1 R/W TAI1/TI1Aat power down : state retainedat reset : 00002 INT pin input disabled INT pin input enabled Falling waveform/“L” level (“L” level is recognized with the SNZI0 instruction) Rising waveform/“H ” level (“H ” level is recognized with the SNZI0 instruction) One-sided edge detected Both edges detected Timer 1 count start synchronous circuit not selected Timer 1 count start synchronous circuit selected This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) V13 V12 V11 V10 V23 V22 V21 V20 Not used Not used Not used Timer 3 interrupt enable bit Interrupt control register V2 at power down : 00002at reset : 00002 Interrupt control register V1 Timer 2 interrupt enable bit Timer 1 interrupt enable bit Not used External 0 interrupt enable bit Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) This bit has no function, but read/write is enabled. Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) at power down : 0000 2at reset : 00002 R/W TAV1/TV1A Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: When the contents of I12 and I13 are changed, the external interrupt request flag (EXF0) may be set. 3: The stopped clock cannot be selected for system clock. 4: “11” cannot be set to the low-order 2 bits (MR 1, MR0) of register MR. R/W TAV2/TV2A MR 3 Clock control register MR Operation mode Through mode Frequency divided by 2 mode Frequency divided by 4 mode Frequency divided by 8 mode System clock f(RING) f(XIN) f(XCIN) Not available (Note 4) at reset : 11002 at power down : state retained MR 3 MR R/W TAMR/ TMRA Operation mode selection bits MR 2 MR MR 2 MR 3 System clock selection bits (Note 3) MR 2

Rev.3.02 Dec 22, 2006 page 69 of 142 REJ03B0025-0302 PWM signal “H ” interval expansion function invalid PWM signal “H ” interval expansion function valid Stop (state retained) Operating X IN input Prescaler output (ORCLK)/2 signal output CNTR pin output control bit PWM signal interrupt valid waveform/ return level selection bit Timer 2 control bit Timer 2 count soruce selection bit Timer control register W2 at power down : 0000 2at reset : 00002 Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: The oscillation circuit selected for system clock cannot be stopped. 3: This function is valid only when the timer 1 count start synchronous circuit is selected (I1 0=“1”). 4: Port C output is invalid when CNTR input is selected for the timer 1 count source. W2 3 W2 2 W2 1 W2 0 Stop (state retained) Operating Prescaler control bit Timer control register PA W TPAAat power down : 02at reset : 02 PA 0 W1 1 Timer 1 count auto-stop circuit not selected Timer 1 count auto-stop circuit selected Stop (state retained) Operating Count source PWM signal (PWMOUT) Prescaler output (ORCLK) Timer 3 underflow signal (T3UDF) CNTR input Timer 1 count auto-stop circuit selection bit (Note 3) Timer 1 control bit Timer 1 count source selection bits (Note 4) Timer control register W1 R/W TAW1/TW1Aat power down : state retainedat reset : 00002 W1 3 W1 2 W1 1 W1 0 W3 1 X CIN input Prescaler output (ORCLK) Stop (Initial state) Operating Count value Underflow occurs every 8192 counts Underflow occurs every 16384 counts Underflow occurs every 32768 counts Underflow occurs every 65536 counts Timer 3 count auto-stop circuit selection bit Timer 3 control bit Timer 3 count value selection bits Timer control register W3 at power down : state retainedat reset : 00002 W3 3 W3 2 W3 1 W3 0 R/W TAW2/TW2A R/W TAW3/TW3A Sub-clock (f(XCIN)) oscillation available, ports D6 and D7 not selected Sub-clock (f(XCIN)) oscillation stop, ports D6 and D7 selected Main clock (f(XIN)) oscillation available Main clock (f(XIN)) oscillation stop On-chip oscillator (f(RING)) oscillation available On-chip oscillator (f(RING)) oscillation stop Sub-clock (f(X CIN)) control bit (Note 2) Main-clock (f(XIN)) control bit (Note 2) On-chip oscillator (f(RING)) control bit (Note 2) Clock control register RG W TRGAat power down : state retainedat reset : 0002 RG 2 RG 1 RG 0

Rev.3.02 Dec 22, 2006 page 70 of 142 REJ03B0025-0302 Stop (state retained) Operating Bit 4 (T3 4) of timer 3 System clock (STCK) CNTR output auto-control circuit not selected CNTR output auto-control circuit selected Falling edge Rising edge Timer LC control bit Timer LC count source selection bit CNTR output auto-control circuit selection bit CNTR pin input count edge selection bit Timer control register W4 at power down : state retainedat reset : 00002 W4 3 W4 2 W4 1 W4 0 R/W TAW4/TW4A Internal dividing resistor for LCD power supply selection bit (Note 2) LCD control bit LCD control register L1 L13 L12 L11 L10 at reset : 00002 at power down : state retained Duty Bias LCD control register L2 at reset : 0000 2 at power down : state retained W TL2A SEG VLC3 SEG 1 VLC2 SEG 2 VLC1 Internal dividing resistor valid Internal dividing resistor invalid L23 L22 L21 L20 SEG 0/VLC3 pin function switch bit (Note 3) SEG 1/VLC2 pin function switch bit (Note 4) SEG 2/VLC1 pin function switch bit (Note 4) Internal dividing resistor for LCD power supply control bit 2r ✕ 3, 2r ✕ 2 r ✕ 3, r ✕ 2 Stop Operating Not available LCD control register L3 at reset : 1111 2 at power down : state retained W TL3A SEG P23 SEG 19 P22 SEG 18 P21 SEG 17 P20 L33 L32 L31 L30 P23/SEG 20 pin function switch bit P22/SEG 19 pin function switch bit P21/SEG 18 pin function switch bit P20/SEG 17 pin function switch bit Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: “r (resistor) multiplied by 3” is used at 1/3 bias, and “r multiplied by 2” is used at 1/2 bias. 3: VLC3 is connected to VDD internally when SEG0 pin is selected. 4: Use internal dividing resistor when SEG1 and SEG2 pins are selected. R/W TAL1/TL1A LCD duty and bias selection bits

Rev.3.02 Dec 22, 2006 page 71 of 142 REJ03B0025-0302 LCD control register C1 at reset : 11112 at power down : state retained W TC1A SEG P03 SEG 23 P02 SEG 22 P01 SEG 21 P00 C1 3 C1 2 C11 C1 0 P03/SEG 24 pin function switch bit P02/SEG 23 pin function switch bit P01/SEG 22 pin function switch bit P00/SEG 21 pin function switch bit LCD control register C2 at reset : 11112 at power down : state retained W TC2A SEG P13 SEG 27 P12 SEG 26 P11 SEG 25 P10 C2 3 C2 2 C2 1 C2 0 P13/SEG 28 pin function switch bit P12/SEG 27 pin function switch bit P11/SEG 26 pin function switch bit P10/SEG 25 pin function switch bit PU0 3 PU0 2 PU0 1 PU0 0 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Port P0 3 pull-up transistor control bit Port P0 2 pull-up transistor control bit Port P01 pull-up transistor control bit Port P0 0 pull-up transistor control bit Pull-up control register PU0 at reset : 00002 at power down : state retained R/W TAPU0/ TPU0A PU1 3 PU1 2 PU1 1 PU1 0 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Port P1 3 pull-up transistor control bit Port P1 2 pull-up transistor control bit Port P1 1 pull-up transistor control bit Port P10 pull-up transistor control bit Pull-up control register PU1 at reset : 00002 at power down : state retained R/W TAPU1/ TPU1A Note: “W ” represents write enabled.

Rev.3.02 Dec 22, 2006 page 72 of 142 REJ03B0025-0302 N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output Ports P1 2, P13 output structure selection bit Ports P1 0, P11 output structure selection bit Ports P0 2, P03 output structure selection bit Ports P00, P01 output structure selection bit Port output structure control register FR0 at reset : 00002 at power down : state retained FR1 3 FR1 2 FR1 1 FR1 0 N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output Port D 3 output structure selection bit Port D2 output structure selection bit Port D1 output structure selection bit Port D0 output structure selection bit Port output structure control register FR1 at reset : 00002 at power down : state retained FR2 3 FR2 2 FR2 1 FR2 0 N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output Ports P2 2, P23 output structure selection bit Ports P20, P21 output structure selection bit Port D5 output structure selection bit Port D4 output structure selection bit Port output structure control register FR2 at reset : 00002 at power down : state retained Note: “W ” represents write enabled. W TFR0A W TFR1A W TFR2A

Rev.3.02 Dec 22, 2006 page 73 of 142 REJ03B0025-0302 Key-on wakeup control register K0 Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Port P12, P13 key-on wakeup control bit (Note 3) Port P10, P11 key-on wakeup control bit (Note 2) Port P02, P03 key-on wakeup control bit Port P0 0, P01 key-on wakeup control bit at reset : 00002 at power down : state retained R/W TAK0/ TK0A Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: To be invalid (K02 = “0”) key-on wakeup of ports P10 and P11, set the registers K10 and K11 to “0”. 3: To be invalid (K03 = “0”) key-on wakeup of ports P12 and P13, set the registers K12 and K13 to “0”. K13 K12 K11 K10 Key-on wakeup control register K1 Returned by edge Returned by level Falling waveform/“L” level Rising waveform/“H ” level Returned by edge Returned by level Falling waveform/“L” level Rising waveform/“H ” level Ports P12, P13 return condition selection bit (Note 3) Ports P12, P13 valid waveform/level selection bit (Note 3) Ports P10, P11 return condition selection bit (Note 2) Ports P1 0, P11 valid waveform/level selection bit (Note 2) at reset : 00002 at power down : state retained K23 K22 K21 K20 Key-on wakeup control register K2 This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Returned by level Returned by edge Key-on wakeup invalid Key-on wakeup valid Not used Not used INT pin return condition selection bit INT pin key-on wakeup control bit at reset : 00002 at power down : state retained R/W TAK1/ TK1A R/W TAK2/ TK2A

Rev.3.02 Dec 22, 2006 page 74 of 142 REJ03B0025-0302 A B DR E MR RG PA PU0 PU1 FR0 FR1 FR2 X Y Z DP PC PC H PC L SK SP CY UPTF RPS R2L R2H RLC

Contents

Register A (4 bits) Register B (4 bits) Register DR (3 bits) Register E (8 bits) Interrupt control register V1 (4 bits) Interrupt control register V2 (4 bits) Interrupt control register I1 (4 bits) Clock control register MR (4 bits) Clock control register RG (3 bits) Timer control register PA (1 bit) Timer control register W1 (4 bits) Timer control register W2 (4 bits) Timer control register W3 (4 bits) Timer control register W4 (4 bits) LCD control register L1 (4 bits) LCD control register L2 (4 bits) LCD control register L3 (4 bits) LCD control register C1 (4 bits) LCD control register C2 (4 bits) Pull-up control register PU0 (4 bits) Pull-up control register PU1 (4 bits) Port output structure control register FR0 (4 bits) Port output structure control register FR1 (4 bits) Port output structure control register FR2 (4 bits) Key-on wakeup control register K0 (4 bits) Key-on wakeup control register K1 (4 bits) Key-on wakeup control register K2 (4 bits) Register X (4 bits) Register Y (4 bits) Register Z (2 bits) Data pointer (10 bits) (It consists of registers X, Y, and Z) Program counter (14 bits) High-order 7 bits of program counter Low-order 7 bits of program counter Stack register (14 bits ✕ 8) Stack pointer (3 bits) Carry flag High-order bit reference enable flag Prescaler reload register (8 bits) Timer 1 reload register (8 bits) Timer 3 reload register (8 bits) Timer 2 reload register (8 bits) Timer 2 reload register (8 bits) Timer LC reload register (4 bits) Timer 1 interrupt request flag Timer 2 interrupt request flag Timer 3 interrupt request flag Watchdog timer flag Watchdog timer enable flag Interrupt enable flag External 0 interrupt request flag Power down flag Port D (8 bits) Port P0 (4 bits) Port P1 (4 bits) Port P2 (4 bits) Port C (1 bit) Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal constant Hexadecimal constant Hexadecimal constant Binary notation of hexadecimal variable A (same for others) Direction of data movement Data exchange between a register and memory Decision of state shown before “?” Contents of registers and memories Negate, Flag unchanged after executing instruction RAM address pointed by the data pointer Label indicating address a 6 a5 a4 a3 a2 a1 a0 Label indicating address a6 a5 a4 a3 a2 a1 a0 in page p6 p5 p4 p3 p2 p1 p0 Hex. C + Hex. number x Symbol PS TLC T1F T2F T3F WDF1 WEF INTE EXF0 P D C x y z p n i j A 3A2A1A0 ( ) M(DP) a p, a C + x INSTRUCTIONS The 4556 Group has the 124 (123) instructions. Each instruction is described as follows; (1) Index list of instruction function (2) Machine instructions (index by alphabet) (3) Machine instructions (index by function) (4) Instruction code table Note : Some instructions of the 4556 Group has the skip function to unexecute the next described instruction. The 4556 Group just invalidates the next instruc- tion when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped. SYMBOL The symbols shown below are used in the following list of instruc- tion function and the machine instructions.

Rev.3.02 Dec 22, 2006 page 75 of 142 REJ03B0025-0302 INDEX LIST OF INSTRUCTION FUNCTION Group- ing RAM addresses Mnemonic XAMI j TMA j LA n TABP p AM AMC A n AND OR SC RC SZC CMA RAR Function (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← n n = 0 to 15 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PC H ) ← p (Note) (PCL) ← (DR2–DR 0, A3–A0) at (UPTF) = 0 (B) ← (ROM(PC)) 7–4 (A) ← (ROM(PC))3–0 at (UPTF) = 1 (DR2) ← (0) (DR1, DR0) ← (ROM(PC))9, 8 (B) ← (ROM(PC))7–4 (A) ← (ROM(PC))3–0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (A) ← (A) + (M(DP)) (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry (A) ← (A) + n n = 0 to 15 (A) ← (A) AND (M(DP)) (A) ← (A) OR (M(DP)) (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → CY → A 3A2A1A0 Mnemonic TAB TBA TAY TYA TEAB TABE TDA TAD TAZ TAX TASP LXY x, y LZ z INY DEY TAM j XAM j XAMD j Function (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) 7–E4) ← (B) (E3–E0) ← (A) (B) ← (E7–E4) (A) ← (E3–E0) (DR 2–DR 0) ← (A2–A0) (A2–A0) ← (DR2–DR 0) (A3) ← 0 (A3, A2) ← 0 (A) ← (X) (A2–A0) ← (SP2–SP 0) (A3) ← 0 (X) ← x x = 0 to 15 (Y) ← y y = 0 to 15 (Z) ← z z = 0 to 3 (Y) ← (Y) + 1 (Y) ← (Y) – 1 (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) – 1 RAM to register transfer Arithmetic operation RAM to register transfer Register to register transfer Group- ing Note: p is 0 to 31 for M34556M4/M4H. p is 0 to 63 for M34556M8/M8H/G8/G8H.

Rev.3.02 Dec 22, 2006 page 76 of 142 REJ03B0025-0302 INDEX LIST OF INSTRUCTION FUNCTION (continued) Group- ingFunction (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15 (PC L) ← a6–a0 (PCH ) ← p (PCL) ← a6–a0 (PCH ) ← p (PCL) ← (DR2–DR 0, A3–A0) (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← 2 (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← (DR2–DR 0, A3–A0) (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 Comparisonoperation Subroutine operation Branch operation Bit operation Return operation Mnemonic SB j RB j SZB j SEAM SEA n B a BL p, a BLA p BM a BML p, a BMLA p RTI RT RTS Group- ing Function (INTE) ← 0 (INTE) ← 1 (EXF0) ← 0 V10 = 1: SNZ0 = NOP (A) ← (V1) (V1) ← (A) (A) ← (V2) (V2) ← (A) (A) ← (I1) (I1) ← (A) (PA) ← (A) (A) ← (W1) (W1) ← (A) (A) ← (W2) (W2) ← (A) (A) ← (W3) (W3) ← (A) (A) ← (W4) (W4) ← (A) (B) ← (TPS7–TPS 4) (A) ← (TPS3–TPS 0) (RPS 7–RPS 4) ← (B) (TPS7–TPS 4) ← (B) (RPS 3–RPS 0) ← (A) (TPS3–TPS 0) ← (A) Interrupt operation Timer operation Note: p is 0 to 31 for M34556M4/M4H. p is 0 to 63 for M34556M8/M8H/G8/G8H. Mnemonic DI EI SNZ0 SNZI0 TAV1 TV1A TAV2 TV2A TAI1 TI1A TPAA TAW1 TW1A TAW2 TW2A TAW3 TW3A TAW4 TW4A TABPS TPSAB

Rev.3.02 Dec 22, 2006 page 77 of 142 REJ03B0025-0302 INDEX LIST OF INSTRUCTION FUNCTION (continued) Group- ing Group- ing Function (B) ← (T17–T14) (A) ← (T13–T10) (R17–R1 4) ← (B) (T17–T14) ← (B) (R13–R1 0) ← (A) (T13–T10) ← (A) (B) ← (T27–T24) (A) ← (T23–T20) (R27–R2 4) ← (B) (T27–T24) ← (B) (R23–R2 0) ← (A) (T23–T20) ← (A) (R2H 7–R2H 4) ← (B) (R2H 3–R2H 0) ← (A) (R17–R1 4) ← (B) (R13–R1 0) ← (A) (T27–T24) ← (R2L7–R2L 4) (T23–T20) ← (R2L3–R2L 0) (LC) ← (A) (RLC) ← (A) (T1F) ← 0 V12 = 1: SNZT1 = NOP (T2F) ← 0 V13 = 1: SNZT2 = NOP (T3F) ← 0 V20 = 1: SNZT3 = NOP (A) ← (P0) (P0) ← (A) (A) ← (P1) (P1) ← (A) (A) ← (P2) (P2) ← (A) Mnemonic TAB1 T1AB TAB2 T2AB T2HAB TR1AB T2R2L TLCA SNZT1 SNZT2 SNZT3 IAP0 OP0A IAP1 OP1A IAP2 OP2A Timer operation Input/Output operation Input/Output operation Function (D) ← 1 (D(Y)) ← 0 (Y) = 0 to 7 (D(Y)) ← 1 (Y) = 0 to 7 (D(Y)) = 0 ? (Y) = 0 to 5 (C) ← 0 (C) ← 1 (A) ← (PU0) (PU0) ← (A) (A) ← (PU1) (PU1) ← (A) (A) ← (K0) (K0) ← (A) (A) ← (K1) (K1) ← (A) (A) ← (K2) (K2) ← (A) (FR0) ← (A) (FR1) ← (A) (FR2) ← (A) RC oscillator selected (A) ← (MR) (MR) ← (A) (RG) ← (A) Mnemonic CLD RD SD SZD RCP SCP TAPU0 TPU0A TAPU1 TPU1A TAK0 TK0A TAK1 TK1A TAK2 TK2A TFR0A TFR1A TFR2A CRCK TAMR TMRA TRGA Clock operation

Rev.3.02 Dec 22, 2006 page 78 of 142 REJ03B0025-0302 INDEX LIST OF INSTRUCTION FUNCTION (continued) Group- ing Function (A) ← (L1) (L1) ← (A) (L2) ← (A) (L3) ← (A) (C1) ← (A) (C2) ← (A) (PC) ← (PC) + 1 Transition to clock operating mode Transition to RAM back-up mode POF, POF2 instructions valid (P) = 1 ? Stop of watchdog timer function enabled System reset (WDF1) = 1 ? (WDF1) ← 0 (UPTF) ← 0 (UPTF) ← 1 At power down mode, voltage drop detection circuit valid Mnemonic TAL1 TL1A TL2A TL3A TC1A TC2A NOP POF POF2 EPOF SNZP DWDT SRST WRST RUPT SUPT SVDE (Note) LCD operation Other operation Note: The SVDE instruction can be used only for the H version.

Rev.3.02 Dec 22, 2006 page 79 of 142 REJ03B0025-0302 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) A n (Add n and accumulator) 000110nnnn 06n 11 – Overflow = 0 Grouping: Arithmetic operation Description:Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation. Operation: (A) ← (A) + n n = 0 to 15 AM (Add accumulator and Memory) 0000001010 00A 11 – – Grouping: Arithmetic operation Description:Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged. Operation: (A) ← (A) + (M(DP)) AMC (Add accumulator, Memory and Carry) 0000001011 00B 11 0/1 – Grouping: Arithmetic operation Description:Adds the contents of M(DP) and carry flag CY to register A. Stores the result in regis- ter A and carry flag CY. Operation: (A) ← (A) + (M(DP)) + (CY) (CY) ← CarryAND (logical AND between accumulator and memory) 0000011000 018 11 –– Grouping: Arithmetic operation Description:Takes the AND operation between the con- tents of register A and the contents of M(DP), and stores the result in register A. Operation: (A) ← (A) AND (M(DP))

Rev.3.02 Dec 22, 2006 page 80 of 142 REJ03B0025-0302 B a (Branch to address a) 011a 6 a5 a4 a3 a2 a1 a0 1a 11 – – Grouping: Branch operation Description:Branch within a page : Branches to address a in the identical page. Note: Specify the branch address within the page including this instruction. Operation: (PCL) ← a6 to a0 BL p, a (Branch Long to address a in page p) 00111p 4 p3 p2 p1 p0 0p 22 –– Grouping: Branch operation Description:Branch out of a page : Branches to address a in page p. Note: p is 0 to 31 for M34556M4/M4H and p is 0 to 63 for M34556M8/M8H/G8/G8H. Operation: (PCH ) ← p (PCL) ← a6 to a0 BLA p (Branch Long to address (D) + (A) in page p) 0000010000 010 22 –– Grouping: Branch operation Description:Branch out of a page : Branches to address (DR 2 DR 1 DR 0 A3 A2 A1 A0)2 specified by registers D and A in page p. Note: p is 0 to 31 for M34556M4/M4H and p is 0 to 63 for M34556M8/M8H/G8/G8H. 2 1610p 5 a6 a5 a4 a3 a2 a1 a0 2a E Operation: (PCH ) ← p (PCL) ← (DR2–DR 0, A3–A0) 2 1610p 5 p4 00p 3 p2 p1 p0 2pp MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) p BM a (Branch and Mark to address a in page 2) 010a 6 a5 a4 a3 a2 a1 a0 1aa 11 – – Grouping: Subroutine call operation Description:Call the subroutine in page 2 : Calls the subroutine at address a in page 2. Note: Subroutine extending from page 2 to an- other page can also be called with the BM instruction when it starts on page 2. Be careful not to over the stack because the maximum level of subroutine nesting is 8. Operation: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PC H ) ← 2 (PCL) ← a6–a0

Rev.3.02 Dec 22, 2006 page 81 of 142 REJ03B0025-0302 BML p, a (Branch and Mark Long to address a in page p) 00110p 4 p3 p2 p1 p0 0p 22 – – Grouping: Subroutine call operation Description:Call the subroutine : Calls the subroutine at address a in page p. Note: p is 0 to 31 for M34556M4/M4H and p is 0 to 63 for M34556M8/M8H/G8/G8H. Be careful not to over the stack because the maximum level of subroutine nesting is 8. Operation: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← a6–a0 BMLA p (Branch and Mark Long to address (D) + (A) in page p) 0000110000 030 22 – – Grouping: Subroutine call operation Description:Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 speci- fied by registers D and A in page p. Note: p is 0 to 31 for M34556M4/M4H and p is 0 to 63 for M34556M8/M8H/G8/G8H. Be careful not to over the stack because the maximum level of subroutine nesting is 8. CLD (CLear port D) 0000010001 011 11 – – Grouping: Input/Output operation Description:Sets (1) to port D. Operation: (D) ← 1 2 1610p 5 a6 a5 a4 a3 a2 a1 a0 2a C Operation: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← (DR2–DR 0, A3–A0) 2 1610p 5 p4 00p 3 p2 p1 p0 2pp MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) p CMA (CoMplement of Accumulator) 0000011100 01C 11 – – Grouping: Arithmetic operation Description:Stores the one’s complement for register A’s contents in register A. Operation: (A) ← (A)

Rev.3.02 Dec 22, 2006 page 82 of 142 REJ03B0025-0302 CRCK (Clock select: Rc oscillation ClocK) 1010011011 29B 11 – – Grouping: Clock control operation Description:Selects the RC oscillation circuit for main clock f(XIN). Operation: RC oscillation circuit selected MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) DI (Disable Interrupt) 0000000100 004 11 – – Grouping: Interrupt control operation Description:Clears (0) to interrupt enable flag INTE, and disables the interrupt. Note: Interrupt is disabled by executing the DI in- struction after executing 1 machine cycle. Operation: (INTE) ← 0 DWDT (Disable WatchDog Timer) 1010011100 29C 11 – – Grouping: Other operation Description:Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction. Operation: Stop of watchdog timer function enabled 0000010111 017 11 – (Y) = 15 Grouping: RAM addresses Description:Subtracts 1 from the contents of register Y. As a result of subtraction, when the con- tents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. Operation: (Y) ← (Y) – 1 DEY (DEcrement register Y)

Rev.3.02 Dec 22, 2006 page 83 of 142 REJ03B0025-0302 EI (Enable Interrupt) 0000000101 005 11 – – Grouping: Interrupt control operation Description:Sets (1) to interrupt enable flag INTE, and enables the interrupt. Note: Interrupt is enabled by executing the EI in- struction after executing 1 machine cycle. Operation: (INTE) ← 1 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) IAP0 (Input Accumulator from port P0) 1001100000 260 11 – – Grouping: Input/Output operation Description:Transfers the input of port P0 to register A. IAP1 (Input Accumulator from port P1) 1001100001 261 11 – – Grouping: Input/Output operation Description:Transfers the input of port P1 to register A. Operation: (A) ← (P1) Operation: (A) ← (P0) 0001011011 05B 11 – – Grouping: Other operation Description:Makes the immediate after POF instruction or POF2 instruction valid by executing the EPOF instruction. Operation: POF instruction, POF2 instruction valid EPOF (Enable POF instruction)

Rev.3.02 Dec 22, 2006 page 84 of 142 REJ03B0025-0302 IAP2 (Input Accumulator from port P2) 1001100010 262 11 –– Grouping: Input/Output operation Description:Transfers the input of port P2 to register A. Operation: (A) ← (P2) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) 11x 3 x2 x1 x0 y3 y2 y1 y0 3xy 11 – Continuous Grouping: RAM addresses Description:Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instruc- tions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continu- ously are skipped. Operation: (X) ← x x = 0 to 15 (Y) ← y y = 0 to 15 LXY x, y (Load register X and Y with x and y) INY (INcrement register Y) 0000010011 013 11 – (Y) = 0 Grouping: RAM addresses Description:Adds 1 to the contents of register Y . As a re- sult of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. Operation: (Y) ← (Y) + 1 LA n (Load n in Accumulator) 000111nnnn 07n 11 – Continuous Grouping: Arithmetic operation Description:Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA in- struction is executed and other LA instructions coded continuously are skipped. Operation: (A) ← n n = 0 to 15

Rev.3.02 Dec 22, 2006 page 85 of 142 REJ03B0025-0302 LZ z (Load register Z with z) 00010010z 1 z0 04 11 – – Grouping: RAM addresses Description:Loads the value z in the immediate field to register Z. Operation: (Z) ← z z = 0 to 3 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) NOP (No OPeration) 0000000000 000 11 –– Grouping: Other operation Description:No operation; Adds 1 to program counter value, and others remain unchanged. Operation: (PC) ← (PC) + 1 OP0A (Output port P0 from Accumulator) 1000100000 220 11 – – Grouping: Input/Output operation Description:Outputs the contents of register A to port P0. Operation: (P0) ← (A) OP1A (Output port P1 from Accumulator) 1000100001 221 11 – – Grouping: Input/Output operation Description:Outputs the contents of register A to port P1. Operation: (P1) ← (A)

Rev.3.02 Dec 22, 2006 page 86 of 142 REJ03B0025-0302 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) OP2A (Output port P2 from Accumulator) 1000100010 222 11 – – Grouping: Input/Output operation Description:Outputs the contents of register A to port P2. Operation: (P2) ← (A) POF (Power OFf) 0000000010 002 11 – – Grouping: Other operation Description:Puts the system in clock operating mode by executing the POF2 instruction after ex- ecuting the EPOF instruction. Note: If the EPOF instruction is not executed before executing this instruction, this instruction is equivalent to the NOP instruction. Operation: Transition to clock operating mode 0000011001 019 11 – – Grouping: Arithmetic operation Description:Takes the OR operation between the con- tents of register A and the contents of M(DP), and stores the result in register A. Operation: (A) ← (A) OR (M(DP)) OR (logical OR between accumulator and memory) POF2 (Power OFf2) 0000001000 008 11 – – Grouping: Other operation Description:Puts the system in RAM back-up state by executing the POF2 instruction after ex- ecuting the EPOF instruction. Note: If the EPOF instruction is not executed before executing this instruction, this instruction is equivalent to the NOP instruction. Operation: Transition to RAM back-up mode

Rev.3.02 Dec 22, 2006 page 87 of 142 REJ03B0025-0302 RB j (Reset Bit) 00010011j j 04 11 –– Grouping: Bit operation Description:Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Operation: (Mj(DP)) ← 0 j = 0 to 3 C MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) RC (Reset Carry flag) 0000000110 006 11 0 – Grouping: Arithmetic operation Description:Clears (0) to carry flag CY. Operation: (CY) ← 0 RAR (Rotate Accumulator Right) 0000011101 01D 1 1 0/1 – Grouping: Arithmetic operation Description:Rotates 1 bit of the contents of register A in- cluding the contents of carry flag CY to the right. Operation: → CY → A3A2A1A0 RCP (Reset Port C) 1010001100 28C 11 0 – Grouping: Input/Output operation Description:Clears (0) to carry flag CY. Operation: (C) ← 0

Rev.3.02 Dec 22, 2006 page 88 of 142 REJ03B0025-0302 RTI (ReTurn from Interrupt) 0001000110 046 11 – – Grouping: Return operation Description:Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y , Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY in- struction, register A and register B to the states just before interrupt. Operation: (PC) ← (SK(SP)) (SP) ← (SP) – 1 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) RTS (ReTurn from subroutine and Skip) 0001000101 045 12 – Skip at uncondition Grouping: Return operation Description:Returns from subroutine to the routine called the subroutine, and skips the next in- struction at uncondition. Operation: (PC) ← (SK(SP)) (SP) ← (SP) – 1 RD (Reset port D specified by register Y) 0000010100 014 11 – – Grouping: Input/Output operation Description:Clears (0) to a bit of port D specified by reg- ister Y . Operation: (D(Y)) ← 0 However, (Y) = 0 to 7 RT (ReTurn from subroutine) 0001000100 044 12 – – Grouping: Return operation Description:Returns from subroutine to the routine called the subroutine. Operation: (PC) ← (SK(SP)) (SP) ← (SP) – 1

Rev.3.02 Dec 22, 2006 page 89 of 142 REJ03B0025-0302 SCP (Set Port C) 1010001101 28D 11 – – Grouping: Input/Output operation Description:Sets (1) to port C. Operation: (C) ← 1 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SB j (Set Bit) 00010111j j 05 11 – – Grouping: Bit operation Description:Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Operation: (Mj(DP)) ← 1 j = 0 to 3 C SC (Set Carry flag) 0000000111 007 11 1 – Grouping: Arithmetic operation Description:Sets (1) to carry flag CY . Operation: (CY) ← 1 RUPT (Reset UPTF flag) 0001011000 058 11 – – Grouping: Other operation Description:Clears (0) to the high-order bit reference enable flag. Operation: (UPTF) ← 0

Rev.3.02 Dec 22, 2006 page 90 of 142 REJ03B0025-0302 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SEAM (Skip Equal, Accumulator with Memory) 0000100110 026 11 – (A) = (M(DP)) Grouping: Comparison operation Description:Skips the next instruction when the con- tents of register A is equal to the contents of M(DP). Executes the next instruction when the con- tents of register A is not equal to the contents of M(DP). Operation: (A) = (M(DP)) ? SNZ0 (Skip if Non Zero condition of external 0 interrupt request flag) 0000111000 038 11 – V10 = 0: (EXF0) = 1 Grouping: Interrupt operation Description:When V1 0 = 0 : Clears (0) to the EXF0 flag and skips the next instruction when external 0 interrupt request flag EXF0 is “1.” When the EXF0 flag is “0,” executes the next in- struction. When V1 0 = 1 : This instruction is equiva- lent to the NOP instruction. Operation: V10 = 0: (EXF0) = 1 ? (EXF0) ← 0 V10 = 1: SNZ0 = NOP (V10 : bit 0 of the interrupt control register V1) SEA n (Skip Equal, Accumulator with immediate data n) 0000100101 025 22 – (A) = n n = 0 to 15 Grouping: Comparison operation Description:Skips the next instruction when the con- tents of register A is equal to the value n in the immediate field. Executes the next instruction when the con- tents of register A is not equal to the value n in the immediate field. Operation: (A) = n ? n = 0 to 15 2 16000111nnnn 07n SD (Set port D specified by register Y) 0000010101 015 11 – – Grouping: Input/Output operation Description:Sets (1) to a bit of port D specified by regis- ter Y. Operation: (D(Y)) ← 1 (Y) = 0 to 7

Rev.3.02 Dec 22, 2006 page 91 of 142 REJ03B0025-0302 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SNZT1 (Skip if Non Zero condition of Timer 1 interrupt request flag) 1010000000 280 Grouping: Timer operation Description:When V1 2 = 0 : Clears (0) to the T1F flag and skips the next instruction when timer 1 interrupt request flag T1F is “1.” When the T1F flag is “0,” executes the next instruc- tion. When V1 2 = 1 : This instruction is equiva- lent to the NOP instruction. Operation: V12 = 0: (T1F) = 1 ? (T1F) ← 0 V12 = 1: SNZT1 = NOP (V12 = bit 2 of interrupt control register V1) SNZT2 (Skip if Non Zero condition of Timer 2 interrupt request flag) 1010000001 281 Grouping: Timer operation Description:When V1 3 = 0 : Clears (0) to the T2F flag and skips the next instruction when timer 2 interrupt request flag T2F is “1.” When the T2F flag is “0,” executes the next instruc- tion. When V1 3 = 1 : This instruction is equiva- lent to the NOP instruction. Operation: V13 = 0: (T2F) = 1 ? (T2F) ← 0 V13 = 1: SNZT2 = NOP (V13 = bit 3 of interrupt control register V1) SNZP (Skip if Non Zero condition of Power down flag) 0000000011 003 11 – (P) = 1 Grouping: Other operation Description:Skips the next instruction when the P flag is “1”. After skipping, the P flag remains un- changed. Executes the next instruction when the P flag is “0.” Operation: (P) = 1 ? SNZI0 (Skip if Non Zero condition of external 0 Interrupt input pin) 0000111010 03A Grouping: Interrupt operation Description:When I12 = 0 : Skips the next instruction when the level of INT pin is “L.” Executes the next instruction when the level of INT pin is “H.” When I12 = 1 : Skips the next instruction when the level of INT pin is “H.” Executes the next instruction when the level of INT pin is “L.” Operation: I1 (I12 : bit 2 of the interrupt control register I1)

Rev.3.02 Dec 22, 2006 page 92 of 142 REJ03B0025-0302 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SNZT3 (Skip if Non Zero condition of Timer 3 interrupt request flag) 1010000010 282 Grouping: Timer operation Description:When V2 0 = 0 : Clears (0) to the T3F flag and skips the next instruction when timer 3 interrupt request flag T3F is “1.” When the T3F flag is “0,” executes the next instruc- tion. When V2 0 = 1 : This instruction is equiva- lent to the NOP instruction. Operation: V20 = 0: (T3F) = 1 ? (T3F) ← 0 V20 = 1: SNZT3 = NOP (V20 = bit 0 of interrupt control register V2) SRST (System ReSeT) 0000000001 001 11 – – Grouping: Other operation Description:System reset occurs. Operation: System reset occurrence SUPT (Set UPTF flag) 0001011001 059 11 – – Grouping: Other operation Description:Sets (1) to high-order bit reference enable flag. Operation: (UPTF) ← 1 SVDE (Se Voltage Detector Enable flag) 1010010011 293 11 – – Grouping: Other operation Description:Voltage drop detection circuit is valid at powerdown mode (clock operating mode, RAM back-up mode) Note: This instruction can be used only for H version. Operation: Voltage drop detection circuit valid at powerdown mode.

Rev.3.02 Dec 22, 2006 page 93 of 142 REJ03B0025-0302 SZB j (Skip if Zero, Bit) 00001000j j 02j 11 – (Mj(DP)) = 0 j = 0 to 3 Grouping: Bit operation Description:Skips the next instruction when the con- tents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0.” Executes the next instruction when the con- tents of bit j of M(DP) is “1.” Operation: (Mj(DP)) = 0 ? j = 0 to 3 SZD (Skip if Zero, port D specified by register Y) 0000100100 024 22 – (D(Y)) = 0 (Y) = 0 to 7 Grouping: Input/Output operation Description:Skips the next instruction when a bit of port D specified by register Y is “0.” Executes the next instruction when the bit is “1.” Note: (Y) = 0 to 5. Do not execute this instruction if values ex- cept above are set to register Y. T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B) 1000110000 230 11 – – Grouping: Timer operation Description:Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 re- load register R1. Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1. Operation: (T1 7–T14) ← (B) (R17–R1 4) ← (B) (T13–T10) ← (A) (R13–R1 0) ← (A) Operation: (D(Y)) = 0 ? (Y) = 0 to 7 2 160000101011 02B MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SZC (Skip if Zero, Carry flag) 0000101111 02F 11 – (CY) = 0 Grouping: Arithmetic operation Description:Skips the next instruction when the con- tents of carry flag CY is “0.” After skipping, the CY flag remains un- changed. Executes the next instruction when the con- tents of the CY flag is “1.“ Operation: (CY) = 0 ?

Rev.3.02 Dec 22, 2006 page 94 of 142 REJ03B0025-0302 TAB (Transfer data to Accumulator from register B) 0000011110 01E 11 – – Grouping: Register to register transfer Description:Transfers the contents of register B to reg- ister A. Operation: (A) ← (B) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) T2R2L (Transfer data to timer 2 from register R2L) 1010010101 295 11 – – Grouping: Timer operation Description:Transfers the contents of reload register R2L to timer 2. Operation: (T27–T20) ← (R2L7–R2L 0) T2AB (Transfer data to timer 2 and register R2L from Accumulator and register B) 1000110001 231 11 – – Grouping: Timer operation Description:Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 re- load register R2L. Transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2L. Operation: (R2L 7–R2L 4) ← (B) (T27–T24) ← (B) (R2L3–R2L 0) ← (A) (T23–T20) ← (A) T2HAB (Transfer data to register R2H from Accumulator and register B) 1010010100 294 11 – – Grouping: Timer operation Description:Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 re- load register R2H. Transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2H. Operation: (R2H 7–R2H 4) ← (B) (R2H 3–R2H 0) ← (A)

TABP p (Transfer data to Accumulator and register B from Program memory in page p) 0010p 5 p4 p3 p2 p1 p0 0p 13 – – Grouping: Arithmetic operationOperation: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (Note) (PCL) ← (DR2–DR 0, A3–A0) at (UPTF) = 0 (B) ← (ROM(PC))7–4 (A) ← (ROM(PC))3–0 Description: UPTF = 0: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 9 to 0 are the ROM pattern in ad-dress (DR

2 DR 1 DR 0 A3 A2 A1 A0)2 specified by

registers A and D in page p. UPTF = 1: Transfers bits 9, 8 to register D, bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. Note: p is 0 to 31 for M34556M4/M4H, and p is 0 to 63 for M34556M8/M8H/G8/G8H. When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. TABE (Transfer data to Accumulator and register B from register E) 0000101010 02A 11 – – Grouping: Register to register transfer Description:Transfers the high-order 4 bits (E7–E4) of register E to register B, and low-order 4 bits of register E to register A. Operation: (B) ← (E 7–E4) (A) ← (E3–E0) TAB1 (Transfer data to Accumulator and register B from timer 1) 1001110000 270 11 – – Grouping: Timer operation Description:Transfers the high-order 4 bits (T17–T14) of timer 1 to register B. Transfers the low-order 4 bits (T1 3–T10) of timer 1 to register A. Operation: (B) ← (T17–T14) (A) ← (T13–T10) TAB2 (Transfer data to Accumulator and register B from timer 2) 1001110001 271 11 – – Grouping: Timer operation Description:Transfers the high-order 4 bits (T27–T24) of timer 2 to register B. Transfers the low-order 4 bits (T2 3–T20) of timer 2 to register A. Operation: (B) ← (T27–T24) (A) ← (T23–T20) at (UPTF) = 1 (DR2) ← (0) (DR1, DR0) ← (ROM(PC))9, 8 (B) ← (ROM(PC))7–4 (A) ← (ROM(PC))3–0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 Skip conditionNumber of cycles Number of words Instruction code D 9 D 0 Flag CY 2 16 Skip conditionNumber of cycles Number of words Instruction code D 9 D 0 Flag CY 2 16 Skip conditionNumber of cycles Number of words Instruction code D 9 D 0 Flag CY 2 16 Skip conditionNumber of cycles Number of words Instruction code D 9 D 0 Flag CY 2 16 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) Rev.3.02 Dec 22, 2006 page 95 of 142 REJ03B0025-0302

Rev.3.02 Dec 22, 2006 page 96 of 142 REJ03B0025-0302 TAD (Transfer data to Accumulator from register D) 0001010001 051 11 – – Grouping: Register to register transfer Description:Transfers the contents of register D to the low-order 3 bits (A2–A0) of register A. Note: When this instruction is executed, “0” is stored to the bit 3 (A3) of register A. Operation: (A2–A0) ← (DR 2–DR 0) (A3) ← 0 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAI1 (Transfer data to Accumulator from register I1) 1001010011 253 11 – – Grouping: Interrupt operation Description:Transfers the contents of interrupt control register I1 to register A. Operation: (A) ← (I1) TAK0 (Transfer data to Accumulator from register K0) 1001010110 256 11 – – Grouping: Input/Output operation Description:Transfers the contents of key-on wakeup control register K0 to register A. Operation: (A) ← (K0) TABPS (Transfer data to Accumulator and register B from PreScaler) 1001110101 275 11 – – Grouping: Timer operation Description:Transfers the high-order 4 bits (TPS7– TPS 4) of prescaler to register B, and transfers the low-order 4 bits (TPS3–TPS 0) of prescaler to register A. Operation: (B) ← (TPS7–TPS 4) (A) ← (TPS3–TPS 0)

Rev.3.02 Dec 22, 2006 page 97 of 142 REJ03B0025-0302 TAK2 (Transfer data to Accumulator from register K2) 1001011010 25A 11 – – Grouping: Input/Output operation Description:Transfers the contents of key-on wakeup control register K2 to register A. Operation: (A) ← (K2) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAM j (Transfer data to Accumulator from Memory) 101100 jjjj 2C j 11 – – Grouping: RAM to register transfer Description:After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the re- sult in register X. Operation: (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 TAK1 (Transfer data to Accumulator from register K1) 1001011001 259 11 – – Grouping: Input/Output operation Description:Transfers the contents of key-on wakeup control register K1 to register A. Operation: (A) ← (K1) TAL1 (Transfer data to Accumulator from register L1) 1001001010 24A 11 – – Grouping: LCD control operation Description:Transfers the contents of LCD control regis- ter L1 to register A. Operation: (A) ← (L1)

Rev.3.02 Dec 22, 2006 page 98 of 142 REJ03B0025-0302 TAPU1 (Transfer data to Accumulator from register PU1) TAPU0 (Transfer data to Accumulator from register PU0) 1001010111 257 11 – – Grouping: Input/Output operation Description:Transfers the contents of pull-up control register PU0 to register A. Operation: (A) ← (PU0) 1001011110 25E 11 – – Grouping: Input/Output operation Description:Transfers the contents of pull-up control register PU1 to register A. Operation: (A) ← (PU1) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) 1001010010 252 11 – – Grouping: Clock operation Description:Transfers the contents of clock control reg- ister MR to register A. Operation: (A) ← (MR) TAMR (Transfer data to Accumulator from register MR) TASP (Transfer data to Accumulator from Stack Pointer) 0001010000 050 11 – – Grouping: Register to register transfer Description:Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2–A0) of register A. Note: After this instruction is executed, “0” is stored to the bit 3 (A3) of register A. Operation: (A2–A0) ← (SP2–SP 0) (A3) ← 0

Rev.3.02 Dec 22, 2006 page 99 of 142 REJ03B0025-0302 TAV1 (Transfer data to Accumulator from register V1) 0001010100 054 11 – – Grouping: Interrupt operation Description:Transfers the contents of interrupt control register V1 to register A. Operation: (A) ← (V1) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAW2 (Transfer data to Accumulator from register W2) 1001001100 24C 11 –– Grouping: Timer operation Description:Transfers the contents of timer control reg- ister W2 to register A. Operation: (A) ← (W2) TAW1 (Transfer data to Accumulator from register W1) 1001001011 24B 11 – – Grouping: Timer operation Description:Transfers the contents of timer control reg- ister W1 to register A. Operation: (A) ← (W1) TAV2 (Transfer data to Accumulator from register V2) 0001010101 055 11 –– Grouping: Interrupt operation Description:Transfers the contents of interrupt control register V2 to register A. Operation: (A) ← (V2)

Rev.3.02 Dec 22, 2006 page 100 of 142 REJ03B0025-0302 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAW3 (Transfer data to Accumulator from register W3) 1001001101 24D 11 – – Grouping: Timer operation Description:Transfers the contents of timer control reg- ister W3 to register A. Operation: (A) ← (W3) TAX (Transfer data to Accumulator from register X) 0001010010 052 11 – – Grouping: Register to register transfer Description:Transfers the contents of register X to reg- ister A. Operation: (A) ← (X) TAW4 (Transfer data to Accumulator from register W4) 1001001110 24E 11 – – Grouping: Timer operation Description:Transfers the contents of timer control reg- ister W4 to register A. Operation: (A) ← (W4) TAY (Transfer data to Accumulator from register Y) 0000011111 01F 11 – – Grouping: Register to register transfer Description:Transfers the contents of register Y to regis- ter A. Operation: (A) ← (Y)

Rev.3.02 Dec 22, 2006 page 101 of 142 REJ03B0025-0302 TBA (Transfer data to register B from Accumulator) 0000001110 00E 11 – – Grouping: Register to register transfer Description:Transfers the contents of register A to regis- ter B. Operation: (B) ← (A) TAZ (Transfer data to Accumulator from register Z) 0001010011 053 11 – – Grouping: Register to register transfer Description:Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. Note: After this instruction is executed, “0” is stored to the high-order 2 bits (A3, A2) of register A. Operation: (A1, A0) ← (Z1, Z0) (A3, A2) ← 0 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TC1A (Transfer data to register C1 from Accumulator) 1010101000 2A8 11 – – Grouping: LCD control operation Description:Transfers the contents of register A to the LCD control register C1. Operation: (C1) ← (A) TC2A (Transfer data to register C2 from Accumulator) 1010101001 2A9 11 – – Grouping: LCD control operation Description:Transfers the contents of register A to the LCD control register C2. Operation: (C2) ← (A)

Rev.3.02 Dec 22, 2006 page 102 of 142 REJ03B0025-0302 TFR1A (Transfer data to register FR1 from Accumulator) 1000101001 229 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to the port output structure control register FR1. Operation: (FR1) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TFR0A (Transfer data to register FR0 from Accumulator) 1000101000 228 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to the port output structure control register FR0. Operation: (FR0) ← (A) TEAB (Transfer data to register E from Accumulator and register B) 0000011010 01A 11 – – Grouping: Register to register transfer Description:Transfers the contents of register B to the high-order 4 bits (E7–E4) of register E, and the contents of register A to the low-order 4 bits (E 3–E0) of register E. Operation: (E7–E4) ← (B) (E3–E0) ← (A) TDA (Transfer data to register D from Accumulator and register B) 0000101001 029 11 – – Grouping: Register to register transfer Description:Transfers the low-order 3 bits (A2–A 0) of register A to register D. Operation: (DR2–DR 0) ← (A2–A0)

Rev.3.02 Dec 22, 2006 page 103 of 142 REJ03B0025-0302 TFR2A (Transfer data to register FR2 from Accumulator) 1000101010 22A 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to the port output structure control register FR2. Operation: (FR2) ← (A) TI1A (Transfer data to register I1 from Accumulator) 1000010111 217 11 –– Grouping: Interrupt operation Description:Transfers the contents of register A to inter- rupt control register I1. Operation: (I1) ← (A) TK0A (Transfer data to register K0 from Accumulator) 1000011011 21B 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to key- on wakeup control register K0. Operation: (K0) ← (A) TK1A (Transfer data to register K1 from Accumulator) 1000010100 214 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to key- on wakeup control register K1. Operation: (K1) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

Rev.3.02 Dec 22, 2006 page 104 of 142 REJ03B0025-0302 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TK2A (Transfer data to register K2 from Accumulator) 1000010101 215 11 –– Grouping: Input/Output operation Description:Transfers the contents of register A to key- on wakeup control register K2. Operation: (K2) ← (A) TL1A (Transfer data to register L1 from Accumulator) 1000001010 20A 11 –– Grouping: LCD control operation Description:Transfers the contents of register A to LCD control register L1. Operation: (L1) ← (A) TL2A (Transfer data to register L2 from Accumulator) 1000001011 20B 11 –– Grouping: LCD control operation Description:Transfers the contents of register A to LCD control register L2. Operation: (L2) ← (A) TL3A (Transfer data to register L3 from Accumulator) 1000001100 20C 11 –– Grouping: LCD control operation Description:Transfers the contents of register A to LCD control register L3. Operation: (L3) ← (A)

Rev.3.02 Dec 22, 2006 page 105 of 142 REJ03B0025-0302 TLCA (Transfer data to register LC from Accumulator) 1000001101 20D 11 – – Grouping: Timer operation Description:Transfers the contents of register A to timer LC and reload register RLC. Operation: (LC) ← (A) (RLC) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TMA j (Transfer data to Memory from Accumulator) 101011 jjjj 2 B j 11 – – Grouping: RAM to register transfer Description:After transferring the contents of register A to M(DP), an exclusive OR operation is per- formed between register X and the value j in the immediate field, and stores the result in register X. Operation: (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 TPAA (Transfer data to register PA from Accumulator) 1010101010 2AA 11 – – Grouping: Timer operation Description:Transfers the contents of lowermost bit (A0) register A to timer control register PA. Operation: (PA0) ← (A0) TMRA (Transfer data to register MR from Accumulator) 1000010110 216 11 –– Grouping: Other operation Description:Transfers the contents of register A to clock control register MR. Operation: (MR) ← (A)

Rev.3.02 Dec 22, 2006 page 106 of 142 REJ03B0025-0302 TPU0A (Transfer data to register PU0 from Accumulator) 1000101101 22D 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to pull- up control register PU0. Operation: (PU0) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TPSAB (Transfer data to Pre-Scaler from Accumulator and register B) 1000110101 235 11 – – Grouping: Timer operation Description:Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS, and transfers the con- tents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS. Operation: (RPS 7–RPS 4) ← (B) (TPS7–TPS 4) ← (B) (RPS 3–RPS 0) ← (A) (TPS3–TPS 0) ← (A) TPU1A (Transfer data to register PU1 from Accumulator) 1000101110 22E 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to pull- up control register PU1. Operation: (PU1) ← (A) TR1AB (Transfer data to register R1 from Accumulator and register B) 1000111111 23F 11 – – Grouping: Timer operation Description:Transfers the contents of register B to the high-order 4 bits (R17–R1 4) of reload regis- ter R1, and the contents of register A to the low-order 4 bits (R13–R1 0) of reload regis- ter R1. Operation: (R17–R1 4) ← (B) (R13–R1 0) ← (A)

Rev.3.02 Dec 22, 2006 page 107 of 142 REJ03B0025-0302 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TRGA (Transfer data to register RG from Accumulator) 1000001001 209 11 – – Grouping: Clock control operation Description:Transfers the contents of register A to regis- ter RG. Operation: (RG) ← (A) TW1A (Transfer data to register W1 from Accumulator) 1000001110 20E 11 –– Grouping: Timer operation Description:Transfers the contents of register A to timer control register W1. Operation: (W1) ← (A) 0000111110 03E 11 – – Grouping: Interrupt operation Description:Transfers the contents of register A to inter- rupt control register V2. Operation: (V2) ← (A) TV2A (Transfer data to register V2 from Accumulator) TV1A (Transfer data to register V1 from Accumulator) 0000111111 03F 11 – – Grouping: Interrupt operation Description:Transfers the contents of register A to inter- rupt control register V1. Operation: (V1) ← (A)

Rev.3.02 Dec 22, 2006 page 108 of 142 REJ03B0025-0302 TW2A (Transfer data to register W2 from Accumulator) 1000001111 20F 11 – – Grouping: Timer operation Description:Transfers the contents of register A to timer control register W2. Operation: (W2) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) Grouping: Timer operation Description:Transfers the contents of register A to timer control register W4. TW4A (Transfer data to register W4 from Accumulator) 1000010001 211 11 – – Operation: (W4) ← (A) TW3A (Transfer data to register W3 from Accumulator) 1000010000 210 11 – – Grouping: Timer operation Description:Transfers the contents of register A to timer control register W3. Operation: (W3) ← (A) TYA (Transfer data to register Y from Accumulator) 0000001100 00C 11 –– Grouping: Register to register transfer Description:Transfers the contents of register A to regis- ter Y. Operation: (Y) ← (A)

Rev.3.02 Dec 22, 2006 page 109 of 142 REJ03B0025-0302 WRST (Watchdog timer ReSeT) 1010100000 2A0 11 – (WDF1) = 1 Grouping: Other operation Description:Clears (0) to the WDF1 flag and skips the next instruction when watchdog timer flag WDF1 is “1.” When the WDF1 flag is “0,” ex- ecutes the next instruction. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction. Operation: (WDF1) = 1 ? (WDF1) ← 0 XAM j (eXchange Accumulator and Memory data) 101101 jjjj 2 D j 11 – – Grouping: RAM to register transfer Description:After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between regis- ter X and the value j in the immediate field, and stores the result in register X. Operation: (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip) 101111 jjjj 2 F j 11 – (Y) = 15 Grouping: RAM to register transfer Description:After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between regis- ter X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the con- tents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. Operation: (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) – 1 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip) 101110 jjjj 2 E j 11 – (Y) = 0 Grouping: RAM to register transfer Description:After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between regis- ter X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y . As a re- sult of addition, when the contents of register Y is 0, the next instruction is skipped. when the contents of register Y is not 0, the next instruction is executed. Operation: (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.3.02 Dec 22, 2006 page 110 of 142 REJ03B0025-0302 (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) (E7–E4) ← (B) (E3–E0) ← (A) (B) ← (E7–E4) (A) ← (E3–E0) (DR 2–DR 0) ← (A2–A0) (A2–A0) ← (DR2–DR 0) (A3) ← 0 (A3, A2) ← 0 (A) ← (X) (A2–A0) ← (SP2–SP 0) (A3) ← 0 (X) ← x x = 0 to 15 (Y) ← y y = 0 to 15 (Z) ← z z = 0 to 3 (Y) ← (Y) + 1 (Y) ← (Y) – 1 (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) – 1 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 TAB TBA TAY TYA TEAB TABE TDA TAD TAZ TAX TASP LXY x, y LZ z INY DEY TAM j XAM j XAMD j XAMI j TMA j MACHINE INSTRUCTIONS (INDEX BY TYPES) 0000011110 0000001110 0000011111 0000001100 0000011010 0000101010 0000101001 0001010001 0001010011 0001010010 0001010000 11x 3 x2 x1 x0 y3 y2 y1 y0 00010010z 1 z0 0000010011 0000010111 101100 jjjj 101101 jjjj 101111 jjjj 101110 jjjj 101011 jjjj 01E 00E 01F 00C 01A 02A 029 051 053 052 050 3xy 048 013 017 2C j 2D j 2Fj 2Ej 2Bj RAM addresses RAM to register transfer Register to register transfer

Skip condition Datailed description Carry flag CY Rev.3.02 Dec 22, 2006 page 111 of 142 REJ03B0025-0302 (Y) = 0 (Y) = 15 (Y) = 15 (Y) = 0 Transfers the contents of register B to register A. Transfers the contents of register A to register B. Transfers the contents of register Y to register A. Transfers the contents of register A to register Y. Transfers the contents of register B to the high-order 4 bits (E 7–E4) of register E, and the contents of regis- ter A to the low-order 4 bits (E3–E0) of register E. Transfers the high-order 4 bits (E7–E4) of register E to register B, and low-order 4 bits (E3–E0) of register E to register A. Transfers the contents of the low-order 3 bits (A2–A0) of register A to register D. Transfers the contents of register D to the low-order 3 bits (A2–A0) of register A. Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. Transfers the contents of register X to register A. Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2–A0) of register A. Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. Loads the value z in the immediate field to register Z. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next in- struction is skipped. When the contents of register Y is not 0, the next instruction is executed. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between reg- ister X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per- formed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per- formed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per- formed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next in- struction is skipped. When the contents of register Y is not 0, the next instruction is executed. After transferring the contents of register A to M(DP), an exclusive OR operation is performed between reg- ister X and the value j in the immediate field, and stores the result in register X.

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.3.02 Dec 22, 2006 page 112 of 142 REJ03B0025-0302 MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) 07n 08p 00A 00B 06n 018 019 007 006 02F 01C 01D 05C 04C 02j 026 025 07n 000111nnnn 0010p 5 p4 p3 p2 p1 p0 0000001010 0000001011 000110nnnn 0000011000 0000011001 0000000111 0000000110 0000101111 0000011100 0000011101 00010111j j 00010011j j 00001000j j 0000100110 0000100101 000111nnnn LA n TABP p AM AMC A n AND OR SC RC SZC CMA RAR SB j RB j SZB j SEAM SEA n Arithmetic operation Comparison operation Bit operation (A) ← n n = 0 to 15 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (Note) (PCL) ← (DR2–DR 0, A3–A0) at (UPTF) = 0 (B) ← (ROM(PC)) 7–4 (A) ← (ROM(PC))3–0 at (UPTF) = 1 (DR2) ← (0) (DR1, DR0) ← (ROM(PC))9, 8 (B) ← (ROM(PC))7–4 (A) ← (ROM(PC))3–0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (A) ← (A) + (M(DP)) (A) ← (A) + (M(DP)) +(CY) (CY) ← Carry (A) ← (A) + n n = 0 to 15 (A) ← (A) AND (M(DP)) (A) ← (A) OR (M(DP)) (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → CY → A 3A2A1A0 (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15 Note: p is 0 to 31 for M34556M4/M4H. p is 0 to 63 for M34556M8/M8H/G8/G8H.

Skip condition Datailed description Carry flag CY Rev.3.02 Dec 22, 2006 page 113 of 142 REJ03B0025-0302 Overflow = 0 (CY) = 0 (Mj(DP)) = 0 j = 0 to 3 (A) = (M(DP)) (A) = n Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. UPTF = 0: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 9 to 0 are the ROM pattern in ad- dress (DR 2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. UPTF = 1: Transfers bits 9, 8 to register D, bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR 2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY re- mains unchanged. Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY . Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation. Takes the AND operation between the contents of register A and the contents of M(DP), and stores the re- sult in register A. Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A. Sets (1) to carry flag CY . Clears (0) to carry flag CY. Skips the next instruction when the contents of carry flag CY is “0.” Stores the one’s complement for register A’s contents in register A. Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0.” Executes the next instruction when the contents of bit j of M(DP) is “1.” Skips the next instruction when the contents of register A is equal to the contents of M(DP). Executes the next instruction when the contents of register A is not equal to the contents of M(DP). Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Executes the next instruction when the contents of register A is not equal to the value n in the immediate field.

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.3.02 Dec 22, 2006 page 114 of 142 REJ03B0025-0302 BL p, a BLA p BM a BML p, a BMLA p RTI RT RTS 011a 6 a5 a4 a3 a2 a1 a0 00111p 4 p3 p2 p1 p0 1p 6 p5 a6 a5 a4 a3 a2 a1 a0 0000010000 1p 6 p5 p4 00p 3 p2 p1 p0 010a 6 a5 a4 a3 a2 a1 a0 00110p 4 p3 p2 p1 p0 1p 6 p5 a6 a5 a4 a3 a2 a1 a0 0000110000 6 p5 p4 00p 3 p2 p1 p0 0001000110 0001000100 0001000101 18a 0Ep 2pa +p +a 010 2pp 1aa 0C p 2pa +p +a 030 2pp 046 044 045 Subroutine operation Return operation MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) (PCL) ← a6–a0 (PCH ) ← p (Note) (PCL) ← a6–a0 (PCH ) ← p (Note) (PCL) ← (DR2–DR 0, A3–A0) (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← 2 (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (Note) (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (Note) (PCL) ← (DR2–DR 0,A3–A0) (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 Branch operation Note: p is 0 to 31 for M34556M4/M4H. p is 0 to 63 for M34556M8/M8H/G8/G8H.

Skip condition Datailed description Carry flag CY Rev.3.02 Dec 22, 2006 page 115 of 142 REJ03B0025-0302 Branch within a page : Branches to address a in the identical page. Branch out of a page : Branches to address a in page p. Branch out of a page : Branches to address (DR

2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in

page p. Call the subroutine in page 2 : Calls the subroutine at address a in page 2. Call the subroutine : Calls the subroutine at address a in page p. Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous de- scription of the LA/LXY instruction, register A and register B to the states just before interrupt. Returns from subroutine to the routine called the subroutine. Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.3.02 Dec 22, 2006 page 116 of 142 REJ03B0025-0302 (INTE) ← 0 (INTE) ← 1 (EXF0) ← 0 V10 = 1: SNZ0 = NOP (A) ← (V1) (V1) ← (A) (A) ← (V2) (V2) ← (A) (A) ← (I1) (I1) ← (A) 004 005 038 03A 054 03F 055 03E 253 217 0000000100 0000000101 0000111000 0000111010 0001010100 0000111111 0001010101 0000111110 1001010011 1000010111 Interrupt operation MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) DI EI SNZ0 SNZI0 TAV1 TV1A TAV2 TV2A TAI1 TI1A Note: p is 0 to 31 for M34556M4/M4H. p is 0 to 63 for M34556M8/M8H/G8/G8H.

Skip condition Datailed description Carry flag CY Rev.3.02 Dec 22, 2006 page 117 of 142 REJ03B0025-0302 0 = 0: (EXF0) = 1 (INT) = “H ” However, I12 = 1 (INT) = “L” However, I12 = 0 Clears (0) to interrupt enable flag INTE, and disables the interrupt. Sets (1) to interrupt enable flag INTE, and enables the interrupt. When V1 0 = 0 : Clears (0) to the EXF0 flag and skips the next instruction when external 0 interrupt request flag EXF0 is “1.” When the EXF0 flag is “0,” executes the next instruction. When V1 0 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register V1) When I12 = 1 : Skips the next instruction when the level of INT pin is “H.” (I12: bit 2 of interrupt control reg- ister I1) When I12 = 0 : Skips the next instruction when the level of INT pin is “L.” Transfers the contents of interrupt control register V1 to register A. Transfers the contents of register A to interrupt control register V1. Transfers the contents of interrupt control register V2 to register A. Transfers the contents of register A to interrupt control register V2. Transfers the contents of interrupt control register I1 to register A. Transfers the contents of register A to interrupt control register I1.

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.3.02 Dec 22, 2006 page 118 of 142 REJ03B0025-0302 (PA) ← (A) (A) ← (W1) (W1) ← (A) (A) ← (W2) (W2) ← (A) (A) ← (W3) (W3) ← (A) (A) ← (W4) (W4) ← (A) (B) ← (TPS 7–TPS 4) (A) ← (TPS3–TPS 0) (RPS 7–RPS 4) ← (B) (TPS7–TPS 4) ← (B) (RPS 3–RPS 0) ← (A) (TPS3–TPS 0) ← (A) (B) ← (T17–T14) (A) ← (T13–T10) (R17–R1 4) ← (B) (T17–T14) ← (B) (R13–R1 0) ← (A) (T13–T10) ← (A) (B) ← (T27–T24) (A) ← (T23–T20) (R2L7–R2L 4) ← (B) (T27–T24) ← (B) (R2L3–R2L 0) ← (A) (T23–T20) ← (A) (R2H 7–R2H 4) ← (B) (R2H 3–R2H 0) ← (A) (R17–R1 4) ← (B) (R13–R1 0) ← (A) (T27–T20) ← (R2L7–R2L 0) (LC) ← (A) (RLC) ← (A) (T1F) ← 0 V12 = 1: SNZT1 = NOP (T2F) ← 0 V13 = 1: SNZT2 = NOP (T3F) ← 0 V20 = 1: SNZT3 = NOP TPAA TAW1 TW1A TAW2 TW2A TAW3 TW3A TAW4 TW4A TABPS TPSAB TAB1 T1AB TAB2 T2AB T2HAB TR1AB T2R2L TLCA SNZT1 SNZT2 SNZT3 Timer operation MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)

Skip condition Datailed description Carry flag CY Rev.3.02 Dec 22, 2006 page 119 of 142 REJ03B0025-0302 2 = 0: (T1F) = 1 V13 = 0: (T2F) =1 V20 = 0: (T3F) = 1 Transfers the contents of register A to timer control register PA. Transfers the contents of timer control register W1 to register A. Transfers the contents of register A to timer control register W1. Transfers the contents of timer control register W2 to register A. Transfers the contents of register A to timer control register W2. Transfers the contents of timer control register W3 to register A. Transfers the contents of register A to timer control register W3. Transfers the contents of timer control register W4 to register A. Transfers the contents of register A to timer control register W4. Transfers the high-order 4 bits of prescaler to register B, and transfers the low-order 4 bits of prescaler to register A. Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS, and transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS. Transfers the high-order 4 bits of timer 1 to register B, and transfers the low-order 4 bits of timer 1 to regis- ter A. Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1, and transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1. Transfers the high-order 4 bits of timer 2 to register B, and transfers the low-order 4 bits of timer 2 to regis- ter A. Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2L, and transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2L. Transfers the contents of register B to the high-order 4 bits of timer 2 reload register R2H, and transfers the contents of register A to the low-order 4 bits of timer 2 reload register R2H. Transfers the contents of register B to the high-order 4 bits of timer 1 reload register R1, and transfers the contents of register A to the low-order 4 bits of timer 1 reload register R1. Transfers the contents of timer 2 reload register R2L to timer 2. Transfers the contents of register A to timer LC and timer LC reload register RLC. When V1 2 = 0 : Clears (0) to the T1F flag and skips the next instruction when timer 1 interrupt request flag T1F is “1”. When the T1F flag is “0”, executes the next instruction. When V1 2 = 1 : This instruction is equivalent to the NOP instruction. (V12: bit 2 of interrupt control register V1) When V1 3 = 0 : Clears (0) to the T2F flag and skips the next instruction when timer 2 interrupt request flag T2F is “1”. When the T2F flag is “0”, executes the next instruction. When V1 3 = 1 : This instruction is equivalent to the NOP instruction. (V13: bit 3 of interrupt control register V1) When V2 0 = 0 : Clears (0) to the T3F flag and skips the next instruction when timer 3 interrupt request flag T3F is “1”. When the T3F flag is “0”, executes the next instruction. When V2 0 = 1 : This instruction is equivalent to the NOP instruction. (V20: bit 0 of interrupt control register V2)

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.3.02 Dec 22, 2006 page 120 of 142 REJ03B0025-0302 (A) ← (P0) (P0) ← (A) (A) ← (P1) (P1) ← (A) (A) ← (P2) (P2) ← (A) (D) ← 1 (D(Y)) ← 0 (Y) = 0 to 7 (D(Y)) ← 1 (Y) = 0 to 7 (D(Y)) = 0 ? (Y) = 0 to 5 (C) ← 0 (C) ← 1 (A) ← (PU0) (PU0) ← (A) (A) ← (PU1) (PU1) ← (A) (A) ← (K0) (K0) ← (A) (A) ← (K1) (K1) ← (A) (A) ← (K2) (K2) ← (A) (FR0) ← (A) (FR1) ← (A) (FR2) ← (A) Input/Output operation

Skip condition Datailed description Carry flag CY Rev.3.02 Dec 22, 2006 page 121 of 142 REJ03B0025-0302 Transfers the input of port P0 to register A. Outputs the contents of register A to port P0. Transfers the input of port P1 to register A. Outputs the contents of register A to port P1. Transfers the input of port P2 to register A. Outputs the contents of register A to port P2. Sets (1) to all port D. Clears (0) to a bit of port D specified by register Y . Sets (1) to a bit of port D specified by register Y. Skips the next instruction when a bit of port D specified by register Y is “0.” Executes the next instruction when a bit of port D specified by register Y is “1.” Clears (0) to port C. Sets (1) to port C. Transfers the contents of pull-up control register PU0 to register A. Transfers the contents of register A to pull-up control register PU0. Transfers the contents of pull-up control register PU1 to register A. Transfers the contents of register A to pull-up control register PU1. Transfers the contents of key-on wakeup control register K0 to register A. Transfers the contents of register A to key-on wakeup control register K0. Transfers the contents of key-on wakeup control register K1 to register A. Transfers the contents of register A to key-on wakeup control register K1. Transfers the contents of key-on wakeup control register K2 to register A. Transfers the contents of register A to key-on wakeup control register K2. Transferts the contents of register A to port output structure control register FR0. Transferts the contents of register A to port output structure control register FR1. Transferts the contents of register A to port output structure control register FR2. (D(Y)) = 0 However, (Y)=0 to 5

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.3.02 Dec 22, 2006 page 122 of 142 REJ03B0025-0302 (A) ← (L1) (L1) ← (A) (L2) ← (A) (L3) ← (A) (C1) ← (A) (C2) ← (A) RC oscillator selected (A) ← (MR) (MR) ← (A) (RG) ← (A) (PC) ← (PC) + 1 Transition to clock operating mode Transition to RAM back-up mode POF, POF2 instructions valid (P) = 1 ? (WDF1) = 1 ? (WDF1) ← 0 Stop of watchdog timer function enabled System reset (UPTF) ← 0 (UPTF) ← 1 At power down mode, voltage drop detection circuit valid MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) LCD operation Clock operation Other operation Note: SVDE instruction can be used only in H version.

Skip condition Datailed description Carry flag CY Rev.3.02 Dec 22, 2006 page 123 of 142 REJ03B0025-0302 (P) = 1 (WDF1) = 1 Transfers the contents of LCD control register L1 to register A. Transfers the contents of register A to LCD control register L1. Transfers the contents of register A to LCD control register L2. Transfers the contents of register A to LCD control register L3. Transfers the contents of register A to LCD control register C1. Transfers the contents of register A to LCD control register C2. Selects the RC oscillation circuit for main clock, stops the on-chip oscillator (internal oscillator). Transfers the contents of clock control regiser MR to register A. Transfers the contents of register A to clock control register MR. Transfers the contents of register A to clock control register RG. No operation; Adds 1 to program counter value, and others remain unchanged. Puts the system in clock operating mode by executing the POF instruction after executing the EPOF instruction. Puts the system in RAM back-up mode by executing the POF2 instruction after executing the EPOF instruction. Makes the immediate after POF or POF2 instruction valid by executing the EPOF instruction. Skips the next instruction when the P flag is “1”. After skipping, the P flag remains unchanged. Clears (0) to the WDF1 flag and skips the next instruction when watchdog timer flag WDF1 is “1.” When the WDF1 flag is “0”, executes the next instruction. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction. Stops the watchdog timer function by the WRST instruction. System reset occurs. Clears (0) to the high-order bit reference enable flag UPTF. Sets (1) to the high-order bit reference enable flag UPTF. Validates the voltage drop detection circuit at power down (clock operating mode and RAM back-up mode).

Rev.3.02 Dec 22, 2006 page 124 of 142 REJ03B0025-0302 D 3–D 0 Hex. notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A B C D E F D 9–D 4 NOP SRST POF SNZP DI EI RC SC POF2 AM AMC TYA TBA 000001 BLA CLD INY RD SD DEY AND OR TEAB CMA RAR TAB TAY 000010 SZB SZB SZB SZB SZD SEAn SEAM TDA TABE SZC 000011 BMLA SNZ0 SNZI0 TV2A TV1A 000100 RT RTS RTI LZ LZ LZ LZ RB RB RB RB 000101 TASP TAD TAX TAZ TAV1 TAV2 RUPT SUPT EPOF SB SB SB SB 000110 A A A A A A A A A A A A A A A A 000111 LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA 001000 TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP 001001 TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP 001010 TABP 32* TABP 33* TABP 34* TABP 35* TABP 36* TABP 37* TABP 38* TABP 39* TABP 40* TABP 41* TABP 42* TABP 43* TABP 44* TABP 45* TABP 46* TABP 47* 001011001100 001101 001110 001111 BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM 010000 010111 011000 011111 18–1F B B B B B B B B B B B B B B B B BL BML BLA BMLA SEA SZD The second word 1p paaa aaaa 1p paaa aaaa 1p pp00 pppp 1p pp00 pppp 00 0111 nnnn 00 0010 1011

• * cannot be used in the M3455xM4/M4H. 10–17 000000 The above table shows the relationship between machine language codes and machine language instructions. D3–D 0 show the low-order 4 bits of the machine language code, and D9–D 4 show the high-order 6 bits of the machine language code. The hexadecimal representa- tion of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below. TABP 48* TABP 49* TABP 50* TABP 51* TABP 52* TABP 53* TABP 54* TABP 55* TABP 56* TABP 57* TABP 58* TABP 59* TABP 60* TABP 61* TABP 62* TABP 63*

Rev.3.02 Dec 22, 2006 page 125 of 142 REJ03B0025-0302 INSTRUCTION CODE TABLE (continued) TRGA TL1A TL2A TL3A TLCA TW1A TW2A TW3A TW4A TK1A TK2A TMRA TI1A TK0A T1AB T2AB TPSAB TR1AB TAL1 TAW1 TAW2 TAW3 TAW4 TAMR TAI1 TAK0 TAPU0 TAK1 TAK2 TAPU1 IAP0 IAP1 IAP2 TAB1 TAB2 TABPS SNZT1 SNZT2 SNZT3 RCP SCP SVDE** T2HAB T2R2L CRCK DWDT WRST TC1A TC2A TPAA TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA BL BML BLA BMLA SEA SZD The second word 1p paaa aaaa 1p paaa aaaa 1p pp00 pppp 1p pp00 pppp 00 0111 nnnn 00 0010 1011 OP0A OP1A OP2A TFR0A TFR1A TFR2A TPU0A TPU1A D 3–D 0 Hex. notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A B C D E F D 9–D 4 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 111111 30–3F 100000 The above table shows the relationship between machine language codes and machine language instructions. D3–D 0 show the low- order 4 bits of the machine language code, and D9–D 4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below.

• ** can be used only in the M3455xM4H/M8H/G8H.

Rev.3.02 Dec 22, 2006 page 126 of 142 REJ03B0025-0302 Input voltage P0, P1, P2, D 0–D 5, RESET , INT, XIN, XCIN Input voltage CNTR Output voltage P0, P1, P2, D0–D 7, RESET , CNTR Output voltage C, XOUT , XCOUT Output voltage SEG0–SEG 28, COM 0–COM 3 Power dissipation Operating temperature range Storage temperature range Conditions Output transistors in cut-off state Ta = 25 °C Symbol VDD VI VI VO VO VO Pd Topr Tstg Unit V V V V V V mW Ratings –0.3 to 6.5 –0.3 to VDD +0.3 –0.3 to VDD +0.3 –0.3 to VDD +0.3 –0.3 to VDD +0.3 –0.3 to VDD +0.3 300 –20 to 85 –40 to 125

ELECTRICAL CHARACTERISTICS

(1) Mask ROM version ABSOLUTE MAXIMUM RATINGS (Mask ROM version)

Rev.3.02 Dec 22, 2006 page 127 of 142 REJ03B0025-0302 RECOMMENDED OPERATING CONDITIONS 1 (Mask ROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) Symbol VDD VDD VDD VRAM VSS VLC3 VIH VIL IOH (peak) IOH (avg) IOL (peak) IOL (avg) ΣIOH (avg) ΣIOL (avg) Parameter Supply voltage (when ceramic resonator is used) Supply voltage (when quartz-crystal/on-chip oscillation is used) Supply voltage (when RC oscillation is used) RAM back-up voltage Supply voltage LCD power supply (Note 1) “H ” level input voltage “L” level input voltage “H ” level peak output current “H ” level average output current (Note 2) “L” level peak output current “L” level average output current (Note 2) “H ” level total average current “L” level total average current Notes 1: At 1/2 bias: VLC1 = VLC2 = (1/2)•VLC3 At 1/3 bias: VLC1 = (1/3)•VLC3, VLC2 = (2/3)•VLC3 2: The average output current is the average value during 100 ms. UnitConditions f(STCK) ≤ 6 MHz f(STCK) ≤ 4.4 MHz f(STCK) ≤ 2.2 MHz f(STCK) ≤ 1.1 MHz f(STCK) ≤ 4.4 MHz at RAM back-up mode P0, P1, P2, D0–D 5 XIN, XCIN RESET INT CNTR P0, P1, P2, D 0–D 5 XIN, XCIN RESET INT CNTR P0, P1, P2, D 0–D 5 C CNTR P0, P1, P2, D 0–D 5 C CNTR P0, P1, P2, D0–D 7, C CNTR RESET P0, P1, P2, D0–D 7, C CNTR RESET P0, P1, P2, D0–D 5, C, CNTR P0, P1, P2, D0–D 5, C, CNTR D 6, D7, RESET Max. 5.5 5.5 5.5 5.5 5.5 5.5 V DD VDD VDD VDD VDD VDD 0.2VDD 0.3VDD 0.3VDD 0.15VDD 0.15VDD –20 –10 –30 –15 –10 –20 –10 –40 Limits Min. 2.7 1.8 1.8 2.7 1.6 1.8 0.8V DD 0.7VDD 0.85VDD 0.85VDD 0.8VDD Typ. VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V V V V V V V V V mA mA mA mA mA mA

Rev.3.02 Dec 22, 2006 page 128 of 142 REJ03B0025-0302 f(XIN) f(XIN) f(XIN) f(XCIN) f(CNTR) tw(CNTR) TPON Oscillation frequency (with a ceramic resonator) Oscillation frequency (at RC oscillation) (Note) Oscillation frequency (with a ceramic oscillation selected, external clock input) Oscillation frequency (sub-clock) Timer external input frequency Timer external input period (“H ” and “L” pulse width) Power-on reset circuit valid supply voltage rising time Conditions MHz MHz MHz kHz Hz s µs Max. 4.4 2.2 1.1 4.4 2.2 4.4 4.4 4.8 3.2 1.6 0.8 4.8 3.2 1.6 4.8 3.2 4.8 f(STCK)/6 100 Limits Through mode Frequency/2 mode Frequency/4 mode Frequency/8 mode VDD = 2.7 to 5.5 V Through mode Frequency/2 mode Frequency/4 mode Frequency/8 mode Quartz-crystal oscillator CNTR CNTR V DD = 0 → 1.8 V Min. 3/f(STCK) Typ. RECOMMENDED OPERATING CONDITIONS 2 (Mask ROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) ParameterSymbol Unit Note: The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits. VDD = 4 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2 to 5.5 V VDD = 1.8 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2 to 5.5 V VDD = 1.8 to 5.5 V VDD = 2 to 5.5 V VDD = 1.8 to 5.5 V VDD = 1.8 to 5.5 V VDD = 4 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2 to 5.5 V VDD = 1.8 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2 to 5.5 V VDD = 1.8 to 5.5 V VDD = 2 to 5.5 V VDD = 1.8 to 5.5 V VDD = 1.8 to 5.5 V

Rev.3.02 Dec 22, 2006 page 129 of 142 REJ03B0025-0302 4.4 2.2 f(STCK) [MHz] 21.8 2.7 5.5 4.5 VDD [V] at ceramic oscillation (Mask ROM version) 1.1 4.4 f(STCK) [MHz] 2.7 5.5 VDD [V] at RC oscillation (Mask ROM version) 4.8 3.2 0.8 f(STCK) [MHz] 2 2.7 5.5 4.5 VDD [V] at external clock oscillation (Mask ROM version) 1.8 1.6 f(STCK) [kHz] 1.8 5.5 VDD [V] at quartz-crystal oscillation (Mask ROM version) Recommended operating conditions Recommended operating conditions Recommended operating conditions Recommended operating conditions System clock (STCK) operating condition map (Mask ROM version)

Rev.3.02 Dec 22, 2006 page 130 of 142 REJ03B0025-0302 ELECTRICAL CHARACTERISTICS 1 (Mask ROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) VOH VOH VOL VOL IIH IIL R PU VT+ – VT– VT+ – VT– VT+ – VT– f(RING) ∆f(XIN) RCOM RSEG RVLC “H ” level output voltage P0, P1, P2, D0–D 5 “H ” level output voltage C, CNTR “L” level output voltage P0, P1, P2, D0–D 7, C, CNTR “L” level output voltage RESET “H ” level input current P0, P1, P2, D0–D 5, XIN, XCIN, RESET CNTR, INT “L” level input current P0, P1, P2, D0–D 5, XIN, XCIN, RESET CNTR, INT Pull-up resistor value P0, P1, RESET Hysteresis RESET Hysteresis INT Hysteresis CNTR On-chip oscillator clock frequency Frequency error (with RC oscillation, error of external R, C not included ) (Note 1) COM output impedance (Note 2) SEG output impedance (Note 2) Internal resistor for LCD power supply V V V V µA µA kΩ V V V kHz kΩ kΩ kΩ Test conditions VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VI = VDD VI = 0 V P0, P1 No pull-up VI = 0 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V ± 10 %, Ta = 25 °C VDD = 3 V ± 10 %, Ta = 25 °C VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V When dividing resistor 2r ✕ 3 selected When dividing resistor 2r ✕ 2 selected When dividing resistor r ✕ 3 selected When dividing resistor r ✕ 2 selected Limits Max. 0.9 1.4 0.9 0.6 0.9 125 250 700 400 ±17 ±17 7.5 7.5 960 640 480 320 IOH = –10 mA IOH = –3 mA IOH = –5 mA IOH = –1 mA IOH = –20 mA IOH = –6 mA IOH = –10 mA IOH = –3 mA IOL = 15 mA IOL = 5 mA IOL = 9 mA IOL = 3 mA IOL = 5 mA IOL = 1 mA IOL = 2 mA VDD = 5 V VDD = 3 V Min. 4.1 2.1 2.4 4.1 2.1 2.4 200 100 300 200 150 100 Typ. Symbol Parameter Unit 120 0.4 0.6 0.3 0.2 0.2 500 250 1.5 1.5 480 320 240 160 Notes 1: When RC oscillation is used, use the external 33 pF capacitor (C). 2: The impedance state is the resistor value of the output voltage. at VLC3 level output: VO = 0.8 VLC3 at VLC2 level output: VO = 0.8 VLC2 at VLC1 level output: VO = 0.2 VLC2 + VLC1 at VSS level output: VO = 0.2 VSS

Rev.3.02 Dec 22, 2006 page 131 of 142 REJ03B0025-0302 ELECTRICAL CHARACTERISTICS 2 (Mask ROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) IDD Supply currentat active mode (with a ceramic resonator) at active mode (with an on-chip oscillator) at active mode (with a quartz-crystal oscillator) at clock operation mode (POF instruction execution) at RAM back-up mode (POF2 instruction execution) mA mA mA µA µA µA µA µA µA Test conditions VDD = 5 V f(XIN) = 6 MHz f(RING) = stop f(X CIN) = stop VDD = 5 V f(XIN) = 4 MHz f(RING) = stop f(X CIN) = stop VDD = 3 V f(XIN) = 4 MHz f(RING) = stop f(XCIN) = stop VDD = 5 V f(XIN) = stop f(RING) = active f(X CIN) = stop VDD = 3 V f(XIN) = stop f(RING) = active f(X CIN) = stop VDD = 5 V f(XIN) = stop f(RING) = stop f(XCIN) = 32 kHz VDD = 3 V f(XIN) = stop f(RING) = stop f(X CIN) = 32 kHz f(XCIN) = 32 kHz Ta = 25 °C VDD = 5 V VDD = 3 V Limits Max. 2.4 2.6 3.2 4.4 1.8 2.4 3.2 0.6 0.8 1.0 1.4 100 120 160 240 Min. Typ. 1.2 1.3 1.6 2.2 0.9 1.2 1.6 0.3 0.4 0.5 0.7 120 0.1 Symbol Parameter Unit f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(RING)/8 f(STCK) = f(RING)/4 f(STCK) = f(RING)/2 f(STCK) = f(RING) f(STCK) = f(RING)/8 f(STCK) = f(RING)/4 f(STCK) = f(RING)/2 f(STCK) = f(RING) f(STCK) = f(X CIN)/8 f(STCK) = f(XCIN)/4 f(STCK) = f(XCIN)/2 f(STCK) = f(XCIN) f(STCK) = f(XCIN)/8 f(STCK) = f(XCIN)/4 f(STCK) = f(XCIN)/2 f(STCK) = f(XCIN) VDD = 5 V VDD = 3 V

Rev.3.02 Dec 22, 2006 page 132 of 142 REJ03B0025-0302 VOLTAGE DROP DETECTION CIRCUIT CHARACTERISTICS (Mask ROM version: Ta = –20 °C to 85 °C, unless otherwise noted) Test conditions Ta = 25 °C -20 °C ≤ Ta < 0 °C 0 °C ≤ Ta < 50 °C 50 °C ≤ Ta ≤ 85 °C Ta = 25 °C -20 °C ≤ Ta < 0 °C 0 °C ≤ Ta < 50 °C 50 °C ≤ Ta ≤ 85 °C VDD = 5 V VDD = 3 V VDD → (VRST – – 0.1 V) Parameter Detection voltage (reset occurs) (Note 2) Detection voltage (reset release) (Note 3) Detection voltage hysteresis Operation current (Note 4) Detection time (Note 5) Symbol VRST – VRST + VRST + – VRST – IRST TRST Limits UnitMin. 1.6 1.7 1.4 1.2 1.7 1.8 1.5 1.3 Typ. 1.8 1.9 0.1 0.2 Max. 2.3 2.2 1.9 2.1 2.4 2.3 100 1.2 V V V µA ms Notes 1: The voltage drop detection circuit is equipped with only the H version. 2: The detection voltage (VRST –) is defined as the voltage when reset occurs when the supply voltage (VDD ) is falling. 3: The detection voltage (VRST +) is defined as the voltage when reset is released when the supply voltage (VDD ) is rising from reset occurs. 4: In the H version, IRST is added to IDD (power current). 5: The detection time (TRST ) is defined as the time until reset occurs when the supply voltage (VDD ) is falling to [VRST – – 0.1 V]. 6: The detection voltages (VRST +, VRST –) are set up lower than the minimum value of the supply voltage of the recommended operating conditions. As for details, refer to the LIST OF PRECAUTIONS.

Rev.3.02 Dec 22, 2006 page 133 of 142 REJ03B0025-0302 Input voltage P0, P1, P2, D0–D 5, RESET , INT, XIN, XCIN Input voltage CNTR Output voltage P0, P1, P2, D0–D 7, RESET , CNTR Output voltage C, XOUT , XCOUT Output voltage SEG0–SEG 28, COM 0–COM 3 Power dissipation Operating temperature range Storage temperature range Conditions Output transistors in cut-off state Ta = 25 °C Symbol V DD VI VI VO VO VO Pd Topr Tstg Unit V V V V V V mW Ratings –0.3 to 4.0 –0.3 to VDD +0.3 –0.3 to VDD +0.3 –0.3 to VDD +0.3 –0.3 to VDD +0.3 –0.3 to VDD +0.3 300 –20 to 85 –40 to 125 (2) One Time PROM version ABSOLUTE MAXIMUM RATINGS (One Time PROM version)

Rev.3.02 Dec 22, 2006 page 134 of 142 REJ03B0025-0302 RECOMMENDED OPERATING CONDITIONS 1 (One Time PROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 3.6 V, unless otherwise noted) Symbol VDD VDD VDD VRAM VSS VLC3 VIH VIL IOH (peak) IOH (avg) IOL (peak) IOL (avg) ΣIOH (avg) ΣIOL (avg) Parameter Supply voltage (when ceramic resonator is used) Supply voltage (when quartz-crystal/on-chip oscillator is used) Supply voltage (when RC oscillation is used) RAM back-up voltage Supply voltage LCD power supply (Note 1) “H ” level input voltage “L” level input voltage “H ” level peak output current “H ” level average output current (Note 2) “L” level peak output current “L” level average output current (Note 2) “H ” level total average current “L” level total average current Notes 1: At 1/2 bias: VLC1 = VLC2 = (1/2)•VLC3 At 1/3 bias: VLC1 = (1/3)•VLC3, VLC2 = (2/3)•VLC3 2: The average output current is the average value during 100 ms. UnitConditions f(STCK) ≤ 4.4 MHz f(STCK) ≤ 2.2 MHz f(STCK) ≤ 1.1 MHz f(STCK) ≤ 4.4 MHz at RAM back-up mode P0, P1, P2, D0–D 5 XIN, XCIN RESET INT CNTR P0, P1, P2, D 0–D 5 XIN, XCIN RESET INT CNTR P0, P1, P2, D 0–D 5 C, CNTR P0, P1, P2, D0–D 5 C, CNTR P0, P1, P2, D0–D 7, C, CNTR RESET P0, P1, P2, D0–D 7, C, CNTR RESET P0, P1, P2, D0–D 5, C, CNTR P0, P1, P2, D0–D 5, C, CNTR D 6, D7, RESET Max. 3.6 3.6 3.6 3.6 3.6 V DD VDD VDD VDD VDD VDD 0.2VDD 0.3VDD 0.3VDD 0.15VDD 0.15VDD –10 –15 –10 –40 Limits Min. 2.7 1.8 1.8 2.7 1.6 1.8 0.8V DD 0.7VDD 0.85VDD 0.85VDD 0.8VDD Typ. VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V V V V V V V V V mA mA mA mA mA mA

Rev.3.02 Dec 22, 2006 page 135 of 142 REJ03B0025-0302 f(XIN) f(XIN) f(XIN) f(XCIN) f(CNTR) tw(CNTR) TPON Oscillation frequency (with a ceramic resonator) Oscillation frequency (at RC oscillation) (Note) Oscillation frequency (with a ceramic oscillation circuit selected, external clock input) Oscillation frequency (with a quartz-crystal oscillator) Timer external input frequency Timer external input period (“H ” and “L” pulse width) Power-on reset circuit valid supply voltage rising time Conditions MHz MHz MHz kHz Hz s µs Max. 4.4 2.2 1.1 4.4 2.2 4.4 4.4 3.2 1.6 0.8 4.8 3.2 1.6 4.8 3.2 4.8 f(STCK)/6 100 Limits Through mode Frequency/2 mode Frequency/4 mode Frequency/8 mode VDD = 2.7 to 3.6 V Through mode Frequency/2 mode Frequency/4 mode Frequency/8 mode Quartz-crystal oscillator CNTR CNTR VDD = 0 → 1.8 V Min. 3/f(STCK) Typ. RECOMMENDED OPERATING CONDITIONS 2 (One Time PROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 3.6 V, unless otherwise noted) ParameterSymbol Unit Note: The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits. VDD = 2.7 to 3.6 V VDD = 2 to 3.6 V VDD = 1.8 to 3.6 V VDD = 2.7 to 3.6 V VDD = 2 to 3.6 V VDD = 1.8 to 3.6 V VDD = 2 to 3.6 V VDD = 1.8 to 3.6 V VDD = 1.8 to 3.6 V VDD = 2.7 to 3.6 V VDD = 2 to 3.6 V VDD = 1.8 to 3.6 V VDD = 2.7 to 3.6 V VDD = 2 to 3.6 V VDD = 1.8 to 3.6 V VDD = 2 to 3.6 V VDD = 1.8 to 3.6 V VDD = 1.8 to 3.6 V

Rev.3.02 Dec 22, 2006 page 136 of 142 REJ03B0025-0302 System clock (STCK) operating condition map (One Time PROM version) 2.2 1.8 V 4.4 2.7 3.6 3.6 DD [V] at ceramic oscillation (One Time PROM version) f(STCK) [MHz] 2.0 2.0 1.1 V 4.4 2.7 DD [V] at RC oscillation (One Time PROM version) f(STCK) [MHz] 1.8 V 2.7 DD [V] at external clock oscillation (One Time PROM version) f(STCK) [MHz] 3.6 3.2 1.6 0.8 1.8 V 3.6 DD [V] at quartz-crystal oscillation (One Time PROM version) f(STCK) [kHz] Recommended operating conditions Recommended operating conditions Recommended operating conditions Recommended operating conditions

Rev.3.02 Dec 22, 2006 page 137 of 142 REJ03B0025-0302 (One Time PROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 3.6 V, unless otherwise noted) VOH VOH VOL VOL IIH IIL R PU VT+ – VT– VT+ – VT– VT+ – VT– f(RING) ∆f(XIN) RCOM RSEG RVLC I DD “H ” level output voltage P0, P1, P2, D0–D 5 “H ” level output voltage C, CNTR “L” level output voltage P0, P1, P2, D 0–D 7, C, CNTR “L” level output voltage RESET “H ” level input current P0, P1, P2, D 0–D 5, XIN, XCIN, RESET CNTR, INT “L” level input current P0, P1, P2, D 0–D 5, XIN, XCIN, RESET CNTR, INT Pull-up resistor value P0, P1, RESET Hysteresis RESET Hysteresis INT Hysteresis CNTR On-chip oscillator clock frequency Frequency error (with RC oscillation, error of external R, C not included ) (Note 1) COM output impedance (Note 2) SEG output impedance (Note 2) Internal resistor for LCD power supply Supply current V V V V µA µA kΩ V V V kHz kΩ kΩ kΩ mA µA µA µA µA Test conditions VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VI = VDD VI = 0 V P0, P1 No pull-up VI = 0 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V ± 10 %, Ta = 25 °C VDD = 3 V VDD = 3 V When dividing resistor 2r ✕ 3 selected When dividing resistor 2r ✕ 2 selected When dividing resistor r ✕ 3 selected When dividing resistor r ✕ 2 selected VDD = 3 V f(XIN) = 4 MHz f(RING) = stop f(X CIN) = stop VDD = 3 V f(XIN) = stop f(RING) = active f(XCIN) = stop VDD = 3 V f(XIN) = stop f(RING) = stop f(X CIN) = 32 kHz VDD = 3 V f(XCIN) = 32 kHz Ta = 25 °C VDD = 3 V Limits Max. 1.4 0.9 0.9 250 400 ±17 960 640 480 320 0.6 0.8 1.2 1.8 IOH = –5 mA IOH = –1 mA IOH = –10 mA IOH = –3 mA IOL = 9 mA IOL = 3 mA IOL = 2 mA Min. 2.1 2.4 2.1 2.4 100 300 200 150 100 Typ. Symbol Parameter Unit 120 0.4 0.3 0.2 250 480 320 240 160 0.3 0.4 0.6 0.9 0.1 Notes 1: When RC oscillation is used, use the external 33 pF capacitor (C). 2: The impedance state is the resistor value of the output voltage. at VLC3 level output: VO = 0.8 VLC3 at VLC2 level output: VO = 0.8 VLC2 at VLC1 level output: VO = 0.2 VLC2 + VLC1 at VSS level output: VO = 0.2 VSS f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(RING)/8 f(STCK) = f(RING)/4 f(STCK) = f(RING)/2 f(STCK) = f(RING) f(STCK) = f(X CIN)/8 f(STCK) = f(XCIN)/4 f(STCK) = f(XCIN)/2 f(STCK) = f(XCIN) at active mode (with a ceramic resonator) at active mode (with an on-chip oscillator) at active mode (with a quartz-crystal oscillator) at clock operation mode (POF instruction execution) at RAM back-up mode (POF2 instruction execution)

Rev.3.02 Dec 22, 2006 page 138 of 142 REJ03B0025-0302 VOLTAGE DROP DETECTION CIRCUIT CHARACTERISTICS (One Time PROM version: Ta = –20 °C to 85 °C, unless otherwise noted) Test conditions Ta = 25 °C -20 °C ≤ Ta < 0 °C 0 °C ≤ Ta < 50 °C 50 °C ≤ Ta ≤ 85 °C Ta = 25 °C -20 °C ≤ Ta < 0 °C 0 °C ≤ Ta < 50 °C 50 °C ≤ Ta ≤ 85 °C VDD = 3 V VDD → (VRST – – 0.1 V) Parameter Detection voltage (reset occurs) (Note 2) Detection voltage (reset release) (Note 3) Detection voltage hysteresis Operation current (Note 4) Detection time (Note 5) Symbol VRST – VRST + VRST + – VRST – IRST TRST Limits UnitMin. 1.6 1.7 1.4 1.2 1.7 1.8 1.5 1.3 Typ. 1.8 1.9 0.1 0.2 Max. 2.3 2.2 1.9 2.1 2.4 2.3 1.2 V V V µA ms Notes 1: The voltage drop detection circuit is equipped with only the H version. 2: The detection voltage (VRST –) is defined as the voltage when reset occurs when the supply voltage (VDD ) is falling. 3: The detection voltage (VRST +) is defined as the voltage when reset is released when the supply voltage (VDD ) is rising from reset occurs. 4: In the H version, IRST is added to IDD (supply current). 5: The detection time (TRST ) is defined as the time until reset occurs when the supply voltage (VDD ) is falling to [VRST – – 0.1 V]. 6: The detection voltages (VRST +, VRST –) are set up lower than the minimum value of the supply voltage of the recommended operating conditions. As for details, refer to the LIST OF PRECAUTIONS.

Rev.3.02 Dec 22, 2006 page 139 of 142 REJ03B0025-0302 Parameter Pin (signal) name Machine cycle Mi Mi+1 D 0–D 7 System clock Port D output Port D input Ports P0, P1, P2 output Ports P0, P1, P2 input D 0–D 5 INTInterrupt input P00–P03 P10–P13 P00–P03 P10–P13 P20–P23 P20–P23

Rev.3.02 Dec 22, 2006 page 140 of 142 REJ03B0025-0302 Table 19 Product of built-in PROM version PROM size (✕ 10 bits) 8192 words RAM size (✕ 4 bits) 288 wordsM34556G8FP M34556G8HFP One Time PROM [shipped in blank]42P2R-A BUILT-IN PROM VERSION In addition to the mask ROM versions, the 4556 Group has the One Time PROM versions whose PROMs can only be written to and not be erased. The built-in PROM version has functions similar to those of the mask ROM versions, but it has PROM mode that enables writing to built-in PROM. (1) PROM mode The 4556 Group has a PROM mode in addition to a normal opera- tion mode. It has a function to serially input/output the command codes, addresses, and data required for operation (e.g., read and program) on the built-in PROM using only a few pins. This mode can be selected by muddog entry after powering on the V DD pin. In the PROM mode, three types of software commands (read, pro- gram, and program verify) can be used. Clock-synchronous serial I/O is used, beginning from the LSB (LSB first). (2) Notes on handling ➀ For the One Time PROM version shipped in blank, Renesas corp. does not perform PROM writing test and screening in the assembly process and following processes. In order to improve reliability after writing, performing writing and test according to the flow shown in Figure 60 before using is recommended (Prod- ucts shipped in blank: PROM contents is not written in factory when shipped). (3) Difference between Mask ROM version and One Time PROM version Mask ROM version and One Time PROM version have some dif- ference of the following characteristics within the limits of an electrical property by difference of a manufacture process, built- in ROM, and a layout pattern.

• a characteristic value
• a margin of operation
• the amount of noise-proof
• noise radiation, etc., Accordingly, be careful of them when swithcing. Fig. 68 Flow of writing and test of the product shipped in blank ROM typePackagePart number Table 19 shows the product of built-in PROM version. Figure 61 shows the pin configurations of built-in PROM versions. The One Time PROM version has pin-compatibility with the mask ROM version. Writing with PROM programmer Screening (Leave at 150 °C for 40 hours) (Note) V e r i f y t e s t w i t h P R O M p r o g r a m m e r Function test in target device S i n c e t h e s c r e e n i n g t e m p e r a t u r e i s h i g h e r t h a n s t o r a g e t e m p e r a t u r e n e v e r e x p o s e t h e m i c r o c o m p u t e r t o C e x c e e d i n g h o u r s N o t e :

Rev.3.02 Dec 22, 2006 page 141 of 142 REJ03B0025-0302 Fig. 69 Pin configuration of built-in PROM version PIN CONFIGURATION (TOP VIEW) M34556G8FP M34556G8HFP XIN XOUT CNV SS XCIN/D6 XCOUT /D7 RESET COM 0 COM 1 COM 2 COM 3 SEG 0/VLC3 SEG 1/VLC2 SEG 2/VLC1 SEG 3 SEG 4 SEG 5 SEG 6 SEG 7 SEG 8 SEG 9 SEG 10 VSS VDD C/CNTR D 5/INT D 4 D 3 D 2 D 1 D 0 P13/SEG 28 P12/SEG 27 P11/SEG 26 P10/SEG 25 P03/SEG 24 P02/SEG 23 P01/SEG 22 P00/SEG 21 P23/SEG 20 P22/SEG 19 P21/SEG 18 P20/SEG 17 VDD VSSXIN XOUT VPP SCLK VDD PGM VDD RESET SDA ROM CODE ACCESS PROTECTION We would like to support a simple ROM code protection function that prevents a party other than the ROM-code owner to read and reprogram the built-in PROM code of the MCU. First, Programmers must check the ID-code of the MCU. If the ID-code is not blank, Programmer verifies it with the input ID- code. When the ID-codes do not match, Programmer will reject all further operations. The MCU has each 10 bits of dedicated ROM spaces in address 0090 16 to 009616, as an ID-code (referred to as “the ID-code”) en- abling a Programmer to verify with the input ID-code and validate further operations. Fig. 70 ROM-Code Protection ID Location ID7 ID6 ID5 ID4 ID3 ID2 ID1 009716 009616 009516 009416 009316 009216 009116 009016 Address

Rev.3.02 Dec 22, 2006 page 142 of 142 REJ03B0025-0302 SSOP42-P-450-0.80 Weight(g) JEDEC Code 0.63 Alloy 42/Cu Alloy 42P2R-A Plastic 42pin 450mil SSOP Symbol Min Nom Max A b c D E L y Dimension in Millimeters H E .350 .050 .130 .317 .28 .6311 .30 .271 .02 .40 .150 .517 .48 .80 .9311 .50 .7651 .4311 .42 .50 .20 .717 .68 .2312 .70 .150 b2 –. 5 0– 0° –1 0 ° e 42 22 211 H E E D e y F A A2 A1 L c e b2 Recommended Mount Pad Detail F z Z1 Detail G –Z1 0.75 0.9 z b G Recommended

REVISION HISTORY

Rev. Date Description Page Summary

4556 Group Data Sheet

1.00 Jul. 23, 2003 1.01 Sep. 17, 2003 2.00 Feb. 24, 2004 First edition issued Voltage drop detection circuit (only in H version) revised. Table 15 revised. Timer functions, Timer control registers, Port level, and Notes 6 and 7) 19 Voltage drop detection circuit (only in H version) revised. Fig.57 revised. FEATURES: G Minimum instruction execution time: time for One Time PROM version added. G Supply voltage of One Time PROM version revised. PERFORMANCE OVERVIEW: Minimum instruction execution time: time for One Time PROM version added. Supply voltage of One Time PROM version revised. Power dissipation: Values only for Mask ROM version are listed. Port block diagram (6): SEG 17–SEG 28 eliminated. Table 9: Timer 3; Count source and Use of output signal revised. (1) Power-on reset : “(only for H version)” eliminated. Description revised. Fig.37: “(only for H version)” added to Voltage drop detection circuit. Fig.40: Note revised. ROM ORDERING METHOD revised. Note on 18 Power-on reset : revised. ELECTRICAL CHARACTERISTICS revised. The table is separated to Mask ROM version and One Time PROM version. Supply voltage and supply current revised mainly. Note 6 is added to VOLTAGE DTOP DETECTION CIRCUIT CHARACTERISTICS. 128 120 to 132 3.00 Jul. 09, 2004 Words standardized: On-chip oscillator Description of RESET pin revised. Fig.23: Note added. Some description revised. Fig.28: "DI" instruction added. (5) LCD power supply circuit G Internal dividing resistor revised. Fig.34 d): “VLC3 , VLC2 , VLC1 ” added. Fig.35, Fig.36: Count revised. Fig.38: State of quartz-crystal oscillator added. Note on Power Source Voltage added. RECOMMENDED OPERATING CONDITIONS 1 V DD (RC oscillation) Max.: 3.6 All pages 128 (1/2)

Rev. Date Description Page Summary 3.01 Jun.15, 2005All pages Delete the following: “PRELIMINARY ”. 36 •Prescaler and Timer 1 count start timing and count time when operation starts,

• Timer 2 and Timer LC count start timing and count time when operation starts added. 61 13 Prescaler and Timer 1 count start timing and count time when operation starts,

14 Timer and Timer LC count start timing and count time when operation starts

added. 3.02 Dec. 22, 2006 29, 33 Use of output signal of prescaler: LC eliminated. 30, 31 Fig.22, Fig.23: Note added. 31 Fig.23: INSTCK (wrong) → INTSNC (correct) 32, 69 PA 0: Stop (state initialized) → (state retained) W3 1 W3 0: Timer 3 count source selection bits → Timer 3 count value selection bits 33 (2) Prescaler (interrupt function): PRS (wrong) → RPS (correct) 34 (5) Timer 3 (interrupt function): Description added. 48 Fig.37: Clock (wrong) → f(RING) (correct)

52 Table 15

Timer 3 function (RAM back-up): O → (Note 3) Timer interrupt request flag (RAM back-up): O → (Note 3) 54 Fig.44: Note 1 added. 55, 73 Table 17: Notes 2 and 3 added. 60 to 63 NOTES ON NOISE added. 64 ➀ Noise and latch-up prevention: Description added. 77, 120, SZD: (Y) = 0 to 7 → 0 to 5 121 93 SZD: Detailed description revised. 132 V RST -, VRST +: Test condition revised. 132, 138 Note 4: (power current) → (supply current) → Pages 16 to 18, 20, 27, 54, 66: RAM back-up mode → power down mode Pages 77, 90 to 92, 116 to 119: SNZ0, SNZT1, SNZT2, SNZT3 revised. Pages 78, 109, 122, 123: WRST revised. (2/2)

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