4554

4554 RENESAS | Alldatasheet

Document overview

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Technical content

DESCRIPTION

The 4554 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with main clock selection function, four 8-bit timers (each timer has one or two reload registers), interrupts, and LCD control circuit. The various microcomputers in the 4554 Group include variations of the built-in memory size as shown in the table below.

FEATURES

(at 6 MHz oscillation frequency, in high-speed through-mode) G Supply voltage (It depends on oscillation frequency and operation mode) G Timers Part number M34554M8-XXXFP M34554MC-XXXFP M34554EDFP ( Note) ROM type Mask ROM Mask ROM One Time PROM Package 64P6N-A 64P6N-A 64P6N-A RAM size (✕ 4 bits) 512 words 512 words 512 words ROM (PROM) size (✕ 10 bits) 8192 words 12288 words 16384 words G LCD control circuit G Watchdog timer G Clock generating circuit Main clock (ceramic resonator/RC oscillation/on-chip oscillator) Sub-clock (quartz-crystal oscillation) G LED drive directly enabled (port D) APPLICATION Remot control transmitter Note: Shipped in blank. Rev.3.00 Aug 06, 2004 page 1 of 136 REJ03B0043-0300Z

4554 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER REJ03B0043-0300Z Rev.3.00 Aug 06, 2004

Rev.3.00 Aug 06, 2004 page 2 of 136 REJ03B0043-0300Z Pin configuration (top view) (4554 Group) OUTLINE 64P6N-A SEG 0/VLC3 SEG 1/VLC2 SEG 2/VLC1 SEG 3 SEG 4 SEG 5 SEG 6 M34554Mx-XXXFP M34554EDFP SEG 7 SEG 8 SEG 9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 D 4 D 5 D 6 CNV SS VDCE XCIN XCOUT VDD VSS XOUT XIN RESET D 7/CNTR0 C/CNTR1 D 8/INT0 D 9/INT1 COM 0 COM 1 COM 2 COM 3 P00 P01 P02 P03 P10 P11 P12 P13 D 0 D 1 D 2 D 3 SEG 16 SEG 17 SEG 18 SEG 19 SEG 20 SEG 21 SEG 22 SEG 23 SEG 24/P33 SEG 25/P32 SEG 26/P31 SEG 27/P30 SEG 28/P23 SEG 29/P22 SEG 30/P21 SEG 31/P20 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6

Rev.3.00 Aug 06, 2004 page 3 of 136 REJ03B0043-0300Z Block diagram (4554 Group) R A M R O M M e m o r y I / O p o r t I n t e r n a l p e r i p h e r a l f u n c t i o n s T i m e r T i m e r b i t s S y s t e m c l o c k g e n e r a t i o n c i r c u i t T i m e r b i t s w o r d s b i t s L C D d i s p l a y R A M i n c l u d i n g w o r d s b i t s 8 1 w o r d s b i t s s e r i e s C P U c o r e R e g i s t e r B b i t s R e g i s t e r A b i t s R e g i s t e r D b i t s R e g i s t e r E b i t s S t a c k r e g i s t e r S K l e v e l s I n t e r r u p t s t a c k r e g i s t e r S D P l e v e l A L U b i t s W a t c h d o g t i m e r b i t s )P o r t P P o r t P P o r t P P o w e r o n r e s e t c i r c u i t V o l t a g e d r o p d e t e c t i o n c i r c u i t T i m e r b i t s T i m e r b i t s L C D d r i v e c o n t r o l c i r c u i t M a x s e g m e n t s c o m m o n X I N X O U T ( M a i n c l o c k X C I N X C O U T ( S u b c l o c k S e g m e n t o u t p u t 3 2 C o m m o n o u t p u t P o r t P P o r t D T i m e r b i t s P o r t C 1

Rev.3.00 Aug 06, 2004 page 4 of 136 REJ03B0043-0300Z 0.5 µs (at 6 MHz oscillation frequency, in high-speed through mode) 8192 words ✕ 10 bits 12288 words ✕ 10 bits 16384 words ✕ 10 bits 512 words ✕ 4 bits (including LCD display RAM 32 words ✕ 4 bits) Eight independent I/O ports. Input is examined by skip decision. The output structure can be switched by software. Port D 7 is also used as CNTR0 pin. Two independent output ports. Ports D8 and D9 are also used as INT0 and INT1, respectively. 4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched by software. 4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched by software. 4-bit input port; Port P20–P23 are also used as SEG31–SEG 28 pins. 4-bit input port; Port P30–P33 are also used as SEG27–SEG 24 pins. 1-bit output; Port C is also used as CNTR1 pin. 8-bit programmable timer with a reload register and has an event counter. 8-bit programmable timer with a reload register. 8-bit programmable timer with a reload register and has an event counter. 8-bit programmable timer with two reload registers. 16-bit timer, fixed dividing frequency 1/2, 1/3 bias 2, 3, 4 duty 2r ✕ 3, 2r ✕ 2, r ✕ 3, r ✕ 2 (they can be switched by software.) 7 (two for external, five for timer) 1 level 8 levels CMOS silicon gate 64-pin plastic molded QFP (64P6N) –20 °C to 85 °C 2 to 5.5 V (It depends on the operation source clock, operation mode and oscillation frequency.) 2.5 to 5.5 V (It depends on the operation source clock, operation mode and oscillation frequency.) 2.8 mA (Ta=25°C, V DD = 5 V, f(XIN) = 6 MHz, f(XCIN) = 32 kHz, f(STCK) = f(XIN)) 20 µA (Ta=25°C, VDD = 5 V, f(XCIN) = 32 kHz) 0.1 µA (Ta=25°C, VDD = 5 V) Parameter Number of basic instructions Minimum instruction execution time Memory sizes Input/Output ports Timers LCD control circuit Interrupt Subroutine nesting Device structure Package Operating temperature range Supply voltage Power dissipation ROM RAM D 0–D 7 D 8, D9 P00–P0 3 P10–P1 3 P20–P2 3 P30–P3 3 C Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 Selective bias value Selective duty value Common output Segment output Internal resistor for power supply Sources Nesting Mask ROM version One Time PROM version Active mode Clock operating mode At RAM back-up M34554M8 M34554MC M34554ED I/O Output I/O I/O Input Input Output

Rev.3.00 Aug 06, 2004 page 5 of 136 REJ03B0043-0300Z V DD VSS CNV SS VDCE RESET X IN XCIN XCOUT Input/Output Input I/O Input Input Output Function Connected to a plus power supply. Connected to a 0 V power supply. Connect CNV SS to VSS and apply “L” (0V) to CNVSS certainly. This pin is used to operate/stop the voltage drop detection circuit. When “H“ level is input to this pin, the circuit starts operating. When “L“ level is input to this pin, the circuit stops operating. An N-channel open-drain I/O pin for a system reset. When the watchdog timer, the built-in power-on reset or the voltage drop detection circuit causes the system to be reset, the RESET pin outputs “L” level. I/O pins of the main clock generating circuit. When using a ceramic resonator, con- nect it between pins X IN and XOUT . A feedback resistor is built-in between them. When using the RC oscillation, connect a resistor and a capacitor to XIN, and leave XOUT pin open. I/O pins of the sub-clock generating circuit. Connect a 32 kHz quartz-crystal oscillator between pins XCIN and XCOUT . A feedback resistor is built-in between them. XOUT Main clock output Output D 0–D 7 D 8, D9 P00–P0 3 P10–P1 3 P20–P2 3 P30–P3 3 Port C COM 0– COM 3 SEG 0–SEG 31 VLC3 –VLC1 CNTR0, CNTR1 INT0, INT1 I/O port D Input is examined by skip decision. Output port D I/O port P0 I/O port P1 Input port P2 Input port P3 Output port C Common output Segment output LCD power supply Timer input/output Interrupt input I/O Output I/O I/O Input Input Output Output Output I/O Input Each pin of port D has an independent 1-bit wide I/O function. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Port D 7 is also used as CNTR0 pin. Each pin of port D has an independent 1-bit wide output function. The output struc- ture is N-channel open-drain. Ports D8 and D9 are also used as INT0 pin and INT1 pin, respectively. Port P0 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Port P0 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Port P1 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Port P1 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Port P2 serves as a 4-bit input port. Ports P2 0–P23 are also used as SEG31–SEG 28, respectively. Port P3 serves as a 4-bit input port. Ports P30–P33 are also used as SEG27–SEG 24, respectively. 1-bit output port. The output structure is CMOS. Port C is also used as CNTR1 pin. LCD common output pins. Pins COM0 and COM 1 are used at 1/2 duty, pins COM0– COM 2 are used at 1/3 duty and pins COM0–COM 3 are used at 1/4 duty. LCD segment output pins. SEG0–SEG 2 pins are used as VLC3 –VLC1 pins, respectively. LCD power supply pins. When the internal resistor is used, V DD pin is connected to VLC3 pin (if luminance ad- justment is required, VDD pin is connected to VLC3 pin through a resistor). When the external power supply is used, apply the voltage 0 ≤ VLC1 ≤ VLC2 ≤ VLC3 ≤ VDD . VLC3 –V LC1 pins are used as SEG0–SEG 2 pins, respectively. CNTR0 pin has the function to input the clock for the timer 1 event counter, and to output the timer 1 or timer 2 underflow signal divided by 2. CNTR1 pin has the function to input the clock for the timer 3 event counter, and to output the PWM signal generated by timer 4.CNTR0 pin and CNTR1 pin are also used as Ports D 7 and C, respectively. INT0 pin and INT1 pin accept external interrupts. They have the key-on wakeup func- tion which can be switched by software. INT0 pin and INT1 pin are also used as Ports D 8 and D9, respectively.

Rev.3.00 Aug 06, 2004 page 6 of 136 REJ03B0043-0300Z DEFINITION OF CLOCK AND CYCLE G Operation source clock The operation source clock is the source clock to operate this product. In this product, the following clocks are used.

• Clock (f(X IN)) by the external ceramic resonator
• Clock (f(XIN)) by the external RC oscillation
• Clock (f(XIN)) by the external input
• Clock (f(RING)) of the on-chip oscillator which is the internal oscillator
• Clock (f(XCIN)) by the external quartz-crystal oscillation Register MR System clock f(STCK) = f(XIN) or f(RING) f(STCK) = f(XCIN) f(STCK) = f(XIN)/2 or f(RING)/2 f(STCK) = f(XCIN)/2 f(STCK) = f(XIN)/4 or f(RING)/4 f(STCK) = f(XCIN)/4 f(STCK) = f(XIN)/8 or f(RING)/8 f(STCK) = f(XCIN)/8 Table Selection of system clock Note: The f(RING)/8 is selected after system is released from reset. MR 2 MR Operation mode High-speed through mode Low-speed through mode High-speed frequency divided by 2 mode Low-speed frequency divided by 2 mode High-speed frequency divided by 4 mode Low-speed frequency divided by 4 mode High-speed frequency divided by 8 mode Low-speed frequency divided by 8 mode G System clock (STCK) The system clock is the basic clock for controlling this product. The system clock is selected by the clock control register MR shown as the table below. G Instruction clock (INSTCK) The instruction clock is the basic clock for controlling CPU. The instruction clock (INSTCK) is a signal derived by dividing the system clock (STCK) by 3. The one instruction clock cycle gen- erates the one machine cycle. G Machine cycle The machine cycle is the standard cycle required to execute the instruction. MR 0 MR 0 or 1 0 or 1 0 or 1 0 or 1 Notes 1: Pins except above have just single function. 2: The output of D8 and D9 can be used even when INT0 and INT1 are selected. 3: The input/output of D7 can be used even when CNTR0 (input) is selected. 4: The input of D7 can be used even when CNTR0 (output) is selected. 5: The port C “H” output function can be used even when CNTR1 (output) is selected. Pin C D D 8 D 9 VLC3 VLC2 VLC1 Multifunction CNTR1 CNTR0 INT0 INT1 SEG SEG 1 SEG 2 MULTIFUNCTION Pin CNTR1 CNTR0 INT0 INT1 SEG SEG 1 SEG 2 Multifunction C D D 8 D 9 VLC3 VLC2 VLC1 Pin P20 P21 P22 P23 P30 P31 P32 P33 Multifunction SEG 31 SEG 30 SEG 29 SEG 28 SEG 27 SEG 26 SEG 25 SEG 24 Pin SEG 31 SEG 30 SEG 29 SEG 28 SEG 27 SEG 26 SEG 25 SEG 24 Multifunction P20 P21 P22 P23 P30 P31 P32 P33

Rev.3.00 Aug 06, 2004 page 7 of 136 REJ03B0043-0300Z SD, RD SZD CLD OP0A IAP0 OP1A IAP1 IAP2 IAP3 RCP SCP Control registers FR1, FR2 I1, I2 FR0 PU0 FR0 PU1 Output structure N-channel open-drain/ CMOS N-channel open-drain N-channel open-drain/ CMOS N-channel open-drain/ CMOS CMOS Input Output I/O (8) Output (2) I/O (4) I/O (4) Input (4) Input (4) Output (1) RemarkPin D 0–D 6, D7/CNTR0 D 8/INT0, D9/INT1 P00–P0 3 P10–P1 3 SEG 31/P20–SEG 28/P23 SEG 27/P30–SEG 24/P33 C/CNTR1 Output structure selection function (programmable) Key-on wakeup function (programmable) Built-in programmable pull-up functions and key-on wakeup functions (programmable) Built-in programmable pull-up functions and key-on wakeup functions (programmable)

Rev.3.00 Aug 06, 2004 page 8 of 136 REJ03B0043-0300Z CONNECTIONS OF UNUSED PINS Connection Connect to VSS . Open. Connect to VSS . Open. Open. Connect to VSS . Open. Connect to V SS . Open. Connect to V SS . Open. Connect to V SS . Open. Open. Connect to Vss. Open. Connect to Vss. Open. Connect to Vss. Open. Connect to Vss. Open. Open. Open. Open. Open. Pin X IN XOUT XCIN XCOUT D 0–D 6 D 7/CNTR0 D 8/INT0 D 9/INT1 C/CNTR1 P00–P03 P10–P13 SEG 31/P20– SEG 28/P23 SEG 27/P30– SEG 24/P33 COM 0–COM 3 SEG 0/VLC3 SEG 1/VLC2 SEG 2/VLC1 SEG 3–SEG 23 Usage condition Internal oscillator is selected (CMCK and CRCK instructions are not executed.) (Note 1) Sub-clock input is selected for system clock (MR 0=1). (Note 2) Internal oscillator is selected (CMCK and CRCK instructions are not executed.) (Note 1) RC oscillator is selected (CRCK instruction is executed) External clock input is selected for main clock (CMCK instruction is executed). (Note 3) Sub-clock input is selected for system clock (MR 0=1). (Note 2) Sub-clock is not used. Sub-clock is not used. External clock input is selected for sub-clock. (Note 4) N-channel open-drain is selected for the output structure. CNTR0 input is not selected for timer 1 count source. N-channel open-drain is selected for the output structure. “0” is set to output latch. “0” is set to output latch. CNTR1 input is not selected for timer 3 count source. The key-on wakeup function is not selected. (Note 4) N-channel open-drain is selected for the output structure. (Note 5) The pull-up function is not selected. (Note 4) The key-on wakeup function is not selected. (Note 4) The key-on wakeup function is not selected. (Note 4) N-channel open-drain is selected for the output structure. (Note 5) The pull-up function is not selected. (Note 4) The key-on wakeup function is not selected. (Note 4) Ports P2 0–P2 3 selected. Ports P30–P3 3 selected. SEG 0 pin is selected. SEG 1 pin is selected. SEG 2 pin is selected. Notes 1: When the CMCK and CRCK instructions are not executed, the internal oscillation (on-chip oscillator) is selected for main clock. 2: When sub-clock (XCIN) input is selected (MR0 = 1) for the system clock by setting “1” to bit 1 (MR1) of clock control register MR, main clock is stopped. 3: Select the ceramic resonance by executing the CMCK instruction to use the external clock input for the main clock. 4: Be sure to select the output structure of ports D 0–D 6 and the pull-up function and key-on wakeup function of P00–P0 3 and P10–P1 3 with every one port. Set the corresponding bits of registers for each port. 5: Be sure to select the output structure of ports P00–P03 and P10–P13 with every two ports. If only one of the two pins is used, leave another one open. (Note when connecting to VSS and VDD ) G Connect the unused pins to VSS and VDD using the thickest wire at the shortest distance against noise.

Rev.3.00 Aug 06, 2004 page 9 of 136 REJ03B0043-0300Z Port block diagram (1) R e g i s t e r Y D e c o d e r SD instruction RD instruction D 0S RQ Skip decision (SZD instruction) (Note 1) F R (Note 2) R e g i s t e r Y D e c o d e r SD instruction RD instruction D 1S RQ Skip decision (SZD instruction) (Note 1) FR1 1 N o t e R e g i s t e r Y D e c o d e r S D i n s t r u c t i o n R D i n s t r u c t i o n D 2S RQ S k i p d e c i s i o n S Z D i n s t r u c t i o n N o t e FR1 2 N o t e R e g i s t e r Y D e c o d e r S D i n s t r u c t i o n R D i n s t r u c t i o n D 3S RQ Skip decision (SZD instruction) CLD instruction N o t e FR1 3 (Note 2) C C N T R (Note 1) N o t e s a n d C l o c k i n p u t f o r t i m e r e v e n t c o u n t D TQ R W

32 W6 1

T i m e r u n d e r f l o w s i g n a l S C P i n s t r u c t i o n R C P i n s t r u c t i o n S R W W Q PWMOD C L D i n s t r u c t i o n CLD instruction CLD instruction This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: When CNTR1 input is selected, output transistor is turned OFF. N o t e s

Rev.3.00 Aug 06, 2004 page 10 of 136 REJ03B0043-0300Z Port block diagram (2) R e g i s g e r Y D e c o d e r S D i n s t r u c t i o n R D i n s t r u c t i o n D 4S RQ Skip decision (SZD instruction) C L D i n s t r u c t i o n N o t e F R D 5S RQ F R D 6S RQ FR2 2 R e g i s g e r Y Regisger Y D e c o d e r D e c o d e r SD instruction RD instruction Skip decision (SZD instruction) C L D i n s t r u c t i o n S D i n s t r u c t i o n R D i n s t r u c t i o n Skip decision (SZD instruction) C L D i n s t r u c t i o n N o t e N o t e N o t e N o t e (Note 2) T h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e o n t h e p o r t A p p l i e d p o t e n t i a l t o t h e s e p o r t s m u s t b e VD D o r l e s s N o t e s

Rev.3.00 Aug 06, 2004 page 11 of 136 REJ03B0043-0300Z Port block diagram (3) U n d e r f l o w s i g n a l d i v i d e d b y o f t i m e r o r t i m e r

2 W1 1

C l o c k i n p u t f o r t i m e r e v e n t c o u n t Register Y D e c o d e r S D i n s t r u c t i o n R D i n s t r u c t i o n S RQ C L D i n s t r u c t i o n Skip decision (SZD instruction)) N o t e FR2 3 W6 0 D 7/CNTR0 N o t e S RQ D 8/INT0 External 0 interrupt circuit External 0 interrupt N o t e )Key-on wakeup Timer 1 count start synchronous circuit input S RQ D 9/INT1 (Note 1) N o t e D i n s t r u c t i o n R D i n s t r u c t i o n C L D i n s t r u c t i o n Register Y D e c o d e r S D i n s t r u c t i o n R D i n s t r u c t i o n C L D i n s t r u c t i o n Register Y D e c o d e r External 1 interrupt circuit External 1 interrupt N o t e )Key-on wakeup T i m e r c o u n t s t a r t s y n c h r o n o u s c i r c u i t i n p u t (Note 1) (Note 2) T h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e o n t h e p o r t A p p l i e d p o t e n t i a l t o t h e s e p o r t s m u s t b e VD D o r l e s s A s f o r d e t a i l s r e f e r t o t h e d e s c r i p t i o n o f e x t e r n a l i n t e r r u p t c i r c u i t Notes 1:

Rev.3.00 Aug 06, 2004 page 12 of 136 REJ03B0043-0300Z Port block diagram (4) P K O P A i n s t r u c t i o n R e g i s t e r A D K e y o n w a k e u p N o t e N o t e FR0 0 I A P i n s t r u c t i o n P U 00P u l l u p t r a n s i s t o r T Q L l e v e l d e t e c t i o n c i r c u i t P K01 D F R P U T Q P K D FR0 1 P U T Q P03 K D F R P U T Q O P A i n s t r u c t i o n R e g i s t e r A Key-on wakeup N o t e N o t e I A P i n s t r u c t i o n P u l l u p t r a n s i s t o r L l e v e l d e t e c t i o n c i r c u i t O P A i n s t r u c t i o n R e g i s t e r A K e y o n w a k e u p N o t e N o t e IAP0 instruction P u l l u p t r a n s i s t o r L l e v e l d e t e c t i o n c i r c u i t O P A i n s t r u c t i o n R e g i s t e r A K e y o n w a k e u p N o t e N o t e I A P i n s t r u c t i o n P u l l u p t r a n s i s t o r L l e v e l d e t e c t i o n c i r c u i t T h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e o n t h e p o r t A p p l i e d p o t e n t i a l t o t h e s e p o r t s m u s t b e VD D o r l e s s N o t e s

Rev.3.00 Aug 06, 2004 page 13 of 136 REJ03B0043-0300Z Port block diagram (5) P K O P A i n s t u c t i o n R e g i s t e r A D K e y o n w a k e u p N o t e N o t e F R I A P i n s t r u c t i o n P U P u l l u p t r a n s i s t o r T Q L l e v e l d e t e c t i o n c i r c u i t P K D F R P U T Q P K D F R P U T Q P K D F R P U T Q O P A i n s t u c t i o n R e g i s t e r A K e y o n w a k e u p I A P i n s t r u c t i o n P u l l u p t r a n s i s t o r L l e v e l d e t e c t i o n c i r c u i t N o t e N o t e O P A i n s t u c t i o n R e g i s t e r A K e y o n w a k e u p I A P i n s t r u c t i o n P u l l u p t r a n s i s t o r L l e v e l d e t e c t i o n c i r c u i t N o t e N o t e O P A i n s t u c t i o n R e g i s t e r A K e y o n w a k e u p I A P i n s t r u c t i o n P u l l u p t r a n s i s t o r L l e v e l d e t e c t i o n c i r c u i t N o t e N o t e T h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e o n t h e p o r t A p p l i e d p o t e n t i a l t o t h e s e p o r t s m u s t b e VD D o r l e s s N o t e s

Rev.3.00 Aug 06, 2004 page 14 of 136 REJ03B0043-0300Z Port block diagram (6) S E G 3 P N o t e L C D c o n t r o l s i g n a l Connecting to • when P2 is selected. LCD power supply L30 R e g i s t e r A I A P i n s t r u c t i o n S E G 3 P L31 SEG 29/P22, SEG 28/P23 L32 AI( N o t e SEG 27/P30 –SEG 24/P33 L33 Aj( N o t e LCD power supply N o t e N o t e L C D c o n t r o l s i g n a l Connecting to • when P2 is selected. L C D p o w e r s u p p l y R e g i s t e r A I A P i n s t r u c t i o n LCD power supply (Note 2) N o t e L C D c o n t r o l s i g n a l Connecting to • when P2 is selected. LCD power supply Register A I A P i n s t r u c t i o n LCD power supply N o t e N o t e L C D c o n t r o l s i g n a l LCD power supply Register A LCD power supply N o t e A P i n s t r u c t i o n Connecting to • when P3 is selected. T h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e o n t h e p o r t A p p l i e d p o t e n t i a l t o t h e s e p o r t s m u s t b e VD D o r l e s s i r e p r e s e n t s j r e p r e s e n t s t o N o t e s

Rev.3.00 Aug 06, 2004 page 15 of 136 REJ03B0043-0300Z Port block diagram (7) VL C VD D ) S E G 0/ VL C L23 VL C SEG 1/VLC2 L22 VL C S E G 2/ VL C L L13 L20 L12 Reset signal EPOF+POF2 instruction (Continuous execution) L11 VDD N o t e L C D c o n t r o l s i g n a l C o n n e c t i n g t o w h e n V L C i s s e l e c t e d L C D p o w e r s u p p l y L C D p o w e r s u p p l y (Notes 2 and 3) L C D p o w e r s u p p l y N o t e L C D c o n t r o l s i g n a l C o n n e c t i n g t o w h e n V L C i s s e l e c t e d L C D p o w e r s u p p l y LCD power supply N o t e L C D p o w e r s u p p l y LCD power supply L C D p o w e r s u p p l y L C D p o w e r s u p p l y LCD control signal N o t e (Note 2) Connecting to • when VLC is selected. T h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e o n t h e p o r t A p p l i e d p o t e n t i a l w h e n V L C i s s e l e c t e d m u s t b e a s f o l l o w s VD D ≥ VL C 3 ≥ VL C 2 ≥ VL C V L C VD D w h e n S E G i s s e l e c t e d Notes 1:

Rev.3.00 Aug 06, 2004 page 16 of 136 REJ03B0043-0300Z Port block diagram (8) COM 0–COM 3 L C D c o n t r o l s i g n a l Pch S E G 3– S E G 2 Pch N c h Nch Pch N c h L C D p o w e r s u p p l y L C D c o n t r o l s i g n a l L C D p o w e r s u p p l y LCD control signal L C D p o w e r s u p p l y LCD control signal L C D p o w e r s u p p l y L C D c o n t r o l s i g n a l L C D p o w e r s u p p l y LCD control signal

Rev.3.00 Aug 06, 2004 page 17 of 136 REJ03B0043-0300Z (1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4- bit data addition, comparison, AND operation, OR operation, and bit manipulation. (2) Register A and carry flag Register A is a 4-bit register used for arithmetic, transfer, ex- change, and I/O operation. Carry flag CY is a 1-bit flag that is set to “1” when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A 0 is stored in carry flag CY with the RAR instruction (Fig- ure 2). Carry flag CY can be set to “1” with the SC instruction and cleared to “0” with the RC instruction. (3) Registers B and E Register B is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3). Register E is undefined after system is released from reset and re- turned from the RAM back-up. Accordingly, set the initial value. (4) Register D Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 4). Register D is undefined after system is released from reset and re- turned from the RAM back-up. Accordingly, set the initial value. Fig. 1 AMC instruction execution example Fig. 2 RAR instruction execution example Fig. 3 Registers A, B and register E Fig. 4 TABP p instruction execution example ( C Y ) ( M ( D P ) ) ( A ) Addition A L U <Carry> < R e s u l t > CY A 3 A2 A1 A0 A0 C YA 3 A2 A1 < R o t a t i o n > R A R i n s t r u c t i o n <Set> SC instruction <Clear> RC instruction A3 A2 A1 A0B3 B2 B1 B0 E7 E6 E5 E4 E3 E2 E1 E0 A3 A2 A1 A0B3 B2 B1 B0 TAB instruction T E A B i n s t r u c t i o n T A B E i n s t r u c t i o n TBA instruction R e g i s t e r BR e g i s t e r A Register B Register A Register E S p e c i f y i n g a d d r e s s TABP p instruction p6 p5 p4 p3 p2 p1 p0 P C H DR 2D R 1D R 0 A3 A2 A1 A0 P C L I m m e d i a t e f i e l d v a l u e p T h e c o n t e n t s o f r e g i s t e r D ROM 840 Middle-order 4 bits L o w - o r d e r 4 b i t s Register A (4) Register B (4) T h e c o n t e n t s o f r e g i s t e r A

Rev.3.00 Aug 06, 2004 page 18 of 136 REJ03B0043-0300Z (5) Stack registers (SKS) and stack pointer (SP) Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when;

• branching to an interrupt service routine (referred to as an inter- rupt service routine),
• performing a subroutine call, or
• executing the table reference instruction (TABP p). Stack registers (SKs) are eight identical registers, so that subrou- tines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be care- ful not to over the stack when performing these operations together. The contents of registers SKs are destroyed when 8 lev- els are exceeded. The register SK nesting level is pointed automatically by 3-bit stack pointer (SP). The contents of the stack pointer (SP) can be transferred to register A with the TASP instruction. Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call. (6) Interrupt stack register (SDP) Interrupt stack register (SDP) is a 1-stage register. When an inter- rupt occurs, this register (SDP) is used to temporarily store the contents of data pointer, carry flag, skip flag, register A, and regis- ter B just before an interrupt until returning to the original routine. Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table refer- ence instruction. (7) Skip flag Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. When an interrupt oc- curs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained. Fig. 5 Stack registers (SKs) structure Fig. 6 Example of operation at subroutine call S K0 S K1 S K2 S K3 S K4 S K5 S K6 S K7 ( S P ) = 0 ( S P ) = 1 ( S P ) = 2 ( S P ) = 3 ( S P ) = 4 ( S P ) = 5 ( S P ) = 6 ( S P ) = 7 Program counter (PC) E x e c u t i n g R T i n s t r u c t i o n Executing BM instruction Stack pointer (SP) points “7” at reset or returning from RAM back-up mode. It points “0” by executing the first BM instruction, and the contents of program counter is stored in SK0. When the BM instruction is executed after eight stack registers are used ((SP) = 7), (SP) = 0 and the contents of SK0 is destroyed. Returning to the BM instruction execution address with the RT instruction, and the BM instruction becomes the NOP instruction. (SP) ← 0 (SK0) ← 000116 (PC) ← SUB1 Main program

000216 NOP

6 N O P

000116 BM SUB1

S U B 1 : NOP RT ( P C ) ← ( S K0) S P Note :

Rev.3.00 Aug 06, 2004 page 19 of 136 REJ03B0043-0300Z (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table refer- ence instruction (TABP p) is executed. Program counter consists of PC H (most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which speci- fies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PC H does not specify after the last page of the built-in ROM. (9) Data pointer (DP) Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y . Register Z specifies a RAM file group, reg- ister X specifies a file, and register Y specifies a RAM digit (Figure 8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 9).

• Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the RAM back-up, set these registers. Fig. 7 Program counter (PC) structure Fig. 8 Data pointer (DP) structure Fig. 9 SD instruction execution example p5 p4 p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0 P r o g r a m c o u n t e r P C H S p e c i f y i n g p a g e P C L S p e c i f y i n g a d d r e s s Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0 D a t a p o i n t e r ( D P ) Register Z (2) R e g i s t e r X ( 4 ) Register Y (4)S p e c i f y i n g R A M d i g i t S p e c i f y i n g R A M f i l e Specifying RAM file group 0 01 1 Set S p e c i f y i n g b i t p o s i t i o n Port D output latchRegister Y (4) D 2D 3 D 1 D 0

Rev.3.00 Aug 06, 2004 page 20 of 136 REJ03B0043-0300Z PROGRAM MEMORY (ROM) The program memory is a mask ROM. 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Fig- ure 10 shows the ROM map of M34554ED. Table 1 ROM size and pages Part number M34554M8 M34554MC M34554ED ROM (PROM) size (✕ 10 bits) 8192 words 12288 words 16384 words Pages 64 (0 to 63) 96 (0 to 95) 128 (0 to 127) Note: Data in pages 64 to 127 can be referred with the TABP p in- struction after the SBK instruction is executed. Data in pages 0 to 63 can be referred with the TABP p in- struction after the RBK instruction is executed. A part of page 1 (addresses 0080 16 to 00FF16) is reserved for in- terrupt addresses (Figure 11). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is executed. When using an interrupt service routine, write the in- struction generating the branch to that routine at an interrupt address. Page 2 (addresses 0100 16 to 017F16) is the special page for sub- routine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM in- struction when it starts on page 2. ROM pattern (bits 7 to 0) of all addresses can be used as data ar- eas with the TABP p instruction. Fig. 10 ROM map of M34554ED Fig. 11 Page 1 (addresses 008016 to 00FF16) structure 90 87654321 I n t e r r u p t a d d r e s s p a g e 0 0 0 01 0 0 8 01 0 1 7F1

6 S u b r o u t i n e s p e c i a l p a g e

F 0 1 8 01 P a g e 1 P a g e 2 P a g e 0 P a g e 3 P a g e 1 2 7 90 87654321 E x t e r n a l 0 i n t e r r u p t a d d r e s s008016 008216

008416 Timer 1 interrupt address

Timer 2 interrupt address008616 008816 008A16 0 0 8 C 1 0 0 8 E1 0 0 F F1 E x t e r n a l 1 i n t e r r u p t a d d r e s s Timer 3 interrupt address Timer 5 interrupt address Timer 4 interrupt address

Rev.3.00 Aug 06, 2004 page 21 of 136 REJ03B0043-0300Z DATA MEMORY (RAM) 1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers Z, X, and Y. Set a value to the data pointer certainly when executing an instruction to access RAM (also, set a value after system returns from RAM back-up). RAM includes the area for LCD. When writing “1” to a bit corresponding to displayed segment, the segment is turned on. Table 2 shows the RAM size. Figure 12 shows the RAM map.

• Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the RAM back-up, set these registers. Fig. 12 RAM map Table 2 RAM size Part number M34554M8 M34554MC M34554ED RAM size 512 words ✕ 4 bits (2048 bits) 512 words ✕ 4 bits (2048 bits) 512 words ✕ 4 bits (2048 bits) R e g i s t e r Y R e g i s t e r Z R e g i s t e r X 1 0 1 1 1 2 0 1 1 3 R A M w o r d s b i t s b i t s 1 1 1 3 1 6 N o t e : T h e n u m b e r s i n t h e s h a d e d a r e a i n d i c a t e t h e c o r r e s p o n d i n g s e g m e n t o u t p u t p i n n u m b e r s . 2 4 2 7 2 8

Rev.3.00 Aug 06, 2004 page 22 of 136 REJ03B0043-0300Z The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the following 3 conditions are satisfied.

• An interrupt activated condition is satisfied (request flag = “1”)
• Interrupt enable bit is enabled (“1”)
• Interrupt enable flag is enabled (INTE = “1”) Table 3 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.) (1) Interrupt enable flag (INTE) The interrupt enable flag (INTE) controls whether the every inter- rupt enable/disable. Interrupts are enabled when INTE flag is set to “1” with the EI instruction and disabled when INTE flag is cleared to “0” with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to “0,” so that other interrupts are disabled until the EI instruction is executed. (2) Interrupt enable bit Use an interrupt enable bit of interrupt control registers V1 and V2 to select the corresponding interrupt or skip instruction. Table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. Table 5 shows the interrupt enable bit function. (3) Interrupt request flag When the activated condition for each interrupt is satisfied, the cor- responding interrupt request flag is set to “1.” Each interrupt request flag is cleared to “0” when either;
• an interrupt occurs, or
• the next instruction is skipped with a skip instruction. Each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its in- terrupt enable bit. Once set, the interrupt request flag retains set until a clear condition is satisfied. Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. If more than one interrupt request flag is set when the interrupt dis- able state is released, the interrupt priority level is as follows shown in Table 3. Table 3 Interrupt sources Activated condition Level change of INT0 pin Level change of INT1 pin Timer 1 underflow Timer 2 underflow Timer 3 underflow Timer 5 underflow Timer 4 underflow Priority level Interrupt name External 0 interrupt External 1 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 5 interrupt Timer 4 interrupt Interrupt request flag EXF0 EXF1 T1F T2F T3F T5F T4F Interrupt name External 0 interrupt External 1 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 5 interrupt Timer 4 interrupt Table 5 Interrupt enable bit function Occurrence of interrupt Enabled Disabled Skip instruction Invalid Valid Interrupt enable bit Interrupt address Address 0 in page 1 Address 2 in page 1 Address 4 in page 1 Address 6 in page 1 Address 8 in page 1 Address A in page 1 Address E in page 1 Table 4 Interrupt request flag, interrupt enable bit and skip in- struction Skip instruction SNZ0 SNZ1 SNZT1 SNZT2 SNZT3 SNZT5 SNZT4 Interrupt enable bit V10 V11 V12 V13 V20 V21 V23

Rev.3.00 Aug 06, 2004 page 23 of 136 REJ03B0043-0300Z (4) Internal state during an interrupt The internal state of the microcomputer during an interrupt is as fol- lows (Figure 14).

• Program counter (PC) An interrupt address is set in program counter. The address to be executed when returning to the main routine is automatically stored in the stack register (SK).
• Interrupt enable flag (INTE) INTE flag is cleared to “0” so that interrupts are disabled.
• Interrupt request flag Only the request flag for the current interrupt source is cleared to “0.”
• Data pointer, carry flag, skip flag, registers A and B The contents of these registers and flags are stored automatically in the interrupt stack register (SDP). (5) Interrupt processing When an interrupt occurs, a program at an interrupt address is ex- ecuted after branching a data store sequence to stack register. Write the branch instruction to an interrupt service routine at an in- terrupt address. Use the RTI instruction to return from an interrupt service routine. Interrupt enabled by executing the EI instruction is performed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction, interrupts are enabled after returning the main routine. (Refer to Figure 13) Fig. 13 Program example of interrupt processing
• Program counter (PC)
• Stack register (SK)
• Interrupt enable flag (INTE)
• Interrupt request flag (only the flag for the current interrupt
• Data pointer, carry flag, registers A and B, skip flag The address of main routine to be executed when returning Fig. 15 Interrupt system diagram Fig. 14 Internal state when interrupt occurs E I R T I I n t e r r u p t s e r v i c e r o u t i n e Interrupt occurs Interrupt is enabled M a i n r o u t i n e : I n t e r r u p t e n a b l e d s t a t e : I n t e r r u p t d i s a b l e d s t a t e V 11 EXF0 V 10 A d d r e s s 2 i n p a g e Address 4 in page 1 Address 0 in page 1 Timer 1 underflow T i m e r 2 u n d e r f l o w T 1 FV 12 R e q u e s t f l a g s t a t e r e t a i n e d Enable bit E n a b l e f l a gActivated condition V13 Address 6 in page 1 I N T E T2F V20T3F V 21 T4F V 23 T5F INT0 pin interrupt waveform input T i m e r 3 u n d e r f l o w T i m e r 5 u n d e r f l o w T i m e r 4 u n d e r f l o w I N T 1 p i n i n t e r r u p t w a v e f o r m i n p u t E X F 1 Address 8 in page 1 A d d r e s s A i n p a g e Address E in page 1

Rev.3.00 Aug 06, 2004 page 24 of 136 REJ03B0043-0300Z (6) Interrupt control registers

• Interrupt control register V1 Interrupt enable bits of external 0, external 1, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A. Table 6 Interrupt control registers Note: “R ” represents read enabled, and “W ” represents write enabled. (7) Interrupt sequence Interrupts only occur when the respective INTE flag, interrupt en- able bits (V10–V1 3, V20, V21, V23), and interrupt request flag are “1.” The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. The interrupt oc- curs after 3 machine cycles only when the three interrupt conditions are satisfied on execution of other than one-cycle in- structions (Refer to Figure 16). V12 V11 V10 Interrupt control register V1 Timer 2 interrupt enable bit Timer 1 interrupt enable bit External 1 interrupt enable bit External 0 interrupt enable bit Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) at power down : 0000 2at reset : 00002 R/W TAV1/TV1A Interrupt disabled (SNZT4 instruction is valid) Interrupt enabled (SNZT4 instruction is invalid) This bit has no function, but read/write is enabled. Interrupt disabled (SNZT5 instruction is valid) Interrupt enabled (SNZT5 instruction is invalid) Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) Timer 4 interrupt enable bit Not used Timer 5 interrupt enable bit Timer 3 interrupt enable bit Interrupt control register V2 at power down : 00002at reset : 00002 R/W TAV2/TV2A
• Interrupt control register V2 The timer 3, timer 5, timer 4 interrupt enable bit is assigned to register V2. Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction can be used to transfer the contents of register V2 to register A. V22 V21 V20

Rev.3.00 Aug 06, 2004 page 25 of 136 REJ03B0043-0300Z Fig. 16 Interrupt sequence T F T F T F T F T F I N T I N T E X F E X F T1 T2 T3 T1 T2 T3 T2 T3T1 T1 T2 T3 T1 T2 G W h e n a n i n t e r r u p t r e q u e s t f l a g i s s e t a f t e r i t s i n t e r r u p t i s e n a b l e d N o t e S y s t e m c l o c k S T C K T h e p r o g r a m s t a r t s f r o m t h e i n t e r r u p t a d d r e s s Interrupt enabled state 1 m a c h i n e c y c l e E I i n s t r u c t i o n e x e c u t i o n c y c l e I n t e r r u p t e n a b l e f l a g I N T E R e t a i n i n g l e v e l o f s y s t e m c l o c k f o r p e r i o d s o r m o r e i s n e c e s s a r y I n t e r r u p t d i s a b l e d s t a t e E x t e r n a l i n t e r r u p t T i m e r 1 , T i m e r T i m e r T i m e r T i m e r i n t e r r u p t s Interrupt activated condition is satisfied. N o t e s 1 : T h e a d d r e s s i s s t a c k e d t o t h e l a s t c y c l e . 2 : T h i s i n t e r v a l o f c y c l e s d e p e n d s o n t h e e x e c u t e d i n s t r u c t i o n a t t h e t i m e w h e n e a c h i n t e r r u p t a c t i v a t e d c o n d i t i o n i s s a t i s f i e d . Flag cleared 2 t o 3 m a c h i n e c y c l e s N o t e s

Rev.3.00 Aug 06, 2004 page 26 of 136 REJ03B0043-0300Z Table 7 External interrupt activated conditions Name External 0 interrupt External 1 interrupt Input pin D 8/INT0 D 9/INT1 Activated condition When the next waveform is input to D8/INT0 pin

• Falling waveform (“H ”→ “L”)
• Both rising and falling waveforms When the next waveform is input to D9/INT1 pin
• Falling waveform (“H ”→ “L”)
• Both rising and falling waveforms Valid waveform selection bit I11 I12 I21 I22 Fig. 17 External interrupt circuit structure EXTERNAL INTERRUPTS The 4554 Group has the external 0 interrupt and external 1 inter- rupt. An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). The external interrupt can be controlled with the interrupt control registers I1 and I2. Rising Falling One-sided edge detection circuit Key-on wakeup E x t e r n a l 1 i n t e r r u p t T i m e r 3 c o u n t s t a r t s y n c h r o n o u s c i r c u i t Level detection circuit Edge detection circuit Skip decision (SNZI1 instruction) B o t h e d g e s d e t e c t i o n c i r c u i t I 22 EXF1 I21 D 9/ I N T 1 K 22 I23 K23 Rising Falling I 12 O n e - s i d e d e d g e d e t e c t i o n c i r c u i t Key-on wakeup EXF0 External 0 interrupt I11 D 8/ I N T 0 K20 Timer 1 count start synchronous circuitI 13 ( N o t e 1 ) Level detection circuit Edge detection circuit K21 Skip decision (SNZI0 instruction) B o t h e d g e s d e t e c t i o n c i r c u i t This symbol represents a parasitic diode on the port.N o t e s (Note 2) ( N o t e 3 ) ( N o t e 1 ) ( N o t e 2 ) ( N o t e 3 ) I I 22) L l e v e l d e t e c t e d I I 22) H l e v e l d e t e c t e d I I 22) F a l l i n g e d g e d e t e c t e d I I 22) R i s i n g e d g e d e t e c t e d

Rev.3.00 Aug 06, 2004 page 27 of 136 REJ03B0043-0300Z (1) External 0 interrupt request flag (EXF0) External 0 interrupt request flag (EXF0) is set to “1” when a valid waveform is input to D8/INT0 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to “0” when an in- terrupt occurs or when the next instruction is skipped with the skip instruction.

• External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to D 8/INT0 pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 0 interrupt is as follows. ➀ Set the bit 3 of register I1 to “1” for the INT0 pin to be in the in- put enabled state. ➁ Select the valid waveform with the bits 1 and 2 of register I1. ➂ Clear the EXF0 flag to “0” with the SNZ0 instruction. ➃ Set the NOP instruction for the case when a skip is performed with the SNZ0 instruction. ➄ Set both the external 0 interrupt enable bit (V1 0) and the INTE flag to “1.” The external 0 interrupt is now enabled. Now when a valid wave- form is input to the D8/INT0 pin, the EXF0 flag is set to “1” and the external 0 interrupt occurs. (2) External 1 interrupt request flag (EXF1) External 1 interrupt request flag (EXF1) is set to “1” when a valid waveform is input to D9/INT1 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF1 flag can be examined with the skip instruction (SNZ1). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF1 flag is cleared to “0” when an in- terrupt occurs or when the next instruction is skipped with the skip instruction.
• External 1 interrupt activated condition External 1 interrupt activated condition is satisfied when a valid waveform is input to D 9/INT1 pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 1 interrupt is as follows. ➀ Set the bit 3 of register I2 to “1” for the INT1 pin to be in the in- put enabled state. ➁ Select the valid waveform with the bits 1 and 2 of register I2. ➂ Clear the EXF1 flag to “0” with the SNZ1 instruction. ➃ Set the NOP instruction for the case when a skip is performed with the SNZ1 instruction. ➄ Set both the external 1 interrupt enable bit (V1 1) and the INTE flag to “1.” The external 1 interrupt is now enabled. Now when a valid wave- form is input to the D9/INT1 pin, the EXF1 flag is set to “1” and the external 1 interrupt occurs.

Rev.3.00 Aug 06, 2004 page 28 of 136 REJ03B0043-0300Z (3) External interrupt control registers

• Interrupt control register I1 Register I1 controls the valid waveform for the external 0 inter- rupt. Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents of register I1 to register A. Table 8 External interrupt control register
• Interrupt control register I2 Register I2 controls the valid waveform for the external 1 inter- rupt. Set the contents of this register through register A with the TI2A instruction. The TAI2 instruction can be used to transfer the contents of register I2 to register A. Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: When the contents of these bits (I12 , I13, I22 and I23) are changed, the external interrupt request flag (EXF0, EXF1) may be set. I13 I12 I11 I10 INT0 pin input control bit (Note 2) Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2) INT0 pin edge detection circuit control bit INT0 pin Timer 1 count start synchronous circuit selection bit Interrupt control register I1 R/W TAI1/TI1Aat power down : state retainedat reset : 00002 INT0 pin input disabled INT0 pin input enabled Falling waveform/“L” level (“L” level is recognized with the SNZI0 instruction) Rising waveform/“H ” level (“H ” level is recognized with the SNZI0 instruction) One-sided edge detected Both edges detected Timer 1 count start synchronous circuit not selected Timer 1 count start synchronous circuit selected I23 I22 I21 I20 INT1 pin input control bit (Note 2) Interrupt valid waveform for INT1 pin/ return level selection bit (Note 2) INT1 pin edge detection circuit control bit INT1 pin Timer 3 count start synchronous circuit selection bit Interrupt control register I2 R/W TAI2/TI2Aat power down : state retainedat reset : 00002 INT1 pin input disabled INT1 pin input enabled Falling waveform/“L” level (“L” level is recognized with the SNZI1 instruction) Rising waveform/“H ” level (“H ” level is recognized with the SNZI1 instruction) One-sided edge detected Both edges detected Timer 3 count start synchronous circuit not selected Timer 3 count start synchronous circuit selected

Rev.3.00 Aug 06, 2004 page 29 of 136 REJ03B0043-0300Z (4) Notes on External 0 interrupts ➀ Note [1] on bit 3 of register I1 When the input of the INT0 pin is controlled with the bit 3 of reg- ister I1 in software, be careful about the following notes.

• Depending on the input state of the D8/INT0 pin, the external 0 in- terrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 18➀ ) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to Figure 18➁ ). Also, set the NOP instruction for the case when a skip is per- formed with the SNZ0 instruction (refer to Figure 18➂ ). LA 4 ; ( ✕✕✕ 0 LA 8 ; (1 ✕✕✕ 2) TI1A ; Control of INT0 pin input is changed SNZ0 ; The SNZ0 instruction is executed (EXF0 flag cleared) ✕ : these bits are not used here. Fig. 18 External 0 interrupt program example-1 ➁ Note [2] on bit 3 of register I1 When the bit 3 of register I1 is cleared to “0”, the RAM back-up mode is selected and the input of INT0 pin is disabled, be careful about the following notes.
• When the key-on wakeup function of INT0 pin is not used (regis- ter K2 0 = “0”), clear bits 2 and 3 of register I1 before system enters to the RAM back-up mode. (refer to Figure 19➀ ).
• ••
• •• LA 0 ; (00 ✕✕ 2) DI EPOF POF2 ; RAM back-up ✕ : these bits are not used here. Fig. 19 External 0 interrupt program example-2
• ••
• •• ➂ Note on bit 2 of register I1 When the interrupt valid waveform of the D8/INT0 pin is changed with the bit 2 of register I1 in software, be careful about the fol- lowing notes.
• Depending on the input state of the D8/INT0 pin, the external 0 in- terrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 20➀ ) and then, change the bit 2 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to Figure 20➁ ). Also, set the NOP instruction for the case when a skip is per- formed with the SNZ0 instruction (refer to Figure 20➂ ). LA 4 ; ( ✕✕✕ 0 LA 12 ; ( ✕ 1✕✕ 2) TI1A ; Interrupt valid waveform is changed SNZ0 ; The SNZ0 instruction is executed (EXF0 flag cleared) ✕ : these bits are not used here. Fig. 20 External 0 interrupt program example-3
• ••
• ••

Rev.3.00 Aug 06, 2004 page 30 of 136 REJ03B0043-0300Z (5) Notes on External 1 interrupts ➀ Note [1] on bit 3 of register I2 When the input of the INT1 pin is controlled with the bit 3 of reg- ister I2 in software, be careful about the following notes.

• Depending on the input state of the D 9/INT1 pin, the external 1 in- terrupt request flag (EXF1) may be set when the bit 3 of register I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 21➀ ) and then, change the bit 3 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to “0” after executing at least one instruction (refer to Figure 21➁ ). Also, set the NOP instruction for the case when a skip is per- formed with the SNZ1 instruction (refer to Figure 21➂ ). LA 4 ; ( ✕✕ 0✕ LA 8 ; (1 ✕✕✕ 2) TI2A ; Control of INT1 pin input is changed SNZ1 ; The SNZ1 instruction is executed (EXF1 flag cleared) ✕ : these bits are not used here. Fig. 21 External 1 interrupt program example-1 ➁ Note [2] on bit 3 of register I2 When the bit 3 of register I2 is cleared to “0”, the RAM back-up mode is selected and the input of INT1 pin is disabled, be careful about the following notes.
• When the key-on wakeup function of INT1 pin is not used (regis- ter K2 2 = “0”), clear bits 2 and 3 of register I2 before system enters to the RAM back-up mode. (refer to Figure 22➀ ).
• ••
• •• LA 0 ; (00 ✕✕ 2) DI EPOF POF2 ; RAM back-up ✕ : these bits are not used here. Fig. 22 External 1 interrupt program example-2
• ••
• •• ➂ Note on bit 2 of register I2 When the interrupt valid waveform of the D9/INT1 pin is changed with the bit 2 of register I2 in software, be careful about the fol- lowing notes.
• Depending on the input state of the D 9/INT1 pin, the external 1 in- terrupt request flag (EXF1) may be set when the bit 2 of register I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 23➀ ) and then, change the bit 2 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to “0” after executing at least one instruction (refer to Figure 23➁ ). Also, set the NOP instruction for the case when a skip is per- formed with the SNZ1 instruction (refer to Figure 23➂ ). LA 4 ; ( ✕✕ 0✕ LA 12 ; ( ✕ 1✕✕ 2) TI2A ; Interrupt valid waveform is changed SNZ1 ; The SNZ1 instruction is executed (EXF1 flag cleared) ✕ : these bits are not used here. Fig. 23 External 1 interrupt program example-3
• ••
• ••

Rev.3.00 Aug 06, 2004 page 31 of 136 REJ03B0043-0300Z The 4554 Group has the following timers.

• Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a set- ting value n. When it underflows (count to n + 1), a timer interrupt request flag is set to “1,” new data is loaded from the reload reg- ister, and count continues (auto-reload function).
• Fixed dividing frequency timer The fixed dividing frequency timer has the fixed frequency divid- ing ratio (n). An interrupt request flag is set to “1” after every n count of a count pulse. Fig. 24 Auto-reload function The 4554 Group timer consists of the following circuits.
• Prescaler : 8-bit programmable timer
• Timer 1 : 8-bit programmable timer
• Timer 2 : 8-bit programmable timer
• Timer 3 : 8-bit programmable timer
• Timer 4 : 8-bit programmable timer
• Timer 5 : 16-bit fixed dividing frequency timer
• Timer LC : 4-bit programmable timer
• Watchdog timer : 16-bit fixed dividing frequency timer (Timers 1, 2, 3, 4 and 5 have the interrupt function, respectively) Prescaler and timers 1, 2, 3, 4, 5 and LC can be controlled with the timer control registers PA, W1 to W6. The watchdog timer is a free counter which is not controlled with the control register. Each function is described below. FF16 n 0016 n : Counter initial value C o u n t s t a r t s R e l o a d Reload 1 s t u n d e r f l o w 2 n d u n d e r f l o w n + 1 c o u n t n + 1 c o u n t T i m e An interrupt occurs or a skip instruction is executed. T i m e r i n t e r r u p t r e q u e s t f l a g T h e c o n t e n t s o f c o u n t e r “ 1 ” “ 0 ”

Rev.3.00 Aug 06, 2004 page 32 of 136 REJ03B0043-0300Z

• Instruction clock (INSTCK)
• Instruction clock (INSTCK)
• Prescaler output (ORCLK)
• Timer 5 underflow (T5UDF)
• CNTR0 input
• System clock (STCK)
• Prescaler output (ORCLK)
• Timer 1 underflow (T1UDF)
• PWM output (PWMOUT)
• PWM output (PWMOUT)
• Prescaler output (ORCLK)
• Timer 2 underflow (T2UDF)
• CNTR1 input
• X IN input
• Prescaler output (ORCLK)
• XCIN input
• Bit 4 of timer 5
• Prescaler output (ORCLK)
• Instruction clock (INSTCK) Structure 8-bit programmable binary down counter 8-bit programmable binary down counter (link to INT0 input) 8-bit programmable binary down counter 8-bit programmable binary down counter (link to INT1 input) 8-bit programmable binary down counter (PWM output function) 16-bit fixed dividing frequency 4-bit programmable binary down counter 16-bit fixed dividing frequency Circuit Prescaler Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 Timer LC Watchdog timer Use of output signal
• Timer 1, 2, 3, 4 and LC count sources
• Timer 2 count source
• CNTR0 output
• Timer 1 interrupt
• Timer 3 count source
• CNTR0 output
• Timer 2 interrupt
• CNTR1 output control
• Timer 3 interrupt
• Timer 2, 3 count source
• CNTR1 output
• Timer 4 interrupt
• Timer 1, LC count source
• Timer 5 interrupt
• LCD clock
• System reset (count twice)
• WDF flag decision Frequency dividing ratio 1 to 256 1 to 256 1 to 256 1 to 256 1 to 256 8192 16384 32768 65536 1 to 16 65534 Control register PA Table 9 Function related timers

Rev.3.00 Aug 06, 2004 page 33 of 136 REJ03B0043-0300Z Fig. 25 Timer structure (1) S T C K W2 2 W 21, W O R C L K T U D F P W M O U T T2F (TAB2) (TAB2) (T2AB)(T2AB) (T2AB) T1UDF W 0 1 T2UDF1 W 0 P o r t D 7 o u t p u t D 7/ C N T R Division circuit Divided by 8 Divided by4 Divided by 2 S y s t e m c l o c k S T C K XC I N Instruction clock (INSTCK)M u l t i p l e x e r C M C K C R C K Q u a r t z c r y s t a l o s c i l l a t i o n M R 0 O R C L K Reload register RPS (8) Prescaler (8) R e g i s t e r B Register A (TABPS) ( T A B P S )(TPSAB) P MR 3, MR2 I N S T C K R S I 12 D 8/ I N T 0 W 13 T U D F I10 I 13 I11 I10 W1 2 W 11, W ORCLK T5UDF D 7/CNTR0 T F (TAB1)(TAB1) ( T A B (T1AB) (T1AB)(TR1AB) T P S A B T P S A B P W M O U T R S I 22 D 9/ I N T 1 W 33 T U D F I20 I23 I 21 I20 W3 2 W 31, W O R C L K T U D F C/CNTR1 T F (TAB3)(TAB3) (T3AB) (T3AB) (T3AB)( T R A B T U D F P W M O U T T i m e r u n d e r f l o w s i g n a l f r o m t i m e r P W M o u t p u t s i g n a l f r o m t i m e r o u t p u t u n i t N o t e (Note 2) (Note 4) N o t e N o t e N o t e On-chip oscillator XI N C e r a m i c r e s o n a n c e C M C K R C o s c i l l a t i o n C R C K Timer 1 (8) Timer 1 interrupt Reload register R1 (8) Register BRegister A T i m e r u n d e r f l o w s i g n a l T U D F O n e - s i d e d e d g e d e t e c t i o n c i r c u i t Both edges detection circuit F a l l i n g R i s i n g N o t e O ne-sided edge detection circuit B o t h e d g e s d e t e c t i o n c i r c u i t Falling Rising T i m e r 2 i n t e r r u p t T i m e r u n d e r f l o w s i g n a l T U D F Timer 2 (8) R e l o a d r e g i s t e r R Register BRegister A Timer 3 interrupt Timer 3 underflow signal (T3UDF) T i m e r 3 ( 8 ) R e l o a d r e g i s t e r R 3 ( 8 ) Register BRegister A I n t e r n a l c l o c k g e n e r a t i n g c i r c u i t d i v i d e d b y Data is set automatically from each reload register when timer underflows (auto-reload function). Notes 1: When CMCK instruction is executed, ceramic resonance is selected. When CRCK instruction is executed, RC oscillation is selected. When any instructions are not executed, on-chip oscillator clock (internal oscillation) is selected. 2: Timer 1 count start synchronous circuit is set by the valid edge of D 8/INT0 pin selected by bits 1 (I11) and 2 (I12) of register I1. 3: Timer 3 count start synchronous circuit is set by the valid edge of D9/INT1 pin selected by bits 1 (I21) and 2 (I22) of register I2. 4: Count source is stopped by clearing to “0.”

Rev.3.00 Aug 06, 2004 page 34 of 136 REJ03B0043-0300Z Fig. 26 Timer structure (2) R e g i s t e r A R e l o a d c o n t r o l c i r c u i t T A B W4 1 Q R T T A B T i m e r R e g i s t e r B R e l o a d r e g i s t e r R H T A B T A B P W M O D (T4R4L) T F O R C L K XI N W4 1 T i m e r i n t e r r u p t W4 0 T H A B T U D F P W M O D P o r t C o u t p u t Q C C N T R W W3 0 W R D TW3 2 W W5 2 0 T i m e r T F T i m e r i n t e r r u p t Timer 5 underflow signal (T5UDF) XC I N W6 3 2 L C D c l o c k Reload register RLC (4) T i m e r L C Register A T L C A ) (TLCA) W O R C L K Watchdog reset signal W a t c h d o g t i m e r QS Q T D WDF2 R e s e t s i g n a l R Q R S W E F Reset signal R WDF1 W R S T i n s t r u c t i o n I N S T C K +DWDT instruction W R S T i n s t r u c t i o n INSTCK : ORCLK : Instruction clock (system clock divided by 3) Prescaler output (instruction clock divided by 1 to 256) N o t e N o t e PWMOUT (To timer 2 and timer 3) W H i n t e r v a l e x p a n s i o n N o t e N o t e (Note 4) N o t e (Note 7) R e g i s t e r AR e g i s t e r B Reload register R4L (8) Data is set automatically from each reload register when timer underflows (auto-reload function). Notes 4: Count source is stopped by clearing to “0.” 5: X IN cannot be used as count source when bit 1 (MR1) of register MR is set to “1” and f(XIN) oscillation is stopped. 6: This timer is initialized (initial value = FFFF16) by stop of count source (W52 = “0”). 7: Flag WDF1 is cleared to “0” and the next instruction is skipped when the WRST instruction is executed while flag WDF1 = “1”. The next instruction is not skipped even when the WRST instruction is executed while flag WDF1 = “0”. 8: Flag WEF is cleared to “0” and watchdog timer reset does not occur when the DWDT instruction and WRST instruction are executed continuously. 9: The WEF flag is set to “1” at system reset or RAM back-up mode. N o t e

Rev.3.00 Aug 06, 2004 page 35 of 136 REJ03B0043-0300Z Timer 1 underflow signal divided by 2 output Timer 2 underflow signal divided by 2 output Stop (state retained) Operating Count source System clock (STCK) Prescaler output (ORCLK) Timer 1 underflow signal (T1UDF) PWM signal (PWMOUT) CNTR0 output control bit Timer 2 control bit Timer 2 count source selection bits Timer control register W2 at power down : state retainedat reset : 00002 Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”). 3: This function is valid only when the timer 3 count start synchronous circuit is selected (I20=“1”). 4: Port C output is invalid when CNTR1 input is selected for the timer 3 count source. W2 3 W2 2 W2 1 W2 0 Stop (state initialized) Operating Prescaler control bit Timer control register PA W TPAAat power down : 02at reset : 02 PA 0 W1 1 Timer 1 count auto-stop circuit not selected Timer 1 count auto-stop circuit selected Stop (state retained) Operating Count source Instruction clock (INSTCK) Prescaler output (ORCLK) Timer 5 underflow signal (T5UDF) CNTR0 input Timer 1 count auto-stop circuit selection bit (Note 2) Timer 1 control bit Timer 1 count source selection bits Timer control register W1 R/W TAW1/TW1Aat power down : state retainedat reset : 00002 W1 3 W1 2 W1 1 W1 0 W3 1 Timer 3 count auto-stop circuit not selected Timer 3 count auto-stop circuit selected Stop (state retained) Operating Count source PWM signal (PWMOUT) Prescaler output (ORCLK) Timer 2 underflow signal (T2UDF) CNTR1 input Timer 3 count auto-stop circuit selection bit (Note 3) Timer 3 control bit Timer 3 count source selection bits (Note 4) Timer control register W3 at power down : state retainedat reset : 00002 W3 3 W3 2 W3 1 W3 0 R/W TAW2/TW2A R/W TAW3/TW3A Table 10 Timer related registers

Rev.3.00 Aug 06, 2004 page 36 of 136 REJ03B0043-0300Z Stop (state retained) Operating Bit 4 (T5 4) of timer 5 Prescaler output (ORCLK) CNTR1 output auto-control circuit not selected CNTR1 output auto-control circuit selected D 7(I/O)/CNTR0 input CNTR0 input/output/D7 (input) Timer LC control bit Timer LC count source selection bit CNTR1 output auto-control circuit selection bit D 7/CNTR0 pin function selection bit (Note 2) Timer control register W6 at power down : state retainedat reset : 00002 W6 3 W6 2 W6 1 W6 0 CNTR1 output invalid CNTR1 output valid PWM signal “H ” interval expansion function invalid PWM signal “H ” interval expansion function valid Stop (state retained) Operating X IN input Prescaler output (ORCLK) divided by 2 CNTR1 output control bit PWM signal “H ” interval expansion function control bit Timer 4 control bit Timer 4 count source selection bit W4 3 W4 2 W4 1 W4 0 W5 1 Not used Timer 5 control bit Timer 5 count value selection bits Timer control register W5 at power down : state retainedat reset : 00002 W5 3 W5 2 W5 1 W5 0 Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: CNTR0 input is valid only when CNTR0 input is selected for the timer 1 count source. This bit has no function, but read/write is enabled. Stop (state initialized) Operating Count value Underflow occurs every 8192 counts Underflow occurs every 16384 counts Underflow occurs every 32768 counts Underflow occurs every 65536 counts R/W TAW4/TW4A Timer control register W4 at power down : 00002at reset : 00002 R/W TAW5/TW5A R/W TAW6/TW6A

Rev.3.00 Aug 06, 2004 page 37 of 136 REJ03B0043-0300Z (1) Timer control registers

• Timer control register PA Register PA controls the count operation of prescaler. Set the contents of this register through register A with the TPAA instruc- tion.
• Timer control register W1 Register W1 controls the selection of timer 1 count auto-stop cir- cuit, and the count operation and count source of timer 1. Set the contents of this register through register A with the TW1A instruc- tion. The TAW1 instruction can be used to transfer the contents of register W1 to register A.
• Timer control register W2 Register W2 controls the selection of CNTR0 output, and the count operation and count source of timer 2. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A.
• Timer control register W3 Register W3 controls the selection of timer 3 count auto-stop cir- cuit, and the count operation and count source of timer 3. Set the contents of this register through register A with the TW3A instruc- tion. The TAW3 instruction can be used to transfer the contents of register W3 to register A.
• Timer control register W4 Register W4 controls the CNTR1 output, the expansion of “H ” in- terval of PWM output, and the count operation and count source of timer 4. Set the contents of this register through register A with the TW4A instruction. The TAW4 instruction can be used to trans- fer the contents of register W4 to register A.
• Timer control register W5 Register W5 controls the count operation and count source of timer 5. Set the contents of this register through register A with the TW5A instruction. The TAW5 instruction can be used to trans- fer the contents of register W5 to register A.
• Timer control register W6 Register W6 controls the operation and count source of timer LC, the selection of CNTR1 output auto-control circuit and the D CNTR0 pin function. Set the contents of this register through reg- ister A with the TW6A instruction. The TAW6 instruction can be used to transfer the contents of register W6 to register A.. (2) Prescaler (interrupt function) Prescaler is an 8-bit binary down counter with the prescaler reload register PRS. Data can be set simultaneously in prescaler and the reload register RPS with the TPSAB instruction. Data can be read from reload register RPS with the TABPS instruction. Stop counting and then execute the TPSAB or TABPS instruction to read or set prescaler data. Prescaler starts counting after the following process; ➀ set data in prescaler, and ➁ set the bit 0 of register PA to “1.” When a value set in reload register RPS is n, prescaler divides the count source signal by n + 1 (n = 0 to 255). Count source for prescaler is the instruction clock (INSTCK). Once count is started, when prescaler underflows (the next count pulse is input after the contents of prescaler becomes “0”), new data is loaded from reload register RPS, and count continues (auto-reload function). The output signal (ORCLK) of prescaler can be used for timer 1, 2, 3, 4 and LC count sources. (3) Timer 1 (interrupt function) Timer 1 is an 8-bit binary down counter with the timer 1 reload reg- ister (R1). Data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. Data can be written to re- load register (R1) with the TR1AB instruction. Data can be read from timer 1 with the TAB1 instruction. Stop counting and then execute the T1AB or TAB1 instruction to read or set timer 1 data. When executing the TR1AB instruction to set data to reload regis- ter R1 while timer 1 is operating, avoid a timing when timer 1 underflows. Timer 1 starts counting after the following process; ➀ set data in timer 1 ➁ set count source by bits 0 and 1 of register W1, and ➂ set the bit 2 of register W1 to “1.” When a value set in reload register R1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes “0”), the timer 1 interrupt request flag (T1F) is set to “1,” new data is loaded from reload register R1, and count continues (auto-reload function). INT0 pin input can be used as the start trigger for timer 1 count op- eration by setting the bit 0 of register I1 to “1.” Also, in this time, the auto-stop function by timer 1 underflow can be performed by setting the bit 3 of register W1 to “1.” Timer 1 underflow signal divided by 2 can be output from CNTR0 pin by clearing bit 3 of register W2 to “0” and setting bit 0 of regis- ter W6 to “1”.

Rev.3.00 Aug 06, 2004 page 38 of 136 REJ03B0043-0300Z (4) Timer 2 (interrupt function) Timer 2 is an 8-bit binary down counter with the timer 2 reload reg- ister (R2). Data can be set simultaneously in timer 2 and the reload register (R2) with the T2AB instruction. Data can be read from timer 2 with the TAB2 instruction. Stop counting and then execute the T2AB or TAB2 instruction to read or set timer 2 data. Timer 2 starts counting after the following process; ➀ set data in timer 2, ➁ select the count source with the bits 0 and 1 of register W2, and ➂ set the bit 2 of register W2 to “1.” When a value set in reload register R2 is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes “0”), the timer 2 interrupt request flag (T2F) is set to “1,” new data is loaded from reload register R2, and count continues (auto-reload function). Timer 2 underflow signal divided by 2 can be output from CNTR0 pin by setting bit 3 of register W2 to “1” and setting bit 0 of register W6 to “1”. (5) Timer 3 (interrupt function) Timer 3 is an 8-bit binary down counter with the timer 3 reload reg- ister (R3). Data can be set simultaneously in timer 3 and the reload register (R3) with the T3AB instruction. Data can be written to re- load register (R3) with the TR3AB instruction. Data can be read from timer 3 with the TAB3 instruction. Stop counting and then execute the T3AB or TAB3 instruction to read or set timer 3 data. When executing the TR3AB instruction to set data to reload regis- ter R3 while timer 3 is operating, avoid a timing when timer 3 underflows. Timer 3 starts counting after the following process; ➀ set data in timer 3 ➁ set count source by bits 0 and 1 of register W3, and ➂ set the bit 2 of register W3 to “1.” When a value set in reload register R3 is n, timer 3 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 3 underflows (the next count pulse is input after the contents of timer 3 becomes “0”), the timer 3 interrupt request flag (T3F) is set to “1,” new data is loaded from reload register R3, and count continues (auto-reload function). INT1 pin input can be used as the start trigger for timer 3 count op- eration by setting the bit 0 of register I2 to “1.” Also, in this time, the auto-stop function by timer 3 underflow can be performed by setting the bit 3 of register W3 to “1.” (6) Timer 4 (interrupt function) Timer 4 is an 8-bit binary down counter with two timer 4 reload reg- isters (R4L, R4H). Data can be set simultaneously in timer 4 and the reload register R4L with the T4AB instruction. Data can be set in the reload register R4H with the T4HAB instruction. The contents of reload register R4L set with the T4AB instruction can be set to timer 4 again with the T4R4L instruction. Data can be read from timer 4 with the TAB4 instruction. Stop counting and then execute the T4AB or TAB4 instruction to read or set timer 4 data. When executing the T4HAB instruction to set data to reload regis- ter R4H while timer 4 is operating, avoid a timing when timer 4 underflows. Timer 4 starts counting after the following process; ➀ set data in timer 4 ➁ set count source by bit 0 of register W4, and ➂ set the bit 1 of register W4 to “1.” When a value set in reload register R4L is n, timer 4 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 4 underflows (the next count pulse is input after the contents of timer 4 becomes “0”), the timer 4 interrupt request flag (T4F) is set to “1,” new data is loaded from reload register R4L, and count continues (auto-reload function). When bit 3 of register W4 is set to “1”, timer 4 reloads data from re- load register R4L and R4H alternately each underflow. Timer 4 generates the PWM signal (PWMOUT) of the “L” interval set as reload register R4L, and the “H ” interval set as reload regis- ter R4H. The PWM signal (PWMOUT) is output from CNTR1 pin. When bit 2 of register W4 is set to “1” at this time, the interval (PWM signal “H ” interval) set to reload register R4H for the counter of timer 4 is extended for a half period of count source. In this case, when a value set in reload register R4H is n, timer 4 divides the count source signal by n + 1.5 (n = 1 to 255). When this function is used, set “1” or more to reload register R4H. When bit 1 of register W6 is set to “1”, the PWM signal output to CNTR1 pin is switched to valid/invalid each timer 3 underflow. However, when timer 3 is stopped (bit 2 of register W3 is cleared to “0”), this function is canceled. Even when bit 1 of a register W4 is cleared to “0” in the “H ” interval of PWM signal, timer 4 does not stop until it next timer 4 underflow. When clearing bit 1 of register W4 to “0” to stop timer 4, avoid a timing when timer 4 underflows.

Rev.3.00 Aug 06, 2004 page 39 of 136 REJ03B0043-0300Z (7) Timer 5 (interrupt function) Timer 5 is a 16-bit binary down counter. Timer 5 starts counting after the following process; ➀ set count value by bits 0 and 1 of register W5, and ➁ set the bit 2 of register W5 to “1.” Count source for timer 5 is the sub-clock input (XCIN). Once count is started, when timer 5 underflows (the set count value is counted), the timer 5 interrupt request flag (T5F) is set to “1,” and count continues. Bit 4 of timer 5 can be used as the timer LC count source for the LCD clock generating. When bit 2 of register W5 is cleared to “0”, timer 5 is initialized to “FFFF 16” and count is stopped. Timer 5 can be used as the counter for clock because it can be op- erated at clock operating mode (POF instruction execution). When timer 5 underflow occurs at clock operating mode, system returns from the power down state. (8) Timer LC Timer LC is a 4-bit binary down counter with the timer LC reload register (RLC). Data can be set simultaneously in timer LC and the reload register (RLC) with the TLCA instruction. Data cannot be read from timer LC. Stop counting and then execute the TLCA in- struction to set timer LC data. Timer LC starts counting after the following process; ➀ set data in timer LC, ➁ select the count source with the bit 2 of register W6, and ➂ set the bit 3 of register W6 to “1.” When a value set in reload register RLC is n, timer LC divides the count source signal by n + 1 (n = 0 to 15). Once count is started, when timer LC underflows (the next count pulse is input after the contents of timer LC becomes “0”), new data is loaded from reload register RLC, and count continues (auto-re- load function). Timer LC underflow signal divided by 2 can be used for the LCD clock. (9) Timer input/output pin (D7/CNTR0 pin, C/CNTR1 pin) CNTR0 pin is used to input the timer 1 count source and output the timer 1 and timer 2 underflow signal divided by 2. CNTR1 pin is used to input the timer 3 count source and output the PWM signal generated by timer 4. When the PWM signal is output from C/CNTR1 pin, set “0” to the output latch of port C. The D 7/CNTR0 pin function can be selected by bit 0 of register W6. The selection of CNTR1 output signal can be controlled by bit 3 of register W4. When the CNTR0 input is selected for timer 1 count source, timer 1 counts the rising waveform of CNTR0 input. When the CNTR1 input is selected for timer 3 count source, timer 3 counts the rising waveform of CNTR1 input. Also, when the CNTR1 input is selected, the output of port C is invalid (high-im- pedance state). (10) Timer interrupt request flags (T1F, T2F, T3F, T4F, T5F) Each timer interrupt request flag is set to “1” when each timer underflows. The state of these flags can be examined with the skip instructions (SNZT1, SNZT2, SNZT3, SNZT4, SNZT5). Use the interrupt control register V1, V2 to select an interrupt or a skip instruction. An interrupt request flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with a skip instruction.

Rev.3.00 Aug 06, 2004 page 40 of 136 REJ03B0043-0300Z (11) Count start synchronization circuit (timer 1, timer 3) Timer 1 and timer 3 have the count start synchronous circuit which synchronizes the input of INT0 pin and INT1 pin, and can start the timer count operation. Timer 1 count start synchronous circuit function is selected by set- ting the bit 0 of register I1 to “1” and the control by INT0 pin input can be performed. Timer 3 count start synchronous circuit function is selected by set- ting the bit 0 of register I2 to “1” and the control by INT1 pin input can be performed. When timer 1 or timer 3 count start synchronous circuit is used, the count start synchronous circuit is set, the count source is input to each timer by inputting valid waveform to INT0 pin or INT1 pin. The valid waveform of INT0 pin or INT1 pin to set the count start synchronous circuit is the same as the external interrupt activated condition. Once set, the count start synchronous circuit is cleared by clearing the bit I1 0 or I20 to “0” or reset. However, when the count auto-stop circuit is selected, the count start synchronous circuit is cleared (auto-stop) at the timer 1 or timer 3 underflow. (12) Count auto-stop circuit (timer 1, timer 3) Timer 1 has the count auto-stop circuit which is used to stop timer 1 automatically by the timer 1 underflow when the count start syn- chronous circuit is used. The count auto-stop cicuit is valid by setting the bit 3 of register W1 to “1”. It is cleared by the timer 1 underflow and the count source to timer 1 is stopped. This function is valid only when the timer 1 count start synchronous circuit is selected. Timer 3 has the count auto-stop circuit which is used to stop timer 3 automatically by the timer 3 underflow when the count start syn- chronous circuit is used. The count auto-stop cicuit is valid by setting the bit 3 of register W3 to “1”. It is cleared by the timer 3 underflow and the count source to timer 3 is stopped. This function is valid only when the timer 3 count start synchronous circuit is selected. (13) Precautions Note the following for the use of timers.

• Prescaler Stop counting and then execute the TABPS instruction to read from prescaler data. Stop counting and then execute the TPSAB instruction to set prescaler data.
• Timer count source Stop timer 1, 2, 3, 4 and LC counting to change its count source.
• Reading the count value Stop timer 1, 2, 3 or 4 counting and then execute the data read instruction (TAB1, TAB2, TAB3, TAB4) to read its data.
• Writing to the timer Stop timer 1, 2, 3, 4 or LC counting and then execute the data write instruction (T1AB, T2AB, T3AB, T4AB, TLCA) to write its data.
• Writing to reload register R1, R3, R4H When writing data to reload register R1, reload register R3 or re- load regiser R4H while timer 1, timer 3 or timer 4 is operating, avoid a timing when timer 1, timer 3 or timer 4 underflows.
• Timer 4 Avoid a timing when timer 4 underflows to stop timer 4. When “H ” interval extension function of the PWM signal is set to be “valid”, set “1” or more to reload register R4H.
• Timer 5 Stop timer 5 counting to change its count source.
• Timer input/output pin Set the port C output latch to “0” to output the PWM signal from C/CNTR pin.

Rev.3.00 Aug 06, 2004 page 41 of 136 REJ03B0043-0300Z Fig. 27 Timer 4 operation (reload register R4L: “0316”, R4H: “0216”) G CNTR1 output: invalid (W43 = “0”) T i m e r c o u n t s o u r c e T i m e r c o u n t v a l u e R e l o a d r e g i s t e r 0216 0 6 0016 0 6 0 6 0 6 0016 0316 0216 0 6 0016 0 6 0216 0 6 0 6 0 6 0 6 0 6 0 R L T i m e r u n d e r f l o w s i g n a l P W M s i g n a l o u t p u t i n v a l i d T i m e r s t a r t P W M s i g n a l L f i x e d 02160 6 0 6 0016 0 6 0 6 0 6 0316 0216 0116 0 6 0216 0 6 0016 0 6 0 6 0 6 0 6 0 6 0 (R2H) PWM period 7 clock PWM period 7 clock 6 0 6 00160216 0216 0116 0 6 0216 0116 00160316 0 6 0116 0 6 0 6 0 6 0 6 0 R L R H ) (R2L) (R2H) ( R L R H PWM period 7.5 clock P W M p e r i o d c l o c k G C N T R o u t p u t v a l i d W P W M s i g n a l H i n t e r v a l e x t e n s i o n f u n c t i o n i n v a l i d W T i m e r c o u n t s o u r c e Timer 4 count value R e l o a d r e g i s t e r Timer 4 underflow signal P W M s i g n a l Timer 4 count source T i m e r c o u n t v a l u e R e l o a d r e g i s t e r Timer 4 underflow signal P W M s i g n a l T i m e r s t a r t T i m e r s t a r t G C N T R o u t p u t v a l i d W P W M s i g n a l H i n t e r v a l e x t e n s i o n f u n c t i o n v a l i d W N o t e Note: At PWM signal “H ” interval extension function: valid, set “0116” or more to reload register R4H. R L (R2H) (R2L) (R2H) (R2L) (R2L) (R2L) ( R L R L 3 clock 3 clock 3.5 clock3.5 clock

Rev.3.00 Aug 06, 2004 page 42 of 136 REJ03B0043-0300Z Fig. 28 CNTR1 output auto-control function by timer 3 C N T R o u t p u t a u t o c o n t r o l c i r c u i t b y t i m e r i s s e l e c t e d C N T R o u t p u t R e g i s t e r W When the CNTR1 output auto-control function is set to be invalid while the CNTR1 output is invalid, the CNTR1 output invalid state is retained. When the CNTR1 output auto-control function is set to be invalid while the CNTR1 output is valid, the CNTR1 output valid state is retained. When timer 3 is stopped, the CNTR1 output auto-control function becomes invalid. Note: When the PWM signal is output from C/CNTR1 pin, set the output latch of port C to “0”. G C N T R o u t p u t v a l i d W C N T R o u t p u t a u t o c o n t r o l c i r c u i t s e l e c t e d W T i m e r u n d e r f l o w s i g n a l PWM signal T i m e r s t a r t C N T R o u t p u t s t a r t G C N T R o u t p u t a u t o c o n t r o l f u n c t i o n CNTR1 output T i m e r u n d e r f l o w s i g n a l PWM signal T i m e r s t a r t CNTR1 output start T i m e r s t o p C N T R o u t p u t s t o p

Rev.3.00 Aug 06, 2004 page 43 of 136 REJ03B0043-0300Z Fig. 29 Timer 4 count start/stop timing (R4L) (R4H) ( R 4 L ) T i m e r 4 c o u n t s t a r t t i m i n g W a v e f o r m e x t e n s i o n f u n c t i o n o f C N T R 1 o u t p u t “ H ” i n t e r v a l : I n v a l i d ( W 42 = “ 0 ” ) , C N T R o u t p u t v a l i d W C o u n t s o u r c e XI N i n p u t s e l e c t e d W R e l o a d r e g i s t e r R L R e l o a d r e g i s t e r R H T i m e r 4 c o u n t s t a r t t i m i n g T W 4 A i n s t r u c t i o n e x e c u t i o n c y c l e ( W 41) ¨ 1 0216 0116 0016 021603160216 0116 00160316 021600160016 0216 0116 0016 0316 0216 01160216 ( R 2 H )(R2L) 0116 ( R 2 H ) ( N o t e 1 ) N o t e s 1 : I n o r d e r t o s t o p t i m e r 4 a t C N T R 1 o u t p u t v a l i d ( W 43 = “ 1 ” ) , a v o i d a t i m i n g w h e n t i m e r 4 u n d e r f l o w s . I f t h e s e t i m i n g s o v e r l a p a h a z a r d m a y o c c u r i n a C N T R o u t p u t w a v e f o r m A t C N T R o u t p u t v a l i d t i m e r s t o p s a f t e r H i n t e r v a l o f P W M s i g n a l s e t b y r e l o a d r e g i s t e r R H i s o u t p u t M i Mi+1 M i + 2 M iM i + 1 M i + 2 0116T i m e r 4 c o u n t v a l u e ( R e l o a d r e g i s t e r ) T i m e r 4 u n d e r f l o w s i g n a l PWM signal M a c h i n e c y c l e XI N i n p u t c o u n t s o u r c e s e l e c t e d S y s t e m c l o c k f S T C K f XI N ) Register W41 G T i m e r 4 c o u n t s t o p t i m i n g TW4A instruction execution cycle (W41) ¨ 0 Timer 4 count stop timing Timer 4 count value (Reload register) T i m e r 4 u n d e r f l o w s i g n a l PWM signal M a c h i n e c y c l e XIN input (count source selected) S y s t e m c l o c k f S T C K f XI N ) R e g i s t e r W 41

Rev.3.00 Aug 06, 2004 page 44 of 136 REJ03B0043-0300Z Watchdog timer provides a method to reset the system when a pro- gram run-away occurs. Watchdog timer consists of timer WDT(16-bit binary counter), watchdog timer enable flag (WEF), and watchdog timer flags (WDF1, WDF2). The timer WDT downcounts the instruction clocks as the count source from “FFFF 16” after system is released from reset. After the count is started, when the timer WDT underflow occurs (after the count value of timer WDT reaches “0000 16,” the next count pulse is input), the WDF1 flag is set to “1.” If the WRST instruction is never executed until the timer WDT un- derflow occurs (until timer WDT counts 65534), WDF2 flag is set to “1,” and the RESET pin outputs “L” level to reset the microcom- puter. Execute the WRST instruction at each period of 65534 machine cycle or less by software when using watchdog timer to keep the microcomputer operating normally. When the WEF flag is set to “1” after system is released from reset, the watchdog timer function is valid. When the DWDT instruction and the WRST instruction are ex- ecuted continuously, the WEF flag is cleared to “0” and the watchdog timer function is invalid. The WEF flag is set to "1" at system reset or RAM back-up mode. The WRST instruction has the skip function. When the WRST in- struction is executed while the WDF1 flag is “1”, the WDF1 flag is cleared to “0” and the next instruction is skipped. When the WRST instruction is executed while the WDF1 flag is “0”, the next instruction is not skipped. The skip function of the WRST instruction can be used even when the watchdog timer function is invalid. Fig. 30 Watchdog timer function c o u n t N o t e V a l u e o f b i t t i m e r W D T W D F f l a g W R S T i n s t r u c t i o n e x e c u t e d s k i p e x e c u t e d R E S E T p i n o u t p u t WDF2 flag ➄ System reset➀ Reset released A f t e r s y s t e m i s r e l e a s e d f r o m r e s e t a f t e r p r o g r a m i s s t a r t e d t i m e r W D T s t a r t s c o u n t d o w n W h e n t i m e r W D T u n d e r f l o w o c c u r s W D F f l a g i s s e t t o W h e n t h e W R S T i n s t r u c t i o n i s e x e c u t e d W D F f l a g i s c l e a r e d t o t h e n e x t i n s t r u c t i o n i s s k i p p e d W h e n t i m e r W D T u n d e r f l o w o c c u r s w h i l e W D F f l a g i s W D F f l a g i s s e t t o a n d t h e w a t c h d o g r e s e t s i g n a l i s o u t p u t T h e o u t p u t t r a n s i s t o r o f R E S E T p i n i s t u r n e d O N b y t h e w a t c h d o g r e s e t s i g n a l a n d s y s t e m r e s e t i s e x e c u t e d N o t e T h e n u m b e r o f c o u n t i s e q u a l t o t h e n u m b e r o f c y c l e b e c a u s e t h e c o u n t s o u r c e o f w a t c h d o g t i m e r i s t h e i n s t r u c t i o n c l o c k F F F 000016 ➁ ➁

Rev.3.00 Aug 06, 2004 page 45 of 136 REJ03B0043-0300Z Fig. 31 Program example to start/stop watchdog timer Fig. 32 Program example to enter the mode when using the watchdog timer WRST ; WDF1 flag cleared DI DWDT ; Wat chdog timer function enabled/disabled WRST ; WEF and WDF1 flags cleared

• ••
• •• WRST ; WDF1 flag cleared NOP DI ; Interrupt disabled EPOF ; POF instruction enabled POF Oscillation stop
• ••
• •• When the watchdog timer is used, clear the WDF1 flag at the pe- riod of 65534 machine cycles or less with the WRST instruction. When the watchdog timer is not used, execute the DWDT instruc- tion and the WRST instruction continuously (refer to Figure 31). The watchdog timer is not stopped with only the DWDT instruction. The contents of WDF1 flag and timer WDT are initialized at the power down mode. When using the watchdog timer and the power down mode, initial- ize the WDF1 flag with the WRST instruction just before the microcomputer enters the power down state (refer to Figure 32). The watchdog timer function is valid after system is returned from the power down. When not using the watchdog timer function, ex- ecute the DWDT instruction and the WRST instruction continuously every system is returned from the power down, and stop the watch- dog timer function.
• ••

Rev.3.00 Aug 06, 2004 page 46 of 136 REJ03B0043-0300Z The 4554 Group has an LCD (Liquid Crystal Display) controller/ driver. When the proper voltage is applied to LCD power supply in- put pins (VLC1 –V LC3 ) and data are set in timer control register (W6), timer LC, LCD control registers (L1, L2), and LCD RAM, the LCD controller/driver automatically reads the display data and con- trols the LCD display by setting duty and bias. 4 common signal output pins and 32 segment signal output pins can be used to drive the LCD. By using these pins, up to 128 seg- ments (when 1/4 duty and 1/3 bias are selected) can be controlled to display. The LCD power input pins (V LC1 –VLC3 ) are also used as pins SEG0–SEG 2. When SEG 0–SEG 2 are selected, the internal power (VDD ) is used for the LCD power. (1) Duty and bias There are 3 combinations of duty and bias for displaying data on the LCD. Use bits 0 and 1 of LCD control register (L1) to select the proper display method for the LCD panel being used.

• 1/2 duty, 1/2 bias
• 1/3 duty, 1/3 bias
• 1/4 duty, 1/3 bias Table 11 Duty and maximum number of displayed pixels (2) LCD clock control The LCD clock is determined by the timer LC count source selec- tion bit (W62), timer LC control bit (W63), and timer LC. Accordingly, the frequency (F) of the LCD clock is obtained by the following formula. Numbers (➀ to ➂ ) shown below the formula cor- respond to numbers in Figure 33, respectively.
• When using the prescaler output (ORCLK) as timer LC count source (W62=“1”) F = ORCLK ✕✕
• When using the bit 4 of timer 5 as timer LC count source (W62=“0”) F = T5 4 ✕✕ [LC: 0 to 15] The frame frequency and frame period for each display method can be obtained by the following formula: Frame frequency = (Hz) Frame period = (s) F: LCD clock frequency 1/n: Duty Fig. 33 LCD clock control circuit structure Duty Used COM pins COM 0, COM 1 (Note) COM 0–COM 2 (Note) COM 0–COM 3 Maximum number of displayed pixels 64 segments 96 segments 128 segments Note: Leave unused COM pins open. LC + 1 ➀➁ ➂ LC + 1 ➀➁ ➂ F n n F N o t e : C o u n t s o u r c e i s s t o p p e d b y s e t t i n g “ 0 ” t o t h i s b i t . Timer LC 1/2 W 63 ( N o t e ) T 54 W 62 1O R C L K L C D c l o c k ( 4 ) Reload register RLC ( 4 ) R e g i s t e r A ( T L C A ) (TLCA)

Rev.3.00 Aug 06, 2004 page 47 of 136 REJ03B0043-0300Z Fig. 34 LCD controller/driver C o m m o n d r i v e r B i a s c o n t r o l M u l t i p l e x e r S e l e c t o r RAM S e g m e n t d r i v e r S e l e c t o r RAM C O M 3 C O M 2 C O M 1 C O M 0 Decoder S E G 3 c o u n t e r LCD clock (from timer block) L 10L 11L 12L Register A L C D O N O F F c o n t r o l Control signal S E G 0/ VL C S E G 3 S e g m e n t d r i v e r ... S E G 1 VL C S E G 2/ VL C S E G 0 t o S E G 2 o u t p u t L 20L 21L22L r r r r r r t o (3) LCD RAM RAM contains areas corresponding to the liquid crystal display. When “1” is written to this LCD RAM, the display pixel correspond- ing to the bit is automatically displayed. (4) LCD drive waveform When “1” is written to a bit in the LCD RAM data, the voltage differ- ence between common pin and segment pin which correspond to the bit automatically becomes lVLC3 l and the display pixel at the cross section turns on. When returning from reset, and in the RAM back-up mode, a dis- play pixel turns off because every segment output pin and common output pin becomes V LC3 level. Fig. 35 LCD RAM map Z X Y Bits 1 0 1 1 1 2 1 3 1 4 1 5 C O M 1 4 321032103210 S E G 1 S E G 2 S E G 3 S E G 4 S E G 5 S E G 6 S E G 7 C O M 3 S E G 1 S E G 2 S E G 3 S E G 4 S E G 5 S E G 6 S E G 7 C O M 2 S E G 1 S E G 2 S E G 3 S E G 4 S E G 5 S E G 6 S E G 7 C O M 1 S E G 1 S E G 2 S E G 3 S E G 4 S E G 5 S E G 6 S E G 7 C O M 0 S E G 9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 C O M 3 C O M 2 C O M 1 COM 0 COM 3 COM 2 C O M 1 COM 0 SEG 9 S E G 1 S E G 1 S E G 1 S E G 1 S E G 1 S E G 1 SEG 9 S E G 1 S E G 1 S E G 1 S E G 1 S E G 1 S E G 1 S E G 0 S E G 0 S E G 0 S E G 0 S E G 8 S E G 1 S E G 1 S E G 1 S E G 1 6SEG 8 SEG 8 S E G 8 S E G 9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 17 SEG 18 SEG 19 SEG 16 S E G 1 SEG 18 S E G 1 S E G 1 S E G 1 SEG 18 S E G 1 S E G 1 1 2 13 N o t e : T h e a r e a m a r k e d “ ” i s n o t t h e L C D d i s p l a y R A M . S E G 2 S E G 2 S E G 2 S E G 2 1 4 3210 COM 3 C O M 2 C O M 1 COM 0 S E G 2 S E G 2 S E G 2 S E G 2 S E G 2 S E G 3 S E G 3 S E G 2 S E G 2 S E G 2 S E G 2 S E G 2 S E G 2 S E G 2 S E G 2 S E G 2 SEG 21 SEG 22 SEG 23 SEG 20 SEG 25 SEG 26 SEG 27 SEG 24 SEG 29 SEG 30 SEG 31 SEG 28 SEG 25 SEG 26 SEG 27 SEG 24 SEG 29 SEG 30 SEG 31 SEG 28 S E G 2 S E G 2 S E G 2 S E G 2 S E G 2 S E G 3 S E G 3 S E G 2

Rev.3.00 Aug 06, 2004 page 48 of 136 REJ03B0043-0300Z Table 12 LCD control registers Internal dividing resistor for LCD power supply selection bit (Note 2) LCD control bit LCD control register L1 L13 L12 L11 L10 at reset : 00002 at power down : state retained Duty Bias LCD control register L2 at reset : 0000 2 at power down : state retained W TL2A SEG VLC3 SEG 1 VLC2 SEG 2 VLC1 Internal dividing resistor valid Internal dividing resistor invalid L23 L22 L21 L20 VLC3 /SEG 0 pin function switch bit (Note 3) VLC2 /SEG 1 pin function switch bit (Note 4) VLC1 /SEG 2 pin function switch bit (Note 4) Internal dividing resistor for LCD power supply control bit 2r ✕ 3, 2r ✕ 2 r ✕ 3, r ✕ 2 Off On Not available R/W TAL1/TL1A LCD duty and bias selection bits LCD control register L3 at reset : 0000 2 at power down : state retained W TL3A SEG 24–SEG 27 P33–P30 SEG 28, SEG29 P23, P22 SEG 30 P21 SEG 31 P20 L33 L32 L31 L30 SEG 24/P33–SEG 27/P30 pin function switch bit SEG 28/P23, SEG29/P22 pin function switch bit SEG 30/P21 pin function switch bit SEG 31/P20 pin function switch bit Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: “r (resistor) multiplied by 3” is used at 1/3 bias, and “r multiplied by 2” is used at 1/2 bias. 3: VLC3 is connected to VDD internally when SEG0 pin is selected. 4: Use internal dividing resistor when SEG1 and SEG2 pins are selected.

Rev.3.00 Aug 06, 2004 page 49 of 136 REJ03B0043-0300Z Fig. 36 LCD controller/driver structure C O M 1 C O M 0 S E G 1 VL C 3 VL C 1= VL C 2 VS S VL C 3 VL C 1= VL C 2 VS S 1 flame (2/F) 1/F O N O F F V o l t a g e l e v e l ( b i t 0 )C O M 0 C O M 1 S E G 1 X X ( b i t 3 ) M ( 1 , 1 4 , 8 ) COM 1 SEG 16 C O M 0 S E G 1 1 flame (3/F) 1/F ON OFF ON COM 2 VL C 3 VL C 2 VLC 1 VS S C O M 1 COM 0 S E G 1 VLC 3 VLC 2 VL C 1 VSS V o l t a g e l e v e l (bit 0)COM 0 C O M 1 C O M 2 S E G 1 X ( b i t 3 ) M ( 1 , 1 4 , 8 ) COM 2 SEG 16 COM 1 SEG 16 COM 0 SEG 16 1 f l a m e ( 4 / F ) 1 / F O NO F F C O M 3 C O M 2 C O M 1 COM 0 S E G 1 VLC 3 VLC 2 VLC 1 VSS VLC 3 VLC 2 VLC 1 VSS Voltage level (bit 0)C O M 0 COM 1 C O M 2 COM 3 SEG 16 (bit 3) M ( 1 , 1 4 , 8 ) COM 3 S E G 1 COM 2 SEG 16 COM 1 SEG 16 COM 0 SEG 16 F : L C D c l o c k f r e q u e n c y X: S e t a n a r b i t r a r y v a l u e . ( T h e s e b i t s a r e n o t r e l a t e d t o se t t h e d r i v e w a v e f o r m a t e a c h d u t y ) O NO F F 1 / 2 D u t y , 1 / 2 B i a s : W h e n w r i t i n g ( X X 1 0 )2 t o a d d r e s s M ( 1 , 1 4 , 8 ) i n R A M . 1/3 Duty, 1/3 Bias: When writing (X101)2 to address M (1, 14, 8) in RAM. 1/4 Duty, 1/3 Bias: When writing (1010)2 to address M (1, 14, 8) in RAM.

Rev.3.00 Aug 06, 2004 page 50 of 136 REJ03B0043-0300Z (5) LCD power supply circuit

• Internal dividing resistor The 4554 Group has the internal dividing resistor for LCD power supply. When bit 0 of register L2 is set to “0”, the internal dividing resis- tor is valid. However, when the LCD is turned off by setting bit 2 of register L1 to “0”, the internal dividing resistor is turned off. The same six resistor (r) is prepared for the internal dividing re- sistor. According to the setting value of bit 3 of register L1 and using bias condition, the resistor is prepared as follows;
• L1 3 = “0”, 1/3 bias used: 2r ✕ 3 = 6r
• L13 = “0”, 1/2 bias used: 2r ✕ 2 = 4r
• L13 = “1”, 1/3 bias used: r ✕ 3 = 3r
• L13 = “1”, 1/2 bias used: r ✕ 2 = 2r
• VLC3 /SEG 0 pin The selection of VLC3 /SEG 0 pin function is controlled with the bit 3 of register L2. When the VLC3 pin function is selected, apply voltage of VLC3 < VDD to the pin externally. When the SEG 0 pin function is selected, VLC3 is connected to VDD internally.
• VLC2 /SEG 1, VLC1 /SEG 2 pin The selection of VLC2 /SEG 1 pin function is controlled with the bit 2 of register L2. The selection of V LC1 /SEG 2 pin function is controlled with the bit 1 of register L2. When the VLC2 pin and VLC1 pin functions are selected and the internal dividing resistor is not used, apply voltage of 0<V LC1 <V LC2 <V LC3 to these pins. Short the VLC2 pin and VLC1 pin at 1/2 bias. When the V LC2 pin and VLC1 pin functions are selected and the internal dividing resistor is used, the dividing voltage value gener- ated internally is output from the VLC1 pin and VLC2 pin. The VLC2 pin and VLC1 pin has the same electric potential at 1/2 bias. When SEG 1 and SEG2 pin function is selected, use the internal dividing resistor. In this time, VLC2 and VLC1 are connected to the generated dividingg voltage.

Rev.3.00 Aug 06, 2004 page 51 of 136 REJ03B0043-0300Z System reset is performed by applying “L” level to RESET pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions. Then when “H ” level is applied to RESET pin, software starts from address 0 in page 0. Fig. 37 Reset release timing Fig. 38 RESET pin input waveform and reset operation f(XIN) R E S E T P r o g r a m s t a r t s a d d r e s s i n p a g e On-chip oscillator (internal oscillator) is counted 5400 to 5424 times. Note: The number of clock cycles depends on the internal state of the microcomputer when reset is performed. RESET VD D 0.85VDD (Note) N o t e K e e p t h e v a l u e o f s u p p l y v o l t a g e t o t h e m i n i m u m v a l u e o r m o r e o f t h e r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s R e s e t i n p u t m a c h i n e c y c l e o r m o r e Program starts (address 0 in page 0) On-chip oscillator (internal oscillator) is counted 5400 to 5424 times.

Rev.3.00 Aug 06, 2004 page 52 of 136 REJ03B0043-0300Z Fig. 39 Structure of reset pin and its peripherals,, and power-on reset operation Name D 0–D 6 D 7/CNTR0 D 8/INT0, D9/INT1 P00–P0 3 P10–P1 3 SEG 31/P20–SEG 28/P23 SEG 27/P30–SEG 24/P33 SEG 0/VLC3 –SEG 2/VLC1 SEG 3–SEG 23 COM 0–COM 3 C/CNTR1 Notes 1: Output latch is set to “1.” 2: Output structure is N-channel open-drain. 3: Pull-up transistor is turned OFF. Function D 0–D 6 D 7 D 8, D9 P00–P0 3 P10–P1 3 SEG 31–SEG 28 SEG 27–SEG 24 SEG 0–SEG 2 SEG 3–SEG 23 COM 0–COM 3 C State High-impedance (Notes 1, 2) High-impedance (Notes 1, 2) High-impedance (Note 1) High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2, 3) V LC3 (VDD ) level VLC3 (VDD ) level VLC3 (VDD ) level VLC3 (VDD ) level VLC3 (VDD ) level “L” (VSS ) level (1) Power-on reset Reset can be automatically performed at power on (power-on re- set) by the built-in power-on reset circuit. When the built-in power-on reset circuit is used, the time for the supply voltage to rise from 0 V must be set to 100 µs or less. If the rising time ex- ceeds 100 µs, connect a capacitor between the RESET pin and V SS at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating volt- age. Table 13 Port state at reset R E S E T p i n W E F Watchdog reset signal N o t e P u l l u p t r a n s i s t o r N o t e P o w e r o n r e s e t c i r c u i t V o l t a g e d r o p d e t e c t i o n c i r c u i t VD D N o t e µs o r l e s s N o t e I n t e r n a l r e s e t s i g n a l P o w e r o n Reset released I n t e r n a l r e s e t s i g n a l Reset state N o t e s This symbol represents a parasitic diode. A p p l i e d p o t e n t i a l t o R E S E T p i n m u s t b e VD D o r l e s s K e e p t h e v a l u e o f s u p p l y v o l t a g e t o t h e m i n i m u m v a l u e o r m o r e o f t h e r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s Power-on reset circuit output

Rev.3.00 Aug 06, 2004 page 53 of 136 REJ03B0043-0300Z Address 0 in page 0 is set to program counter. Fig. 40 Internal state at reset (2) Internal state at reset Figure 40 shows internal state at reset (they are the same after sys- tem is released from reset). The contents of timers, registers, flags and RAM except shown in Figure 40 are undefined, so set the ini- tial value to them. “✕ ” represents undefined. 00000000000000 0 (Interrupt disabled) 0 0 0 0 (Interrupt disabled) 0 0 0 0 (Interrupt disabled) 0000 0000 0 (Prescaler stopped) 0 0 0 0 (Timer 1 stopped) 0 0 0 0 (Timer 2 stopped) 0 0 0 0 (Timer 3 stopped) 0 0 0 0 (Timer 4 stopped) 0 0 0 0 (Timer 5 stopped) 0 0 0 0 (Timer LC stopped) 1100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ✕✕✕ 0000 0000 111

Rev.3.00 Aug 06, 2004 page 54 of 136 REJ03B0043-0300Z VOLTAGE DROP DETECTION CIRCUIT The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value. Fig. 41 Voltage drop detection reset circuit Fig. 42 Voltage drop detection circuit operation waveform Table 14 Voltage drop detection circuit operation state VDCE pin “L” “H ” At CPU operating Invalid Valid At power down (SVDE instruction is not executed) Invalid Invalid At power down (SVDE instruction is executed) Invalid Valid E P O F i n s t r u c t i o n P O F i n s t r u c t i o n E P O F i n s t r u c t i o n P O F i n s t r u c t i o n Q S R S V D E i n s t r u c t i o n I n t e r n a l r e s e t s i g n a l V o l t a g e d r o p d e t e c t i o n c i r c u i t R e s e t s i g n a l VRST V o l t a g e d r o p d e t e c t i o n c i r c u i t V D C E I n t e r n a l r e s e t s i g n a l T F f l a g K e y o n w a k e u p s i g n a l Q S R VDD Voltage drop detection circuit Reset signal Microcomupter starts operation after on-chip oscillator (internal oscillator) clock is counted 5400 to 5424 times. VR S T d e t e c t i o n v o l t a g e R E S E T p i n N o t e D e t e c t i o n v o l t a g e o f v o l t a g e d r o p d e t e c t i o n c i r c u i t d o e s n o t h a v e h y s t e r e s i s (2) Note on voltage drop detection circuit The voltage drop detection circuit detection voltage of this prod- uct is set up lower than the minimum value of the supply voltage of the recommended operating conditions. When the supply voltage of a microcomputer falls below to the minimum value of recommended operating conditions and re- goes up (ex. battery exchange of an application product), depending on the capacity value of the bypass capacitor added to the power supply pin, the following case may cause program failure (Figure 43); supply voltage does not fall below to VRST, and its voltage re-goes up with no reset. In such a case, please design a system which supply voltage is once reduced below to VRST and re-goes up after that. Fig. 43 VDD and VRST VDD Recommended operatng condition min.value No reset Program failure may occur. V RST VDD Recommended operatng condition min.value V RST → Normal operation Reset

Rev.3.00 Aug 06, 2004 page 55 of 136 REJ03B0043-0300Z Table 15 Functions and states retained at power down Function Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2) Contents of RAM Interrupt control registers V1, V2 Interrupt control registers I1, I2 Selected oscillation circuit Clock control register MR Timer 1 to timer 4 functions Timer 5 function Timer LC function Watchdog timer function Timer control registers PA, W4 Timer control registers W1 to W3, W5, W6 LCD display function LCD control registers L1 to L3 Voltage drop detection circuit Port level Pull-up control registers PU0, PU1 Key-on wakeup control registers K0 to K2 Port output format control registers FR0 to FR2 External interrupt request flags (EXF0, EXF1) Timer interrupt request flags (T1F to T4F) Timer interrupt request flag (T5F) Interrupt enable flag (INTE) Watchdog timer flags (WDF1, WDF2) Watchdog timer enable flag (WEF) O O O O (Note 3) O (Note 3) ✕ (Note 4) O (Note 5) O (Note 6) (Note 7) O O O (Note 3) O ✕ (Note 4) ✕ (Note 4) Notes 1:“O” represents that the function can be retained, and “✕ ” repre- sents that the function is initialized. Registers and flags other than the above are undefined at RAM back-up, and set an initial value after returning. 2: The stack pointer (SP) points the level of the stack register and is initialized to “7” at RAM back-up. 3: The state of the timer is undefined. 4: Initialize the watchdog timer with the WRST instruction, and then go into the power down state. 5: LCD is turned off. 6: When the SVDE instruction is executed while the VDCE pin is in the “H“ state, this function is valid at power down. 7: In the power down mode, C/CNTR1 pin outputs “L” level. However, when the CNTR input is selected (W1 1, W10=“11”), C/ CNTR1 pin is in an input enabled state (output=high-impedance). Other ports retain their respective output levels. Power down mode O O O O (Note 3) O O ✕ (Note 4) O O O (Note 6) (Note 7) O O O (Note 3) O ✕ (Note 4) ✕ (Note 4) POWER DOWN FUNCTION The 4554 Group has 2-type power down functions. System enters into each power down state by executing the follow- ing instructions. When the EPOF instruction is not executed before the POF or POF2 instruction is executed, these instructions are equivalent to the NOP instruction. (1) Clock operating mode The following functions and states are retained.

• RAM
• Reset circuit
• X CIN–XCOUT oscillation
• LCD display
• Timer 5 (2) RAM back-up mode The following functions and states are retained.
• RAM
• Reset circuit (3) Warm start condition The system returns from the power down state when;
• External wakeup signal is input
• Timer 5 underflow occurs in the power down mode. In either case, the CPU starts executing the software from address 0 in page 0. In this case, the P flag is “1.” (4) Cold start condition The CPU starts executing the software from address 0 in page 0 when;
• reset pulse is input to RESET pin,
• reset by watchdog timer is performed, or
• reset by the voltage drop detection circuit is performed. In this case, the P flag is “0.” (5) Identification of the start condition Warm start or cold start can be identified by examining the state of the power down flag (P) with the SNZP instruction. The warm start condition from the clock operating mode can be identified by exam- ining the state of T5F flag. Clock operating RAM back-up

Rev.3.00 Aug 06, 2004 page 56 of 136 REJ03B0043-0300Z (6) Return signal An external wakeup signal or timer 5 interrupt request flag (T5F) is used to return from the clock operating mode. An external wakeup signal is used to return from the RAM back-up mode because the oscillation is stopped. Table 16 shows the return condition for each return source. (7) Control registers

• Key-on wakeup control register K0 Register K0 controls the port P0 key-on wakeup function. Set the contents of this register through register A with the TK0A instruc- tion. In addition, the TAK0 instruction can be used to transfer the contents of register K0 to register A.
• Key-on wakeup control register K1 Register K1 controls the port P1 key-on wakeup function. Set the contents of this register through register A with the TK1A instruc- tion. In addition, the TAK1 instruction can be used to transfer the contents of register K0 to register A.
• Key-on wakeup control register K2 Register K2 controls the INT0 and INT1 pin key-on wakeup func- tion. Set the contents of this register through register A with the TK2A instruction. In addition, the TAK2 instruction can be used to transfer the contents of register K2 to register A. Table 16 Return source and return condition RemarksReturn condition External wakeup signal Return source Ports P00–P03 Ports P10–P13 INT0 pin INT1 pin
• Pull-up control register PU0 Register PU0 controls the ON/OFF of the port P0 pull-up transis- tor. Set the contents of this register through register A with the TPU0A instruction. In addition, the TAPU0 instruction can be used to transfer the contents of register PU0 to register A.
• Pull-up control register PU1 Register PU1 controls the ON/OFF of the port P1 pull-up transis- tor. Set the contents of this register through register A with the TPU1A instruction. In addition, the TAPU1 instruction can be used to transfer the contents of register PU1 to register A.
• External interrupt control register I1 Register I1 controls the valid waveform of the external 0 inter- rupt, the input control of INT0 pin and the return input level. Set the contents of this register through register A with the TI1A in- struction. In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A.
• External interrupt control register I2 Register I2 controls the valid waveform of the external 1 inter- rupt, the input control of INT1 pin and the return input level. Set the contents of this register through register A with the TI2A in- struction. In addition, the TAI2 instruction can be used to transfer the contents of register I2 to register A. Return by an external “L” level in- put. Return by an external “H ” level or “L” level input, or rising edge (“L ”→ “H ”) or falling edge When the return level is input, the interrupt request flag (EXF0, EXF1) is not set. Return by timer 5 underflow or by setting T5F to “1”. It can be used in the clock operat- ing mode. The key-on wakeup function can be selected by one port unit. Set the port using the key-on wakeup function to “H ” level before going into the power down state. Select the return level (“L” level or “H ” level) with register I1 (I2) and return condition (return by level or edge) with register K2 according to the external state before going into the power down state. Clear T5F with the SNZT5 instruction before system enters into the power down state. When system enters into the power down state while T5F is “1”, system re- turns from the state immediately because it is recognized as return condition. Timer 5 interrupt request flag (T5F)

Rev.3.00 Aug 06, 2004 page 57 of 136 REJ03B0043-0300Z Fig. 44 State transition Fig. 45 Set source and clear source of the P flag Fig. 46 Start condition identified example using the SNZP instruction R e s e t B Operation state O p e r a t i o n s o u r c e c l o c k f XI N ) O s c i l l a t i o n c i r c u i t C e r a m i c r e s o n a t o r O n c h i p o s c i l l a t o r S t o p R C o s c i l l a t i o n c i r c u i t S t o p A C E C l o c k o p e r a t i n g m o d e Main clock: stop Sub-clock: operating K e y o n w a k e u p S t a b i l i z i n g t i m e c P O F i n s t r u c t i o n e x e c u t i o n F R A M b a c k u p m o d e POF2 instruction execution High-speed mode D

• Operation clock: f(XCIN)
• Oscillation circuit: Quartz-crystal oscillation MR 0← 0 (Note 4) M R 0← 1 N o t e L o w s p e e d m o d e K e y o n w a k e u p S t a b i l i z i n g t i m e b POF2 instruction execution K e y o n w a k e u p (Stabilizing time d ) P O F i n s t r u c t i o n e x e c u t i o n K e y o n w a k e u p (Stabilizing time e ) P O F i n s t r u c t i o n e x e c u t i o n K e y o n w a k e u p (Stabilizing time e ) P O F i n s t r u c t i o n e x e c u t i o n K e y o n w a k e u p (Stabilizing time d ) P O F i n s t r u c t i o n e x e c u t i o n K e y o n w a k e u p S t a b i l i z i n g t i m e b S t a b i l i z i n g t i m e a P O F i n s t r u c t i o n e x e c u t i o n K e y o n w a k e u p S t a b i l i z i n g t i m e c Main clock: stop Sub-clock: stop C M C K i n s t r u c t i o n e x e c u t i o n N o t e Operation state
• Operation source clock: f(RING)
• Oscillation circuit: On-chip oscillator
• Ceramic resonator: Operating (Note 2)
• RC oscillation circuit: Stop C R C K i n s t r u c t i o n e x e c u t i o n N o t e O p e r a t i o n s t a t e O p e r a t i o n s o u r c e c l o c k f XI N ) O s c i l l a t i o n c i r c u i t R C o s c i l l a t i o n O n c h i p o s c i l l a t o r S t o p C e r a m i c r e s o n t o r S t o p Operation state Stabilizing time a : Microcomputer starts its operation after counting the on-chip oscillator clock 5400 to 5424 times. Stabilizing time b : In high-speed through-mode, microcomputer starts its operation after counting the f(RING) 675 times. In high-speed/2 mode, microcomputer starts its operation after counting the f(RING) 1350 times. In high-speed/4 mode, microcomputer starts its operation after counting the f(RING) 2700 times. In high-speed/8 mode, microcomputer starts its operation after counting the f(RING) 5400 times. Stabilizing time c : In high-speed through-mode, microcomputer starts its operation after counting the f(X IN) 675 times. In high-speed/2 mode, microcomputer starts its operation after counting the f(XIN) 1350 times. In high-speed/4 mode, microcomputer starts its operation after counting the f(XIN) 2700 times. In high-speed/8 mode, microcomputer starts its operation after counting the f(XIN) 5400 times. Stabilizing time d : In high-speed through-mode, microcomputer starts its operation after counting the f(XIN) 21 times. In high-speed/2 mode, microcomputer starts its operation after counting the f(XIN) 42 times. In high-speed/4 mode, microcomputer starts its operation after counting the f(XIN) 84 times. In high-speed/8 mode, microcomputer starts its operation after counting the f(XIN) 168 times. Stabilizing time e : In low-speed through-mode, microcomputer starts its operation after counting the f(XCIN) 675 times. In low-speed/2 mode, microcomputer starts its operation after counting the f(XCIN) 1350 times. In low-speed/4 mode, microcomputer starts its operation after counting the f(XCIN) 2700 times. In low-speed/8 mode, microcomputer starts its operation after counting the f(XCIN) 5400 times. Notes 1: Continuous execution of the EPOF instruction and the POF instruction is required to go into the clock operating state. Continuous execution of the EPOF instruction and the POF2 instruction is required to go into the RAM back-up state. 2: Through the ceramic resonator is operating, the on-chip oscillator clock is selected as the operation source clock. 3: The oscillator clock corresponding to each instruction is selected as the operation source clock, and the on-chip oscillator is stopped. 4: The main clock (f(XIN) or f(RING)) or sub-clock (f(XCIN)) is selected for operation source clock by the bit 0 of clock control register MR. 5: The sub-clock (quartz-crystal oscillation) is operating except in state F. S R Q P o w e r d o w n f l a g PP O F o r P O F i n s t r u c t i o n Reset inpu t G S e t s o u r c e G C l e a r s o u r c e R e s e t i n p u t E P O F i n s t r u c t i o n + POF or POF2 instruction EPOF instruction + P r o g r a m s t a r t P = “1” Yes Warm start C o l d s t a r t No T F Yes No R e t u r n f r o m t i m e r u n d e r f l o w Return from external wakeup signal

Rev.3.00 Aug 06, 2004 page 58 of 136 REJ03B0043-0300Z Table 17 Key-on wakeup control register, pull-up control register and interrupt control register K03 K02 K01 K00 Key-on wakeup control register K0 Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Port P0 3 key-on wakeup control bit Port P0 2 key-on wakeup control bit Port P0 1 key-on wakeup control bit Port P00 key-on wakeup control bit at reset : 00002 at power down : state retained Note: “R ” represents read enabled, and “W ” represents write enabled. K13 K12 K11 K10 Key-on wakeup control register K1 Key-on wakeup used Key-on wakeup not used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Port P1 3 key-on wakeup control bit Port P12 key-on wakeup control bit Port P1 1 key-on wakeup control bit Port P1 0 key-on wakeup control bit at reset : 00002 at power down : state retained K23 K22 K21 K20 Key-on wakeup control register K2 Return by level Return by edge Key-on wakeup not used Key-on wakeup used Return by level Return by edge Key-on wakeup not used Key-on wakeup used INT1 pin return condition selection bit INT1 pin key-on wakeup control bit INT0 pin return condition selection bit INT0 pin key-on wakeup control bit at reset : 00002 at power down : state retained R/W TAK0/ TK0A R/W TAK1/ TK1A R/W TAK2/ TK2A

Rev.3.00 Aug 06, 2004 page 59 of 136 REJ03B0043-0300Z Port P02 pull-up transistor control bit Port P0 1 pull-up transistor control bit Port P0 0 pull-up transistor control bit Pull-up control register PU0 at reset : 00002 at power down : state retained PU1 3 PU1 2 PU1 1 PU1 0 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Port P1 3 pull-up transistor control bit Port P1 2 pull-up transistor control bit Port P11 pull-up transistor control bit Port P1 0 pull-up transistor control bit Pull-up control register PU1 at reset : 00002 at power down : state retained I13 I12 I11 I10 INT0 pin input control bit (Note 2) Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2) INT0 pin edge detection circuit control bit INT0 pin Timer 1 count start synchronous circuit selection bit Interrupt control register I1 R/W TAI1/TI1Aat power down : state retainedat reset : 00002 INT0 pin input disabled INT0 pin input enabled Falling waveform/“L” level (“L” level is recognized with the SNZI0 instruction) Rising waveform/“H ” level (“H ” level is recognized with the SNZI0 instruction) One-sided edge detected Both edges detected Timer 1 count start synchronous circuit not selected Timer 1 count start synchronous circuit selected I23 I22 I21 I20 INT1 pin input control bit (Note 2) Interrupt valid waveform for INT1 pin/ return level selection bit (Note 2) INT1 pin edge detection circuit control bit INT1 pin Timer 3 count start synchronous circuit selection bit Interrupt control register I2 R/W TAI2/TI2Aat power down : state retainedat reset : 00002 INT1 pin input disabled INT1 pin input enabled Falling waveform/“L” level (“L” level is recognized with the SNZI1 instruction) Rising waveform/“H ” level (“H ” level is recognized with the SNZI1 instruction) One-sided edge detected Both edges detected Timer 3 count start synchronous circuit not selected Timer 3 count start synchronous circuit selected Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: When the contents of I12, I13 I22 and I23 are changed, the external interrupt request flag (EXF0, EXF1) may be set. R/W TAPU0/ TPU0A R/W TAPU1/ TPU1A

Rev.3.00 Aug 06, 2004 page 60 of 136 REJ03B0043-0300Z The clock control circuit consists of the following circuits.

• On-chip oscillator (internal oscillator)
• Ceramic resonator
• RC oscillation circuit
• Quartz-crystal oscillation circuit
• Multi-plexer (clock selection circuit)
• Frequency divider
• Internal clock generating circuit Fig. 47 Clock control circuit structure The system clock and the instruction clock are generated as the source clock for operation by these circuits. Figure 47 shows the structure of the clock control circuit. The 4554 Group operates by the on-chip oscillator clock (f(RING)) which is the internal oscillator after system is released from reset. Also, the ceramic resonator or the RC oscillation can be used for the main clock (f(X IN)) of the 4554 Group. The CMCK instruction or CRCK instruction is executed to select the ceramic resonator or RC oscillator, respectively. The quartz-crystal oscillator can be used for sub-clock (f(X CIN)). MR 3, MR 2 Q S QR Q S R CRCK instruction QS R CMCK instruction QS R Internal reset signal XOUT XI N W a i t t i m e c o n t r o l c i r c u i t N o t e P r o g r a m s t a r t s i g n a l Key-on wakeup signal Notes 1: System operates by the on-chip oscillator clock (f(RING)) until the CMCK or CRCK instruction is executed after system is released from reset. 2: The wait time control circuit is used to generate the time required to stabilize the f(XIN) or f(XCIN) oscillation. After the certain oscillation stabilizing wait time elapses, the program start signal is output. This circuit operates when system is released from reset or returned from RAM back-up. EPOF instruction POF2 instruction+ XC O U T XC I N QS R EPOF instruction POF instruction+ T F f l a g M R 1 M R 0 D i v i s i o n c i r c u i t D i v i d e d b y D i v i d e d b y D i v i d e d b y System clock (STCK) Instruction clock (INSTCK) M u l t i p l e x e r Q u a r t z c r y s t a l o s c i l l a t i o n O n c h i p o s c i l l a t o r i n t e r n a l o s c i l l a t o r N o t e C e r a m i c r e s o n a n c e RC oscillation Internal clock generating circuit (divided by 3)

Rev.3.00 Aug 06, 2004 page 61 of 136 REJ03B0043-0300Z Fig. 48 Switch to ceramic resonance/RC oscillation Fig. 49 Handling of XIN and XOUT when operating on-chip oscillator Fig. 50 Ceramic resonator external circuit Fig. 51 External RC oscillation circuit Execute the CMCK instruc- tion in program. Note: Externally connect a damping resistor Rd depending on the oscillation frequency. (A feedback resistor is built-in.) Use the resonator manu- facturer’s recommended value because constants such as ca- pacitance depend on the resonator. (1) Main clock generating circuit (f(XIN)) The ceramic resonator or RC oscillation can be used for the main clock of this MCU. After system is released from reset, the MCU starts operation by the clock output from the on-chip oscillator which is the internal os- cillator. When the ceramic resonator is used, execute the CMCK instruc- tion. When the RC oscillation is used, execute the CRCK instruction. The oscillation circuit by the CMCK or CRCK instruction can be selected only at once. The oscillation circuit corresponding to the first executed one of these two instructions is valid. Other os- cillation circuit and the on-chip oscillator stop. Execute the CMCK or the CRCK instruction in the initial setting rou- tine of program (executing it in address 0 in page 0 is recommended). Also, when the CMCK or the CRCK instruction is not executed in program, this MCU operates by the on-chip oscilla- tor. (2) On-chip oscillator operation When the MCU operates by the on-chip oscillator as the main clock (f(X IN)) without using the ceramic resonator or the RC oscillator, connect XIN pin to VSS and leave XOUT pin open (Figure 49). The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. (3) Ceramic resonator When the ceramic resonator is used as the main clock (f(XIN)), con- nect the ceramic resonator and the external circuit to pins XIN and XOUT at the shortest distance. Then, execute the CMCK instruction. A feedback resistor is built in between pins XIN and XOUT (Figure 50). (4) RC oscillation When the RC oscillation is used as the main clock (f(XIN)), connect the XIN pin to the external circuit of resistor R and the capacitor C at the shortest distance and leave XOUT pin open. Then, execute the CRCK instruction (Figure 51). The frequency is affected by a capacitor, a resistor and a micro- computer. So, set the constants within the range of the frequency limits. R e s e t O n c h i p o s c i l l a t o r o p e r a t i o n C M C K i n s t r u c t i o n C R C K i n s t r u c t i o n

• Ceramic resonator valid
• On-chip oscillator stop
• RC oscillation stop R C o s c i l l a t i o n v a l i d O n c h i p o s c i l l a t o r s t o p C e r a m i c r e s o n a t o r s t o p M34554 XI N XO U T Do not use the CMCK instruction and CRCK instruction in program. M34554 XIN XOUT R d C IN C O U T M XI N XO U TR C x e c u t e t h e C R C K i n s t r u c t i o n i n p r o g r a m

Rev.3.00 Aug 06, 2004 page 62 of 136 REJ03B0043-0300Z (5) External clock When the external clock signal is used as the main clock (f(XIN)), connect the XIN pin to the clock source and leave XOUT pin open. Then, execute the CMCK instruction (Figure 52). Be careful that the maximum value of the oscillation frequency when using the external clock differs from the value when using the ceramic resonator (refer to the recommended operating condition). Also, note that the power down mode (POF and POF2 instructions) cannot be used when using the external clock. (6) Sub-clock generating circuit f(XCIN) Sub-clock signal f(XCIN ) is obtained by externally connecting a quartz-crystal oscillator. Connect this external circuit and a quartz- crystal oscillator to pins X CIN and XCOUT at the shortest distance. A feedback resistor is built in between pins XCIN and XCOUT (Figure 53). (7) Clock control register MR Register MR controls system clock. Set the contents of this register through register A with the TMRA instruction. In addition, the TAMR instruction can be used to transfer the contents of register MR to register A. Table 18 Clock control register MR Fig. 52 External clock input circuit Note : “R ” represents read enabled, and “W ” represents write enabled. Fig. 53 External quartz-crystal circuit MR 3 Clock control register MR Operation mode Through mode (frequency not divided) Frequency divided by 2 mode Frequency divided by 4 mode Frequency divided by 8 mode Main clock oscillation enabled Main clock oscillation stop Main clock (f(X IN) or f(RING)) Sub-clock (f(XCIN)) at reset : 11002 at power down : state retained MR 3 R/W TAMR/ TMRA Main clock oscillation circuit control bit System clock selection bit Operation mode selection bits MR MR 1 MR 0 MR 2 ROM ORDERING METHOD 1.Mask ROM Order Confirmation Form• 2.Mark Specification Form• 3.Data to be written to ROM, in EPROM form (three identical cop- ies) or one floppy disk.

• For the mask ROM confirmation and the mark specifications, refer to the “Renesas Technology Corp.” Homepage (http://www.renesas.com/en/rom). Note: Externally connect a damping resistor Rd depending on the oscillation frequency. (A feedback resistor is built-in.) Use the quartz-crystal manu- facturer’s recommended value because constants such as ca- pacitance depend on the resonator. M XI N XO U T E x t e r n a l o s c i l l a t i o n c i r c u i t VD D VSS E x e c u t e t h e C M C K i n s t r u c t i o n i n p r o g r a m M XC IN XCOUT Rd C IN C O U T

Rev.3.00 Aug 06, 2004 page 63 of 136 REJ03B0043-0300Z ➈ Writing to reload register R1, R3, R4H When writing data to reload register R1, reload register R3 or re- load regiser R4H while timer 1, timer 3 or timer 4 is operating, avoid a timing when timer 1, timer 3 or timer 4 underflows. Timer 4 Avoid a timing when timer 4 underflows to stop timer 4. When “H ” interval extension function of the PWM signal is set to be “valid”, set “1” or more to reload register R4H. Timer 5 Stop timer 5 counting to change its count source. Timer input/output pin Set the port C output latch to “0” to output the PWM signal from C/CNTR pin. Watchdog timer

• The watchdog timer function is valid after system is released from reset. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously, and clear the WEF flag to “0” to stop the watchdog timer function.
• The watchdog timer function is valid after system is returned from the power down state. When not using the watchdog timer func- tion, execute the DWDT instruction and the WRST instruction continuously every system is returned from the power down state, and stop the watchdog timer function.
• When the watchdog timer function and power down function are used at the same time, execute the WRST instruction before sys- tem enters into the power down state and initialize the flag WDF1. Multifunction
• Be careful that the output of ports D 8 and D9 can be used even when INT0 and INT1 pins are selected.
• Be careful that the input/output of port D7 can be used even when input of CNTR0 pin are selected.
• Be careful that the input of port D7 can be used even when out- put of CNTR0 pin are selected.
• Be careful that the “H ” output of port C can be used even when output of CNTR1 pin are selected. Program counter Make sure that the PCH does not specify after the last page of the built-in ROM. LIST OF PRECAUTIONS ➀ Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up;
• connect a bypass capacitor (approx. 0.1 µF) between pins VDD and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use relatively thick wire. In the One Time PROM version, CNVSS pin is also used as VPP pin. Accordingly, when using this pin, connect this pin to VSS through a resistor about 5 kΩ (connect this resistor to CNVSS / VPP pin as close as possible). ➁ Register initial values 1 The initial value of the following registers are undefined after sys- tem is released from reset. After system is released from reset, set initial values.
• Register Z (2 bits)
• Register D (3 bits)
• Register E (8 bits) ➂ Register initial values 2 The initial value of the following registers are undefined at RAM back- up. After system is returned from RAM back-up, set initial values.
• Register Z (2 bits)
• Register X (4 bits)
• Register Y (4 bits)
• Register D (3 bits)
• Register E (8 bits) ➃ Stack registers (SKS) Stack registers (SKs) are eight identical registers, so that subrou- tines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accord- ingly, be careful not to over the stack when performing these operations together. ➄ Prescaler Stop counting and then execute the TABPS instruction to read from prescaler data. Stop counting and then execute the TPSAB instruction to set prescaler data. ➅ Timer count source Stop timer 1, 2, 3, 4 and LC counting to change its count source. ➆ Reading the count value Stop timer 1, 2, 3 or 4 counting and then execute the data read instruction (TAB1, TAB2, TAB3, TAB4) to read its data. ➇ Writing to the timer Stop timer 1, 2, 3, 4 or LC counting and then execute the data write instruction (T1AB, T2AB, T3AB, T4AB, TLCA) to write its data.

Rev.3.00 Aug 06, 2004 page 64 of 136 REJ03B0043-0300Z ❶ Note [1] on bit 3 of register I1 When the input of the INT0 pin is controlled with the bit 3 of reg- ister I1 in software, be careful about the following notes.

• Depending on the input state of the D 8/INT0 pin, the external 0 in- terrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 54➀ ) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to Figure 54➁ ). Also, set the NOP instruction for the case when a skip is per- formed with the SNZ0 instruction (refer to Figure 54➂ ). LA 4 ; ( ✕✕✕ 0 LA 8 ; (1 ✕✕✕ 2) TI1A ; Control of INT0 pin input is changed SNZ0 ; The SNZ0 instruction is executed (EXF0 flag cleared) ✕ : these bits are not used here. Fig. 54 External 0 interrupt program example-1 ❷ Note [2] on bit 3 of register I1 When the bit 3 of register I1 is cleared to “0”, the RAM back-up mode is selected and the input of INT0 pin is disabled, be careful about the following notes.
• When the key-on wakeup function of INT0 pin is not used (regis- ter K2 0 = “0”), clear bits 2 and 3 of register I1 before system enters to the RAM back-up mode. (refer to Figure 55➀ ).
• ••
• •• LA 0 ; (00 ✕✕ 2) DI EPOF POF2 ; RAM back-up ✕ : these bits are not used here. Fig. 55 External 0 interrupt program example-2
• ••
• •• ❸ Note on bit 2 of register I1 When the interrupt valid waveform of the D8/INT0 pin is changed with the bit 2 of register I1 in software, be careful about the fol- lowing notes.
• Depending on the input state of the D 8/INT0 pin, the external 0 in- terrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 56➀ ) and then, change the bit 2 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to Figure 56➁ ). Also, set the NOP instruction for the case when a skip is per- formed with the SNZ0 instruction (refer to Figure 56➂ ). LA 4 ; ( ✕✕✕ 0 LA 12 ; ( ✕ 1✕✕ 2) TI1A ; Interrupt valid waveform is changed SNZ0 ; The SNZ0 instruction is executed (EXF0 flag cleared) ✕ : these bits are not used here. Fig. 56 External 0 interrupt program example-3
• ••
• ••

Rev.3.00 Aug 06, 2004 page 65 of 136 REJ03B0043-0300Z ❶ Note [1] on bit 3 of register I2 When the input of the INT1 pin is controlled with the bit 3 of reg- ister I2 in software, be careful about the following notes.

• Depending on the input state of the D 9/INT1 pin, the external 1 in- terrupt request flag (EXF1) may be set when the bit 3 of register I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 57➀ ) and then, change the bit 3 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to “0” after executing at least one instruction (refer to Figure 57➁ ). Also, set the NOP instruction for the case when a skip is per- formed with the SNZ1 instruction (refer to Figure 57➂ ). LA 4 ; ( ✕✕ 0✕ LA 8 ; (1 ✕✕✕ 2) TI2A ; Control of INT1 pin input is changed SNZ1 ; The SNZ1 instruction is executed (EXF1 flag cleared) ✕ : these bits are not used here. Fig. 57 External 1 interrupt program example-1 ❷ Note [2] on bit 3 of register I2 When the bit 3 of register I2 is cleared to “0”, the RAM back-up mode is selected and the input of INT1 pin is disabled, be careful about the following notes.
• When the key-on wakeup function of INT1 pin is not used (regis- ter K2 2 = “0”), clear bits 2 and 3 of register I2 before system enters to the RAM back-up mode. (refer to Figure 58➀ ).
• ••
• •• LA 0 ; (00 ✕✕ 2) DI EPOF POF2 ; RAM back-up ✕ : these bits are not used here. Fig. 58 External 1 interrupt program example-2
• ••
• •• ❸ Note on bit 2 of register I2 When the interrupt valid waveform of the D9/INT1 pin is changed with the bit 2 of register I2 in software, be careful about the fol- lowing notes.
• Depending on the input state of the D9/INT1 pin, the external 1 in- terrupt request flag (EXF1) may be set when the bit 2 of register I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 59➀ ) and then, change the bit 2 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to “0” after executing at least one instruction (refer to Figure 59➁ ). Also, set the NOP instruction for the case when a skip is per- formed with the SNZ1 instruction (refer to Figure 59➂ ). LA 4 ; ( ✕✕ 0✕ LA 12 ; ( ✕ 1✕✕ 2) TI2A ; Interrupt valid waveform is changed SNZ1 ; The SNZ1 instruction is executed (EXF1 flag cleared) ✕ : these bits are not used here. Fig. 59 External 1 interrupt program example-3
• ••
• ••

Rev.3.00 Aug 06, 2004 page 66 of 136 REJ03B0043-0300Z Execute the CMCK or the CRCK instruction in the initial setting routine of program (executing it in address 0 in page 0 is recom- mended). The oscillation circuit by the CMCK or CRCK instruction can be selected only at once. The oscillation circuit corresponding to the first executed one of these two instruction is valid. Other oscilla- tion circuits and the on-chip oscillator stop. On-chip oscillator The clock frequency of the on-chip oscillator depends on the sup- ply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. Also, the oscillation stabilize wait time after system is released from reset is generated by the on-chip oscillator clock. When considering the oscillation stabilize wait time after system is re- leased from reset, be careful that the variable frequency of the on-chip oscillator clock. External clock When the external signal clock is used as the source oscillation (f(X IN)), note that the power down mode (POF and POF2 instruc- tions) cannot be used. Difference between Mask ROM version and One Time PROM version Mask ROM version and One Time PROM version have some dif- ference of the following characteristics within the limits of an electrical property by difference of a manufacture process, built- in ROM, and a layout pattern.

• a characteristic value
• a margin of operation
• the amount of noise-proof
• noise radiation, etc., Accordingly, be careful of them when swithcing. Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. Fig. 60 VDD and VRST POF and POF2 instructions When the POF or POF2 instruction is executed continuously af- ter the EPOF instruction, system enters the power down state. Note that system cannot enter the power down state when ex- ecuting only the POF or POF2 instruction. Be sure to disable interrupts by executing the DI instruction be- fore executing the EPOF instruction and the POF or POF2 instruction continuously. Power-on reset When the built-in power-on reset circuit is used, the time for the supply voltage to rise from 0 V to 2.0 V must be set to 100 µs or less. If the rising time exceeds 100 µs, connect a capacitor be- tween the RESET pin and V SS at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage. Note on voltage drop detection circuit The voltage drop detection circuit detection voltage of this prod- uct is set up lower than the minimum value of the supply voltage of the recommended operating conditions. When the supply voltage of a microcomputer falls below to the minimum value of recommended operating conditions and re- goes up (ex. battery exchange of an application product), depending on the capacity value of the bypass capacitor added to the power supply pin, the following case may cause program failure (Figure 60); supply voltage does not fall below to VRST, and its voltage re-goes up with no reset. In such a case, please design a system which supply voltage is once reduced below to VRST and re-goes up after that. VDD Recommended operatng condition min.value No reset Program failure may occur. V RST VDD Recommended operatng condition min.value V RST → Normal operation Reset

Rev.3.00 Aug 06, 2004 page 67 of 136 REJ03B0043-0300Z INT0 pin input control bit (Note 2) Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2) INT0 pin edge detection circuit control bit INT0 pin Timer 1 count start synchronous circuit selection bit Interrupt control register I1 R/W TAI1/TI1Aat power down : state retainedat reset : 00002 INT0 pin input disabled INT0 pin input enabled Falling waveform/“L” level (“L” level is recognized with the SNZI0 instruction) Rising waveform/“H ” level (“H ” level is recognized with the SNZI0 instruction) One-sided edge detected Both edges detected Timer 1 count start synchronous circuit not selected Timer 1 count start synchronous circuit selected Interrupt disabled (SNZT4 instruction is valid) Interrupt enabled (SNZT4 instruction is invalid) This bit has no function, but read/write is enabled. Interrupt disabled (SNZT5 instruction is valid) Interrupt enabled (SNZT5 instruction is invalid) Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) V13 V12 V11 V10 V23 V22 V21 V20 Timer 4 interrupt enable bit Not used Timer 5 interrupt enable bit Timer 3 interrupt enable bit Interrupt control register V2 at power down : 00002at reset : 00002 Interrupt control register V1 Timer 2 interrupt enable bit Timer 1 interrupt enable bit External 1 interrupt enable bit External 0 interrupt enable bit Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) at power down : 0000 2at reset : 00002 R/W TAV1/TV1A I23 I22 I21 I20 INT1 pin input control bit (Note 2) Interrupt valid waveform for INT1 pin/ return level selection bit (Note 2) INT1 pin edge detection circuit control bit INT1 pin Timer 3 count start synchronous circuit selection bit Interrupt control register I2 R/W TAI2/TI2Aat power down : state retainedat reset : 00002 INT1 pin input disabled INT1 pin input enabled Falling waveform/“L” level (“L” level is recognized with the SNZI1 instruction) Rising waveform/“H ” level (“H ” level is recognized with the SNZI1 instruction) One-sided edge detected Both edges detected Timer 3 count start synchronous circuit not selected Timer 3 count start synchronous circuit selected Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: When the contents of I12, I13 I22 and I23 are changed, the external interrupt request flag (EXF0, EXF1) may be set. R/W TAV2/TV2A

Rev.3.00 Aug 06, 2004 page 68 of 136 REJ03B0043-0300Z Timer 1 underflow signal divided by 2 output Timer 2 underflow signal divided by 2 output Stop (state retained) Operating Count source System clock (STCK) Prescaler output (ORCLK) Timer 1 underflow signal (T1UDF) PWM signal (PWMOUT) CNTR0 output control bit Timer 2 control bit Timer 2 count source selection bits Timer control register W2 at power down : state retainedat reset : 00002 Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”). 3: This function is valid only when the timer 3 count start synchronous circuit is selected (I20=“1”). 4: Port C output is invalid when CNTR1 input is selected for the timer 3 count source. W2 3 W2 2 W2 1 W2 0 MR 3 Clock control register MR Operation mode Through mode Frequency divided by 2 mode Frequency divided by 4 mode Frequency divided by 8 mode Main clock oscillation enabled Main clock oscillation stop Main clock (f(X IN) or f(RING)) Sub-clock (f(XCIN)) at reset : 11002 at power down : state retained MR 3 R/W TAMR/ TMRA Main clock oscillation circuit control bit System clock selection bit Operation mode selection bits MR MR 1 MR 0 MR 2 Stop (state initialized) Operating Prescaler control bit Timer control register PA W TPAAat power down : 02at reset : 02 PA 0 W1 1 Timer 1 count auto-stop circuit not selected Timer 1 count auto-stop circuit selected Stop (state retained) Operating Count source Instruction clock (INSTCK) Prescaler output (ORCLK) Timer 5 underflow signal (T5UDF) CNTR0 input Timer 1 count auto-stop circuit selection bit (Note 2) Timer 1 control bit Timer 1 count source selection bits Timer control register W1 R/W TAW1/TW1Aat power down : state retainedat reset : 00002 W1 3 W1 2 W1 1 W1 0 W3 1 Timer 3 count auto-stop circuit not selected Timer 3 count auto-stop circuit selected Stop (state retained) Operating Count source PWM signal (PWMOUT) Prescaler output (ORCLK) Timer 2 underflow signal (T2UDF) CNTR1 input Timer 3 count auto-stop circuit selection bit (Note 3) Timer 3 control bit Timer 3 count source selection bits (Note 4) Timer control register W3 at power down : state retainedat reset : 00002 W3 3 W3 2 W3 1 W3 0 R/W TAW2/TW2A R/W TAW3/TW3A

Rev.3.00 Aug 06, 2004 page 69 of 136 REJ03B0043-0300Z Stop (state retained) Operating Bit 4 (T5 4) of timer 5 Prescaler output (ORCLK) CNTR1 output auto-control circuit not selected CNTR1 output auto-control circuit selected D 7(I/O)/CNTR0 input CNTR input/output/D7 (input) Timer LC control bit Timer LC count source selection bit CNTR1 output auto-control circuit selection bit D 7/CNTR0 pin function selection bit (Note 2) Timer control register W6 at power down : state retainedat reset : 00002 W6 3 W6 2 W6 1 W6 0 CNTR1 output invalid CNTR1 output valid PWM signal “H ” interval expansion function invalid PWM signal “H ” interval expansion function valid Stop (state retained) Operating X IN input Prescaler output (ORCLK) divided by 2 CNTR1 output control bit PWM signal “H ” interval expansion function control bit Timer 4 control bit Timer 4 count source selection bit W4 3 W4 2 W4 1 W4 0 W5 1 Not used Timer 5 control bit Timer 5 count value selection bits Timer control register W5 at power down : state retainedat reset : 00002 W5 3 W5 2 W5 1 W5 0 Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: CNTR0 input is valid only when CNTR0 input is selected for the timer 1 count source. This bit has no function, but read/write is enabled. Stop (state initialized) Operating Count value Underflow occurs every 8192 counts Underflow occurs every 16384 counts Underflow occurs every 32768 counts Underflow occurs every 65536 counts R/W TAW4/TW4A Timer control register W4 at power down : 00002at reset : 00002 R/W TAW5/TW5A R/W TAW6/TW6A

Rev.3.00 Aug 06, 2004 page 70 of 136 REJ03B0043-0300Z Internal dividing resistor for LCD power supply selection bit (Note 2) LCD control bit LCD duty and bias selection bits LCD control register L1 L13 L12 L11 L10 at reset : 00002 at power down : state retained Duty Bias LCD control register L2 at reset : 0000 2 at power down : state retained W TL2A SEG VLC3 SEG 1 VLC2 SEG 2 VLC1 Internal dividing resistor valid Internal dividing resistor invalid L23 L22 L21 L20 VLC3 /SEG 0 pin function switch bit (Note 3) VLC2 /SEG 1 pin function switch bit (Note 4) VLC1 /SEG 2 pin function switch bit (Note 4) Internal dividing resistor for LCD power supply control bit 2r ✕ 3, 2r ✕ 2 r ✕ 3, r ✕ 2 Off On Not available LCD control register L3 at reset : 0000 2 at power down : state retained W TL3A SEG 24–SEG 27 P33–P30 SEG 28, SEG29 P23, P22 SEG 30 P21 SEG 31 P20 L33 L32 L31 L30 SEG 24/P33–SEG 27/P30 pin function switch bit SEG 28/P23, SEG29/P22 pin function switch bit SEG 30/P21 pin function switch bit SEG 31/P20 pin function switch bit Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: “r (resistor) multiplied by 3” is used at 1/3 bias, and “r multiplied by 2” is used at 1/2 bias. 3: VLC3 is connected to VDD internally when SEG0 pin is selected. 4: Use internal dividing resistor when SEG1 and SEG2 pins are selected. R/W TAL1/TL1A

Rev.3.00 Aug 06, 2004 page 71 of 136 REJ03B0043-0300Z Port P02 pull-up transistor control bit Port P0 1 pull-up transistor control bit Port P0 0 pull-up transistor control bit Pull-up control register PU0 at reset : 00002 at power down : state retained R/W TAPU0/ TPU0A PU1 3 PU1 2 PU1 1 PU1 0 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Port P1 3 pull-up transistor control bit Port P1 2 pull-up transistor control bit Port P11 pull-up transistor control bit Port P1 0 pull-up transistor control bit Pull-up control register PU1 at reset : 00002 at power down : state retained FR0 3 FR0 2 FR0 1 FR0 0 N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output Ports P1 2, P13 output structure selection bit Ports P1 0, P11 output structure selection bit Ports P0 2, P03 output structure selection bit Ports P00, P01 output structure selection bit Port output structure control register FR0 at reset : 00002 at power down : state retained FR1 3 FR1 2 FR1 1 FR1 0 N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output Port D 3 output structure selection bit Port D2 output structure selection bit Port D1 output structure selection bit Port D0 output structure selection bit Port output structure control register FR1 at reset : 00002 at power down : state retained FR2 3 FR2 2 FR2 1 FR2 0 N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output Port D 7/CNTR0 output structure selection bit Port D6 output structure selection bit Port D5 output structure selection bit Port D4 output structure selection bit Port output structure control register FR2 at reset : 00002 at power down : state retained Note: “R ” represents read enabled, and “W ” represents write enabled. R/W TAPU1/ TPU1A W TFR0A W TFR1A W TFR2A

Rev.3.00 Aug 06, 2004 page 72 of 136 REJ03B0043-0300Z Key-on wakeup control register K0 Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Port P0 3 key-on wakeup control bit Port P0 2 key-on wakeup control bit Port P01 key-on wakeup control bit Port P0 0 key-on wakeup control bit at reset : 00002 at power down : state retained R/W TAK0/ TK0A Note: “R ” represents read enabled, and “W ” represents write enabled. K13 K12 K11 K10 Key-on wakeup control register K1 Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Port P1 3 key-on wakeup control bit Port P12 key-on wakeup control bit Port P11 key-on wakeup control bit Port P10 key-on wakeup control bit at reset : 00002 at power down : state retained K23 K22 K21 K20 Key-on wakeup control register K2 Returned by level Returned by edge Key-on wakeup invalid Key-on wakeup valid Returned by level Returned by edge Key-on wakeup invalid Key-on wakeup valid INT1 pin return condition selection bit INT1 pin key-on wakeup control bit INT0 pin return condition selection bit INT0 pin key-on wakeup control bit at reset : 00002 at power down : state retained R/W TAK1/ TK1A R/W TAK2/ TK2A

Rev.3.00 Aug 06, 2004 page 73 of 136 REJ03B0043-0300Z A B DR E MR PA PU0 PU1 FR0 FR1 FR2 FR3 X Y Z DP PC PC H PC L SK SP CY RPS R4L R4H RLC

Contents

Register A (4 bits) Register B (4 bits) Register DR (3 bits) Register E (8 bits) Interrupt control register V1 (4 bits) Interrupt control register V2 (4 bits) Interrupt control register I1 (4 bits) Interrupt control register I2 (4 bits) Clock control register MR (4 bits) Timer control register PA (1 bit) Timer control register W1 (4 bits) Timer control register W2 (4 bits) Timer control register W3 (4 bits) Timer control register W4 (4 bits) Timer control register W5 (4 bits) Timer control register W6 (4 bits) LCD control register L1 (4 bits) LCD control register L2 (4 bits) LCD control register L3 (4 bits) Pull-up control register PU0 (4 bits) Pull-up control register PU1 (4 bits) Port output format control register FR0 (4 bits) Port output format control register FR1 (4 bits) Port output format control register FR2 (4 bits) Port output format control register FR3 (4 bits) Key-on wakeup control register K0 (4 bits) Key-on wakeup control register K1 (4 bits) Key-on wakeup control register K2 (4 bits) Register X (4 bits) Register Y (4 bits) Register Z (2 bits) Data pointer (10 bits) (It consists of registers X, Y, and Z) Program counter (14 bits) High-order 7 bits of program counter Low-order 7 bits of program counter Stack register (14 bits ✕ 8) Stack pointer (3 bits) Carry flag Prescaler reload register (8 bits) Timer 1 reload register (8 bits) Timer 2 reload register (8 bits) Timer 3 reload register (8 bits) Timer 4 reload register (8 bits) Timer 4 reload register (8 bits) Timer LC reload register (4 bits) Timer 1 interrupt request flag Timer 2 interrupt request flag Timer 3 interrupt request flag Timer 4 interrupt request flag Timer 5 interrupt request flag Watchdog timer flag Watchdog timer enable flag Interrupt enable flag External 0 interrupt request flag External 1 interrupt request flag Power down flag Port D (10 bits) Port P0 (4 bits) Port P1 (4 bits) Port P2 (4 bits) Port P3 (4 bits) Port C (1 bit) Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal constant Hexadecimal constant Hexadecimal constant Binary notation of hexadecimal variable A (same for others) Direction of data movement Data exchange between a register and memory Decision of state shown before “?” Contents of registers and memories Negate, Flag unchanged after executing instruction RAM address pointed by the data pointer Label indicating address a 6 a5 a4 a3 a2 a1 a0 Label indicating address a6 a5 a4 a3 a2 a1 a0 in page p5 p4 p3 p2 p1 p0 Hex. C + Hex. number x Symbol PS TLC T1F T2F T3F T4F T5F WDF1 WEF INTE EXF0 EXF1 P D C x y z p n i j A 3A2A1A0 ( ) M(DP) a p, a C + x INSTRUCTIONS The 4554 Group has the 136 instructions. Each instruction is de- scribed as follows; (1) Index list of instruction function (2) Machine instructions (index by alphabet) (3) Machine instructions (index by function) (4) Instruction code table Note : Some instructions of the 4554 Group has the skip function to unexecute the next described instruction. The 4554 Group just invalidates the next instruc- tion when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped. SYMBOL The symbols shown below are used in the following list of instruc- tion function and the machine instructions.

Rev.3.00 Aug 06, 2004 page 74 of 136 REJ03B0043-0300Z INDEX LIST OF INSTRUCTION FUNCTION Group- ing RAM addresses Mnemonic XAMI j TMA j LA n TABP p AM AMC A n AND OR SC RC SZC CMA RAR Function (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← n n = 0 to 15 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PC H ) ← p (PCL) ← (DR2–DR 0, A3–A0) (B) ← (ROM(PC))7–4 (A) ← (ROM(PC))3–0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (A) ← (A) + (M(DP)) (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry (A) ← (A) + n n = 0 to 15 (A) ← (A) AND (M(DP)) (A) ← (A) OR (M(DP)) (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → CY → A3A2A1A0 Mnemonic TAB TBA TAY TYA TEAB TABE TDA TAD TAZ TAX TASP LXY x, y LZ z INY DEY TAM j XAM j XAMD j Function (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) 7–E4) ← (B) (E3–E0) ← (A) (B) ← (E7–E4) (A) ← (E3–E0) (DR 2–DR 0) ← (A2–A0) (A2–A0) ← (DR2–DR 0) (A3) ← 0 (A3, A2) ← 0 (A) ← (X) (A2–A0) ← (SP2–SP 0) (A3) ← 0 (X) ← x x = 0 to 15 (Y) ← y y = 0 to 15 (Z) ← z z = 0 to 3 (Y) ← (Y) + 1 (Y) ← (Y) – 1 (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) – 1 RAM to register transfer Arithmetic operation RAM to register transfer Register to register transfer Group- ingPage 95, 112 103, 112 102, 112 110, 112 103, 112 96, 112 103, 112 97, 112 102, 112 102, 112 100, 112 84, 112 84, 112 83, 112 81, 112 99, 112 111, 112 111, 112 Page 111, 112 106, 112 84, 114 96, 114 78, 114 78, 114 78, 114 78, 114 85, 114 89, 114 87, 114 93, 114 80, 114 86, 114 Note: p is 0 to 63 for M34554M8, p is 0 to 95 for M34554MC and p is 0 to 127 for M34554ED.

Rev.3.00 Aug 06, 2004 page 75 of 136 REJ03B0043-0300Z INDEX LIST OF INSTRUCTION FUNCTION (continued) Group- ingFunction (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15 (PC L) ← a6–a0 (PCH ) ← p (PCL) ← a6–a0 (PCH ) ← p (PCL) ← (DR2–DR 0, A3–A0) (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← 2 (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← (DR2–DR 0, A3–A0) (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 Comparisonoperation Subroutine operation Branch operation Bit operation Return operation Mnemonic SB j RB j SZB j SEAM SEA n B a BL p, a BLA p BM a BML p, a BMLA p RTI RT RTS Group- ing Page 88, 114 86, 114 93, 114 90, 114 89, 114 79, 116 79, 116 79, 116 79, 116 80, 116 80, 116 88, 116 87, 116 88, 116 Function (INTE) ← 0 (INTE) ← 1 After skipping, (EXF0) ← 0 V10 = 1: SNZ0 = NOP After skipping, (EXF1) ← 0 V11 = 1: SNZ1 = NOP (A) ← (V1) (V1) ← (A) (A) ← (V2) (V2) ← (A) (A) ← (I1) (I1) ← (A) (A) ← (I2) (I2) ← (A) (PA0) ← (A0) (A) ← (W1) (W1) ← (A) (A) ← (W2) (W2) ← (A) (A) ← (W3) (W3) ← (A) Interrupt operation Page 81, 118 82, 118 90, 118 90, 118 90, 118 91, 118 100, 118 108, 118 100, 118 109, 118 97, 118 104, 118 97, 118 104, 118 107, 118 100, 118 109, 118 101, 118 109, 118 101, 118 109, 118 Timer operation Note: p is 0 to 63 for M34554M8, p is 0 to 95 for M34554MC and p is 0 to 127 for M34554ED. Mnemonic DI EI SNZ0 SNZ1 SNZI0 SNZI1 TAV1 TV1A TAV2 TV2A TAI1 TI1A TAI2 TI2A TPAA TAW1 TW1A TAW2 TW2A TAW3 TW3A

Rev.3.00 Aug 06, 2004 page 76 of 136 REJ03B0043-0300Z INDEX LIST OF INSTRUCTION FUNCTION (continued) Group- ing Group- ing Function (A) ← (W4) (W4) ← (A) (A) ← (W5) (W5) ← (A) (A) ← (W6) (W6) ← (A) (B) ← (TPS7–TPS 4) (A) ← (TPS3–TPS 0) (RPS 7–RPS 4) ← (B) (TPS7–TPS 4) ← (B) (RPS 3–RPS 0) ← (A) (TPS3–TPS 0) ← (A) (B) ← (T17–T14) (A) ← (T13–T10) (R17–R1 4) ← (B) (T17–T14) ← (B) (R13–R1 0) ← (A) (T13–T10) ← (A) (B) ← (T27–T24) (A) ← (T23–T20) (R27–R2 4) ← (B) (T27–T24) ← (B) (R23–R2 0) ← (A) (T23–T20) ← (A) (B) ← (T37–T34) (A) ← (T33–T30) (R37–R3 4) ← (B) (T37–T34) ← (B) (R33–R3 0) ← (A) (T33–T30) ← (A) (B) ← (T47–T44) (A) ← (T43–T40) (R4L7–R4L 4) ← (B) (T47–T44) ← (B) (R4L3–R4L 0) ← (A) (T43–T40) ← (A) Mnemonic TAW4 TW4A TAW5 TW5A TAW6 TW6A TABPS TPSAB TAB1 T1AB TAB2 T2AB TAB3 T3AB TAB4 T4AB Timer operation Page 101, 118 110, 118 101, 120 110, 120 102, 120 110, 120 97, 120 107, 120 95, 120 93, 120 95, 120 94, 120 96, 120 94, 120 96, 120 94, 120 Page 94, 120 108, 120 108, 120 95, 120 106, 120 91, 122 91, 122 92, 122 92, 122 92, 122 82, 122 85, 122 83, 122 85, 122 83, 122 83, 122 Input/Output operation Mnemonic T4HAB TR1AB TR3AB T4R4L TLCA SNZT1 SNZT2 SNZT3 SNZT4 SNZT5 IAP0 OP0A IAP1 OP1A IAP2 IAP3 Function (R4H 7–R4H 4) ← (B) (R4H 3–R4H 0) ← (A) (R17–R1 4) ← (B) (R13–R1 0) ← (A) (R37–R3 4) ← (B) (R33–R3 0) ← (A) (T47–T44) ← (R4L7–R4L 4) (T43–T40) ← (R4L3–R4L 0) (LC) ← (A) After skipping, (T1F) ← 0 After skipping, (T2F) ← 0 After skipping, (T3F) ← 0 After skipping, (T4F) ← 0 After skipping, (T5F) ← 0 (A) ← (P0) (P0) ← (A) (A) ← (P1) (P1) ← (A) (A) ← (P2) (A) ← (P3) Timer operation

Rev.3.00 Aug 06, 2004 page 77 of 136 REJ03B0043-0300Z INDEX LIST OF INSTRUCTION FUNCTION (continued) Group- ing Group- ing Page 80, 122 87, 122 89, 122 93, 122 87, 122 89, 122 99, 122 107, 122 99, 122 108, 122 98, 124 105, 124 98, 124 105, 124 98, 124 105, 124 103, 124 104, 124 104, 124 81, 124 81, 124 99, 124 107, 124 Page 116, 124 124, 124 124, 124 113, 124 128, 124 108, 124 107, 124 115, 124 123, 124 112, 146 116, 146 114, 146 92, 146 106, 146 Input/Output operation Function (D) ← 1 (D(Y)) ← 0 (Y) = 0 to 9 (D(Y)) ← 1 (Y) = 0 to 9 (D(Y)) = 0 ? (Y) = 0 to 7 (C) ← 0 (C) ← 1 (A) ← (PU0) (PU0) ← (A) (A) ← (PU1) (PU1) ← (A) (A) ← (K0) (K0) ← (A) (A) ← (K1) (K1) ← (A) (A) ← (K2) (K2) ← (A) (FR0) ← (A) (FR1) ← (A) (FR2) ← (A) Ceramic resonator selected RC oscillator selected (A) ← (MR) (MR) ← (A) Mnemonic CLD RD SD SZD RCP SCP TAPU0 TPU0A TAPU1 TPU1A TAK0 TK0A TAK1 TK1A TAK2 TK2A TFR0A TFR1A TFR2A CMCK CRCK TAMR TMRA Function (A) ← (L1) (L1) ← (A) (L2) ← (A) (L3) ← (A) (PC) ← (PC) + 1 Transition to clock operating mode Transition to RAM back-up mode POF, POF2 instructions valid (P) = 1 ? Stop of watchdog timer function enabled (WDF1) = 1 ? After skipping, (WDF1) ← 0 When TABP p instruction is ex- ecuted, P 6 ← 0 When TABP p instruction is ex- ecuted, P6 ← 1 At power down mode, voltage drop detection circuit valid Mnemonic TAL1 TL1A TL2A TL3A NOP POF POF2 EPOF SNZP DWDT WRST RBK* SBK* SVDE LCD operation Clock operation Other operation Note: *(RBK, SBK) cannot be used in the M34554M8.

Rev.3.00 Aug 06, 2004 page 78 of 136 REJ03B0043-0300Z AND (logical AND between accumulator and memory) 0000011000 018 11 – – Grouping: Arithmetic operation Description:Takes the AND operation between the con- tents of register A and the contents of M(DP), and stores the result in register A. Operation: (A) ← (A) AND (M(DP)) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) A n (Add n and accumulator) 000110nnnn 06n 11 – Overflow = 0 Grouping: Arithmetic operation Description:Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation. Operation: (A) ← (A) + n n = 0 to 15 AM (Add accumulator and Memory) 0000001010 00A 11 – – Grouping: Arithmetic operation Description:Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged. Operation: (A) ← (A) + (M(DP)) AMC (Add accumulator, Memory and Carry) 0000001011 00B 11 0/1 – Grouping: Arithmetic operation Description:Adds the contents of M(DP) and carry flag CY to register A. Stores the result in regis- ter A and carry flag CY. Operation: (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry

Rev.3.00 Aug 06, 2004 page 79 of 136 REJ03B0043-0300Z B a (Branch to address a) 011a 6 a5 a4 a3 a2 a1 a0 1a 11 –– Grouping: Branch operation Description:Branch within a page : Branches to address a in the identical page. Note: Specify the branch address within the page including this instruction. Operation: (PCL) ← a6 to a0 BL p, a (Branch Long to address a in page p) 00111p 4 p3 p2 p1 p0 0p 22 – – Grouping: Branch operation Description:Branch out of a page : Branches to address a in page p. Note: p is 0 to 63 for M34554M8, and p is 0 to 95 for M34554MC, and p is 0 to 127 for M34554ED. Operation: (PC H ) ← p (PCL) ← a6 to a0 BLA p (Branch Long to address (D) + (A) in page p) 0000010000 010 22 – – Grouping: Branch operation Description:Branch out of a page : Branches to address (DR 2 DR 1 DR 0 A3 A2 A1 A0)2 specified by registers D and A in page p. Note: p is 0 to 63 for M34554M8, and p is 0 to 95 for M34554MC, and p is 0 to 127 for M34554ED. 2 161p 6 p5 a6 a5 a4 a3 a2 a1 a0 a E Operation: (PCH ) ← p (PCL) ← (DR2–DR 0, A3–A0) 2 161p 6 p5 p4 00p 3 p2 p1 p0 pp MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) p BM a (Branch and Mark to address a in page 2) 010a 6 a5 a4 a3 a2 a1 a0 1aa 11 – – Grouping: Subroutine call operation Description:Call the subroutine in page 2 : Calls the subroutine at address a in page 2. Note: Subroutine extending from page 2 to an- other page can also be called with the BM instruction when it starts on page 2. Be careful not to over the stack because the maximum level of subroutine nesting is 8. Operation: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PC H ) ← 2 (PCL) ← a6–a0

Rev.3.00 Aug 06, 2004 page 80 of 136 REJ03B0043-0300Z CMA (CoMplement of Accumulator) 0000011100 01C 11 – – Grouping: Arithmetic operation Description:Stores the one’s complement for register A’s contents in register A. Operation: (A) ← (A) BML p, a (Branch and Mark Long to address a in page p) 00110p 4 p3 p2 p1 p0 0p 22 – – Grouping: Subroutine call operation Description:Call the subroutine : Calls the subroutine at address a in page p. Note: p is 0 to 63 for M34554M8, and p is 0 to 95 for M34554MC, and p is 0 to 127 for M34554ED. Be careful not to over the stack because the maximum level of subroutine nesting is 8. Operation: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PC H ) ← p (PCL) ← a6–a0 BMLA p (Branch and Mark Long to address (D) + (A) in page p) 0000110000 030 22 – – Grouping: Subroutine call operation Description:Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 speci- fied by registers D and A in page p. Note: p is 0 to 63 for M34554M8, and p is 0 to 95 for M34554MC, and p is 0 to 127 for M34554ED. Be careful not to over the stack because the maximum level of subroutine nesting is 8. CLD (CLear port D) 0000010001 011 11 – – Grouping: Input/Output operation Description:Sets (1) to port D. Operation: (D) ← 1 2 161p 6 p5 a6 a5 a4 a3 a2 a1 a0 a C Operation: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← (DR2–DR 0, A3–A0) 2 161p 6 p5 p4 00p 3 p2 p1 p0 pp MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) p

Rev.3.00 Aug 06, 2004 page 81 of 136 REJ03B0043-0300Z CMCK (Clock select: ceraMic oscillation ClocK) 1010011010 29A 11 – – Grouping: Other operation Description:Selects the ceramic oscillation circuit and stops the on-chip oscillator. Operation: Ceramic oscillation circuit selected CRCK (Clock select: Rc oscillation ClocK) 1010011011 29B 11 – – Grouping: Other operation Description:Selects the RC oscillation circuit and stops the on-chip oscillator. Operation: RC oscillation circuit selected DEY (DEcrement register Y) 0000010111 017 11 – (Y) = 15 Grouping: RAM addresses Description:Subtracts 1 from the contents of register Y. As a result of subtraction, when the con- tents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. Operation: (Y) ← (Y) – 1 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) DI (Disable Interrupt) 0000000100 004 11 – – Grouping: Interrupt control operation Description:Clears (0) to interrupt enable flag INTE, and disables the interrupt. Note: Interrupt is disabled by executing the DI in- struction after executing 1 machine cycle. Operation: (INTE) ← 0

Rev.3.00 Aug 06, 2004 page 82 of 136 REJ03B0043-0300Z IAP0 (Input Accumulator from port P0) 1001100000 260 11 – – Grouping: Input/Output operation Description:Transfers the input of port P0 to register A. Operation: (A) ← (P0) DWDT (Disable WatchDog Timer) 1010011100 29C 11 – – Grouping: Other operation Description:Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction. Operation: Stop of watchdog timer function enabled EPOF (Enable POF instruction) 0001011011 05B 11 – – Grouping: Other operation Description:Makes the immediate after POF or POF2 instruction valid by executing the EPOF in- struction. Operation: POF instruction, POF2 instruction valid EI (Enable Interrupt) 0000000101 005 11 – – Grouping: Interrupt control operation Description:Sets (1) to interrupt enable flag INTE, and enables the interrupt. Note: Interrupt is enabled by executing the EI in- struction after executing 1 machine cycle. Operation: (INTE) ← 1 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

Rev.3.00 Aug 06, 2004 page 83 of 136 REJ03B0043-0300Z IAP1 (Input Accumulator from port P1) 1001100001 261 11 – – Grouping: Input/Output operation Description:Transfers the input of port P1 to register A. Operation: (A) ← (P1) IAP2 (Input Accumulator from port P2) 1001100010 262 11 – – Grouping: Input/Output operation Description:Transfers the input of port P2 to register A. Operation: (A) ← (P2) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) IAP3 (Input Accumulator from port P3) 1001100011 263 11 – – Grouping: Input/Output operation Description:Transfers the input of port P3 to register A. Operation: (A) ← (P3) INY (INcrement register Y) 0000010011 013 11 – (Y) = 0 Grouping: RAM addresses Description:Adds 1 to the contents of register Y. As a re- sult of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. Operation: (Y) ← (Y) + 1

Rev.3.00 Aug 06, 2004 page 84 of 136 REJ03B0043-0300Z LZ z (Load register Z with z) 00010010z 1 z0 04 11 – – Grouping: RAM addresses Description:Loads the value z in the immediate field to register Z. Operation: (Z) ← z z = 0 to 3 NOP (No OPeration) 0000000000 000 11 – – Grouping: Other operation Description:No operation; Adds 1 to program counter value, and others remain unchanged. Operation: (PC) ← (PC) + 1 LA n (Load n in Accumulator) 000111nnnn 07n 11 – Continuous Grouping: Arithmetic operation Description:Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA in- struction is executed and other LA instructions coded continuously are skipped. Operation: (A) ← n n = 0 to 15 LXY x, y (Load register X and Y with x and y) 11x 3 x2 x1 x0 y3 y2 y1 y0 3xy 11 – Continuous Grouping: RAM addresses Description:Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instruc- tions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continu- ously are skipped. Operation: (X) ← x x = 0 to 15 (Y) ← y y = 0 to 15 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

Rev.3.00 Aug 06, 2004 page 85 of 136 REJ03B0043-0300Z OP0A (Output port P0 from Accumulator) 1000100000 220 11 – – Grouping: Input/Output operation Description:Outputs the contents of register A to port P0. Operation: (P0) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) OP1A (Output port P1 from Accumulator) 1000100001 221 11 – – Grouping: Input/Output operation Description:Outputs the contents of register A to port P1. Operation: (P1) ← (A) OR (logical OR between accumulator and memory) 0000011001 019 11 – – Grouping: Arithmetic operation Description:Takes the OR operation between the con- tents of register A and the contents of M(DP), and stores the result in register A. Operation: (A) ← (A) OR (M(DP)) POF (Power OFf1) 0000000010 002 11 – – Grouping: Other operation Description:Puts the system in clock operating state by executing the POF instruction after execut- ing the EPOF instruction. Note: If the EPOF instruction is not executed before executing this instruction, this instruction is equivalent to the NOP instruction. Operation: Transition to clock operating mode

Rev.3.00 Aug 06, 2004 page 86 of 136 REJ03B0043-0300Z RBK (Reset Bank flag) 0001000000 040 11 –– Grouping: Other operation Description:Sets referring data area to pages 0 to 63 when the TABP p instruction is executed. Note: This instruction cannot be used in M34554M8. Operation: When TABP p instruction is executed, P6 ← 0 POF2 (Power OFf2) 0000001000 008 11 – – Grouping: Other operation Description:Puts the system in RAM back-up state by executing the POF2 instruction after ex- ecuting the EPOF instruction. Note: If the EPOF instruction is not executed before executing this instruction, this instruction is equivalent to the NOP instruction. Operation: Transition to RAM back-up mode RAR (Rotate Accumulator Right) 0000011101 01D 1 1 0/1 – Grouping: Arithmetic operation Description:Rotates 1 bit of the contents of register A in- cluding the contents of carry flag CY to the right. Operation: → CY → A3A2A1A0 RB j (Reset Bit) 00010011j j 04 11 – – Grouping: Bit operation Description:Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Operation: (Mj(DP)) ← 0 j = 0 to 3 C MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

Rev.3.00 Aug 06, 2004 page 87 of 136 REJ03B0043-0300Z RD (Reset port D specified by register Y) 0000010100 014 11 – – Grouping: Input/Output operation Description:Clears (0) to a bit of port D specified by reg- ister Y . Operation: (D(Y)) ← 0 However, (Y) = 0 to 9 RC (Reset Carry flag) 0000000110 006 11 0 – Grouping: Arithmetic operation Description:Clears (0) to carry flag CY. Operation: (CY) ← 0 RCP (Reset Port C) 1010001100 28C 11 – – Grouping: Input/Output operation Description:Clears (0) to port C. Operation: (C) ← 0 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) RT (ReTurn from subroutine) 0001000100 044 12 – – Grouping: Return operation Description:Returns from subroutine to the routine called the subroutine. Operation: (PC) ← (SK(SP)) (SP) ← (SP) – 1

Rev.3.00 Aug 06, 2004 page 88 of 136 REJ03B0043-0300Z SBK (Set Bank flag) 0001000001 041 11 – – Grouping: Other operation Description:Sets referring data area to pages 64 to 127 when the TABP p instruction is executed. Note: This instruction cannot be used in M34554M8. In M34554MC, referring data area is pages 64 to 95. Operation: When TABP p instruction is executed, P6 ← 1 RTI (ReTurn from Interrupt) 0001000110 046 11 – – Grouping: Return operation Description:Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y , Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY in- struction, register A and register B to the states just before interrupt. RTS (ReTurn from subroutine and Skip) 0001000101 045 12 – Skip at uncondition Grouping: Return operation Description:Returns from subroutine to the routine called the subroutine, and skips the next in- struction at uncondition. Operation: (PC) ← (SK(SP)) (SP) ← (SP) – 1 Operation: (PC) ← (SK(SP)) (SP) ← (SP) – 1 SB j (Set Bit) 00010111j j 05 11 – – Grouping: Bit operation Description:Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Operation: (Mj(DP)) ← 1 j = 0 to 3 C MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

Rev.3.00 Aug 06, 2004 page 89 of 136 REJ03B0043-0300Z SCP (Set Port C) 1010001101 28D 11 – – Grouping: Input/Output operation Description:Sets (1) to port C. Operation: (C) ← 1 SD (Set port D specified by register Y) 0000010101 015 11 – – Grouping: Input/Output operation Description:Sets (1) to a bit of port D specified by regis- ter Y. Operation: (D(Y)) ← 1 (Y) = 0 to 9 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SC (Set Carry flag) 0000000111 007 11 1 – Grouping: Arithmetic operation Description:Sets (1) to carry flag CY. Operation: (CY) ← 1 SEA n (Skip Equal, Accumulator with immediate data n) 0000100101 025 22 – (A) = n Grouping: Comparison operation Description:Skips the next instruction when the con- tents of register A is equal to the value n in the immediate field. Executes the next instruction when the con- tents of register A is not equal to the value n in the immediate field. Operation: (A) = n ? n = 0 to 15 2 16000111nnnn 07n

Rev.3.00 Aug 06, 2004 page 90 of 136 REJ03B0043-0300Z SNZI0 (Skip if Non Zero condition of external 0 Interrupt input pin) 0000111010 03A Grouping: Interrupt operation Description:When I12 = 0 : Skips the next instruction when the level of INT0 pin is “L.” Executes the next instruction when the level of INT0 pin is “H.” When I12 = 1 : Skips the next instruction when the level of INT0 pin is “H.” Executes the next instruction when the level of INT0 pin is “L.” Operation: I1 (I12 : bit 2 of the interrupt control register I1) SNZ0 (Skip if Non Zero condition of external 0 interrupt request flag) 0000111000 038 11 – V10 = 0: (EXF0) = 1 Grouping: Interrupt operation Description:When V1 0 = 0 : Skips the next instruction when external 0 interrupt request flag EXF0 is “1.” After skipping, clears (0) to the EXF0 flag. When the EXF0 flag is “0,” executes the next instruction. When V1 0 = 1 : This instruction is equiva- lent to the NOP instruction. Operation: V10 = 0: (EXF0) = 1 ? After skipping, (EXF0) ← 0 V10 = 1: SNZ0 = NOP (V10 : bit 0 of the interrupt control register V1) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SEAM (Skip Equal, Accumulator with Memory) 0000100110 026 11 – (A) = (M(DP)) Grouping: Comparison operation Description:Skips the next instruction when the con- tents of register A is equal to the contents of M(DP). Executes the next instruction when the con- tents of register A is not equal to the contents of M(DP). Operation: (A) = (M(DP)) ? SNZ1 (Skip if Non Zero condition of external 1 interrupt request flag) 0000111001 039 11 – V11 = 0: (EXF1) = 1 Grouping: Interrupt operation Description:When V1 1 = 0 : Skips the next instruction when external 1 interrupt request flag EXF1 is “1.” After skipping, clears (0) to the EXF1 flag. When the EXF1 flag is “0,” executes the next instruction. When V1 1 = 1 : This instruction is equiva- lent to the NOP instruction. Operation: V11 = 0: (EXF1) = 1 ? After skipping, (EXF1) ← 0 V11 = 1: SNZ1 = NOP (V11 : bit 1 of the interrupt control register V1)

Rev.3.00 Aug 06, 2004 page 91 of 136 REJ03B0043-0300Z SNZP (Skip if Non Zero condition of Power down flag) 0000000011 003 11 – (P) = 1 Grouping: Other operation Description:Skips the next instruction when the P flag is “1”. After skipping, the P flag remains un- changed. Executes the next instruction when the P flag is “0.” Operation: (P) = 1 ? SNZI1 (Skip if Non Zero condition of external 1 Interrupt input pin) 0000111011 03B Grouping: Interrupt operation Description:When I2 2 = 0 : Skips the next instruction when the level of INT1 pin is “L.” Executes the next instruction when the level of INT1 pin is “H.” When I2 2 = 1 : Skips the next instruction when the level of INT1 pin is “H.” Executes the next instruction when the level of INT1 pin is “L.” Operation: I22 = 0 : (INT1) = “L” ? (I22 : bit 2 of the interrupt control register I2) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SNZT1 (Skip if Non Zero condition of Timer 1 interrupt request flag) 1010000000 280 Grouping: Timer operation Description:When V1 2 = 0 : Skips the next instruction when timer 1 interrupt request flag T1F is “1.” After skipping, clears (0) to the T1F flag. When the T1F flag is “0,” executes the next instruction. When V1 2 = 1 : This instruction is equiva- lent to the NOP instruction. Operation: V12 = 0: (T1F) = 1 ? After skipping, (T1F) ← 0 V12 = 1: SNZT1 = NOP (V12 = bit 2 of interrupt control register V1) SNZT2 (Skip if Non Zero condition of Timer 2 interrupt request flag) 1010000001 281 Grouping: Timer operation Description:When V1 3 = 0 : Skips the next instruction when timer 2 interrupt request flag T2F is “1.” After skipping, clears (0) to the T2F flag. When the T2F flag is “0,” executes the next instruction. When V1 3 = 1 : This instruction is equiva- lent to the NOP instruction. Operation: V13 = 0: (T2F) = 1 ? After skipping, (T2F) ← 0 V13 = 1: SNZT2 = NOP (V13 = bit 3 of interrupt control register V1)

Rev.3.00 Aug 06, 2004 page 92 of 136 REJ03B0043-0300Z SNZT4 (Skip if Non Zero condition of Timer 4 inerrupt request flag) SNZT5 (Skip if Non Zero condition of Timer 5 inerrupt request flag) SVDE (Set Voltage Detector Enable flag) 1010000011 283 Grouping: Timer operation Description:When V2 3 = 0 : Skips the next instruction when timer 4 interrupt request flag T4F is “1.” After skipping, clears (0) to the T4F flag. When the T4F flag is “0,” executes the next instruction. When V2 3 = 1 : This instruction is equiva- lent to the NOP instruction. Operation: V23 = 0: (T4F) = 1 ? After skipping, (T4F) ← 0 V23 = 1: SNZT4 = NOP (V23 = bit 3 of interrupt control register V2) 1010000100 284 Grouping: Timer operation Description:When V2 1 = 0 : Skips the next instruction when timer 5 interrupt request flag T5F is “1.” After skipping, clears (0) to the T5F flag. When the T5F flag is “0,” executes the next instruction. When V2 1 = 1 : This instruction is equiva- lent to the NOP instruction. Operation: V21 = 0: (T5F) = 1 ? After skipping, (T5F) ← 0 V21 = 1: SNZT5 = NOP (V21 = bit 1 of interrupt control register V2) 1010010011 293 11 – – Grouping: Other operation Description:Validates the voltage drop detection circuit at power down (clock operating mode and RAM back-up mode) when VDCE pin is “H ”. Operation: At power down mode, voltage drop detection circuit valid MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SNZT3 (Skip if Non Zero condition of Timer 3 interrupt request flag) 1010000010 282 Grouping: Timer operation Description:When V2 0 = 0 : Skips the next instruction when timer 3 interrupt request flag T3F is “1.” After skipping, clears (0) to the T3F flag. When the T3F flag is “0,” executes the next instruction. When V2 0 = 1 : This instruction is equiva- lent to the NOP instruction. Operation: V20 = 0: (T3F) = 1 ? After skipping, (T3F) ← 0 V20 = 1: SNZT3 = NOP (V20 = bit 0 of interrupt control register V2)

Rev.3.00 Aug 06, 2004 page 93 of 136 REJ03B0043-0300Z MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SZB j (Skip if Zero, Bit) 00001000j j 02j 11 – (Mj(DP)) = 0 j = 0 to 3 Grouping: Bit operation Description:Skips the next instruction when the con- tents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0.” Executes the next instruction when the con- tents of bit j of M(DP) is “1.” Operation: (Mj(DP)) = 0 ? j = 0 to 3 SZC (Skip if Zero, Carry flag) 0000101111 02F 11 – (CY) = 0 Grouping: Arithmetic operation Description:Skips the next instruction when the con- tents of carry flag CY is “0.” After skipping, the CY flag remains un- changed. Executes the next instruction when the con- tents of the CY flag is “1.“ Operation: (CY) = 0 ? SZD (Skip if Zero, port D specified by register Y) 0000100100 024 22 – (D(Y)) = 0 (Y) = 0 to 7 Grouping: Input/Output operation Description:Skips the next instruction when a bit of port D specified by register Y is “0.” Executes the next instruction when the bit is “1.” T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B) 1000110000 230 11 – – Grouping: Timer operation Description:Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 re- load register R1. Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1. Operation: (T1 7–T14) ← (B) (R17–R1 4) ← (B) (T13–T10) ← (A) (R13–R1 0) ← (A) Operation: (D(Y)) = 0 ? (Y) = 0 to 7 2 160000101011 02B

Rev.3.00 Aug 06, 2004 page 94 of 136 REJ03B0043-0300Z T2AB (Transfer data to timer 2 and register R2 from Accumulator and register B) 1000110001 231 11 – – Grouping: Timer operation Description:Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 re- load register R2. Transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2. Operation: (T2 7–T24) ← (B) (R27–R2 4) ← (B) (T23–T20) ← (A) (R23–R2 0) ← (A) T3AB (Transfer data to timer 3 and register R3 from Accumulator and register B) T4AB (Transfer data to timer 4 and register R4L from Accumulator and register B) T4HAB (Transfer data to register R4H from Accumulator and register B) 1000110010 232 11 – – Grouping: Timer operation Description:Transfers the contents of register B to the high-order 4 bits of timer 3 and timer 3 re- load register R3. Transfers the contents of register A to the low-order 4 bits of timer 3 and timer 3 reload register R3. Operation: (T3 7–T34) ← (B) (R37–R3 4) ← (B) (T33–T30) ← (A) (R33–R3 0) ← (A) 1000110011 233 11 – – Grouping: Timer operation Description:Transfers the contents of register B to the high-order 4 bits of timer 4 and timer 4 re- load register R4L. Transfers the contents of register A to the low-order 4 bits of timer 4 and timer 4 reload register R4L. Operation: (T4 7–T44) ← (B) (R4L7–R4L 4) ← (B) (T43–T40) ← (A) (R4L3–R4L 0) ← (A) 1000110111 237 11 – – Grouping: Timer operation Description:Transfers the contents of register B to the high-order 4 bits of timer 4 and timer 4 re- load register R4H. Transfers the contents of register A to the low-order 4 bits of timer 4 and timer 4 reload register R4H. Operation: (R4H 7–R4H 4) ← (B) (R4H 3–R4H 0) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

Rev.3.00 Aug 06, 2004 page 95 of 136 REJ03B0043-0300Z TAB (Transfer data to Accumulator from register B) 0000011110 01E 11 – – Grouping: Register to register transfer Description:Transfers the contents of register B to reg- ister A. TAB1 (Transfer data to Accumulator and register B from timer 1) 1001110000 270 11 – – Grouping: Timer operation Description:Transfers the high-order 4 bits (T17–T14) of timer 1 to register B. Transfers the low-order 4 bits (T13–T10) of timer 1 to register A. Operation: (B) ← (T17–T14) (A) ← (T13–T10) TAB2 (Transfer data to Accumulator and register B from timer 2) 1001110001 271 11 – – Grouping: Timer operation Description:Transfers the high-order 4 bits (T27–T24) of timer 2 to register B. Transfers the low-order 4 bits (T2 3–T20) of timer 2 to register A. Operation: (B) ← (T27–T24) (A) ← (T23–T20) Operation: (A) ← (B) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) T4R4L (Transfer data to timer 4 from register R4L) 1010010111 297 11 – – Grouping: Timer operation Description:Transfers the contents of reload register R4L to timer 4. Operation: (T47–T44) ← (R4L7–R4L 4) (T43–T40) ← (R4L3–R4L 0)

Rev.3.00 Aug 06, 2004 page 96 of 136 REJ03B0043-0300Z TABP p (Transfer data to Accumulator and register B from Program memory in page p) 0010p 5 p4 p3 p2 p1 p0 0p 13 – – Grouping: Arithmetic operationOperation: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← (DR2–DR 0, A3–A0) (B) ← (ROM(PC))7–4 (A) ← (ROM(PC))3–0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 Description: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by reg- isters A and D in page p. The pages which can be referred as follows; after the SBK instruction: 64 to 127 after the RBK instruction: 0 to 63 after system is released from reset or returned from power down: 0 to 63. Note: p is 0 to 63 for M34554M8, and p is 0 to 95 for M34554MC, and p is 0 to 127 for M34554ED. When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. TABE (Transfer data to Accumulator and register B from register E) 0000101010 02A 11 – – Grouping: Register to register transfer Description:Transfers the high-order 4 bits (E7–E4) of register E to register B, and low-order 4 bits of register E to register A. Operation: (B) ← (E 7–E4) (A) ← (E3–E0) TAB4 (Transfer data to Accumulator and register B from timer 4) TAB3 (Transfer data to Accumulator and register B from timer 3) 1001110010 272 11 – – Grouping: Timer operation Description:Transfers the high-order 4 bits (T37–T34) of timer 3 to register B. Transfers the low-order 4 bits (T3 3–T30) of timer 3 to register A. Operation: (B) ← (T37–T34) (A) ← (T33–T30) 1001110011 273 11 – – Grouping: Timer operation Description:Transfers the high-order 4 bits (T47–T44) of timer 4 to register B. Transfers the low-order 4 bits (T4 3–T40) of timer 4 to register A. Operation: (B) ← (T47–T44) (A) ← (T43–T40) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

Rev.3.00 Aug 06, 2004 page 97 of 136 REJ03B0043-0300Z TAD (Transfer data to Accumulator from register D) 0001010001 051 11 – – Grouping: Register to register transfer Description:Transfers the contents of register D to the low-order 3 bits (A2–A0) of register A. Note: When this instruction is executed, “0” is stored to the bit 3 (A3) of register A. Operation: (A2–A0) ← (DR 2–DR 0) (A3) ← 0 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TABPS (Transfer data to Accumulator and register B from PreScaler) 1001110101 275 11 –– Grouping: Timer operation Description:Transfers the high-order 4 bits (TPS7– TPS 4) of prescaler to register B, and transfers the low-order 4 bits (TPS3–TPS 0) of prescaler to register A. Operation: (B) ← (TPS7–TPS 4) (A) ← (TPS3–TPS 0) TAI1 (Transfer data to Accumulator from register I1) 1001010011 253 11 – – Grouping: Interrupt operation Description:Transfers the contents of interrupt control register I1 to register A. Operation: (A) ← (I1) TAI2 (Transfer data to Accumulator from register I2) 1001010100 254 11 – – Grouping: Interrupt operation Description:Transfers the contents of interrupt control register I2 to register A. Operation: (A) ← (I2)

Rev.3.00 Aug 06, 2004 page 98 of 136 REJ03B0043-0300Z TAL1 (Transfer data to Accumulator from register L1) 1001001010 24A 11 – – Grouping: LCD control operation Description:Transfers the LCD control register L1 to register A. Operation: (A) ← (L1) TAK0 (Transfer data to Accumulator from register K0) 1001010110 256 11 – – Grouping: Input/Output operation Description:Transfers the contents of key-on wakeup control register K0 to register A. Operation: (A) ← (K0) TAK1 (Transfer data to Accumulator from register K1) 1001011001 259 11 – – Grouping: Input/Output operation Description:Transfers the contents of key-on wakeup control register K1 to register A. Operation: (A) ← (K1) TAK2 (Transfer data to Accumulator from register K2) 1001011010 25A 11 –– Grouping: Input/Output operation Description:Transfers the contents of key-on wakeup control register K2 to register A. Operation: (A) ← (K2) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

Rev.3.00 Aug 06, 2004 page 99 of 136 REJ03B0043-0300Z TAM j (Transfer data to Accumulator from Memory) 101100 jjjj 2 C j 11 – – Grouping: RAM to register transfer Description:After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the re- sult in register X. TAMR (Transfer data to Accumulator from register MR) 1001010010 252 11 – – Grouping: Clock operation Description:Transfers the contents of clock control reg- ister MR to register A. Operation: (A) ← (MR) Operation: (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAPU1 (Transfer data to Accumulator from register PU1) TAPU0 (Transfer data to Accumulator from register PU0) 1001010111 257 11 –– Grouping: Input/Output operation Description:Transfers the contents of pull-up control register PU0 to register A. Operation: (A) ← (PU0) 1001011110 25E 11 – – Grouping: Input/Output operation Description:Transfers the contents of pull-up control register PU1 to register A. Operation: (A) ← (PU1)

Rev.3.00 Aug 06, 2004 page 100 of 136 REJ03B0043-0300Z TAW1 (Transfer data to Accumulator from register W1) 1001001011 24B 11 –– Grouping: Timer operation Description:Transfers the contents of timer control reg- ister W1 to register A. Operation: (A) ← (W1) TASP (Transfer data to Accumulator from Stack Pointer) 0001010000 050 11 – – Grouping: Register to register transfer Description:Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2–A0) of register A. Note: After this instruction is executed, “0” is stored to the bit 3 (A3) of register A. TAV1 (Transfer data to Accumulator from register V1) 0001010100 054 11 – – Grouping: Interrupt operation Description:Transfers the contents of interrupt control register V1 to register A. Operation: (A) ← (V1) TAV2 (Transfer data to Accumulator from register V2) 0001010101 055 11 – – Grouping: Interrupt operation Description:Transfers the contents of interrupt control register V2 to register A. Operation: (A) ← (V2) Operation: (A2–A0) ← (SP2–SP 0) (A3) ← 0 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

Rev.3.00 Aug 06, 2004 page 101 of 136 REJ03B0043-0300Z TAW2 (Transfer data to Accumulator from register W2) 1001001100 24C 11 – – Grouping: Timer operation Description:Transfers the contents of timer control reg- ister W2 to register A. Operation: (A) ← (W2) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAW3 (Transfer data to Accumulator from register W3) TAW4 (Transfer data to Accumulator from register W4) 1001001110 24E 11 –– Grouping: Timer operation Description:Transfers the contents of timer control reg- ister W4 to register A. Operation: (A) ← (W4) 1001001101 24D 11 – – Grouping: Timer operation Description:Transfers the contents of timer control reg- ister W3 to register A. Operation: (A) ← (W3) TAW5 (Transfer data to Accumulator from register W5) 1001001111 24F 11 – – Grouping: Timer operation Description:Transfers the contents of timer control reg- ister W5 to register A. Operation: (A) ← (W5)

Rev.3.00 Aug 06, 2004 page 102 of 136 REJ03B0043-0300Z TAZ (Transfer data to Accumulator from register Z) 0001010011 053 11 – – Grouping: Register to register transfer Description:Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. Note: After this instruction is executed, “0” is stored to the high-order 2 bits (A3, A2) of register A. Operation: (A1, A0) ← (Z1, Z0) (A3, A2) ← 0 TAW6 (Transfer data to Accumulator from register W6) 1001010000 250 11 – – Grouping: Timer operation Description:Transfers the contents of timer control reg- ister W6 to register A. TAX (Transfer data to Accumulator from register X) 0001010010 052 11 –– Grouping: Register to register transfer Description:Transfers the contents of register X to reg- ister A. Operation: (A) ← (X) Operation: (A) ← (W6) TAY (Transfer data to Accumulator from register Y) 0000011111 01F 11 –– Grouping: Register to register transfer Description:Transfers the contents of register Y to regis- ter A. Operation: (A) ← (Y) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

Rev.3.00 Aug 06, 2004 page 103 of 136 REJ03B0043-0300Z TBA (Transfer data to register B from Accumulator) 0000001110 00E 11 – – Grouping: Register to register transfer Description:Transfers the contents of register A to regis- ter B. TDA (Transfer data to register D from Accumulator) 0000101001 029 11 – – Grouping: Register to register transfer Description:Transfers the contents of the low-order 3 bits (A2–A0) of register A to register D. Operation: (DR 2–DR 0) ← (A2–A0) TEAB (Transfer data to register E from Accumulator and register B) 0000011010 01A 11 – – Grouping: Register to register transfer Description:Transfers the contents of register B to the high-order 4 bits (E7–E4) of register E, and the contents of register A to the low-order 4 bits (E 3–E0) of register E. Operation: (E7–E4) ← (B) (E3–E0) ← (A) Operation: (B) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TFR0A (Transfer data to register FR0 from Accumulator) 1000101000 228 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to the port output structure control register FR0. Operation: (FR0) ← (A)

Rev.3.00 Aug 06, 2004 page 104 of 136 REJ03B0043-0300Z TI1A (Transfer data to register I1 from Accumulator) 1000010111 217 11 – – Grouping: Interrupt operation Description:Transfers the contents of register A to inter- rupt control register I1. Operation: (I1) ← (A) TI2A (Transfer data to register I2 from Accumulator) 1000011000 218 11 –– Grouping: Interrupt operation Description:Transfers the contents of register A to inter- rupt control register I2. Operation: (I2) ← (A) TFR2A (Transfer data to register FR2 from Accumulator) TFR1A (Transfer data to register FR1 from Accumulator) 1000101001 229 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to the port output structure control register FR1. Operation: (FR1) ← (A) 1000101010 22A 11 –– Grouping: Input/Output operation Description:Transfers the contents of register A to the port output structure control register FR2. Operation: (FR2) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

Rev.3.00 Aug 06, 2004 page 105 of 136 REJ03B0043-0300Z TK0A (Transfer data to register K0 from Accumulator) 1000011011 21B 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to key- on wakeup control register K0. Operation: (K0) ← (A) TK1A (Transfer data to register K1 from Accumulator) 1000010100 214 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to key- on wakeup control register K1. TK2A (Transfer data to register K2 from Accumulator) 1000010101 215 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to key- on wakeup control register K2. Operation: (K2) ← (A) Operation: (K1) ← (A) TL1A (Transfer data to register L1 from Accumulator) 1000001010 20A 11 – – Grouping: LCD operation Description:Transfers the contents of register A to LCD control register L1. Operation: (L1) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

Rev.3.00 Aug 06, 2004 page 106 of 136 REJ03B0043-0300Z TL3A (Transfer data to register L3 from Accumulator) TLCA (Transfer data to timer LC and register RLC from Accumulator) TMA j (Transfer data to Memory from Accumulator) 101011 jjjj 2 B j 11 – – Grouping: RAM to register transfer Description:After transferring the contents of register A to M(DP), an exclusive OR operation is per- formed between register X and the value j in the immediate field, and stores the result in register X. Operation: (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 1000001100 20C 11 –– Grouping: LCD operation Description:Transfers the contents of register A to LCD control register L3. Operation: (L3) ← (A) 1000001101 20D 11 – – Grouping: Timer operation Description:Transfers the contents of register A to timer LC and reload register RLC. Operation: (LC) ← (A) (RLC) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TL2A (Transfer data to register L2 from Accumulator) 1000001011 20B 11 – – Grouping: LCD operation Description:Transfers the contents of register A to LCD control register L2. Operation: (L2) ← (A)

Rev.3.00 Aug 06, 2004 page 107 of 136 REJ03B0043-0300Z TPU0A (Transfer data to register PU0 from Accumulator) 1000101101 22D 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to pull- up control register PU0. Operation: (PU0) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TPAA (Transfer data to register PA from Accumulator) TPSAB (Transfer data to Pre-Scaler from Accumulator and register B) 1010101010 2AA 11 – – Grouping: Timer operation Description:Transfers the contents of lowermost bit (A0) register A to timer control register PA. Operation: (PA0) ← (A0) 1000110101 235 11 – – Grouping: Timer operation Description:Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS, and transfers the con- tents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS. Operation: (RPS 7–RPS 4) ← (B) (TPS7–TPS 4) ← (B) (RPS 3–RPS 0) ← (A) (TPS3–TPS 0) ← (A) TMRA (Transfer data to register MR from Accumulator) 1000010110 216 11 – – Grouping: Other operation Description:Transfers the contents of register A to clock control register MR. Operation: (MR) ← (A)

Rev.3.00 Aug 06, 2004 page 108 of 136 REJ03B0043-0300Z MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TV1A (Transfer data to register V1 from Accumulator) 0000111111 03F 11 – – Grouping: Interrupt operation Description:Transfers the contents of register A to inter- rupt control register V1. Operation: (V1) ← (A) TR3AB (Transfer data to register R3 from Accumulator and register B) 1000111011 23B 11 – – Grouping: Timer operation Description:Transfers the contents of register B to the high-order 4 bits (R37–R3 4) of reload regis- ter R3, and the contents of register A to the low-order 4 bits (R3 3–R3 0) of reload regis- ter R3. Operation: (R37–R3 4) ← (B) (R33–R3 0) ← (A) TR1AB (Transfer data to register R1 from Accumulator and register B) 1000111111 23F 11 – – Grouping: Timer operation Description:Transfers the contents of register B to the high-order 4 bits (R17–R1 4) of reload regis- ter R1, and the contents of register A to the low-order 4 bits (R13–R1 0) of reload regis- ter R1. Operation: (R17–R1 4) ← (B) (R13–R1 0) ← (A) TPU1A (Transfer data to register PU1 from Accumulator) 1000101110 22E 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to pull- up control register PU1. Operation: (PU1) ← (A)

Rev.3.00 Aug 06, 2004 page 109 of 136 REJ03B0043-0300Z TW3A (Transfer data to register W3 from Accumulator) TW1A (Transfer data to register W1 from Accumulator) 1000001110 20E 11 – – Grouping: Timer operation Description:Transfers the contents of register A to timer control register W1. Operation: (W1) ← (A) TW2A (Transfer data to register W2 from Accumulator) 1000001111 20F 11 –– Grouping: Timer operation Description:Transfers the contents of register A to timer control register W2. Operation: (W2) ← (A) 1000010000 210 11 – – Grouping: Timer operation Description:Transfers the contents of register A to timer control register W3. Operation: (W3) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TV2A (Transfer data to register V2 from Accumulator) 0000111110 03E 11 – – Grouping: Interrupt operation Description:Transfers the contents of register A to inter- rupt control register V2. Operation: (V2) ← (A)

Rev.3.00 Aug 06, 2004 page 110 of 136 REJ03B0043-0300Z TYA (Transfer data to register Y from Accumulator) 0000001100 00C 11 – – Grouping: Register to register transfer Description:Transfers the contents of register A to regis- ter Y. Operation: (Y) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TW5A (Transfer data to register W5 from Accumulator) TW6A (Transfer data to register W6 from Accumulator) 1000010011 213 11 – – Grouping: Timer operation Description:Transfers the contents of register A to timer control register W6. Operation: (W6) ← (A) 1000010010 212 11 – – Grouping: Timer operation Description:Transfers the contents of register A to timer control register W5. Operation: (W5) ← (A) TW4A (Transfer data to register W4 from Accumulator) 1000010001 211 11 – – Grouping: Timer operation Description:Transfers the contents of register A to timer control register W4. Operation: (W4) ← (A)

Rev.3.00 Aug 06, 2004 page 111 of 136 REJ03B0043-0300Z XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip) 101110 jjjj 2 E j 11 – (Y) = 0 Grouping: RAM to register transfer Description:After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between regis- ter X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a re- sult of addition, when the contents of register Y is 0, the next instruction is skipped. when the contents of register Y is not 0, the next instruction is executed. Operation: (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 2 16 XAM j (eXchange Accumulator and Memory data) 101101 jjjj 2 D j 11 – – Grouping: RAM to register transfer Description:After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between regis- ter X and the value j in the immediate field, and stores the result in register X. Operation: (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip) 101111 jjjj 2 F j 11 – (Y) = 15 Grouping: RAM to register transfer Description:After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between regis- ter X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the con- tents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. Operation: (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) – 1 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) WRST (Watchdog timer ReSeT) 1010100000 2A0 11 – (WDF1) = 1 Grouping: Other operation Description:Skips the next instruction when watchdog timer flag WDF1 is “1.” After skipping, clears (0) to the WDF1 flag. When the WDF1 flag is “0,” executes the next instruction. Also, stops the watchdog timer function when ex- ecuting the WRST instruction immediately after the DWDT instruction. Operation: (WDF1) = 1 ? After skipping, (WDF1) ← 0

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.3.00 Aug 06, 2004 page 112 of 136 REJ03B0043-0300Z (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) (E7–E4) ← (B) (E3–E0) ← (A) (B) ← (E7–E4) (A) ← (E3–E0) (DR 2–DR 0) ← (A2–A0) (A2–A0) ← (DR2–DR 0) (A3) ← 0 (A3, A2) ← 0 (A) ← (X) (A2–A0) ← (SP2–SP 0) (A3) ← 0 (X) ← x x = 0 to 15 (Y) ← y y = 0 to 15 (Z) ← z z = 0 to 3 (Y) ← (Y) + 1 (Y) ← (Y) – 1 (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) – 1 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 TAB TBA TAY TYA TEAB TABE TDA TAD TAZ TAX TASP LXY x, y LZ z INY DEY TAM j XAM j XAMD j XAMI j TMA j MACHINE INSTRUCTIONS (INDEX BY TYPES) 0000011110 0000001110 0000011111 0000001100 0000011010 0000101010 0000101001 0001010001 0001010011 0001010010 0001010000 11x 3 x2 x1 x0 y3 y2 y1 y0 00010010z 1 z0 0000010011 0000010111 101100 jjjj 101101 jjjj 101111 jjjj 101110 jjjj 101011 jjjj 01E 00E 01F 00C 01A 02A 029 051 053 052 050 3xy 048 013 017 2C j 2D j 2Fj 2Ej 2Bj RAM addresses RAM to register transfer Register to register transfer

Skip condition Datailed description Carry flag CY Rev.3.00 Aug 06, 2004 page 113 of 136 REJ03B0043-0300Z (Y) = 0 (Y) = 15 (Y) = 15 (Y) = 0 Transfers the contents of register B to register A. Transfers the contents of register A to register B. Transfers the contents of register Y to register A. Transfers the contents of register A to register Y. Transfers the contents of register B to the high-order 4 bits (E 7–E4) of register E, and the contents of regis- ter A to the low-order 4 bits (E3–E0) of register E. Transfers the high-order 4 bits (E7–E4) of register E to register B, and low-order 4 bits (E3–E0) of register E to register A. Transfers the contents of the low-order 3 bits (A2–A0) of register A to register D. Transfers the contents of register D to the low-order 3 bits (A2–A0) of register A. Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. Transfers the contents of register X to register A. Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2–A0) of register A. Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. Loads the value z in the immediate field to register Z. Adds 1 to the contents of register Y . As a result of addition, when the contents of register Y is 0, the next in- struction is skipped. When the contents of register Y is not 0, the next instruction is executed. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between reg- ister X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per- formed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per- formed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per- formed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y . As a result of addition, when the contents of register Y is 0, the next in- struction is skipped. When the contents of register Y is not 0, the next instruction is executed. After transferring the contents of register A to M(DP), an exclusive OR operation is performed between reg- ister X and the value j in the immediate field, and stores the result in register X.

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.3.00 Aug 06, 2004 page 114 of 136 REJ03B0043-0300Z MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) 07n 08p 00A 00B 06n 018 019 007 006 02F 01C 01D 05C 04C 02j 026 025 07n 000111nnnn 0010p 5 p4 p3 p2 p1 p0 0000001010 0000001011 000110nnnn 0000011000 0000011001 0000000111 0000000110 0000101111 0000011100 0000011101 00010111j j 00010011j j 00001000j j 0000100110 0000100101 000111nnnn LA n TABP p AM AMC A n AND OR SC RC SZC CMA RAR SB j RB j SZB j SEAM SEA n Arithmetic operation Comparison operation Bit operation (A) ← n n = 0 to 15 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (Note) (PCL) ← (DR2–DR 0, A3–A0) (B) ← (ROM(PC))7–4 (A) ← (ROM(PC))3–0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (A) ← (A) + (M(DP)) (A) ← (A) + (M(DP)) +(CY) (CY) ← Carry (A) ← (A) + n n = 0 to 15 (A) ← (A) AND (M(DP)) (A) ← (A) OR (M(DP)) (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → CY → A 3A2A1A0 (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15 Note: p is 0 to 63 for M34554M8, p is 0 to 95 for M34554MC and p is 0 to 127 for M34554ED.

Skip condition Datailed description Carry flag CY Rev.3.00 Aug 06, 2004 page 115 of 136 REJ03B0043-0300Z Overflow = 0 (CY) = 0 (Mj(DP)) = 0 j = 0 to 3 (A) = (M(DP)) (A) = n Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in ad- dress (DR 2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. The pages which can be referred as follows; after the SBK instruction: 64 to 127 after the RBK instruction: 0 to 63 after system is released from reset or returned from power down: 0 to 63. Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY re- mains unchanged. Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation. Takes the AND operation between the contents of register A and the contents of M(DP), and stores the re- sult in register A. Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A. Sets (1) to carry flag CY. Clears (0) to carry flag CY. Skips the next instruction when the contents of carry flag CY is “0.” Stores the one’s complement for register A’s contents in register A. Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0.” Executes the next instruction when the contents of bit j of M(DP) is “1.” Skips the next instruction when the contents of register A is equal to the contents of M(DP). Executes the next instruction when the contents of register A is not equal to the contents of M(DP). Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Executes the next instruction when the contents of register A is not equal to the value n in the immediate field.

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.3.00 Aug 06, 2004 page 116 of 136 REJ03B0043-0300Z BL p, a BLA p BM a BML p, a BMLA p RTI RT RTS 011a 6 a5 a4 a3 a2 a1 a0 00111p 4 p3 p2 p1 p0 1p 6 p5 a6 a5 a4 a3 a2 a1 a0 0000010000 1p 6 p5 p4 00p 3 p2 p1 p0 010a 6 a5 a4 a3 a2 a1 a0 00110p 4 p3 p2 p1 p0 1p 6 p5 a6 a5 a4 a3 a2 a1 a0 0000110000 6 p5 p4 00p 3 p2 p1 p0 0001000110 0001000100 0001000101 18a 0Ep 2pa +p +a 010 2pp 1aa 0C p 2pa +p +a 030 2pp 046 044 045 Subroutine operation Return operation MACHINE INSTRUCTIONS (continued) (PCL) ← a6–a0 (PCH ) ← p (Note) (PCL) ← a6–a0 (PCH ) ← p (Note) (PCL) ← (DR2–DR 0, A3–A0) (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← 2 (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (Note) (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (Note) (PCL) ← (DR2–DR 0,A3–A0) (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 Branch operation Note: p is 0 to 63 for M34554M8, p is 0 to 95 for M34554MC and p is 0 to 127 for M34554ED.

Skip condition Datailed description Carry flag CY Rev.3.00 Aug 06, 2004 page 117 of 136 REJ03B0043-0300Z Branch within a page : Branches to address a in the identical page. Branch out of a page : Branches to address a in page p. Branch out of a page : Branches to address (DR

2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in

page p. Call the subroutine in page 2 : Calls the subroutine at address a in page 2. Call the subroutine : Calls the subroutine at address a in page p. Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous de- scription of the LA/LXY instruction, register A and register B to the states just before interrupt. Returns from subroutine to the routine called the subroutine. Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.

(INTE) ← 0 (INTE) ← 1 After skipping, (EXF0) ← 0 V10 = 1: SNZ0 = NOP After skipping, (EXF1) ← 0 V11 = 1: SNZ1 = NOP (A) ← (V1) (V1) ← (A) (A) ← (V2) (V2) ← (A) (A) ← (I1) (I1) ← (A) (A) ← (I2) (I2) ← (A) (PA0) ← (A0) (A) ← (W1) (W1) ← (A) (A) ← (W2) (W2) ← (A) (A) ← (W3) (W3) ← (A) (A) ← (W4) (W4) ← (A) (A) ← (W5) (W5) ← (A) 004 005 038 039 03A 03B 054 03F 055 03E 253 217 254 218 2AA 24B 20E 24C 20F 24D 210 24E 211 24F 212 0000000100 0000000101 0000111000 0000111001 0000111010 0000111011 0001010100 0000111111 0001010101 0000111110 1001010011 1000010111 1001010100 1000011000 1010101010 1001001011 1000001110 1001001100 1000001111 1001001101 1000010000 1001001110 1000010001 1001001111 1000010010 Interrupt operation Timer operation Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Rev.2.00 Jul 01, 2003 page 118 of 136

0 = 0: (EXF0) = 1 (INT0) = “H ” However, I12 = 1 (INT0) = “L” However, I12 = 0 (INT1) = “H ” However, I22 = 1 (INT1) = “L” However, I22 = 0 Skip condition Datailed description Carry flag CY Clears (0) to interrupt enable flag INTE, and disables the interrupt. Sets (1) to interrupt enable flag INTE, and enables the interrupt. When V1 0 = 0 : Skips the next instruction when external 0 interrupt request flag EXF0 is “1.” After skipping, clears (0) to the EXF0 flag. When the EXF0 flag is “0,” executes the next instruction. When V1 0 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register V1) When V1 1 = 0 : Skips the next instruction when external 1 interrupt request flag EXF1 is “1.” After skipping, clears (0) to the EXF1 flag. When the EXF1 flag is “0,” executes the next instruction. When V1 1 = 1 : This instruction is equivalent to the NOP instruction. (V11: bit 1 of interrupt control register V1) When I12 = 1 : Skips the next instruction when the level of INT0 pin is “H.” (I12: bit 2 of interrupt control reg- ister I1) When I12 = 0 : Skips the next instruction when the level of INT0 pin is “L.” When I22 = 1 : Skips the next instruction when the level of INT1 pin is “H.” (I22: bit 2 of interrupt control reg- ister I2) When I22 = 0 : Skips the next instruction when the level of INT1 pin is “L.” Transfers the contents of interrupt control register V1 to register A. Transfers the contents of register A to interrupt control register V1. Transfers the contents of interrupt control register V2 to register A. Transfers the contents of register A to interrupt control register V2. Transfers the contents of interrupt control register I1 to register A. Transfers the contents of register A to interrupt control register I1. Transfers the contents of interrupt control register I2 to register A. Transfers the contents of register A to interrupt control register I2. Transfers the contents of register A to timer control register PA. Transfers the contents of timer control register W1 to register A. Transfers the contents of register A to timer control register W1. Transfers the contents of timer control register W2 to register A. Transfers the contents of register A to timer control register W2. Transfers the contents of timer control register W3 to register A. Transfers the contents of register A to timer control register W3. Transfers the contents of timer control register W4 to register A. Transfers the contents of register A to timer control register W4. Transfers the contents of timer control register W5 to register A. Transfers the contents of register A to timer control register W5. Rev.2.00 Jul 01, 2003 page 119 of 136

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.3.00 Aug 06, 2004 page 120 of 136 REJ03B0043-0300Z (A) ← (W6) (W6) ← (A) (B) ← (TPS 7–TPS 4) (A) ← (TPS3–TPS 0) (RPS 7–RPS 4) ← (B) (TPS7–TPS 4) ← (B) (RPS 3–RPS 0) ← (A) (TPS3–TPS 0) ← (A) (B) ← (T17–T14) (A) ← (T13–T10) (R17–R1 4) ← (B) (T17–T14) ← (B) (R13–R1 0) ← (A) (T13–T10) ← (A) (B) ← (T27–T24) (A) ← (T23–T20) (R27–R2 4) ← (B) (T27–T24) ← (B) (R23–R2 0) ← (A) (T23–T20) ← (A) (B) ← (T37–T34) (A) ← (T33–T30) (R37–R3 4) ← (B) (T37–T34) ← (B) (R33–R3 0) ← (A) (T33–T30) ← (A) (B) ← (T47–T44) (A) ← (T43–T40) (R4L7–R4L 4) ← (B) (T47–T44) ← (B) (R4L3–R4L 0) ← (A) (T43–T40) ← (A) (R4H 7–R4H 4) ← (B) (R4H 3–R4H 0) ← (A) (R17–R1 4) ← (B) (R13–R1 0) ← (A) (R37–R3 4) ← (B) (R33–R3 0) ← (A) (T47–T40) ← (R4L7–R4L 0) (LC) ← (A) (RLC) ← (A) TAW6 TW6A TABPS TPSAB TAB1 T1AB TAB2 T2AB TAB3 T3AB TAB4 T4AB T4HAB TR1AB TR3AB T4R4L TLCA Timer operation

Skip condition Datailed description Carry flag CY Rev.3.00 Aug 06, 2004 page 121 of 136 REJ03B0043-0300Z Transfers the contents of timer control register W6 to register A. Transfers the contents of register A to timer control register W6. Transfers the high-order 4 bits of prescaler to register B, and transfers the low-order 4 bits of prescaler to register A. Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS, and transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS. Transfers the high-order 4 bits of timer 1 to register B, and transfers the low-order 4 bits of timer 1 to regis- ter A. Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1, and transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1. Transfers the high-order 4 bits of timer 2 to register B, and transfers the low-order 4 bits of timer 2 to regis- ter A. Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2, and transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2. Transfers the high-order 4 bits of timer 3 to register B, and transfers the low-order 4 bits of timer 3 to regis- ter A. Transfers the contents of register B to the high-order 4 bits of timer 3 and timer 3 reload register R3, and transfers the contents of register A to the low-order 4 bits of timer 3 and timer 3 reload register R3. Transfers the high-order 4 bits of timer 4 to register B, and transfers the low-order 4 bits of timer 4 to regis- ter A. Transfers the contents of register B to the high-order 4 bits of timer 4 and timer 4 reload register R4L, and transfers the contents of register A to the low-order 4 bits of timer 4 and timer 4 reload register R4L. Transfers the contents of register B to the high-order 4 bits of timer 4 reload register R4H, and transfers the contents of register A to the low-order 4 bits of timer 4 reload register R4H. Transfers the contents of register B to the high-order 4 bits of timer 1 reload register R1, and transfers the contents of register A to the low-order 4 bits of timer 1 reload register R1. Transfers the contents of register B to the high-order 4 bits of timer 3 reload register R3, and transfers the contents of register A to the low-order 4 bits of timer 3 reload register R3. Transfers the contents of timer 4 reload register R4L to timer 4. Transfers the contents of register A to timer LC and timer LC reload register RLC.

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.3.00 Aug 06, 2004 page 122 of 136 REJ03B0043-0300Z 2 = 0: (T1F) = 1 ? After skipping, (T1F) ← 0 V12 = 1: NOP After skipping, (T2F) ← 0 V13 = 1: NOP After skipping, (T3F) ← 0 V20 = 1: NOP After skipping, (T4F) ← 0 V23 = 1: NOP After skipping, (T5F) ← 0 V21 = 1: NOP (A) ← (P0) (P0) ← (A) (A) ← (P1) (P1) ← (A) (A) ← (P2) (A) ← (P3) (D) ← 1 (D(Y)) ← 0 (Y) = 0 to 9 (D(Y)) ← 1 (Y) = 0 to 9 (D(Y)) = 0 ? (Y) = 0 to 7 (C) ← 0 (C) ← 1 (A) ← (PU0) (PU0) ← (A) (A) ← (PU1) (PU1) ← (A) Input/Output operation Timer operation

Skip condition Datailed description Carry flag CY Rev.3.00 Aug 06, 2004 page 123 of 136 REJ03B0043-0300Z Skips the next instruction when the contents of bit 2 (V12) of interrupt control register V1 is “0” and the con- tents of T1F flag is “1.” After skipping, clears (0) to T1F flag. Skips the next instruction when the contents of bit 3 (V13) of interrupt control register V1 is “0” and the con- tents of T2F flag is “1.” After skipping, clears (0) to T2F flag. Skips the next instruction when the contents of bit 0 (V20) of interrupt control register V2 is “0” and the con- tents of T3F flag is “1.” After skipping, clears (0) to T3F flag. Skips the next instruction when the contents of bit 3 (V23) of interrupt control register V2 is “0” and the con- tents of T4F flag is “1.” After skipping, clears (0) to T4F flag. Skips the next instruction when the contents of bit 1 (V21) of interrupt control register V2 is “0” and the con- tents of T5F flag is “1.” After skipping, clears (0) to T5F flag. Transfers the input of port P0 to register A. Outputs the contents of register A to port P0. Transfers the input of port P1 to register A. Outputs the contents of register A to port P1. Transfers the input of port P2 to register A. Transfers the input of port P3 to register A. Sets (1) to all port D. Clears (0) to a bit of port D specified by register Y. Sets (1) to a bit of port D specified by register Y. Skips the next instruction when a bit of port D specified by register Y is “0.” Executes the next instruction when a bit of port D specified by register Y is “1.” Clears (0) to port C. Sets (1) to port C. Transfers the contents of pull-up control register PU0 to register A. Transfers the contents of register A to pull-up control register PU0. Transfers the contents of pull-up control register PU1 to register A. Transfers the contents of register A to pull-up control register PU1. 2 = 0: (T1F) = 1 V13 = 0: (T2F) =1 V20 = 0: (T3F) = 1 V23 = 0: (T4F) =1 V21 = 0: (T5F) =1 (D(Y)) = 0 However, (Y)=0 to 7

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.3.00 Aug 06, 2004 page 124 of 136 REJ03B0043-0300Z RBK* SBK* SVDE 256 21B 259 214 25A 215 228 229 22A 24A 20A 20B 20C 29A 29B 252 216 000 002 008 05B 003 2A0 29C 040 041 293 1001010110 1000011011 1001011001 1000010100 1001011010 1000010101 1000101000 1000101001 1000101010 1001001010 1000001010 1000001011 1000001100 1010011010 1010011011 1001010010 1000010110 0000000000 0000000010 0000001000 0001011011 0000000011 1010100000 1010011100 0001000000 0001000001 1010010011 Input/Output operation (A) ← (K0) (K0) ← (A) (A) ← (K1) (K1) ← (A) (A) ← (K2) (K2) ← (A) (FR0) ← (A) (FR1) ← (A) (FR2) ← (A) (A) ← (L1) (L1) ← (A) (L2) ← (A) (L3) ← (A) Ceramic resonator selected RC oscillator selected (A) ← (MR) (MR) ← (A) (PC) ← (PC) + 1 Transition to clock operating mode Transition to RAM back-up mode POF, POF2 instructions valid (P) = 1 ? (WDF1) = 1 ? After skipping, (WDF1) ← 0 Stop of watchdog timer function enabled When TABP p instruction is executed, P 6 ← 0 When TABP p instruction is executed, P6 ← 1 At power down mode, voltage drop detection circuit valid MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) LCD operation Clock operation Other operation Note: * (SBK, RBK) cannot be used in the M34554M8. The pages which can be referred by the TABP instruction after the SBK instruction is executed are 64 to 95 in the M34554MC.

Skip condition Datailed description Carry flag CY Rev.3.00 Aug 06, 2004 page 125 of 136 REJ03B0043-0300Z (P) = 1 (WDF1) = 1 Transfers the contents of key-on wakeup control register K0 to register A. Transfers the contents of register A to key-on wakeup control register K0. Transfers the contents of key-on wakeup control register K1 to register A. Transfers the contents of register A to key-on wakeup control register K1. Transfers the contents of key-on wakeup control register K2 to register A. Transfers the contents of register A to key-on wakeup control register K2. Transferts the contents of register A to port output format control register FR0. Transferts the contents of register A to port output format control register FR1. Transferts the contents of register A to port output format control register FR2. Transfers the contents of LCD control register L1 to register A. Transfers the contents of register A to LCD control register L1. Transfers the contents of register A to LCD control register L2. Transfers the contents of register A to LCD control register L3. Selects the ceramic resonator for main clock, stops the on-chip oscillator (internal oscillator). Selects the RC oscillation circuit for main clock, stops the on-chip oscillator (internal oscillator). Transfers the contents of clock control regiser MR to register A. Transfers the contents of register A to clock control register MR. No operation; Adds 1 to program counter value, and others remain unchanged. Puts the system in clock operating mode by executing the POF instruction after executing the EPOF instruction. Puts the system in RAM back-up state by executing the POF2 instruction after executing the EPOF instruction. Makes the immediate after POF or POF2 instruction valid by executing the EPOF instruction. Skips the next instruction when the P flag is “1”. After skipping, the P flag remains unchanged. Skips the next instruction when watchdog timer flag WDF1 is “1.” After skipping, clears (0) to the WDF1 flag. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction. Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction. Sets referring data area to pages 0 to 63 when the TABP p instruction is executed. This instruction is valid only for the TABP p instruction. Sets referring data area to pages 64 to 127 when the TABP p instruction is executed. This instruction is valid only for the TABP p instruction. Validates the voltage drop detection circuit at power down (clock operating mode and RAM back-up mode) when VDCE pin is “H ”.

Rev.3.00 Aug 06, 2004 page 126 of 136 REJ03B0043-0300Z D 3–D 0 Hex. notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A B C D E F D 9–D 4 NOP POF SNZP DI EI RC SC POF2 AM AMC TYA TBA 000001 BLA CLD INY RD SD DEY AND OR TEAB CMA RAR TAB TAY 000010 SZB SZB SZB SZB SZD SEAn SEAM TDA TABE SZC 000011 BMLA SNZ0 SNZ1 SNZI0 SNZI1 TV2A TV1A 000100 RBK SBK RT RTS RTI LZ LZ LZ LZ RB RB RB RB 000101 TASP TAD TAX TAZ TAV1 TAV2 EPOF SB SB SB SB 000110 A A A A A A A A A A A A A A A A 000111 LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA 001000 TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP 001001 TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP 001010 TABP 32* TABP 33* TABP 34* TABP 35* TABP 36* TABP 37* TABP 38* TABP 39* TABP 40* TABP 41* TABP 42* TABP 43* TABP 44* TABP 45* TABP 46* TABP 47* 001011001100 001101 001110 001111 BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM 010000 010111 011000 011111 18–1F B B B B B B B B B B B B B B B B BL BML BLA BMLA SEA SZD The second word 1p paaa aaaa 1p paaa aaaa 1p pp00 pppp 1p pp00 pppp 00 0111 nnnn 00 0010 1011

• ** (SBK and RBK instructions) cannot be used in the M34554M8.
• * cannot be used after the SBK instruction is executed in the M34554MC.
• A page referred by the TABP instruction can be switched by the SBK and RBK instructions in the M34554MC/ED.
• The pages which can be referred by the TABP instruction after the SBK instruction is executed are 64 to 95 in the M34554MC.
• The pages which can be referred by the TABP instruction after the SBK instruction is executed are 64 to 127 in the M34554ED. (Ex. TABP 0 → TABP 64) The pages which can be referred by the TABP instruction after the RBK instruction is executed are 0 to 63.
• When the SBK instruction is not used, the pages which can be referred by the TABP instruction are 0 to 63. 10–17 000000 The above table shows the relationship between machine language codes and machine language instructions. D3–D 0 show the low-order 4 bits of the machine language code, and D9–D 4 show the high-order 6 bits of the machine language code. The hexadecimal representa- tion of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below. TABP 48* TABP 49* TABP 50* TABP 51* TABP 52* TABP 53* TABP 54* TABP 55* TABP 56* TABP 57* TABP 58* TABP 59* TABP 60* TABP 61* TABP 62* TABP 63*

Rev.3.00 Aug 06, 2004 page 127 of 136 REJ03B0043-0300Z INSTRUCTION CODE TABLE (continued) TL1A TL2A TL3A TLCA TW1A TW2A TW3A TW4A TW5A TW6A TK1A TK2A TMRA TI1A TI2A TK0A T1AB T2AB T3AB T4AB TPSAB T4HAB TR3AB TR1AB TAL1 TAW1 TAW2 TAW3 TAW4 TAW5 TAW6 TAMR TAI1 TAI2 TAK0 TAPU0 TAK1 TAK2 TAPU1 IAP0 IAP1 IAP2 IAP3 TAB1 TAB2 TAB3 TAB4 TABPS SNZT1 SNZT2 SNZT3 SNZT4 SNZT5 RCP SCP SVDE T4R4L CMCK CRCK DWDT WRST TPAA TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA BL BML BLA BMLA SEA SZD The second word 1p paaa aaaa 1p paaa aaaa 1p pp00 pppp 1p pp00 pppp 00 0111 nnnn 00 0010 1011 OP0A OP1A TFR0A TFR1A TFR2A TPU0A TPU1A D 3–D 0 Hex. notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A B C D E F D 9–D 4 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 111111 30–3F 100000 The above table shows the relationship between machine language codes and machine language instructions. D3–D 0 show the low- order 4 bits of the machine language code, and D9–D 4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below.

Rev.3.00 Aug 06, 2004 page 128 of 136 REJ03B0043-0300Z Input voltage P0, P1, P2, P3, D0–D 7, RESET , XIN, XCIN, VDCE Input voltage CNTR0, CNTR1, INT0, INT1 Output voltage P0, P1, D0–D 9, RESET , CNTR0, CNTR1 Output voltage C, XOUT , XCOUT Output voltage SEG0–SEG 31, COM 0–COM 3 Power dissipation Operating temperature range Storage temperature range Conditions Output transistors in cut-off state Ta = 25 °C Symbol V DD VI VI VO VO VO Pd Topr Tstg Unit V V V V V V mW Ratings –0.3 to 6.5 –0.3 to VDD +0.3 –0.3 to VDD +0.3 –0.3 to VDD +0.3 –0.3 to VDD +0.3 –0.3 to VDD +0.3 300 –20 to 85 –40 to 125 ABSOLUTE MAXIMUM RATINGS

Rev.3.00 Aug 06, 2004 page 129 of 136 REJ03B0043-0300Z RECOMMENDED OPERATING CONDITIONS 1 (Mask ROM version: Ta = –20 °C to 85 °C, VDD = 2 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted) Symbol VDD VDD VRAM VSS VLC3 VIH VIH VIH VIH VIL VIL VIL VIL IOH (peak) IOH (peak) IOH (avg) IOH (avg) IOL (peak) IOL (peak) IOL (peak) IOL (avg) IOL (avg) IOL (avg) ΣIOH (avg) ΣIOL (avg) Parameter Supply voltage (when ceramic resonator is used) Supply voltage (when RC oscillation is used) RAM back-up voltage Supply voltage LCD power supply (Note 1) “H ” level input voltage “H ” level input voltage “H ” level input voltage “H ” level input voltage “L” level input voltage “L” level input voltage “L” level input voltage “L” level input voltage “H ” level peak output current “H ” level peak output current “H ” level average output current (Note 2) “H ” level average output current (Note 2) “L” level peak output current “L” level peak output current “L” level peak output current “L” level average output current (Note 2) “L” level average output current (Note 2) “L” level average output current (Note 2) “H ” level total average current “L” level total average current Notes 1: At 1/2 bias: VLC1 = VLC2 = (1/2)•VLC3 At 1/3 bias: VLC1 = (1/3)•VLC3, VLC2 = (2/3)•VLC3 2: The average output current is the average value during 100 ms. UnitConditions Mask ROM version One Time PROM version f(STCK) ≤ 4.4 MHz at RAM back-up mode Mask ROM version One Time PROM version P0, P1, P2, P3, D 0–D 7, VDCE XIN, XCIN RESET CNTR0, CNTR1, INT0, INT1 P0, P1, P2, P3, D0–D 7, VDCE XIN, XCIN RESET CNTR0, CNTR1, INT0, INT1 P0, P1, D 0–D 6 D 7, C CNTR0, CNTR1 P0, P1, D0–D 6 D 7, C CNTR0, CNTR1 P0, P1 D 0–D 6, C CNTR0, CNTR1 RESET P0, P1 D 0–D 6, C CNTR0, CNTR1 RESET P0, P1, D0–D 6 D 7, C, CNTR0, CNTR1 P0, P1, D0–D 6 D 7–D 9, C, RESET , CNTR0, CNTR1 Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 V DD VDD VDD VDD VDD VDD 0.2VDD 0.3VDD 0.3VDD 0.15VDD –20 –10 –30 –15 –10 –20 –10 –60 –60 Limits Min. 2.7 2.7 2.5 2.7 1.8 2.5 0.8V DD 0.7VDD 0.85VDD 0.8VDD Typ. f(STCK) ≤ 6 MHz f(STCK) ≤ 4.4 MHz f(STCK) ≤ 2.2 MHz f(STCK) ≤ 6 MHz f(STCK) ≤ 4.4 MHz f(STCK) ≤ 2.2 MHz VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V V V V V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA

Rev.3.00 Aug 06, 2004 page 130 of 136 REJ03B0043-0300Z f(XIN) f(XIN) f(XIN) f(XCIN) f(CNTR) tw(CNTR) TPON Oscillation frequency (with a ceramic resonator) Oscillation frequency (at RC oscillation) (Note) Oscillation frequency (with a ceramic resonator selected, external clock input) Oscillation frequency (sub-clock) Timer external input frequency Timer external input period (“H ” and “L” pulse width) Power-on reset circuit valid supply voltage rising time Conditions MHz MHz MHz kHz Hz s µs Max. 4.4 2.2 4.4 4.4 2.2 4.4 4.4 4.8 3.2 1.6 4.8 3.2 4.8 4.8 3.2 1.6 4.8 3.2 4.8 f(STCK)/6 100 100 Limits Mask ROM version One Time PROM version VDD = 2.7 to 5.5 V Mask ROM version One Time PROM version Quartz-crystal oscillator CNTR0, CNTR1 CNTR0, CNTR1 Mask ROM version One Time PROM version Min. 3/f(STCK) Typ. RECOMMENDED OPERATING CONDITIONS 2 (Mask ROM version: Ta = –20 °C to 85 °C, VDD = 2 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted) ParameterSymbol Unit Note: The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits. VDD = 4 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2 to 5.5 V VDD = 2 to 5.5 V VDD = 4 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.5 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.5 to 5.5 V VDD = 2.5 to 5.5 V VDD = 4 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2 to 5.5 V VDD = 2 to 5.5 V VDD = 4 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.5 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.5 to 5.5 V VDD = 2.5 to 5.5 V VDD = 0 → 2 V VDD = 0 → 2.5 V Through mode Frequency/2 mode Frequency/4, 8 mode Through mode Frequency/2 mode Frequency/4, 8 mode Through mode Frequency/2 mode Frequency/4, 8 mode Through mode Frequency/2 mode Frequency/4, 8 mode 4.4 2.2 f(STCK) [MHz] (2.5) 2.7 5.5 4 VV VDD [V] ➀ When ceramic resonator is used. <System clock (STCK) Operating condition map> Recommended operating condition 4.4 2.7 5.5 DD [V] ➁ When RC oscillation is used. f(STCK) [MHz] 3.2 1.6 (2.5) 2.7 5.5 4 DD [V] ➂ When external clock is used. 4.8 f(STCK) [MHz] Recommended operating condition Recommended operating condition

Rev.3.00 Aug 06, 2004 page 131 of 136 REJ03B0043-0300Z ELECTRICAL CHARACTERISTICS 1 (Mask ROM version: Ta = –20 °C to 85 °C, VDD = 2 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted) VOH VOH VOL VOL VOL IIH IIL “H ” level output voltage P0, P1, D0–D 6 “H ” level output voltage D 7, C, CNTR0, CNTR1 “L” level output voltage P0, P1 “L” level output voltage D 0–D 9, C, CNTR0, CNTR1 “L” level output voltage RESET “H ” level input current P0, P1, P2, P3, D0–D 7, VDCE, RESET CNTR0, CNTR1, INT0, INT1 “L” level input current P0, P1, P2, P3, D0–D 7, VDCE, CNTR0, CNTR1, INT0, INT1 V V V V V µA µA Test conditions VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VI = VDD VI = 0 V P0, P1 No pull-up Limits Max. 0.9 0.9 0.6 0.9 1.4 0.9 0.6 0.9 IOH = –10 mA IOH = –3 mA IOH = –5 mA IOH = –1 mA IOH = –20 mA IOH = –6 mA IOH = –10 mA IOH = –3 mA IOL = 12 mA IOL = 4 mA IOL = 6 mA IOL = 2 mA IOL = 15 mA IOL = 5 mA IOL = 9 mA IOL = 3 mA IOL = 5 mA IOL = 1 mA IOL = 2 mA Min. 4.1 2.1 2.4 4.1 2.1 2.4 Typ. Symbol Parameter Unit

Rev.3.00 Aug 06, 2004 page 132 of 136 REJ03B0043-0300Z ELECTRICAL CHARACTERISTICS 2 (Mask ROM version: Ta = –20 °C to 85 °C, VDD = 2 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted) IDD R PU VT+ – VT– VT+ – VT– f(RING) ∆ f(XIN) RCOM RSEG RVLC Supply current Pull-up resistor value P0, P1, RESET Hysteresis CNTR0, CNTR1, INT0, INT1 Hysteresis RESET On-chip oscillator clock frequency Frequency error (with RC oscillation, error of external R, C not included ) (Note) COM output impedance SEG output impedance Internal resistor for LCD power supply at active mode (with a ceramic resonator) at active mode (with a quartz-crystal oscillator) at clock operation mode (POF instruction execution) at RAM back-up mode (POF2 instruction execution) mA mA mA µA µA µA µA kΩ V V MHz kΩ kΩ kΩ Test conditions VDD = 5 V f(XIN) = 6 MHz f(XCIN) = 32 kHz VDD = 5 V f(XIN) = 4 MHz f(XCIN) = 32 kHz VDD = 3 V f(XIN) = 4 MHz f(XCIN) = 32 kHz VDD = 5 V f(XIN) = stop f(XCIN) = 32 kHz VDD = 3 V f(XIN) = stop f(XCIN) = 32 kHz f(XCIN) = 32 kHz Ta = 25 °C VDD = 5 V VDD = 3 V VI = 0 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V ± 10 %, Ta = 25 °C VDD = 5 V ± 10 %, Ta = 25 °C VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V When dividing resistor 2r ✕ 3 selected When dividing resistor 2r ✕ 2 selected When dividing resistor r ✕ 3 selected When dividing resistor r ✕ 2 selected Limits Max. 2.8 3.2 5.6 2.2 2.4 0.8 1.2 1.6 110 120 130 140 125 250 1.8 ±17 ±17 7.5 7.5 960 640 480 320 Min. 0.5 300 200 150 100 Typ. 1.4 1.6 2.8 1.1 1.2 1.5 0.4 0.5 0.6 0.8 0.1 120 0.2 0.2 0.4 1.5 1.5 480 320 240 160 Symbol Parameter Unit Note: When RC oscillation is used, use the external 33 pF capacitor (C). f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V

Rev.3.00 Aug 06, 2004 page 133 of 136 REJ03B0043-0300Z VOLTAGE DROP DETECTION CIRCUIT CHARACTERISTICS (Ta = –20 °C to 85 °C, unless otherwise noted) Test conditions Ta = 25 °C at power down V DD = 5 V (Note 2) V DD = 3 V VDD → (VRST–0.1 V) (Note 3) Parameter Detection voltage (Note 1) Operation current Detection time Symbol VRST IRST TRST Limits UnitMin. 1.4 1.1 Typ. 1.5 0.2 Max. 1.6 1.9 100 1.2 V µA ms Notes 1: The detected voltage (VRST ) is defined as the voltage when reset occurs when the supply voltage (VDD ) is falling. 2: After the SVDE instruction is executed, the voltage drop detectin circuit is valid at power down mode. 3: The detection time (T RST ) is defined as the time until reset occurs when the supply voltage (VDD ) is falling to [VRST –0.1 V]. STCK P a r a m e t e r P i n ( s i g n a l ) n a m e M a c h i n e c y c l e M iM i + 1 D 0– D 9 System clock Port D output Port D input Ports P0, P1 output P o r t s P 0 , P 1 , P 2 , P 3 i n p u t D 0– D 7 I N T 0 , I N T 1I n t e r r u p t i n p u t P00–P03 P10–P13 P 00– P 03 P10–P13 P20–P23 P 30– P 33

Rev.3.00 Aug 06, 2004 page 134 of 136 REJ03B0043-0300Z Table 25 Product of built-in PROM version PROM size (✕ 10 bits) 16384 words RAM size (✕ 4 bits) 512 wordsM34554EDFP One Time PROM [shipped in blank]64P6N-A BUILT-IN PROM VERSION In addition to the mask ROM versions, the 4554 Group has the One Time PROM versions whose PROMs can only be written to and not be erased. The built-in PROM version has functions similar to those of the mask ROM versions, but it has PROM mode that enables writing to built-in PROM. Table 25 shows the product of built-in PROM version. Figure 61 shows the pin configurations of built-in PROM versions. The One Time PROM version has pin-compatibility with the mask ROM version. ROM typePackagePart number Fig. 61 Pin configuration of built-in PROM version PIN CONFIGURATION (TOP VIEW) SEG 0/VLC3 SEG 1/VLC2 SEG 2/VLC1 SEG 3 SEG 4 SEG 5 SEG 6 M34554EDFPSEG 7 SEG 8 SEG 9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 D 4 D 5 D 6 CNV SS VDCE XCIN XCOUT VDD VSS XOUT XIN RESET D 7/CNTR0 C/CNTR1 D 8/INT0 D 9/INT1 COM 0 COM 1 COM 2 COM 3 P00 P01 P02 P03 P10 P11 P12 P13 D 0 D 1 D 2 D 3 SEG 16 SEG 17 SEG 18 SEG 19 SEG 20 SEG 21 SEG 22 SEG 23 SEG 24/P33 SEG 25/P32 SEG 26/P31 SEG 27/P30 SEG 28/P23 SEG 29/P22 SEG 30/P21 SEG 31/P20 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6

Rev.3.00 Aug 06, 2004 page 135 of 136 REJ03B0043-0300Z (1) PROM mode The built-in PROM version has a PROM mode in addition to a nor- mal operation mode. The PROM mode is used to write to and read from the built-in PROM. In the PROM mode, the programming adapter can be used with a general-purpose PROM programmer to write to or read from the built-in PROM as if it were M5M27C256K. Programming adapter is listed in Table 26. Contact addresses at the end of this data sheet for the appropriate PROM programmer.

• Writing and reading of built-in PROM Programming voltage is 12.5 V. Write the program in the PROM of the built-in PROM version as shown in Figure 62. (2) Notes on handling ➀ A high-voltage is used for writing. Take care that overvoltage is not applied. Take care especially at turning on the power. ➁ For the One Time PROM version shipped in blank, Renesas Technology corp. does not perform PROM writing test and screening in the assembly process and following processes. In order to improve reliability after writing, performing writing and test according to the flow shown in Figure 63 before using is rec- ommended (Products shipped in blank: PROM contents is not written in factory when shipped). (3) Difference between Mask ROM version and One Time PROM version Mask ROM version and One Time PROM version have some differ- ence of the following characteristics within the limits of an electrical property by difference of a manufacture process, built-in ROM, and a layout pattern.
• a characteristic value
• a margin of operation
• the amount of noise-proof
• noise radiation, etc., Accordingly, be careful of them when swithcing. Fig. 62 PROM memory map Fig. 63 Flow of writing and test of the product shipped in blank Part number M34554EDFP Name of Programming Adapter PCA7448 Table 26 Programming adapter A d d r e s s 3FFF 16 7FFF 16 1 11 D 4 D 3 D 2 D 1 D 0 H i g h - o r d e r 5 b i t s 1 11 D 4 D 3 D 2 D 1 D 0 L o w - o r d e r 5 b i t s 400016 Writing with PROM programmer S c r e e n i n g ( L e a v e a t 1 5 0 ° C f o r 4 0 h o u r s ) (N o t e) V e r i f y t e s t w i t h P R O M p r o g r a m m e r Function test in target device Since the screening temperature is higher than storage temperature, never expose the microcomputer to 150 °C exceeding 100 hours. N o t e :

Rev.3.00 Aug 06, 2004 page 136 of 136 REJ03B0043-0300Z QFP64-P-1414-0.80 1.11 Weight(g) JEDEC CodeEIAJ Package Code Lead Material Alloy 42 64P6N-A Plastic 64pin 14✕ 14mm body QFP Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D A1 0.20.1 0.5 ——I2 1.3 ——M D 14.6 ——M E 14.6 10¡0¡ 0.1 1.4 0.80.60.4 17.116.816.5 17.116.816.5 0.8 14.214.013.8 14.214.013.8 0.20.150.13 0.450.350.3 2.8 3.05 e e e E c H E 64 49 H D D M D M E A F b A1 A2 L y Recommended Mount Pad Detail F PACKAGE OUTLINE

REVISION HISTORY

Rev. Date Description Page Summary

4554 Group Data Sheet

1.00 Nov. 27, 2001 First edition issued – 2.00 Jul. 01, 2003 2.01 Sep.18, 2003 “Preliminary Notice: This is not a final specification. Some parametric limits are subject to change.” eliminated. Note on voltage drop detection circuit added. Table 15 Port level revised. Note on voltage drop detection circuit added. All pages 3.00 Aug. 06, 2004All pages Words standardized: On-chip oscillator 4 Power dissipation: “Ta=25°C” added. Description of RESET pin revised. 29 Fig.20: Some description added. 30 Fig.23: Some description added. 34 Fig.26 : Note 9 added. 44 Some description revised. 45 Fig.31 : “DI” instruction added. 50 (5) LCD power supply circuit revised. 53 Fig.40 : State of quartz-crystal oscillator added. 57 Fig.44 : Note 5 added. 64 Fig.56: Some description added. 65 Fig.57: Some description added. 66 Note on Power Source Voltage added.

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