NCP45495 ONSEMI | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 19
Technical content
Features
- Translates and Scales Shunt and Bus V oltages up to 26 V
- Single Device Monitors Four Supplies
- May Be Paired for Monitoring Up To Eight Supplies
- Very Low Powerdown Current
- All Channels Individually Gain Programmable via I2C Interface
- Fast Settling Time
- Real−Time Bus V oltages Valid Signal
- Adjustable Output Common−Mode V oltage
- RoHS/REACH Compliant Device
Applications
- Computers / Notebooks / Graphics Cards
- Power Management / Power Control Loops
- Battery Chargers (Top View) QFN32 4x4 CASE 485CD 45495 = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week /C0071 = Pb−Free Package 45495 ALYW /C0071 MARKING DIAGRAM Device Package Shipping †
ORDERING INFORMATION
(Green) 4000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. PIN CONFIGURATION 33:GND IN_N1 IN_P1 BV_IN1 IN_N2 IN_P2 BV_IN2 IMON_IN1 IMON_IN2 SDA SCL ADRS[1] ADRS[0] DIFF_OUT_P DIFF_OUT_N BV_REF BG_REF_OUT RGND NC BV_IN3 IN_P3 IN_N3 BV_IN4 IN_P4 IN_N4 NC SYNC BV_OK MUX_SEL EN_B VCC NC SKIP
Figure 1. Block Diagram Table 1. PIN DESCRIPTION
9 RGND GND Reference Ground for multiplexer and differential amplifier
17 BG_REF_OUT AO Buffered Bandgap Voltage Output
18 BV_REF AI BV_OK comparator threshold reference
19 DIFF_OUT_N AO Differential Output, Negative
20 DIFF_OUT_P AO Differential Output, Positive
23 SCL DI I2C Clock
24 SDA DI/DO I2C Data Signal
27 VCC PWR Device Power
28 EN_B DI Device Enable. When high, places device in low−power state.
29 MUX_SEL DI Multiplexer Select Input
30 BV_OK DO Bus OK output (open−drain; high impedance = BUS OK)
31 SYNC DO Sync pin outputs a pulse at the beginning of every MUX_SEL sequence
33 GND GND Device Ground
Table 2. MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected. Table 3. ESD RATINGS
- Tested by the following methods @ T A = 25°C
Table 4. RECOMMENDED OPERATING RANGES the Recommended Operating Ranges limits may affect device reliability.
Table 5. ELECTRICAL CHARACTERISTICS VIN_PX = 15 V, VEN_B = 0 V, Vcc = 3.3 V, unless indicated otherwise. Min and Max performance may not be indicated by the Electrical Characteristics if operated under different conditions.
- BV_OK should be connected to a pull up resistor of value 10 K /C0087 or greater.
- Vcc detection for BV_OK must trip in this range. Device can be either Full Function or Limited Function mode in this range
- Shunt Monitor Offset Voltage and Offset Voltage Drift are referred to the IN_Px and IN_Nx pins.
- Differential Amplifier Input Offset Voltage is referred to the multiplexer input pins
10.Specifications for VBUS current draw are only applicable when VCC = 2.8 V to 3.8 V.
- 3−sigma variation specification
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
- BV_OK should be connected to a pull up resistor of value 10 K /C0087 or greater.
- Vcc detection for BV_OK must trip in this range. Device can be either Full Function or Limited Function mode in this range
- Shunt Monitor Offset Voltage and Offset Voltage Drift are referred to the IN_Px and IN_Nx pins.
- Differential Amplifier Input Offset Voltage is referred to the multiplexer input pins
10.Specifications for VBUS current draw are only applicable when VCC = 2.8 V to 3.8 V.
- 3−sigma variation specification
register set the differential amplifier common mode voltage. internal resistor R SC2 to create the internal shunt voltage. The resulting voltage is fed into the multiplexer for readout. The table below shows the available shunt gain settings. Table 6. SHUNT CURRENT PROGRAMMABLE GAIN
divided by the VBUS attenuation. Table 7. VBUS PROGRAMMABLE ATTENUATION represents the voltage on the IMON_INx pin. before the cycle will repeat. must match between the 2 devices. function with all VBUS channels considered active. be tied to used VBUS inputs.
Table 9. REGISTER MAP
5 R/W Enable iMon Channel 2 0 At next
4 R/W Enable iMon Channel 1 0 At next
3 R/W Enable Channel 4 1 At next
2 R/W Enable Channel 3 1 At next
1 R/W Enable Channel 2 1 At next
0 R/W Enable Channel 1 1 At next
0 At next
0 Immediately
0 R/W Lock I2C interface reads / writes 0 Immediately
Figure 13. Six−Channel Paired Device Signal Characteristics with 6 Channels Activated enabled in paired mode. The register settings for each device are shown below.
www.onsemi.com Clock Cycle Diff Output (Device A) Diff Output (Device B)
0 High Z High Z
1 Ch 1 Bus Voltage High Z
2 Ch 1 Shunt Current High Z
3 Ch 2 Bus Voltage High Z
4 Ch 2 Shunt Current High Z
5 Ch 3 Bus Voltage High Z
6 Ch 3 Shunt Current High Z
7 Ch 4 Bus Voltage High Z
8 Ch 4 Shunt Current High Z
11 Ref GND High Z
12 High Z Ch 1 Bus Voltage
13 High Z Ch 1 Shunt Current
14 High Z Ch 2 Bus Voltage
15 High Z Ch 2 Shunt Current
16 High Z Ch 3 Bus Voltage
17 High Z Ch 3 Shunt Current
18 High Z Ch 4 Bus Voltage
19 High Z Ch 4 Shunt Current
20 High Z iMon1
21 High Z iMon2
22 High Z Ref GND
23 Ch 1 Bus Voltage Reversed High Z
24 Ch 1 Shunt Current Reversed High Z
25 Ch 2 Bus Voltage Reversed High Z
26 Ch 2 Shunt Current Reversed High Z
27 Ch 3 Bus Voltage Reversed High Z
28 Ch 3 Shunt Current Reversed High Z
29 Ch 4 Bus Voltage Reversed High Z
30 Ch 4 Shunt Current Reversed High Z
33 Ref GND Reversed High Z
34 High Z Ch 1 Bus Voltage Reversed
35 High Z Ch 1 Shunt Current Reversed
36 High Z Ch 2 Bus Voltage Reversed
37 High Z Ch 2 Shunt Current Reversed
38 High Z Ch 3 Bus Voltage Reversed
39 High Z Ch 3 Shunt Current Reversed
40 High Z Ch 4 Bus Voltage Reversed
41 High Z Ch 4 Shunt Current Reversed
42 High Z iMon1 Reversed
43 High Z iMon2 Reversed
44 High Z Ref GND Reversed
45 Ch 1 Bus Voltage High Z
www.onsemi.com AUXILIARY FUNCTIONS Bus Comparator (BV_OK): The BV_OK pin provides a real−time indication that V CC and all bus voltages (as measured on the BV_INx pins) are valid. BV_OK remains low until all used BV_INx pins are above a user −defined threshold voltage. The BV_OK threshold is set by an external resistor divider on the BV_REF pin. The internal BV_OK comparator has built in hysteresis of 10% to prevent chatter as voltage busses come up. All channels specified in the ACTIVE_CHAN register will be represented. If desired, the user can use the SKIP pin to modify the logic as shown in the corresponding table (H = high, L = low, Z = tristate, X = don’t care). The SKIP pin can also be used to hold BV_OK = L in the absence of V CC. VCC EN_B VB_INx SKIP BV_OK Notes LL X L open drain No Power Provided to Part LL X H L SKIP Pin Provides Power Needed to Hold BV_OK Low HH X L open drain Standby Mode HH X H L Standby Mode H Z/L L H L Functional or Limited Mode H Z/L H H open drain Functional or Limited Mode H Z/L X L open drain Functional or Limited Mode Reset/Timeout: If the timeout is enabled, holding the MUX_SEL pin HIGH or LOW linger then 45 /C0109s will reset to the beginning of the MUX_SEL sequence. If the timeout has been disabled, then the MUX_SEL must cycle through all set channels to return to the beginning of the sequence. Toggling the EN_B pin will also reset the sequence back to the beginning. Bandgap Reference: The BG_REF_OUT pin provides a high−accuracy voltage that can be used to generate the BV_REF voltage for the BV_OK comparators. Enable Function: The EN_B pin controls device operation according to the corresponding table. EN_B LOGIC Level Device Operation LOW Fully Functional Tri−state (floating) Limited Function: BG_REF_OUT is valid, BV_OK comparators and output are functional. All other functions to be disabled. DIFF_OUT to be Hi−Z and multiplexer select logic is held in reset. HIGH Standby: Power down state. Nothing is active. Input Filtering: If additional filtering is needed on the input bus lines, external filtering can be added as shown below. R VBUS1 RSENSE RF RF CF BV_IN1 IN_P1 IN_N1 Mismatch between the 2 RF values will contribute to the overall measurement offset error. To avoid this, the tolerance of external R F resistors should be < 1%. External RF values should not exceed 20 k/C0087. Layout Considerations Sensitive signals that require special attention in board layout include the channel inputs (IN_N, IN_P, and BV_IN signals), the differential output signals, and the MUX_SEL signal. The IN_N and IN_P signals require a direct kelvin connection to the leads of the sense resistor to avoid parasitic trace resistance affecting the shunt current measurement. This direct connection is shown below. The sense resistors and connections from source to load for each channel need to be large enough to accommodate the expected high load currents.
www.onsemi.com Top down view of PCB IN_N1 IN_P1 BV_IN1 IN_N2 IN_P2 BV_IN2 IMON_IN1 IMON_IN2 RGND NC BV_IN3 IN_P3 IN_N3 BV_IN4 IN_P4 BG_OUT BV_REF DIFF_OUTN DIFF_OUTP ADRS[0] ADRS[1] SCL SDA NC SYNC BV_OK MUX_SEL EN_B VCC SKIP NC IN_N4 VBUS To L O A DRsense >= 6mil >= 6mil >= 6mil Width based on expected load current Matched length and width Channel 1 (Repeat circuit for each channel) Optional Input Filter Not Shown For Clarity Imon1 input voltage Imon1 input voltage To GND Connect back paddle to GND R3 R4 To GND Tie to GND or VCC to set Address 0 Bit I2C Clock Input I2C Data Signal Anti-Aliasing Filter To ADC Keep Differential Pair close together and matched Tie to GND or VCC to set Address 1 Bit Tie to VCC, GND, or Float To 3.3V Supply Enable Bar Input Keep MUX_SEL isolated from other dynamic signalsSYNC Output GND Width based on expected load current Care should be taken to keep DIFF_OUT_P and DIFF_OUT_N matched. As a differential pair, any noise introduced to the pair will be common and will be rejected if the signals are close together and matched in length. Care should be taken to keep the MUX_SEL line isolated from other dynamically changing signals. Unused Channels Unused channels should be disabled by setting Register 0x04 over I 2C. The IN_P and IN_N pins for an unused channel should have the same connection. The following table details the recommended connections for unused pins. Unused Pins Connection BV_INx Connect to BV_IN pin of a previous channel or GND IN_Px Connect to the same potential as BV_INx or Float IN_Nx IMONx Float or GND SYNC Float
QFN32 4x4, 0.4P CASE 485CD ISSUE A DATE 09 OCT 2012SCALE 2:1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP . 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ AD E B C0.10 PIN ONE REFERENCE TOP VIEW SIDE VIEW BOTTOM VIEW A KD2 C C0.10 C0.05 C0.05 A1 SEATING PLANE e 32X NOTE 3 b32X C C A B DIM MIN MAX MILLIMETERS A 0.80 1.00 A1 0.00 0.05 b 0.15 0.25 D 4.00 BSC D2 2.60 2.80 E 4.00 BSC E2 2.60 2.80 e 0.40 BSC L 0.25 0.45 32X 0.40 PITCH 4.30 0.58 4.30 DIMENSIONS: MILLIMETERS 0.25 32X L A3 0.20 REF MOUNTING FOOTPRINT NOTE 4 XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week /C0071 = Pb−Free Package GENERIC MARKING DIAGRAM* *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G”, may or not be present. XXXXXX XXXXXX ALYW/C0071 /C0071 (Note: Microdot may be in either location) DETAIL B 2.80 2.80 PACKAGE OUTLINE DETAIL A DETAIL A L ALTERNATE TERMINAL CONSTRUCTIONS L ÉÉÉÉ ÉÉ DETAIL B MOLD CMPDEXPOSED Cu ALTERNATE CONSTRUCTION L1 −−− 0.15 DETAIL C CORNER LEAD CONSTRUCTION DETAIL C
0.10 C A BB
M0.07 M0.05 K2 0.45 REF K 0.30 REF RECOMMENDED 8X C0.08 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 98AON66248EDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1QFN32 4X4, 0.4P © Semiconductor Components Industries, LLC, 2019 www.onsemi.com
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