4532M

SSM4532M SSC | Alldatasheet

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www.SiliconStandard.com 1 of 11 SSM4532M COMPLEMENTARY N AND P-CHANNEL ENHANCEMENT-MODE POWER MOSFETS Simple drive requirement N-ch BV DSS +30V Low on-resistance R DS(ON) 50mΩ Fast switching ID +5A P-ch BVDSS -30V RDS(ON) 70mΩ Description ID -4A Absolute Maximum Ratings Symbol Parameter Rating Units N-channel P-channel VDS Drain-Source Voltage +30 -30 V VGS Gate-Source Voltag ±20 ±20 V I D @ TA=25°C Continuous Drain Current3 +5 -4 A I D @ TA=70°C Continuous Drain Current3 +4 -3.2 A IDM Pulsed Drain Current1,4 +20 -20 A PD @ TA=25°C Total Power Dissipation 2.0 W Linear Derating Factor 0.016 W/°C TSTG Storage Temperature Range -55 to 150 °C TJ Operating Junction Temperature Range -55 to 150 °C Symbol Value Unit Rthj-amb Thermal Resistance Junction-ambient Max. 62.5 °C/W Parameter Thermal Data MOSFETs from Silicon Standard Corp. provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost- effectiveness. The SO-8 package is widely preferred for commercial and industrial surface mount applications and is well suited for low-voltage applications such as DC/DC converters. SO-8 Rev.2.01 7/01/2004

www.SiliconStandard.com 2 of 11 SSM4532M N-channel Electrical Characteristics @ Tj=25oC (unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Units BVDSS Drain-Source Breakdown Voltage VGS=0V, ID=250uA 30 - - V ΔBVDSS/ ΔTj Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=1mA - 0.037 -V/°C RDS(ON) Static Drain-Source On-Resistance VGS=10V, ID=5A - - 50 mΩ VGS=4.5V, ID=4.2A - - 70 mΩ VGS(th) Gate Threshold Voltage VDS=VGS, ID=250uA 1 - 3 V gfs Forward Transconductance VDS=10V, ID=5A - 8 - S IDSS Drain-Source Leakage Current (Tj=25oC) VDS=30V, VGS=0V - - 1 uA Drain-Source Leakage Current (Tj=55oC) VDS=24V, VGS=0V - - 25 uA IGSS Gate-Source Leakage VGS=±20V - - nA Qg Total Gate Charge2 ID=5A - 10.2 20 nC Qgs Gate-Source Charge VDS=10V - 1.2 - nC Qgd Gate-Drain ("Miller") Charge VGS=10V - 3.4 - nC td(on) Turn-on Delay Time2 VDS=10V - 6 12 ns tr Rise Time ID=1A - 9 18 ns td(off) Turn-off Delay Time RG=6Ω ,VGS=10V - 15 30 ns tf Fall Time RD=10Ω - 5.5 12 ns Ciss Input Capacitance VGS=0V - 240 360 pF Coss Output Capacitance VDS=25V - 145 210 pF Crss Reverse Transfer Capacitance f=1.0MHz - 55 80 pF Source-Drain Diode Symbol Parameter Test Conditions Min. Typ. Max. Units IS Continuous Source Current ( Body Diode ) VD=VG=0V , VS=1.2V - - 1.7 A ISM Pulsed Source Current ( Body Diode )1 --2 0 A VSD Forward On Voltage2 Tj=25°C, IS=1.7A, VGS=0V - 0.8 1.2 V Notes: 1.Pulse width limited by max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on FR4 board, t<10sec. 4.Pulse width <10us , duty cycle <1%. ±100 Rev.2.01 7/01/2004

www.SiliconStandard.com 3 of 11 SSM4532M P-channel Electrical Characteristics @ Tj=25oC (unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Units BVDSS Drain-Source Breakdown Voltage VGS=0V, ID=250uA -30 - - V ΔBVDSS/ΔTj Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=-1mA - -0.028 -V/°C RDS(ON) Static Drain-Source On-Resistance VGS=-10V, ID=-4A - - 70 mΩ VGS=-4.5V, ID=-3A - - 90 mΩ VGS(th) Gate Threshold Voltage VDS=VGS, ID=-250uA -1 - -3 V gfs Forward Transconductance VDS=-10V, ID=-4A - 5 - S IDSS Drain-Source Leakage Current (Tj=25oC) VDS=-30V, VGS=0V - - -1 uA Drain-Source Leakage Current (Tj=55oC) VDS=-24V, VGS=0V - - -25 uA IGSS Gate-Source Leakage VGS=- - nA Qg Total Gate Charge2 ID=-4A - 18.3 36 nC Qgs Gate-Source Charge VDS=-10V - 3.6 - nC Qgd Gate-Drain ("Miller") Charge VGS=-10V - 1.5 - nC td(on) Turn-on Delay Time2 VDS=-10V - 8 16 ns tr Rise Time ID=-1A - 9 18 ns td(off) Turn-off Delay Time R G=6Ω ,VGS=-10V - 21 40 ns tf Fall Time RD=10Ω -1 02 0 ns Ciss Input Capacitance VGS=0V - 760 1140 pF Coss Output Capacitance VDS=-25V - 345 518 pF Crss Reverse Transfer Capacitance f=1.0MHz - 90 135 pF Source-Drain Diode Symbol Parameter Test Conditions Min. Typ. Max. Units IS Continuous Source Current ( Body Diode ) VD=VG=0V , VS=-1.2V - - -1.7 A ISM Pulsed Source Current ( Body Diode )1 - - -20 A VSD Forward On Voltage2 Tj=25°C, IS=-1.7A, VGS=0V - - -1.2 V Notes: 1.Pulse width limited by max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on FR4 board, t<10sec. 4.Pulse width <10us , duty cycle <1%. ± 20V ±100 Rev.2.01 7/01/2004

www.SiliconStandard.com 4 of 11 SSM4532M N-channel Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 0123456789 VDS , Drain-to-Source Voltage (V) ID , Drain Current (A) T C =25 oC V G =10V V G =4.0V V G =8.0V V G =6.0V V G =3.0V 01234567 VDS , Drain-to-Source Voltage (V) ID , Drain Current (A) T C =150 oC V G =4.0V V G =6.0V V G =8.0V V G =10V V G =3.0V 34567891 01 1 V GS (V) RDSON (mΩ ) Id=5A T c =25°C 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -50 0 50 100 150 T j , Junction Temperature ( oC) Normalized RDS(ON) I D =5A V G =10V Rev.2.01 7/01/2004

www.SiliconStandard.com 5 of 11 SSM4532M N-channel Fig 5. Maximum Drain Current vs. Fig 6. Typical Power Dissipation Case Temperature Fig 7. Maximum Safe Operating Area Fig 8. Effective Transient Thermal Impedance 25 50 75 100 125 150 T c , Case Temperature ( oC) ID , Drain Current (A) 0 50 100 150 T c ,Case Temperature ( oC) PD (W) 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 1 10 100 1000 t , Pulse Width (s) Normalized Thermal Response (Rthja) PDM Duty factor = t/T Peak Tj = PDM x Rthja + Ta t T 0.02 0.01 0.05 0.1 0.2 DUTY=0.5 SINGLE PULSE 0.1 100 0.1 1 10 100 V DS (V) ID (A) T c =25 oC Single Pulse 10us 100us 1ms 10ms 100ms Rev.2.01 7/01/2004

www.SiliconStandard.com 6 of 11 SSM4532M N-channel Fig 9. Gate Charge Characteristics Fig 10. Typical Capacitance Characteristics Fig 11. Forward Characteristic of Fig 12. Gate Threshold Voltage vs. Reverse Diode Junction Temperature 100 1000 1 5 9 13 17 21 25 29 V DS (V) C (pF) f=1.0MHz Ciss Coss Crss 024681 01 2 Q G , Total Gate Charge (nC) VGS , Gate to Source Voltage (V) I D =5A V DS =10V 0.01 0.10 1.00 10.00 100.00 V SD (V) IS(A) T j =25 oC T j =150 oC 0.5 1.5 2.5 -50 0 50 100 150 T j ,Junction Temperature ( oC) VGS(th) (V) Rev.2.01 7/01/2004

www.SiliconStandard.com 7 of 11 SSM4532M N-channel Fig 13. Switching Time Circuit Fig 14. Switching Time Waveform Fig 15. Gate Charge Circuit Fig 16. Gate Charge Waveform td(on) tr td(off) tf VDS VGS 10% 90% Q VG 10V QGS QGD QG Charge 0.33x RATED VDS TO THE OSCILLOSCOPE 10V D G S VDS VGS RG RD 0.33 x RATED VDS TO THE OSCILLOSCOPE D G S VDS VGS I D I G 1~ 3 mA Rev.2.01 7/01/2004

www.SiliconStandard.com 8 of 11 SSM4532M P-channel Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 0.6 0.8 1.2 1.4 1.6 1.8 -50 0 50 100 150 T j , Junction Temperature ( o C) Normalized RDS(ON) V G = -10V I D =-4.0A 01234 -V DS , Drain-to-Source Voltage (V) -ID , Drain Current (A) T C =25 o C V G =-10V V G =-8.0V V G =-6.0V V G =-4.0V 012 345 -V DS , Drain-to-Source Voltage (V) -ID , Drain Current (A) T C =150 o C V G =-10V V G =-4.0V V G =-6.0V V G =-8.0V 34567891 01 1 -V GS (V) RDSON (mΩ ) Id=-4.0A T c =25°C Rev.2.01 7/01/2004

www.SiliconStandard.com 9 of 11 SSM4532M P-channel Fig 5. Maximum Drain Current vs. Fig 6. Typical Power Dissipation Case Temperature Fig 7. Maximum Safe Operating Area Fig 8. Effective Transient Thermal Impedance 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 1 10 100 1000 t , Pulse Width (s) Normalized Thermal Response (Rthja) PDM Duty factor = t/T Peak Tj = PDM x Rthja+ Ta t T 0.02 0.01 0.05 0.1 0.2 DUTY=0.5 SINGLE PULSE 25 50 75 100 125 150 T c , Case Temperature ( o C) -ID , Drain Current (A) 0.5 1.5 2.5 0 50 100 150 T c ,Case Temperature ( o C) PD (W) 0.1 100 0.1 1 10 100 -V DS (V) -ID (A) T c =25 o C Single Pulse 10us 100us 1ms 10ms 100ms Rev.2.01 7/01/2004

www.SiliconStandard.com 10 of 11 SSM4532M P-channel Fig 9. Gate Charge Characteristics Fig 10. Typical Capacitance Characteristics Fig 11. Forward Characteristic of Fig 12. Gate Threshold Voltage vs. Reverse Diode Junction Temperature 0.01 0.10 1.00 10.00 100.00 -V SD (V) -IS(A) T j =25 o C T j =150 o C 100 1000 10000 1 5 9 1 31 72 12 52 9 -V DS (V) C (pF) f=1.0MHz Ciss Coss Crss 0.5 1.5 2.5 -50 0 50 100 150 T j ,Junction Temperature ( o C) -VGS(th) (V) 0 2 4 6 8 10 12 14 16 18 20 Q G , Total Gate Charge (nC) -VGS , Gate to Source Voltage (V) I D =-4A V DS =-10V Rev.2.01 7/01/2004

www.SiliconStandard.com 11 of 11 Fig 13. Switching Time Circuit Fig 14. Switching Time Waveform Fig 15. Gate Charge Circuit Fig 16. Gate Charge Waveform td(on) tr td(off) tf VDS VGS 10% 90% Q VG -10V QGS QGD QG Charge 0.33 x RATED VDS TO THE OSCILLOSCOPE -10 V D G S VDS VGS RG RD 0.33 x RATED VDS TO THE OSCILLOSCOPE D G S VDS VGS IDI G -1~-3mA Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expre ss or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. SSM4532M P-channel Rev.2.01 7/01/2004