453-00137

Ezurio

60 Series SOM 16 Apr 2025 Version 4.0

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60-SOM EZURIO | Alldatasheet

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Technical content

60 Series SOM

Version 4.0

Revision History

Version Date Notes Contributors Approver 1.0 13 Nov 2018 Initial Version Andrew Chen Jay White 1.1 13 Feb 2019 Updated logos and URLs Sue White 1.2 14 Feb 2019 Changed ATSAMA5D34 to ATSAMA5D36 Sue White Jay White 1.3 25 Feb 2019 Updated mechanical drawing Andrew Chen Jay White 1.4 15 Apr 2019 Fixed headings for tables 9 and 10; corrected C16 pin name and

description

1.5 29 Apr 2019 Fixed pin numbers (C21 and C22 to D21 and D22) Andrew Chen Jay White 1.6 19 July 2019 Updated Certification section Andrew Chen Jay White 1.7 23 July 2019 Updated processor name John Nosky Jay White 1.8 28 Aug 2019 Updated to Bluetooth 5.1 Jay White 1.9 23 Oct 2019 Updated warranty information (one year vs. three) Jay White 1.10 13 Dec 2019 Added double memory SOM option to the datasheet Fixed Power Supply drawing Updated Booting section with more information on boot strategies, required hardware, etc. Boris Krasnovskiy Andrew Dobbing 1.11 06 May 2020 Update block diagram (antenna description) Kai Wei Jay White 1.12 09 May 2020 Minor changes Dave Drogowski Jay White 1.13 10 Aug 2020 Updated EU Regulatory section Sue White Ryan Urness 1.14 20 Oct 2020 Updated the Regulatory section Maggie Teng Ryan Urness 2.0 21 Jan 2021 Transferred all regulatory information into separate document Maggie Teng Jonathan Kaye 2.1 19 Mar 2021 Added pin # clarification to the mechanical drawings Bob Monroe Andrew Chen 2.2 24 Mar 2021 Added PN 453-00004 (2 Gb LPDDR1 RAM and 4 Gb NAND flash) Dan Kephart Jonathan Kaye 2.3 2 May 2021 Added clarification for the NRST pin operation Boris Krasnovskiy Dan Kephart 2.4 26 July 2021 Updated Support contact info Alex Mohr Sue White 2.5 20 Aug 2021 Added EN 300 440 compliance Alex Mohr Jonathan Kaye 2.6 24 Aug 2021 Updated supported security types Dan Kephart Dave Drogowski 2.7 5 Oct 2021 Updated Mechanical Specifications: Figure 8: Mechanical Details Figure 9: PCB footprint recommendation for 60-SOM John Nosky Andrew Chen Dave Drogowski 2.8 16 Nov 2021 Removed CCX / WFA Certifications info Dan Kephart Dave Drogowski 2.9 23 Dec 2021 Updated Mechanical Specifications. Dave Drogowski Andrew Chen 3.0 14 Jan 2021 Added orderable part 455-00039 to Ordering Information Dave Drogowski Dan Kephart 3.1 11 Feb 2022 Added Module Washing and Cleaning section Dave Drogowski Andrew Chen 3.2 28 Apr 2022 Added UKCA to 6.1.1 WLAN RF Channels and Regulatory Domains Dave Drogowski Brian Petted 3.3 2 May 2022 Updated to latest Wi-Fi/BT Specifications Dave Drogowski Dan Kephart 3.4 12 May 2022 EU supported 5GHz U-NII-3 band EU and JP do not support CH144 Kai Wei Andrew Chen 3.5 19 April 2023 Add new LPDDR2 versions (453-00137 and 453-00138) and associated devkits Dave Drogowski Dan Kephart 3.6 19 Oct 2023 Added Bluetooth SIG Qualification Dave Drogowski John Nosky 3.7 1 Nov 2024 Updates to Bluetooth SIG Qualification Dave Drogowski Jonathan Kaye 4.0 16 Apr 2025 Ezurio rebranding Sue White Dave Drogowski

1 Scope

This document describes key hardware aspects of the Ezurio 60 Series system on module (SOM) (part number 453-00003 and 453-00004). This document is intended to assist device manufacturers and related parties with the integration of this radio into their host de vices. Data in this document is drawn from many sources and includes information found in the Ezurio 60-SIPT, Marvell 88W8997/88PG823. Note that the information in this document is subject to change. Please contact Ezurio to obtain the most recent version of this document.

2 Introduction

2.1 General Description

The Ezurio 60 Series SOM (part number 453-00003 and 453-00004) wireless bridge module is a wireless communications subsystem that may be integrated into a variety of host devices via many available electronic and logical interfaces. The SOM provides complete enterprise-class Wi-Fi connectivity with an integrated TCP/IP stack. It also provides full support for 2x2 MIMO 802.11 a/b/g/n/ac WLAN plus Bluetooth 5.1 dual mode dual- mode air standards with a fully integrated security supplicant providing WPA/WPA2/WPA3 authentication, data encryption, and BT protocol stacks. The 60-SOM has a wide variety of interfaces including RMII, RGMII, serial UART, Hi-Speed USB, SPI, SDIO, TTL RGB, PCM, and I2C. The wireless bridge may be configured, monitored, and managed via a Command Line Interface (CLI) over an available dedicated console port, via a web interface over a wireless or Ethernet interface, or via a remote SDK interface over wireless or Ethernet. The 60-SOM incorporates the Ezurio 60-SIPT Wi-Fi SiP module which uses Marvell 88W8997/88PG823. The product also features the ARM® Cortex®-A5 processor running at 536 MHz and an MCP memory with 1 Gb or 2 Gb 32-bit LPDDR1 or LPDDR2 memory, and 2 Gb or 4 Gb 8-bit SLC NAND flash storage. Several GPIO lines are available for data acquisition and similar applications. A software developer’s kit (SDK) with Application Programming Interfaces (API) and software tools are available for the development of custom software applications on the devi ce.

2.2 Features and Functionality

The 60-SOM has several interfaces, some of which are multiplexed and not available simultaneously. The module has the following features:

Atmel single ARM Cortex-A5 core operating at speeds up to 536 MHz: – 32-Kb L1 instruction cache – 32-Kbyte data cache, 32-Kbyte instruction cache, Virtual Memory System Architecture (VMSA) – 160-Kbyte internal ROM single-cycle access at system speed. – One 128-Kbyte internal SRAM, single-cycle access at system speed – Very slow clock operating mode, software programmable power optimization capabilities
Security: – TRNG: True random number generator – AES: 256-bit, 192-bit, 128-bit key algorithm, compliant with FIPS PUB 197 Specifications – TDES: Two-key or three-key algorithms, compliant with FIPS PUB 46-3 Specifications – Atmel/Microchip secure boot solution
Memory, option 1: – 1 Gb, 32-bits of Lower Power DDR (LPDDR) memory – 2 Gb, 8-bits of SLC NAND flash memory
Memory, option 2: – 2 Gb, 32-bits of Lower Power DDR (LPDDR) memory – 4 Gb, 8-bits of SLC NAND flash memory
Memory, option 3: – 1 Gb, 32-bits of Lower Power DDR2 (LPDDR2) memory – 2 Gb, 8-bits of SLC NAND flash memory
Memory, option 4: – 2 Gb, 32-bits of Lower Power DDR2 (LPDDR2) memory – 4 Gb, 8-bits of SLC NAND flash memory

2X2 IEEE 802.11 a/b/g/n/ac WLAN interface
Bluetooth version 5.1 dual-mode
Support interface: – 24-bits TTL RGB bus for TFT LCD display – X1 MMC/SD/SDIO port – X3 HS/FS/LS USB Ports with: X1 USB device port. X2 USB host ports. – X1 10/100/1000 Mbps reduced Gigabit media independent interface (RGMII) – X1 10/100 Mbps reduced media-independent interface (RMII) – X1 CAN bus, fully compliant with CAN 2.0 Part A and 2.0 Part B – X3 UARTs – X1 DBGU for debug purpose – X2 Master/Slave serial peripheral interfaces – X1 Synchronous serial controllers – X2 Two-wire interface up to 400 Kbit/s supporting I2C Protocol and SMBUS – ADC and GPIOs
Ultra-miniature low profile SMT module (30 x 30 x 2.8 mm) based on 188 pads 2 row LGA package. The 60-SOM provides the following two U. FL type antenna connectors that provide two streams MIMO operation to reach the maximum data ra te:
Main/ANT0 antenna – Wi-Fi only
Auxiliary/ANT1 – Wi-Fi and Bluetooth Bluetooth signals can only be presented at the auxiliary/ANT1. Supported host device antenna types include dipole and monopol e antennas. Regulatory operational requirements are included in this document and may be incorporated into the operating manual of any de vice into which the 60-SOM is installed. The 60-SOM is designed for installation into mobile devices which typically operate at distances greater than 20 cm from the human body and portable devices which typically operate at distances less than 20 cm from the human body. See Documentation Requirements for more information. The 60-SOM modules include two product SKUs which have different supported software features. Please check Ezurio sales/FAE for further information. Order information is listed below: Part Number Description 453-00137 60 Series SOM using 1 Gb LPDDR2 RAM and 2 Gb NAND flash 453-00138 60 Series SOM using 2 Gb LPDDR2 RAM and 4 Gb NAND flash 453-00003 60 Series SOM using 1 Gb LPDDR1 RAM and 2 Gb NAND flash 453-00004 60 Series SOM using 2 Gb LPDDR1 RAM and 4 Gb NAND flash 453-00137-K1 Development Board for the 60 Series SOM using 1 Gb LPDDR2 RAM and 2 Gb NAND flash 453-00138-K1 Development Board for the 60 Series SOM using 2 Gb LPDDR2 RAM and 4 Gb NAND flash 455-00003 Development Board for the 60 Series SOM using 1 Gb LPDDR1 RAM and 2 Gb NAND flash 455-00039 Development Board for the 60 Series SOM using 2 Gb LPDDR1 RAM and 4 Gb NAND flash 455-00004 LCD Touchscreen for the 60 Series SOM development board (add-on) CAUTION: The 60-SOM only allows one time reflow during the SMT assembly process. Applying more than one time reflow during this process will damage the module.

2.3 Block Diagram

Figure 1 show block diagrams of the Ezurio 60-SOM. Figure 1: Ezurio 60-SOM module block diagrams Note: Transmitter frequencies for Wi-Fi are 2412-2462 MHz and 5180-5805 MHz. Transmitter frequencies for Bluetooth are 2402-2480 MHz.

3 Pin Definitions and Signal Descriptions

Note: PWR Power Input I/O Input and output I Input O Output PU Pull-up PD Pull-down Table 1: 60-SOM pin definitions Pin # Name Type Pins map to CPU Voltage Ref. DVK Function If Not Used G1 GND - - - Ground GND A1 VCC3_3 PWR - - DC 3.3V input for the module -- A2 GND - - - Ground GND A3 G_125CK I PB18 VDDIOP1 RGMII 125 MHz input clock NC A4 G_RXCK I PB11 VDDIOP1 RGMII Receive clock NC A5 G_RXER I PB13 VDDIOP1 RGMII Receive error NC A6 GND - - - Ground GND A7 G_RX3 I PB7 VDDIOP1 RGMII Receive data NC A8 G_MDIO I/O PB17 VDDIOP1 RGMII Management data Input/Output NC A9 G_RX1 I PB5 VDDIOP1 RGMII Receive data NC A10 G_RX0 I PB4 VDDIOP1 RGMII Receive data NC A11 G_RX2 I PB6 VDDIOP1 RGMII Receive data NC A12 GND - - - Ground GND A13 GND - - - Ground GND A14 G_TXCK O PB8 VDDIOP1 RGMII Transmit clock or Reference clock NC A15 G_TXEN O PB9 VDDIOP1 RGMII Transmit Enable NC A16 GND - - - Ground GND A17 G_TX2 O PB2 VDDIOP1 RGMII Transmit data NC A18 G_TX3 O PB3 VDDIOP1 RGMII Transmit data NC A19 G_TX0 O PB0 VDDIOP1 RGMII Transmit data NC A20 G_TX1 O PB1 VDDIOP1 RGMII Transmit data NC A21 G_MDC O PB16 VDDIOP1 RGMII Management data clock NC A22 GND - - - Ground GND A23 GND - - - Ground GND A24 TW_CLK I/O PA31 VDDIOP0 Two-wire Serial clock NC A25 TW_D I/O PA30 VDDIOP0 Two-wire Serial data NC A26 GND - - - Ground GND A27 ADTRG I PD19 VDDIOP1 ADC Trigger NC A28 AD3 I PD23 VCC3_3 Touchscreen Analog-to-Digital Converter – ADC Lower Right touch panel NC

https://www.ezurio.com/ 9 © Copyright 2025 Ezurio All Rights Reserved Pin # Name Type Pins map to CPU Voltage Ref. DVK Function If Not Used A29 AD4 I PD24 VCC3_3 Touchscreen Analog-to-Digital Converter – ADC Panel Input NC A30 AD0 I PD20 VCC3_3 Touchscreen Analog-to-Digital Converter – ADC Upper-left touch panel NC A31 AD5 I PD25 VCC3_3 Analog Input NC A32 AD1 I PD21 VCC3_3 Touchscreen Analog-to-Digital Converter – ADC Upper-right touch panel NC A33 AD2 I PD22 VCC3_3 Touchscreen Analog-to-Digital Converter – ADC Lower-left touch panel NC A34 GND - - - Ground GND A35 FIQ I/PU PC31 VDDIOP0 Fast Interrupt Default: Interrupt signal from Audio Codec chip. NC A36 GND - - Ground GND A37 VDDIOP1 PWR - - I/O Port 1 Reference Voltage; 1.8V or 3.3V -- A38 URXD0 I PC29 VDDIOP0 UART0 Receive data NC A39 UTXD0 O PC30 VDDIOP0 UART0 Transmit data NC A40 GND - - - Ground GND A41 TK0 I/O PC16 VDDIOP0 Synchronous Serial Controller (SSC) Transmit clock NC A42 TD0 O PC18 VDDIOP0 Synchronous Serial Controller (SSC) Transmit data NC A43 PCK2 O PC15 VDDIOP0 Programmable Clock Output; Default: Master clock for Audio CODEC NC A44 RF0 I/O PC20 VDDIOP0 Synchronous Serial Controller (SSC) Receive Frame Sync NC A45 TF0 I/O PC17 VDDIOP0 Synchronous Serial Controller (SSC) Transmit Frame Sync NC A46 RD0 I PC21 VDDIOP0 Synchronous Serial Controller (SSC) Receive data NC A47 RK0 I/O PC19 VDDIOP0 Synchronous Serial Controller (SSC) Receive clock NC G2 GND - - - Ground GND B1 VCC3_3 PWR - - DC 3.3V input for the module -- B2 GND - - - Ground GND B3 GPIO Default: VBUS_SENSE I PC14 VDDIOP0 Device USB Bus Power Sense H – USB device port is plugged into a host L – USB device port is NOT plugged into a host 10k;PL B4 E_TXEN O PC4 VDDIOP0 RMII Transmit Enable NC B5 GPIO Default: E_INT I PC10 VDDIOP0 RMII Interrupt Input from Ethernet PHY NC B6 E_RXD1 I PC3 VDDIOP0 RMII Receive data NC B7 E_MDIO I/O PC9 VDDIOP0 RMII Management Data Input/Output NC B8 E_RXD0 I PC2 VDDIOP0 RMII Receive data NC B9 E_RXER I PC6 VDDIOP0 RMII Receive error NC

https://www.ezurio.com/ 10 © Copyright 2025 Ezurio All Rights Reserved Pin # Name Type Pins map to CPU Voltage Ref. DVK Function If Not Used B10 E_CRSDV I PC5 VDDIOP0 RMII Carrier Sense/Data Valid NC B11 E_MDC O PC8 VDDIOP0 RMII Management Data clock NC B12 E_TXD1 O PC1 VDDIOP0 RMII Transmit data NC B13 E_TXD0 O PC0 VDDIOP0 RMII Transmit data NC B14 GND - - - Ground GND B15 E_REFCK I PC7 VDDIOP0 RMII Transmit Clock or Reference clock NC B16 GND - - - Ground GND B17 SPI1_CLK I/O PC24 VDDIOP0 SPI1 Serial clock NC B18 GND - - - Ground GND B19 SPI1_MISO I/O PC22 VDDIOP0 SPI1 Master In Slave Out NC B20 SPI1_MOSI I/O PC23 VDDIOP0 SPI1 Master Out Slave In NC B21 SPI1_NPCS2 Default: TW_CK1 I/O PC27 VDDIOP0 SPI1 Peripheral Chip Select TW_CK1: Two-wire Serial clock NC B22 GND - - - Ground GND B23 LCD_DAT4 O PA4 VDDIOP0 LCD Controller (LCDC) data bus NC B24 LCD_DAT2 O PA2 VDDIOP0 LCD Controller (LCDC) data bus NC B25 LCD_DAT14 O PA14 VDDIOP0 LCD Controller (LCDC) data bus NC B26 LCD_PWM O PA24 VDDIOP0 LCDPWM for LCD Panel Contrast Control NC B27 LCD_DAT10 O PA10 VDDIOP0 LCD Controller (LCDC) data bus NC B28 LCD_DAT0 O PA0 VDDIOP0 LCD Controller (LCDC) data bus NC B29 LCD_DAT12 O PA12 VDDIOP0 LCD Controller (LCDC) data bus NC B30 GND - - - Ground GND B31 LCD_PCK O PA28 VDDIOP0 LCD Controller (LCDC) LCD pixel clock NC B32 GND - - - Ground GND B33 LCD_DAT22 O PA22 VDDIOP0 LCD Controller (LCDC) data bus NC B34 LCD_DAT20 O PA20 VDDIOP0 LCD Controller (LCDC) data bus NC B35 LCD_DAT8 O PA8 VDDIOP0 LCD Controller (LCDC) data bus NC B36 LCD_VSYNC O PA26 VDDIOP0 LCD Controller (LCDC) LCD vertical synchronization NC B37 LCD_DAT3 O PA3 VDDIOP0 LCD Controller (LCDC) data bus NC B38 LCD_HSYNC O PA27 VDDIOP0 LCD Controller (LCDC) LCD horizontal synchronization NC B39 LCD_DAT16 O PA16 VDDIOP0 LCD Controller (LCDC) data bus NC B40 LCD_DAT6 O PA6 VDDIOP0 LCD Controller (LCDC) data bus NC B41 LCD_DAT1 O PA1 VDDIOP0 LCD Controller (LCDC) data bus NC B42 LCD_DISP O PA25 VDDIOP0 LCD Controller (LCDC) LCD Display ON/OFF NC B43 LCD_DAT18 O PA18 VDDIOP0 LCD Controller (LCDC) data bus NC B44 LCD_DAT15 O PA15 VDDIOP0 LCD Controller (LCDC) data bus NC B45 LCD_DAT13 O PA13 VDDIOP0 LCD Controller (LCDC) data bus NC

https://www.ezurio.com/ 11 © Copyright 2025 Ezurio All Rights Reserved Pin # Name Type Pins map to CPU Voltage Ref. DVK Function If Not Used B46 LCD_DAT17 O PA17 VDDIOP0 LCD Controller (LCDC) data bus NC B47 LCD_DEN O PA29 VDDIOP0 LCD Controller (LCDC) LCD data enable NC G3 GND - - - Ground GND C1 LCD_DAT19 O PA19 VDDIOP0 LCD Controller (LCDC) data bus NC C2 LCD_DAT23 O PA23 VDDIOP0 LCD Controller (LCDC) data bus NC C3 LCD_DAT21 O PA21 VDDIOP0 LCD Controller (LCDC) data bus NC C4 GND - - - Ground GND C5 SPI1_NPCS3 Default: TW_IRQ1 I/O PC28 VDDIOP0 SPI1 Peripheral Chip Select TW_IRQ1: Two-wire interrupt Touch screen change Interrupt (I/P) NC C6 SPI1_NPCS1 Default: TW_D1 I/O PC26 VDDIOP0 SPI1 Peripheral Chip Select TW_D1: Two-wire serial data NC C7 SPI1_NPCS0 Default: LCD_Mode O PC25 VDDIOP0 SPI1 Peripheral Chip Select LCD Mode Select: H – DE mode, L – HSD/VSD mode NC C8 LCD_DAT7 O PA7 VDDIOP0 LCD Controller (LCDC) data bus NC C9 LCD_DAT9 O PA9 VDDIOP0 LCD Controller (LCDC) data bus NC C10 LCD_DAT5 O PA5 VDDIOP0 LCD Controller (LCDC) data bus NC C11 LCD_DAT11 O PA11 VDDIOP0 LCD Controller (LCDC) data bus NC C12 GND - - - Ground GND C13 GND - - - Ground GND C14 GND - - - Ground GND C15 WIFI_3V3 PWR 3.3V Power Supply for Wi-Fi SIP on the module -- C16 LTE_SIN I - VDDIOP1 LTE Coex. Signal Input NC C17 LTE_SOUT O - VDDIOP1 LTE Coex. Signal Output NC C18 GND - - - Ground GND C19 GPIO Default: eMMC_EN I/O PE30 1.8V GPIO: eMMC Card slot Power Supply Control O/P: Open Drain, 10K external pull-up required Set Low to disable the eMMC power NC C20 IRQ Default: eMMC_CD I/O PE31 1.8V IRQ eMMC Card Detect I/P: Low Active. L – detect SDIO card inserted 10K;PU C21 GND - - - Ground GND C22 GND - - - Ground GND C23 VDDIOP1 PWR - - I/O Port 1 Reference Voltage; 1.8V or 3.3V -- C24 SPI0_MISO I/O PD10 VDDIOP1 SPI0 Master In Slave Out NC C25 GND - - Ground GND

https://www.ezurio.com/ 12 © Copyright 2025 Ezurio All Rights Reserved Pin # Name Type Pins map to CPU Voltage Ref. DVK Function If Not Used C26 SPI0_CLK I/O PD12 VDDIOP1 SPI0 serial clock NC C27 GND - - - Ground GND C28 SPI0_MOSI I/O PD11 VDDIOP1 SPI0 Master Out Slave In NC C29 SPI0_NPCS0 O PD13 VDDIOP1 SPI0 Peripheral Chip Select NC C30 GND - - - Ground GND C31 GND - - - Ground GND C32 GND - - - Ground GND C33 GND - - - Ground GND C34 RXD_2 I PE25 1.8V USART2 Receive data NC C35 GND - - Ground GND C36 GPIO/SCK_2 Default: INTn_IO_Ex I/O PE20 1.8V General purpose I/O/USART2 Serial clock Default: Interrupt signal from I/O expander chip. I/P; “Low” active NC C37 RTS_2 O PE24 1.8V USART2 Request-to-Send NC C38 CTS_2 I PE23 1.8V USART2 Clear-to-Send NC C39 TXD_2 O PE26 1.8V USART2 Transmit data NC C40 GND - - - Ground GND C41 GND - - - Ground GND C42 BT_PCM_IN I - VDDIOP1 Bluetooth PCM Input NC C43 BT_PCM_SYNC I/O - VDDIOP1 Bluetooth PCM Sync NC C44 BT_PCM_OUT O - VDDIOP1 Bluetooth PCM Output NC C45 BT_PCM_CLK I/O - VDDIOP1 Bluetooth PCM Clock NC C46 GND - - - Ground GND C47 RXD_3 I PE18 1.8V USART3 Receive data NC G4 GND - - - Ground GND D1 CTS_3 I PE16 1.8V USART3 Clear-to-Send NC D2 GPIO SCK_3 I/O PE15 1.8V General purpose I/O USART3 Serial clock NC D3 TXD_3 O PE19 1.8V USART3 Transmit data NC D4 RTS_3 O PE17 1.8V USART3 Request-to-Send NC D5 GND - - - Ground GND D6 GPIO/SCK_1 Default: GETH_INT I/O PB25 VDDIOP1 General purpose I/O; USART1 Serial clock GETN_INT: Interrupt input from RGMII PHY; Low active 4.7K;PU D7 RTS_1 O PB27 VDDIOP1 USART1 Request-to-Send NC D8 RXD_1 I PB28 VDDIOP1 USART1 Receive data NC D9 CTS_1 I PB26 VDDIOP1 USART1 Clear-to-Send NC D10 TXD_1 O PB29 VDDIOP1 USART1 Transmit data NC D11 SHDN O VDD_BU Shutdown Control; NC

https://www.ezurio.com/ 13 © Copyright 2025 Ezurio All Rights Reserved Pin # Name Type Pins map to CPU Voltage Ref. DVK Function If Not Used SHDN Use to turn off the external PMU for VCC3_3 O/P; Low Active D12 GND - - - Ground GND D13 GND - - - Ground GND D14 HHSDPC A HHSDPC - USB Host Port C High Speed Data + NC D15 HHSDMC A HHSDMC - USB Host Port C High Speed Data - NC D16 GND - - - Ground GND D17 GND - - - Ground GND D18 HHSDPB A HHSDPB - USB Host Port B High Speed Data + NC D19 HHSDMB A HHSDMB - USB Host Port B High Speed Data - NC D20 GND - - - Ground GND D21 HSDMA HSDMA USB Device Port A High-Speed Data - NC D22 HSDPA HSDPA USB Device Port A High-Speed Data + NC D23 GND - - - Ground GND D24 VDD_BU PWR - - Module Backup Power for RTC mode Note: VDD_BU need to be same Voltage level as VDDIOP1 D25 WKUP I/PU WKUP VDD_BU Wake-Up: Wake up Module from RTC Mode. I/P; Low Active. Has 100K pull-up in the module design NC D26 BMS I/PU BMS VDDIOP0 Boot Mode Select. Has 10K pull-up in the SOM module design NC: Normal Boot from NAND flash on the module GND: Boot from External Memory NC D27 NRST I/O NRST VDDIOP0 Microcontroller/Peripheral Reset; Low Active External 10K pulled-up is needed Put the 10K Ω pulled-up resistor close to this pin. And keep the trace as short as possible and avoid noise and ESD source. Pin operate as the Open Drain output if requested by software or during exit from external reset 10K PU D28 GND - - - Ground GND D29 D_TXD O PB31 VDDIOP1 Debug UART Transmit data NC D30 D_RXD I PB30 VDDIOP1 Debug UART Receive data NC D31 CAN_RX1 I PB14 VDDIOP1 CAN input NC D32 GND - - - Ground GND D33 CAN_TX1 O PB16 VDDIOP1 CAN output NC D34 GND - - - Ground GND D35 MC_DA3 I/O PD4 VDDIOP1 High Speed Multimedia Card data NC D36 MC_DA5 I/O PD6 VDDIOP1 High Speed Multimedia Card data NC D37 MC_DA1 I/O PD2 VDDIOP1 High Speed Multimedia Card data NC

https://www.ezurio.com/ 14 © Copyright 2025 Ezurio All Rights Reserved Pin # Name Type Pins map to CPU Voltage Ref. DVK Function If Not Used D38 MC_DA7 I/O PD8 VDDIOP1 High Speed Multimedia Card data NC D39 MC_DA4 I/O PD5 VDDIOP1 High Speed Multimedia Card data NC D40 MC_CDA I/O PD0 VDDIOP1 High Speed Multimedia Card Command NC D41 MC_DA6 I/O PD7 VDDIOP1 High Speed Multimedia Card data NC D42 GND - - - Ground GND D43 MC_DA0 I/O PD1 VDDIOP1 High Speed Multimedia Card data NC D44 MC_CLK I/O PD9 VDDIOP1 High Speed Multimedia Card clock NC D45 MC_DA2 I/O PD3 VDDIOP1 High Speed Multimedia Card data NC D46 GND - - - Ground GND D47 VDDIOP0 PWR - - I/O Port 0 Reference Voltage; 1.8V or 3.3V -- G5- G13 GND - - - Ground GND

4 Power Consideration

4.1 Power Supply

Figure 2: 60-SOM module power supply

WiFi_3V3 – Mainly used for the 60-SIPT Wi-Fi/BT SIP on the 60-SOM.
VCC3_3 – Provides the input power for the processor and memory on the 60-SOM. Several DC/DC regulators and LDO generate required voltages and power on sequence (POS) timing for the processor.
VDD_BU – Provides the backup power to the Atmel/Microchip processor on the 60-SOM. It also powers the slow clock oscillator (32.768 kHz) that provides slow clock to both the Atmel/Microchip processor and the 60-SIPT when the 60-SOM is in deep sleep mode. The VDDIOP0 and VDDIOP1 are the Peripheral I/O’s DC Supply Voltage which could be set to 1.8V or 3.3V according to the application required. Due to the VDDIOP1 defined the slow clock signal level of the 60-SIPT as well, always keep the VDD_BU and VDDIOP1 at the same voltage.

4.2 Power on Sequence

When the power supply is connected to the 60-SOM, most of the power on sequence are designed and performed inside the 60-SOM. No specific order and timing required for the VDD_BU, VDDIOP0, VDDIOP1, WIFI_3V3, and VCC3_3. However, minimum of 5 ms (t1) is needed for the reset (NRST) to power up. Table 2: Power on sequence Symbol Parameter Conditions Min Max Unit t1 Reset Delay at Power-Up From the Group established supply to NRST high 5 - ms Figure 3: Power on sequence

4.3 Power Down Sequence

Table 3 provides the 60-SOM power-down sequence that starts by asserting the NRST line to 0. Once NRST is asserted, the supply inputs can be immediately shut down without any specific timing or order. Do not shut down VDD_BU if the application uses a backup battery on this supply input. Table 3: Power down sequence Symbol Parameter Conditions Min Max Unit tRSTPD : Reset Delay at Power-Down From NRST low to the group supply turn-off 0 - ms

5 Booting

The following boot options are available:

SD Card / eMMC
NAND Flash
SPI NOR Flash
I2C EEPROM
Atmel/Microchip SAM-BA The ROM code standard sequence executes a basic chip initialization and attempts to retrieve a valid code from external non-volatile memories (NVM). For the complete description, see Section 11 of ATSAMA5D36 datasheet. The default boot order is as follows:
SPI0 NPCS0
SD Card / eMMC (MCI0)
NAND Flash
SPI1 NPCS0
TWI0 EEPROM
Atmel/Microchip SAM-BA (USB Peripheral)

5.1 Initial Boot or Failure Recovery Boot

CAUTION: The 60-SOM is shipped blank from the factory, i.e. without any software (unless customer and Ezurio have agreed to pre-load the 60-SOM with a custom created image). The 60-SOM is a solder down SOM, and as such, boot methods must be thought through beforehand. Once the module is soldered onto the customer product, updates to the image within the 60-SOM are only possible using the hardware interfaces a customer has exposed in their design. It is recommended for user to provision their base board with the hardware to preform Initial or Recovery boot. The following options are recommended:

Micro SD Card connector (for SD Card boot)
Peripheral Micro USB connector (for Atmel/Microchip SAM-BA boot) Ezurio recommends Micro SD Card to simplify and speedup software development process, production, and end user device recovery.

5.2 Force Boot from Atmel/Microchip SAM-BA

Shorting points A and B together bypasses the onboard NAND flash on the 60-SOM and forces the module into ROM boot status. This allows you to program the NAND flash through Atmel/Microchip SAM-BA.

5.3 Secure Boot Provisioning

Provisioning module with secure boot requires specialized tools and possibly hardware interfaces. Contact Ezurio to arrange module provisioning and/or discuss possible options. Secure boot key cannot be changed or removed after it has been programmed into the module. CAUTION: The 60-SOM provisioned with Secure Boot key becomes unique and locked to the particular company, product, etc. as customer desires. Customer must establish proper manufacturing controls internally and with Contract Manufacturers, so that 60-SOM modules destined for the different products or companies do not mix.

6 Wireless Interface

The Ezurio 60-SOM combines a wireless local area network (WLAN) and dual-mode Bluetooth (BT) solution to support IEEE 802.11 a/b/g/n/ac 2X2 MIMO WLAN standards and BT 5.1 with the integration of WLAN/BT and Low Energy (BLE) technology. The following sections include specifications for the wireless interfaces available on the 60-SOM. 6.1 WLAN 802.11a/b/g/n/ac The 2.4 GHz band on the 60-SOM supports 20 MHz bandwidths and the 5 GHz band supports 20/40/80 MHz bandwidths. The following sections specify the performance of the WLAN IEEE 802.11a/b/g/n/ac interface on the 60-SOM module.

6.1.1 WLAN RF Channels and Regulatory Domains

The 60-SOM supports the following channels and regulatory domains. Table 4: Supported WLAN RF channels and regulatory domains Feature Description Regulatory Domain Support FCC EU UKCA ISED Canada MIC (Japan) – Option KC (Korea) – Option

2.4 GHz Operating Channels

(Wi-Fi) EU – 13 (3 non-overlapping) FCC – 11 (3 non-overlapping) MIC – 14 (4 non-overlapping) KC – 13 (3 non-overlapping)

5 GHz Frequency Bands EU

5.15 GHz to 5.35 GHz (Ch 36/40/44/48/52/56/60/64) 5.47 GHz to 5.725 GHz (Ch 100/104/108/112/116/120/124/128/132/136/140) 5.725 GHz to 5.825 GHz (Ch 149/153/157/161/165) FCC 5.15 GHz to 5.35 GHz (Ch 36/40/44/48/52/56/60/64) 5.47 GHz to 5.725 GHz (Ch 100/104/108/112/116/120/124/128/132/136/140/144) 5.725 GHz to 5.825 GHz (Ch 149/153/157/161/165) MIC (Japan) 5.15 GHz to 5.35 GHz (Ch 36/40/44/48/52/56/60/64) 5.47 GHz to 5.725 GHz (Ch 100/104/108/112/116/120/124/128/132/136/140) KC 5.15 GHz to 5.35 GHz (Ch 36/40/44/48/52/56/60/64) 5.47 GHz to 5.725 GHz (Ch 100/104/108/112/116/120/124) 5.725 GHz to 5.825 GHz (Ch 149/153/157/161/165)

5 GHz Operating Channels

(Wi-Fi) EU – 24 non-overlapping FCC – 25 non-overlapping MIC (Japan) – 19 non-overlapping KC – 20 non-overlapping

6.1.2 WLAN Modulation and Data Rate

802.11k, 802.11v Supported Wi-Fi Data Rates Support 802.11 ac/a/b/g/n 2X2 MIMO 802.11b (DSSS, CCK) 1, 2, 5.5, 11 Mbps 802.11a/g (OFDM) 6, 9, 12, 18, 24, 36, 48, 54 Mbps 802.11n (OFDM, HT20/HT40, MCS 0-15) 802.11ac (OFDM, HT20, MCS0-8; OFDM HT40/HT80, MCS 0-9) Modulation BPSK, QPSK, CCK, 16-QAM, 64-QAM, and 256-QAM. Details in the following table: 802.11ac HT MCS Index VHT MCS Index Spatial Streams Modulation Coding

20 MHz 40 MHz 80 MHz

802.11n No SGI SGI No SGI SGI No SGI SGI 1 1 1 QPSK 1/2 13 14.4 27 30 58.5 65 3 3 1 16-QAM 1/2 26 28.9 54 60 117 130 4 4 1 16-QAM 3/4 39 43.3 81 90 175.5 195 5 5 1 64-QAM 2/3 52 57.8 108 120 234 260 6 6 1 64-QAM 3/4 58.5 65 121.5 135 263.3 292.5 7 7 1 64-QAM 5/6 65 72.2 135 150 292.5 325 8 1 256-QAM 3/4 78 86.7 162 180 351 390 9 1 256-QAM 5/6 N/A N/A 180 200 390 433.3 8 0 2 BPSK 1/2 13 14.4 27 30 58.5 65 9 1 2 QPSK 1/2 26 28.9 54 60 117 130 10 2 2 QPSK 3/4 39 43.3 81 90 175.5 195

https://www.ezurio.com/ 20 © Copyright 2025 Ezurio All Rights Reserved 11 3 2 16-QAM 1/2 52 57.8 108 120 234 260 12 4 2 16-QAM 3/4 78 86.7 162 180 351 390 13 5 2 64-QAM 2/3 104 115.6 216 240 468 520 14 6 2 64-QAM 3/4 117 130.3 243 270 526.5 585 15 7 2 64-QAM 5/6 130 144.4 270 300 585 650 8 2 256-QAM 3/4 156 173.3 324 360 702 180 9 2 256-QAM 5/6 N/A N/A 360 400 780 866.7

6.1.3 WLAN Security

Wireless Equivalent Privacy (WEP) Wi-Fi Protected Access (WPA) WPA2-Personal WPA2-Enterprise WPA3-Personal WPA3-Enterprise SuiteB 192-bit Wireless Equivalent Privacy (WEP, RC4 Algorithm) Temporal Key Integrity Protocol (TKIP, RC4 Algorithm) Advanced Encryption Standard (AES CCM Algorithm) Encryption Key Provisioning Static (40-bit and 128-bit lengths) Pre-Shared (PSK) Dynamic 802.1X Extensible Authentication Protocol Types EAP-FAST EAP-TLS EAP-TTLS PEAP-GTC PEAP-MSCHAPv2 PEAP-TLS LEAP

6.1.4 WLAN TX Power and RX Sensitivity

Note: Transmit power on each channel varies according to individual country regulations. All values are nominal with +/-2 dBm tolerance at room temperature. Tolerance could be up to +/-2.5 dBm across operating temperature. Note: HT20 – 20 MHz-wide channels 802.11a

6 Mbps 18 dBm (63 mW)

54 Mbps 16 dBm (40 mW)

802.11b

1 Mbps 18 dBm (63 mW)

11 Mbps 18 dBm (63 mW)

802.11g

6.5 Mbps (MCS0-5/MCS8-13; HT20) 18 dBm (63 mW)

65 Mbps (MCS6-7/MCS14-15; HT20)

13.5Mbps (MCS0-5/MCS8-13; HT40) 135Mbps (MCS6-7/MCS14-15; HT40) 16 dBm (40 mW) 16 dBm (40 mW) 14 dBm (25 mW) 802.11ac (5 GHz) 6.5/13 Mbps (MCS0-6; Ntst=1,2; HT20) 18 dBm (63 mW)

https://www.ezurio.com/ 21 © Copyright 2025 Ezurio All Rights Reserved HT40 – 40 Mhz-wide channels HT80 – 80 MHz-wide channels 78/156 Mbps (MCS7-8; Ntst=1,2; HT20) 13.5/27Mbps (MCS0-6; Ntst=1,2; HT40) 180/360Mbps (MCS7-9; Ntst=1,2; HT40) 29.3/58.5 Mbps (MCS0-5; Ntst=1,2; HT80) 263.3/526.5 Mbps (MCS6-8; Ntst=1,2; HT80) 390/780 Mbps (MCS9; Ntst=1,2; HT80) 16 dBm (40 mW) 16 dBm (40 mW) 12 dBm (25 mW) 14 dBm (25 mW) 12 dBm (15.8 mW) 10 dBm (10 mW) Typical Receiver Sensitivity (PER <= 10%) Note: All values nominal, +/-3 dBm. Sensitivity on CH13/CH155 (WLAN); CH78 (BT) decades up to 4-6 dB. 802.11a:

6 Mbps -90 dBm

54 Mbps -74 dBm

802.11b:

1 Mbps -95 dBm

11 Mbps -90 dBm (PER<8%)

802.11g:

6 Mbps -91 dBm

54 Mbps -75 dBm

802.11n (2.4 GHz)

6.5 Mbps (MCS0; HT20) -91 dBm

65 Mbps (MCS7; HT20)

13.5Mbps (MCS0; HT40) 135Mbps (MCS7; HT40) -73 dBm -85 dBm -70 dBm 802.11n (5 GHz)

6.5 Mbps (MCS0; HT20) -89 dBm

13.5Mbps (MCS0; HT40) 135Mbps (MCS7; HT40) -70 dBm -86 dBm -69 dBm 802.11ac (5 GHz)

78 Mbps (MCS8; HT20)

13.5 Mbps (MCS0; HT40)

180 Mbps (MCS9; HT40)

29.3 Mbps (MCS0; HT80)

390/780 Mbps (MCS9; HT80) -67 dBm -86 dBm -63 dBm -81 dBm -55 dBm

6.2 Bluetooth

The 60-SOM includes a fully-integrated Bluetooth baseband/radio. Several features and functions are listed in Table 5. Table 5: Bluetooth functions Feature Description Bluetooth Interface • Voice interface: – Hardware support for continual PCM data transmission/reception without processor overhead – Standard PCM clock rates from 64 kHz to 2.048 MHz with multi-slot handshake and synchronization – A-law, U-law, and linear voice PCM encoding/decoding

High-speed UART interface

Bluetooth 5.1
Bluetooth Class 1
WLAN and Bluetooth share same LNA and antenna
Digital audio interfaces with PCM/TDM interface for voice application
Baseband and radio BDR and EDR package type: 1 Mbps, 2 Mbps, 3 Mbps
Fully functional Bluetooth baseband: AFH, forward error correction, header error control, access code correction, CRC, encryption bit stream generation, and whitening
Adaptive Frequency Hopping (AFH) using Packet Error Rate (PER)
Interlaced scan for faster connection setup
Simultaneous active ACL connection setup
Automatic ACL package type selection
Full master and slave piconet support
Scatter net support
SCO/eSCO links with hardware accelerated audio signal processing and hardware supported PPEC algorithm for speech quality improvement
All standard SCO/eSCO voice coding
All standard pairing, authentication, link key, and encryption operations
Encryption (AES) support BLE Core Functionality • Advertiser, scanner, initiator, master, and slave roles support (connects up to 16 links)
WLAN/Bluetooth coexistence (BCA) protocol support
Shared RF with BDR/EDR
Encryption (AES) support
Intelligent Adaptive Frequency Hopping (AFH)
LE privacy 1.2
LE secure connection
LE data length extension
LE advertising length extension
2vMbps LE

6.2.1 Bluetooth Specification

Bluetooth Media Frequency Hopping Spread Spectrum (FHSS) Bluetooth Standards Bluetooth 5.1 (Bluetooth Low Energy or BLE) Supported Bluetooth Data Rates 1, 2, 3 Mbps Bluetooth Modulation GFSK@ 1 Mbps Pi/4-DQPSK@ 2 Mbps 8-DPSK@ 3 Mbps Regulatory Domain Support FCC EU ISED Canada MIC (Japan) KC (Korea) 2.4 GHz Frequency Bands 2.4 GHz to 2.483 GHz Transmit Power Note: Transmit power on each channel varies according to individual country regulations. All values are nominal with +/-2 dBm tolerance at Bluetooth 1 Mbps (1DH5) 10 dBm (12.5 mW) 2 Mbps 7 dBm (6.3 mW) 3 Mbps 7 dBm (6.3 mW)

https://www.ezurio.com/ 23 © Copyright 2025 Ezurio All Rights Reserved room temperature. Tolerance could be up to +/-2.5 dBm across operating temperature. BLE (1 Mbps) 7 dBm (6.3 mW) Typical Receiver Sensitivity (PER <= 10%) Note: All values nominal, +/-3 dBm. Note: Sensitivity on CH13 (WLAN)/CH78 (BT) will decade up to 4-6dB. Bluetooth:

1 Mbps (1DH5)

2 Mbps (2DH5)

-95 dBm -94 dBm

3 Mbps (3DH5) -88 dBm

7 Module Specification

Physical Interface Two-row LGA SMD type with 1.0 mm pin pitch Ethernet Interface X1, 10/100 Mbps Reduced Media Independent Interface (RMII) X1, 10/100/1000 Mbps Reduced Gigabit Media Independent Interface (RGMII) Asynchronous Serial Port Interfaces X3, Four-wire UART with hardware handshaking (up to 921,600 baud) Note: UART2/UART3 are for 1.8V only. SPI Interface X2, master and slave modes supported with multiple chip select pins CAN bus X1, CAN bus, fully compliant with CAN 2.0 Part A and 2.0 Part B USB Interfaces X1, USB device port with high speed/full speed/low speed data rates X2, USB host ports with high speed/full speed/low speed data rates SD/eMMC interface X1, High-speed multimedia card data Two Wire Interface X1, Two-wire I2C The other two-wire interface is multiplexed with SPI bus Debug Interface X1, Two-wire UART (console) for debug purpose Digital GPIO X6, Digital General Purpose I/O (GPIO) Analog-to-Digital Converter – ADC X6, Analog-to-Digital converter for touch panel Audio interface X1, Synchronous Serial Controller (SSC) Video interface X1, 24-bits TTL RGB LCD display interface PCM interface 13-bit or 16-bit linear, 8-bit μ-law or A-law compounded sample formats for Bluetooth Antenna Interface Two Hirose U.FL connectors for Wi-Fi (Main/AUX) and BT (AUX only) separately, 50 ohm Wi-Fi Interface Marvell 88W8997 2x2 802.11a/b/g/n/ac on 20/40/80 MHz bandwidth Bluetooth Interface Marvell 88W8997 Bluetooth 5.1 dual-mode (EDR+BLE) Operating System Embedded Ezurio Linux Memory 128 MB (1 Gb) and 256 MB (2 Gb) of LPDDR1 or LPDDR2 DRAM Storage 256 MB (2Gb) and 512 MB (4 Gb) SLC NAND flash Input Voltage Requirements VDD_BU; VDDIOP0; VDDIOP1: 3.3V+/-10% or 1.8V+/-0.15V VCC3_3; WIFI_3V3: 3.3V+/-10% Note: Keep regulated voltage ripple less than 30 mV. Operating Temperature -30° to +85°C (-22°F to 185°F) Operating Humidity 10 to 90% (non-condensing) Storage Temperature -40° to 85°C (-40° to 185°F) Storage Humidity 10 to 90% (non-condensing) Maximum Electrostatic Discharge Conductive 8 kV; Air coupled 12 kV follow EN61000-4-2 Size 30 mm (length) x 30 mm (width) x 2.8 mm (thickness) Weight 5.0 g

https://www.ezurio.com/ 25 © Copyright 2025 Ezurio All Rights Reserved Wireless Equivalent Privacy (WEP) Wi-Fi Protected Access (WPA) WPA2-Personal WPA2-Enterprise WPA3-Personal WPA3-Enterprise SuiteB 192-bit Encryption Wireless Equivalent Privacy (WEP, RC4 Algorithm) Temporal Key Integrity Protocol (TKIP, RC4 Algorithm) Advanced Encryption Standard (AES CCM Algorithm) Encryption Key Provisioning Static (40-bit and 128-bit lengths) Pre-Shared (PSK) Dynamic 802.1X Extensible Authentication Protocol Types EAP-FAST EAP-TLS EAP-TTLS PEAP-GTC PEAP-MSCHAPv2 PEAP-TLS LEAP Compliance EU Regulatory EN 300 328 EN 301 489-1 EN 301 489-17 EN 301 893 EN 300 440 62311:2008 EN 50665:2017 EN 50385:2017 EU 2015/863 (RoHS 3) FCC Regulatory ISED Canada 47 CFR FCC Part 15.247 47 CFR FCC Part 15.407 47 CFR FCC Part 2.1091 FCC Part 15 Subpart B Class B ICES-003 ANSI C63.4:2014 RSS-102 RSS-247 AS/NZS Regulatory AS/NZS 2772.2:2011 AS/NZS 4268:2017 Certifications Bluetooth® SIG Qualification Warranty One Year Warranty All specifications are subject to change without notice

8 Electrical Characteristics

8.1 Absolute Maximum Ratings

Table 6 summarizes the absolute maximum ratings and Table 7 lists the recommended operating conditions for the 60-SOM. Absolute maximum ratings are those values beyond which damage to the device can occur. Functional operation under these conditions, or at any other condition beyond those indicated in the operational sections of this document, is not recommended. Note: Maximum rating for signals follows the supply domain of the signals. Table 6: Absolute maximum ratings Symbol (Domain) Parameter Max Rating Unit VCC3_3 DC 3.3V input for the module 4.0 V WIFI_3V3 3.3V Power Supply for Wi-Fi SIP on the module (for 1.8V system) (for 3.3V system) 4.0 V VDD_BU Backup Power for RTC mode 4.0 V VDDIOP0 VDDIOP1 I/O configuration power supply (for 1.8V system) (for 3.3V system) 2.2 4.0 V Storage Storage Temperature -40 to +85 °C Voltage on Input Pins With respect to Ground VDDIO+0.3 (4.0 max) V ANT0; ANT1 Maximum RF input (reference to 50-Ω input) +10 dBm

8.2 Recommended Operating Conditions

Table 7: Recommended operating conditions Symbol (Domain) Parameter Min Typ Max Unit VCC3_3; WIFI_3V3 External 3.3V power supply 3.0 3.30 3.6 V VDD_BU; VDDIOP0; VDDIOP1 T-ambient Ambient temperature -30 25 85 °C

8.3 DC Electrical Characteristics

Table 8 lists the general DC electrical characteristics over recommended operating conditions (unless otherwise specified). Table 8: General DC electrical characteristics Symbol Parameter Conditions Min Typ Max Unit VIL Input Low-level Voltage VDDIOPx in 3.3V range -0.3 - 0.8 V VDDIOPx in 1.8V range -0.3 - 0.54 VIH Input High-level Voltage VDDIOPx in 3.3V range 2.4 - 3.6 V VDDIOPx in 1.8V range 1.26 - 2.1 Vhys Schmitt trigger Hysteresis VDDIOPx in 3.3V range 0.34 - - V VDDIOPx in 1.8V range 0.21 - - VOL Output Low-level Voltage IO Max - - 0.4 V VOH Output High-level Voltage IO Max VDDIOP-0.4 - - V RPULL VDDIOPx in 3.3V range 45 70 130 kΩ

https://www.ezurio.com/ 27 © Copyright 2025 Ezurio All Rights Reserved Symbol Parameter Conditions Min Typ Max Unit Pull-up/Pull-down Resistance VDDIOPx in 1.8V range 100 160 310 IO Output Current VDDIOPx in 3.3V range 8 (LO_DRIVE) (ME_DRIVE) (HI_DRIVE) mA VDDIOPx in 1.8V range 5 (LO_DRIVE) (ME_DRIVE) (HI_DRIVE) SCK_1/GETH_INT; 3 (LO_DRIVE) (ME_DRIVE) (HI_DRIVE) RS Series Resistor VBUS_SENSE - 30 - Ω SCK_1/GETH_INT - 13 -

8.4 Power Consumption

Table 9 and Table 10 show the power consumption of the 60-SOM when transmitting in 2.4 GHz and 5 GHz modes. Table 9: WLAN transmitter characteristics for 2.4 GHz per chain operation Freq. Mode/Rate (Mbps) Output Power Per Stream (dBm) Typical Current Consumption Single Stream (mA)8 Max. Current Consumption Dual Stream (mA)8

2417 MHz 1 Mbps 18 dBm 550 1050

54 Mbps 16 dBm 450 820

2442 MHz

1 Mbps 18 dBm 550 1050

54 Mbps 16 dBm 460 820

Table 10: WLAN current consumption on 5 GHz Freq. Mode/Rate [Mbps] Output Power Per Stream [dBm] Typical Current Consumption Single Stream (mA) Typical Current Consumption Dual Stream (mA)

5200 MHz

5190 MHz

6 Mbps 18 dBm 580 1100

54 Mbps 16 dBm 520 970

5600 MHz

5510 MHz

6 Mbps 18 dBm 600 1200

54 Mbps 16 dBm 530 970

https://www.ezurio.com/ 28 © Copyright 2025 Ezurio All Rights Reserved Freq. Mode/Rate [Mbps] Output Power Per Stream [dBm] Typical Current Consumption Single Stream (mA) Typical Current Consumption Dual Stream (mA)

5825 MHz

5795 MHz

6 Mbps 18 dBm 590 1150

54 Mbps 16 dBm 520 980

Note: Final TX power values on each channel are limited by the regulatory certification test limit.

9 Interface Specifications

9.1 Ethernet

There are two Ethernet interfaces available on the 60-SOM that support RMII (10/100) and RGMII (10/100/1000) to comply with IEEE Standard 802.3.

9.2 Display Interface LCD

The LCD interface on 60-SOM transfers the LCD image data to an LCD display module. The LCD is programmable on a per overlay basis and supports different LCD resolutions, window sizes, image formats, and pixel depths. The following is a list of features:

Dual AHB master interface
Supports Single Scan Active TFT display
Supports 12-, 16-, 18-, and 24-bit output mode through the spatial dithering unit
Supports asynchronous output mode (at synthesis time)
1, 2, 4, 8 bits per pixel (palletized)
12, 16, 18, 19, 24, 25, and 32 bits per pixel (non-palletized)
Supports one base layer (background)
Supports two overlay layer windows
Supports one high end overlay (HEO) window
Supports one hardware cursor, fixed or free size
Hardware cursor fixed size on the following patterns: 32 x 32, 64 x 64, and 128 x 128
Little Endian Memory Organization
Programmable timing engine, with integer clock divider
Programmable polarity for data, line synchro and frame synchro
Display size up to 2048 x 2048 or up to 720 p in video format
Color lookup table with up to 256 entries and predefined 8-bit Alpha
Programmable negative and positive row striding for all layers
Programmable negative and positive pixel striding for all overlay1, overlay2, and HEO Layers
High-end overlay supports 4:2:0 planar mode and semi-planar mode
High-end overlay supports 4:2:2 planar mode, semi-planar mode and packed
High-end overlay includes chroma oversampling unit
Horizontal and vertical rescaling unit with edge interpolation and independent non-integer ratio
Hidden layer removal supported
Integrates fully-programmable color space conversion
Overlay1, Overlay2, and high-end Overlay Integrate Rotation Engine: 90, 180, 270
Blender function supports arbitrary 8-bit alpha value and chroma keying
DMA user interface uses linked list structure and add-to-queue structure Table 11 shows the I/O lines description of the LCD bus.

https://www.ezurio.com/ 29 © Copyright 2025 Ezurio All Rights Reserved Table 11: I/O lines description Name Description Type LCD_PWM Contrast control signal using pulse width modulation Output LCD_HSYNC Horizontal synchronization pulse Output LCD_VSYNC Vertical synchronization pulse Output LCD_DAT[23:0] LCD 24-bit data bus Output LCD_DEN Data enable Output LCD_DISP Display enable signal Output LCD_PCLK Pixel clock Output

9.3 Audio Interface (Synchronous Serial Controller)

The Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, and Long Frame Sync. The SSC contains an independent receiver and transmitter and a common clock divider. Both the receiver and the transmitter interface with three signals:

TD/RD signal for data
TK/RK signal for the clock
TF/RF signal for the Frame Sync. The transfers can be programmed to start automatically or on different events detected on the Frame Sync signal. Table 12: SSC I/O lines description Name Description Type RF Receiver Frame Synchro Input/Output RK Receiver Clock Input/Output RD Receiver Data Input TF Transmitter Frame Synchro Input/Output TK Transmitter Clock Input/Output TD Transmitter Data Output Typical application block diagram of SSC bus is shown in Figure 6. Figure 6: Typical application block diagram of SSC bus

9.4 High Speed Multimedia Card Interface

The high-speed Multimedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD memory card specification V2.0, and the SDIO V2.0 specification. The SD memory card communication is based on a nine-pin interface (clock, command, four data, and three power lines) and the high-speed MMC on a seven-pin interface (clock, command, one data, three power lines, and one reserved for future use). The SD memory card interface also supports high-speed MMC operations. The main differences between SD and high-speed MultiMedia cards are the initialization process and the bus topology. Table 13: HSMCI I/O lines description Name Description Type Comments MC_CDA Command/Response I/O/PP/OD CMD of an MMC or SD Card/SDIO MC_CK Clock I/O CLK of an MMC or SD Card/SDIO MC_DA0–MC_DA7 Data 0..7 I/O/PP DAT[0..7] of an MMC DAT[0..3] of an SD Card/SDIO

9.5 Serial Peripheral Interface (SPI)

The SPI system consists of two data lines and two control lines:

Master Out/Slave In (SPI_MOSI) – This data line supplies the output data from the master shifted into the input(s) of the slave(s).
Master In/Slave Out (SPI_MISO) – This data line supplies the output data from a slave to the input of the master. There may be no more than one slave transmitting data during any particular transfer.
Serial Clock (SPI_CLK)—This control line is driven by the master and regulates the flow of the data bits. The master can transmit data at a variety of baud rates; there is one SPI_CLK pulse for each bit that is transmitted.
Slave Select (SPI_NPCS)—This control line allows slaves to be turned on and off by hardware. Table 14: SPI I/O lines descriptions Name Description Type Master Slave SPIx_MISO Master in/Slave out Input Output SPIx_MOSI Master out/Slave in Output Input SPIx_CLK Serial clock Output Input SPIx_NPCS[1-3] Peripheral chip selects Output Unused SPI1_NPCS0 Peripheral chip select/slave select Output Input Typical application block diagram of SPI bus is shown in Figure 7.

9.6 Can Bus Interface

The CAN bus offers optimized features to support the Time Triggered Communication (TTC) protocol.

Fully compliant with CAN 2.0 Part A and 2.0 Part B
Bit rates up to one Mbit/second
Eight object-oriented mailboxes with the following properties: – CAN Specification 2.0 Part A or 2.0 Part B programmable for each message – Object configurable in receive (with overwrite or not) or transmit modes – Independent 29-bit identifier and mask defined for each mailbox – 32-bit access to data registers for each mailbox data object – Uses a 16-bit timestamp on receive and transmit messages – Hardware concatenation of ID masked bitfields to speed up family ID processing
16-bit internal timer for timestamping and network synchronization
Programmable reception buffer length up to eight mailbox objects
Priority management between transmission mailboxes
Autobaud and listening mode
Low-power mode and programmable wake-up on bus activity or by the application
Data, remote, error and overload frame handling
Register write protection Table 15: Can bus interface I/O lines description Name Description Type CAN_TX1 CAN Receive Serial Data Input CAN_RX1 CAN Transmit Serial Data Output

9.7 Two-Wire Interface (TWI)

The Atmel/Microchip two-wire interface (TWI) interconnects components on a unique two-wire bus. It is made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel/Microchip two-wire interface bus Serial EEPROM and I²C compatible device such as a Real Time Clock (RTC), dot matrix/graphic LCD controllers, and temperature sensor. The TWI is programmable as a master or a slave with sequential or single-byte access. Multiple master capability is supported. Table 16 lists the compatibility level of the Atmel/Microchip two-wire Interface in Master mode and a full I2C compatible device.

https://www.ezurio.com/ 32 © Copyright 2025 Ezurio All Rights Reserved Table 16: Atmel/Microchip TWI compatibility with I2C standard I2C Standard Atmel/Microchip TWI Standard mode speed (100 kHz) Supported Fast mode speed (400 kHz) Supported 7- or 10-bit slave addressing Supported START byte(1) Not Supported Repeated start (Sr) condition Supported ACK and NACK management Supported Slope control and input filtering (fast mode) Not Supported Clock stretching/synchronization Supported Multi Master Capability Supported Note 1: START + b000000001 + Ack + Sr Table 17: TWI I/O lines description Name Description Type TW_D Two-wire Serial Data (drives external serial data line – SDA) Input/Output TW_CLK Two-wire Serial Clock (drives external serial clock line – SCL) Input/Output

9.8 Analog-to-Digital Converter (ADC)

There are six analog input channels available on the 60-SOM. The analog power supply (VDDANA) and the reference voltage (ADVREF) are set to 3.3V on the module. Analog inputs between these voltages (3.3V) convert to values based on a linear conversion. Software trigger, external trigger on rising edge of the ADTRG pin or internal triggers from Timer Counter output(s) are configurable. Table 18: ADC I/O lines description Name Description Type AD0 Analog input channels (Upper-left touch panel) Analog AD1 Analog input channels (Upper-right touch panel) Analog AD2 Analog input channels (Lower-left touch panel) Analog AD3 Analog input channels (Lower-right touch panel) Analog AD4 Analog input channels (Panel input) Analog AD5 Analog input channels Analog ADTRG External trigger Input

10 Mechanical Specifications

The 60-SOM measures 30 x 30 x 2.8 mm. Detail drawings are shown in Figure 8. Figure 8: Mechanical Details Note: The Wi-Fi MAC address is located on the product label. The last digit of the Wi-Fi MAC address is assigned to end with either 0, 4, 8, or C. The BT MAC address is the Wi-Fi MAC address plus 3. The 10/100 Ethernet LAN MAC (ELAN) address is also shown in the label on the 60-SOM. The other 10/100/1000 Giga-bits Ethernet LAN MAC address is the 10/100 Ethernet LAN MAC address plus 1.

https://www.ezurio.com/ 34 © Copyright 2025 Ezurio All Rights Reserved Figure 9: PCB footprint recommendation for 60-SOM Recommended landing pad for the 60-SOM. More ground via and the use of 1-oz copper is recommended in our design to get better thermal dissipation. Note: The stencil thickness should be ≥ 0.1 mm and adjust the opening size/ratio and the SMT reflow thermal profile accordingly to minimize the void (less than 30% according to IPC standard) in the landing pad as possible.

11 Assembly Instructions

11.1 Required Storage Conditions

11.1.1 Prior to Opening the Dry Packing

The following are required storage conditions prior to opening the dry packing:

Normal temperature: 5~40℃
Normal humidity: 80% (Relative humidity) or less
Storage period: One year or less Note: Humidity refers to relative humidity.

11.1.2 After Opening the Dry Packing

The following are required storage conditions after opening the dry packing (to prevent moisture absorption):

Storage conditions for one-time soldering: – Temperature: 5~25℃ – Humidity: 60% or less – Period: 72 hours or less after opening
Storage conditions for two-time soldering Storage conditions following opening and prior to performing the 1st reflow: – Temperature: 5~25℃ – Humidity: 60% or less – Period: 48 hours or less after opening Note: This module only allows one time reflow process. Applying more than one time reflow will cause damage.

11.1.3 Temporary Storage Requirements after Opening

The following are temporary storage requirements after opening:

Put the device back to dry packing immediately when it is not used.
Use a dry box or place desiccant (with a blue humidity indicator) with the devices and perform dry packing again using heat -sealing. The following indicate the required storage period, temperature, and humidity for this temporary storage: Storage temperature and humidity *** - External atmosphere temperature and humidity of the dry packing Storage period
X1+X2 – Refer to After Opening the Dry Packing storage requirements. Keep is X1+X2 within 72 hours.
Y – Two weeks or less Temperature: 5-40°C Humidity: 80% or less Temperature: 5-25°C *Humidity: 60% or less Temperature: 5-40°C *Humidity: 80% or less Temperature: 5-25°C Humidity: 60% or less

11.2 Baking Conditions

Baking conditions and processes for the 60-SOM follow the J-STD-033 standard which includes the following:

The calculated shelf life in a sealed bag is 12 months at <40℃ and <80% relative humidity.
Once the packaging is opened, the 60-SOM must be mounted (according to MSL4/Moisture Sensitivity Level 4) within 72 hours at <30℃ and <60% relative humidity according to IPC/JEDEC J-STD -033C.
If the 60-SOM is not mounted within 72 hours or if, when the packaging is opened, the humidity indicator card displays >10% humidity, then the product must be baked for 48 hours at 125℃ (±5℃).

11.3 Module Washing and Cleaning

In general, cleaning the populated modules is strongly discouraged. Residuals under the module cannot be easily removed with any cleaning process. Module appearance may be changed after cleanin g process as well.

11.4 Surface Mount Conditions

The following soldering conditions are recommended to ensure device quality. You must adjust for your platform PCB size, thickness of stencil, and the solder paste you use to get optimized solder quality.

11.4.1 Soldering

Convection reflows or IR/Convection reflow (one-time soldering or two-time soldering in air or nitrogen environment)

Measuring point – IC package surface
Temperature profile: Pin

11.4.2 Cautions on Removing the 60-SOM from the Platform for RMA

Bake the platform before removing the Wi-Fi/BT SIP from the platform. Reference baking conditions.
Remove the Wi-Fi/BT SIP by using a hot air gun. This process should be carried out by a skilled technician. Suggestion conditions:
One-side component platform: – Set the hot plate at 280°C. – Put the platform on the hot plate for 8~10 seconds. – Remove the SIP from platform.
Two-side components platform: – Use two hot air guns – On the bottom side, use a pre-heated nozzle (temperature setting of 200~250°C) at a suitable distance from the platform PCB. – On the top side, apply a remove nozzle (temperature setting of 330°C). Heat the SIP until it can be removed from platform PCB.
Remove the residue solder under the bottom side of 60-SOM. (Not accepted for RMA) (Accepted for RMA analysis) With residue solder on the bottom Without residue solder on the bottom
Remove and clean the residue flux is needed. Pre-heat Nozzle Platform PCB SIP Remove Nozzle

11.4.3 Precautions for Use

Opening/handing/removing must be done on an anti-ESD treated workbench. All workers must also have undergone anti-ESD treatment. The devices should be mounted within one year of the date of delivery.

12 Regulatory

Note: For complete regulatory information, refer to the 60 Series SOM Regulatory Information document which is also available from the 60 Series SOM product page. The 60-SOM holds current certifications in the following countries: Country/Region Regulatory ID USA (FCC) SQG-SU60SOMC EU N/A Canada (ISED) 3147A-SU60SOMC MIC 003-180100 Part Number Description 453-00137 60 Series SOM using 1 Gb LPDDR2 RAM and 2 Gb NAND flash 453-00138 60 Series SOM using 2 Gb LPDDR2 RAM and 4 Gb NAND flash 453-00003 60 Series SOM using 1 Gb LPDDR1 RAM and 2 Gb NAND flash 453-00004 60 Series SOM using 2 Gb LPDDR1 RAM and 4 Gb NAND flash 453-00137-K1 Development Board for the 60 Series SOM using 1 Gb LPDDR2 RAM and 2 Gb NAND flash 453-00138-K1 Development Board for the 60 Series SOM using 2 Gb LPDDR2 RAM and 4 Gb NAND flash 455-00003 Development Board for the 60 Series SOM using 1 Gb LPDDR1 RAM and 2 Gb NAND flash 455-00039 Development Board for the 60 Series SOM using 2 Gb LPDDR1 RAM and 4 Gb NAND flash 455-00004 LCD Touchscreen for the 60 Series SOM development board (add-on)

14 Bluetooth SIG Qualification

14.1 Overview

The Bluetooth Qualification Process promotes global product interoperability and reinforces the strength of the Bluetooth® brand and ecosystem to the benefit of all Bluetooth SIG members. The Bluetooth Qualification Process helps member companies ensure their products that incorporate Bluetooth technology comply with the Bluetooth Patent & Copyright License Agreement and the Bluetooth Trademark License Agreement (collectively, the Bluetooth License Agreement) and Bluetooth Specifications. The Bluetooth Qualification Process is defined by the Qualification Program Reference Document (QPRD) v3. To demonstrate that a product complies with the Bluetooth Specification(s), each member must for each of its products:

Identify the product, the design included in the product, the Bluetooth Specifications that the design implements, and the fe atures of each implemented specification
Complete the Bluetooth Qualification Process by submitting the required documentation for the product under a user account be longing to your company The Bluetooth Qualification Process consists of the phases shown below: To complete the Qualification Process the company developing a Bluetooth End Product shall be a member of the Bluetooth SIG. To start the application please use the following link: Apply for Adopter Membership

14.2 Scope

This guide is intended to provide guidance on the Bluetooth Qualification Process for End Products that reference multiple ex isting designs, that have not been modified, (refer to Section 3.2.2.1 of the Qualification Program Reference Document v3). For a Product that includes a new Design created by combining two or more unmodified designs that have DNs or QDIDs into one of the permitted combinations in Table 3.1 of the QPRDv3, a Member must also provide the following information:

DNs or QDIDs for Designs included in the new Design
The desired Core Configuration of the new Design (if applicable, see Table 3.1 below)
The active TCRL Package version used for checking the applicable Core Configuration (including transport compatibility) and e valuating test requirements Any included Design must not implement any Layers using withdrawn specification(s). When creating a new Design using Option 2a, the Inter-Layer Dependency (ILD) between Layers included in the Design will be checked based on the latest TCRL Package version used among the included Designs. For the purposes of this document, it is assumed that the member is combining unmodified Core-Controller Configuration and Core-Host Configuration designs, to complete a Core-Complete Configuration.

14.3 Qualification Steps When Referencing multiple existing designs, (unmodified) –

For this qualification option, follow these steps: 1. To start a listing, go to: https://qualification.bluetooth.com/ 2. Select Start the Bluetooth Qualification Process. 3. Product Details to be entered:

Project Name (this can be the product name or the Bluetooth Design name).
Product Description
Model Number

Product Publication Date (the product publication date may not be later than 90 days after submission)
Product Website (optional)
Internal Visibility (this will define if the product will be visible to other users prior to publication) ▪ If you have multiple End Products to list then you can select ‘Import Multiple Products’, firstly downloading and completing the template, then by ‘Upload Product List’. This will populate Qualification Workspace with all your products. 4. Specify the Design:
Do you include any existing Design(s) in your Product? Answer Yes, I do.
Enter the multiple DNs or QDIDs used in your, (for Option 2a two or more DNs or QDIDs must be referenced)
Select ‘I’m finished entering DN’s
Once the DNs or QDIDs are selected they will appear on the left-hand side, indicating the layers covered by the design (should show Core-Controller and Core Host Layers covered).
What do you want to do next? Answer, ‘Combine unmodified Designs’.
The Qualification Workspace Tool will indicate that a new Design will be created and what type of Core-Complete configuration is selected.
An active TCRL will be selected for the design.
Perform the Consistency Check, which should result in no inconsistencies
If there are any inconsistencies these will need to be resolved before proceeding
Save and go to Test Plan and Documentation 5. Test Plan and Documentation a. As no modifications have been made to the combined designs the tool should report the following message: ‘No test plan has been generated for your new Design. Test declarations and test reports do not need to be submitted. You can continue to the next step.’ b. Save and go to Product Qualification fee 6. Product Qualification Fee: ▪ It’s important to make sure a Prepaid Product Qualification fee is available as it is required at this stage to complete the Qualification Process. ▪ Prepaid Product Qualification Fee’s will appear in the available list so select one for the listing. ▪ If one is not available select ‘Pay Product Qualification Fee’, payment can be done immediately via credit card, or you can p ay via Invoice. Payment via credit will release the number immediately, if paying via invoice the number will not be released until the invoice is paid. ▪ Once you have selected the Prepaid Qualification Fee, select ‘Save and go to Submission’ 7. Submission:
Some automatic checks occur to ensure all submission requirements are complete.
To complete the listing any errors must be corrected
Once you have confirmed all design information is correct, tick all of the three check boxes and add your name to the signatu re page.
Now select ‘Complete the Submission’.
You will be asked a final time to confirm you want to proceed with the submission, select ‘Complete the Submission’.
Qualification Workspace will confirm the submission has been submitted. The Bluetooth SIG will email confirmation once the submission has been accepted, (normally this takes 1 working day). 8. Download Product and Design Details (SDoC): a. You can now download a copy of the confirmed listing from the design listing page and save a copy in your Compliance Folder For further information, please refer to the following webpage: https://www.bluetooth.com/develop-with-bluetooth/qualification-listing/

14.4 Example Design Combinations

The following gives an example of a design possible under option 2a: Ezurio Controller Subsystem + BlueZ 5.50 Host Stack (Ezurio 60 Series based design) Design Name Owner Declaration ID QD ID Link to listing on the SIG website 60-SIPT/60-2230/60-SOM Ezurio D046328 137590 https://qualification.bluetooth.com/ListingDetails/93157 BlueZ 5.50 Host Stack Ezurio D046330 138224 https://qualification.bluetooth.com/ListingDetails/93911

14.5 Qualify More Products

If you develop further products based on the same design in the future, it is possible to add them free of charge. The new p roduct must not modify the existing design i.e add ICS functionality, otherwise a new design listing will be required. To add more products to your design, select ‘Manage Submitted Products’ in the Getting Started page, Actions, Qualify More Products. The tool will take you through the updating process.

15 Additional Information

Please contact your local sales representative or our support team for further assistance: Headquarters Ezurio 50 S. Main St. Suite 1100 Akron, OH 44308 USA Website http://www.ezurio.com Technical Support http://www.ezurio.com/resources/support Sales Contact http://www.ezurio.com/contact Note: Information contained in this document is subject to change. Ezurio’s products are subject to standard Terms & Conditions. © Copyright 2025 Ezurio All Rights Reserved. Any information furnished by Ezurio and its agents is believed to be accurate but cannot be gua ranteed. All specifications are subject to change without notice. Responsibility for the use and application of Ezurio materials or products rests with the end user since Ezurio and its agents cannot be aware of all potential uses. Ezurio makes no warrant ies as to non-infringement nor as to the fitness, merchantability, or sustainability of any Ezurio materials or products for any specific or general uses. Ezurio or any of its affiliates or agents shall not be liable for incidental or consequential damages of any kind. All Ezurio products are sold pursuant to the Ezurio Terms and Conditions of Sale in effect from time to time, a copy of which will be furnished upon request. Nothing herein provides a license under any Ezurio or any third -party intellectual property right. Ezurio and its associated logos are trademarks owned by Ezurio and/or its affiliates.

Product Information

453-00137 specifications and overview.

Summary

60 Series SOM 16 Apr 2025 Version 4.0

Description

60 Series SOM 16 Apr 2025 Version 4.0

Source title 453-00137 Datasheet(PDF) - Ezurio

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60-SOM EZURIO | Alldatasheet

Document overview

Technical content

60 Series SOM

Revision History

description

Contents

1 Scope

2 Introduction

2.1 General Description

2.2 Features and Functionality

2.3 Block Diagram

3 Pin Definitions and Signal Descriptions

4 Power Consideration

4.1 Power Supply

4.2 Power on Sequence

4.3 Power Down Sequence

5 Booting

5.1 Initial Boot or Failure Recovery Boot

5.2 Force Boot from Atmel/Microchip SAM-BA

5.3 Secure Boot Provisioning

6 Wireless Interface

6.1.1 WLAN RF Channels and Regulatory Domains

2.4 GHz Operating Channels

5 GHz Frequency Bands EU

5 GHz Operating Channels

6.1.2 WLAN Modulation and Data Rate

20 MHz 40 MHz 80 MHz

6.1.3 WLAN Security

6.1.4 WLAN TX Power and RX Sensitivity

6 Mbps 18 dBm (63 mW)

54 Mbps 16 dBm (40 mW)

1 Mbps 18 dBm (63 mW)

11 Mbps 18 dBm (63 mW)

6.5 Mbps (MCS0-5/MCS8-13; HT20) 18 dBm (63 mW)

65 Mbps (MCS6-7/MCS14-15; HT20)

6 Mbps -90 dBm

54 Mbps -74 dBm

1 Mbps -95 dBm

11 Mbps -90 dBm (PER<8%)

6 Mbps -91 dBm

54 Mbps -75 dBm

6.5 Mbps (MCS0; HT20) -91 dBm

65 Mbps (MCS7; HT20)

6.5 Mbps (MCS0; HT20) -89 dBm

78 Mbps (MCS8; HT20)

13.5 Mbps (MCS0; HT40)

180 Mbps (MCS9; HT40)

29.3 Mbps (MCS0; HT80)

6.2 Bluetooth

6.2.1 Bluetooth Specification

1 Mbps (1DH5)

2 Mbps (2DH5)

3 Mbps (3DH5) -88 dBm

7 Module Specification

8 Electrical Characteristics

8.1 Absolute Maximum Ratings

8.2 Recommended Operating Conditions

8.3 DC Electrical Characteristics

8.4 Power Consumption

2417 MHz 1 Mbps 18 dBm 550 1050

54 Mbps 16 dBm 450 820

2442 MHz

1 Mbps 18 dBm 550 1050

54 Mbps 16 dBm 460 820

5200 MHz

5190 MHz

6 Mbps 18 dBm 580 1100

54 Mbps 16 dBm 520 970

5600 MHz

5510 MHz

6 Mbps 18 dBm 600 1200

54 Mbps 16 dBm 530 970

5825 MHz

5795 MHz

6 Mbps 18 dBm 590 1150

54 Mbps 16 dBm 520 980

9 Interface Specifications