4519

4519 RENESAS | Alldatasheet

Document overview

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Technical content

DESCRIPTION

The 4519 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with serial interface, four 8-bit timers (each timer has one or two reload registers), a 10-bit A/D converter, interrupts, and oscillation circuit switch function. The various microcomputers in the 4519 Group include variations of the built-in memory size as shown in the table below.

FEATURES

(at 6 MHz oscillation frequency, in XIN through-mode) G Supply voltage (It depends on operation source clock, oscillation frequency and op- eration mode) G Timers Part number M34519M6-XXXFP M34519M8-XXXFP M34519E8FP ( Note) ROM type Mask ROM Mask ROM One Time PROM Package 42P2R-A 42P2R-A 42P2R-A RAM size (✕ 4 bits) 384 words 384 words 384 words ROM (PROM) size (✕ 10 bits) 6144 words 8192 words 8192 words G Voltage drop detection circuit G Watchdog timer G Clock generating circuit (ceramic resonator/RC oscillation/quartz-crystal oscillation/on- chip oscillator) G LED drive directly enabled (port D) APPLICATION Electrical household appliance, consumer electronic products, of- fice automation equipment, etc. Note: Shipped in blank. PIN CONFIGURATION Pin configuration (top view) (4519 Group) OUTLINE 42P2R-A M34519Mx-XXXFP M34519E8FP8 P12 P11 P10 P03 P02 P01 P00 P43/AIN7 P42/AIN6 P41/AIN5 P40/AIN4 P63/AIN3 P62/AIN2 P61/AIN1 P60/AIN0 P33 P32 P31/INT1 P30/INT0 VDCE V DD P13 D 0 D 1 D 2 D 3 D 4 D 5 D 6/CNTR0 D 7/CNTR1 P50 P51 P52 P53 P20/SCK P21/SOUT P22/SIN RESET CNV SS XOUT XIN VSS Rev.3.01 2005.06.15 page 1 of 160 REJ03B0007-0301

4519 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER REJ03B0007-0301 Rev.3.01 2005.06.15

Rev.3.01 2005.06.15 page 2 of 160 REJ03B0007-0301 Block diagram (4519 Group) RAMROM Memory I/O portInternal peripheral functions Timer Timer 1(8 bits) System clock generation circuit Timer 2(8 bits) 384 words ✕ 4 bits 6144, 8192 words ✕ 10 bits 4500 seriesCPU core Register B (4 bits) Register A (4 bits)Register D (3 bits) Register E (8 bits) Stack register SK (8 levels) Interrupt stack register SDP (1 level) ALU(4 bits) Watchdog timer (16 bits) Port P0 Port P1 Port P2 Voltage drop detection circuit Timer 3(8 bits)Timer 4(8 bits) X IN OUT (Ceramic/Quartz-crystal/RC) On-chip oscillator Port P3 Port D Port P6 Serial I/O(8 bits ✕ 1) A/D converter(10 bits ✕ 8 ch) Port P4 Port P5

Rev.3.01 2005.06.15 page 3 of 160 REJ03B0007-0301 PERFORMANCE OVERVIEW Function 153 0.5 µs (at 6.0 MHz oscillation frequency, in XIN through-mode) 6144 words ✕ 10 bits 8192 words ✕ 10 bits 384 words ✕ 4 bits Eight independent I/O ports; Ports D6 and D7 are also used as CNTR0 and CNTR1, respectively. The output structure is switched by software. 4-bit I/O port; a pull-up function, a key-on wakeup function and output structure can be switched by software. 4-bit I/O port; a pull-up function, a key-on wakeup function and output structure can be switched by software. 3-bit I/O port; ports P20, P21 and P22 are also used as SCK , SOUT and SIN, respectively. 4-bit I/O port ; ports P30 and P31 are also used as INT0 and INT1, respectively. 4-bit I/O port ; ports P40–P43 are also used as AIN4–AIN7, respectively. 4-bit I/O port ; the output structure is switched by software. 4-bit I/O port ; ports P6 0–P63 are also used as AIN0–AIN3, respectively. 8-bit timer with a reload register is also used as an event counter. Also, this is equipped with a period/pulse width measurement function. 8-bit timer with a reload register. 8-bit timer with a reload register is also used as an event counter. 8-bit timer with two reload registers and PWM output function. 10-bit wide ✕ 8 ch, This is equipped with an 8-bit comparator function. 8-bit ✕ 1 8 (two for external, four for timer, one for A/D, and one for serial I/O) 1 level 8 levels CMOS silicon gate 42-pin plastic molded SSOP (42P2R-A) –20 °C to 85 °C 1.8 V to 5.5 V (It depends on operation source clock, oscillation frequency and operating mode.) 2.5 V to 5.5 V (It depends on operation source clock, oscillation frequency and operating mode.) 2.8 mA (Ta=25 °C, VDD =5V, f(XIN)=6 MHz, f(STCK)=f(XIN), on-chip oscillator stop) 70 µA (Ta=25 °C, VDD =5V, f(XIN)=32 kHz, f(STCK)=f(XIN), on-chip oscillator stop) 150 µA (Ta=25 °C, VDD =5V, on-chip oscillator is used, f(STCK)=f(RING), f(XIN) stop) 0.1 µA (Ta=25 °C, VDD = 5 V, output transistors in the cut-off state) Parameter Number of basic instructions Minimum instruction execution time Memory sizes Input/Output ports Timers A/D converter Serial I/O Interrupt Subroutine nesting Device structure Package Operating temperature range Supply voltage Power dissipation (typical value) ROM RAM D 0–D 7 P00–P03 P10–P13 P20–P22 P30–P33 P40–P43 P50–P53 P60–P63 Timer 1 Timer 2 Timer 3 Timer 4 Sources Nesting Mask ROM version One Time PROM version Active mode RAM back-up mode I/O (Input is examined by skip decision) I/O I/O I/O I/O I/O I/O I/O M34519M6 M34519M8/E8 M34519M6/M8/E8

Rev.3.01 2005.06.15 page 4 of 160 REJ03B0007-0301 V DD VSS CNV SS VDCE RESET X IN Input/Output Input I/O Input Function Connected to a plus power supply. Connected to a 0 V power supply. Connect CNV SS to VSS and apply “L” (0V) to CNVSS certainly. This pin is used to operate/stop the voltage drop detection circuit. When “H “ level is input to this pin, the circuit starts operating. When “L“ level is input to this pin, the circuit stops operating. An N-channel open-drain I/O pin for a system reset. When the SRST instruction, watchdog timer, the built-in power-on reset or the voltage drop detection circuit causes the system to be reset, the RESET pin outputs “L” level. I/O pins of the main clock generating circuit. When using a ceramic resonator, connect it between pins XIN and XOUT . When using a 32 kHz quartz-crystal oscillator, connect it between pins XIN and XOUT . A feedback resistor is built-in between them. When using the RC oscillation, connect a resistor and a capacitor to XIN, and leave XOUT pin open. XOUT Main clock output Output D 0–D 7 P00–P03 P10–P13 P20–P23 P30–P33 P40–P43 P50–P53 P60–P63 CNTR0, CNTR1 INT0, INT1 AIN0–AIN7 SCK SOUT SIN I/O port D Input is examined by skip decision. I/O port P0 I/O port P1 I/O port P2 I/O port P3 I/O port P4 I/O port P5 I/O port P6 Timer input/output Interrupt input Analog input Serial I/O data I/O Serial I/O data output Serial I/O clock input I/O I/O I/O I/O I/O I/O I/O I/O I/O Input Input I/O Output Input Each pin of port D has an independent 1-bit wide I/O function. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Ports D 6, D7 is also used as CNTR0 pin and CNTR1 pin, respectively. Port P0 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Port P0 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Port P1 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Port P1 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Port P2 serves as a 3-bit I/O port. The output structure is N-channel open-drain. For input use, set the latch of the specified bit to “1”. Ports P2 0–P22 are also used as SCK , SOUT , SIN, respectively. Port P3 serves as a 4-bit I/O port. The output structure is N-channel open-drain. For input use, set the latch of the specified bit to “1”. Ports P30 and P31 are also used as INT0 pin and INT1 pin, respectively. Port P4 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain. For input use, set the latch of the specified bit to “1”. Ports P40–P43 are also used as AIN4–AIN7, respectively. Port P5 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Port P6 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain. For input use, set the latch of the specified bit to “1”. Ports P6 0–P63 are also used as AIN0–AIN3, respectively. CNTR0 pin has the function to input the clock for the timer 1 event counter, and to output the timer 1 or timer 2 underflow signal divided by 2. CNTR1 pin has the function to input the clock for the timer 3 event counter, and to output the PWM signal generated by timer 4.CNTR0 pin and CNTR1 pin are also used as Ports D 6 and D7, respectively. INT0 pin and INT1 pin accept external interrupts. They have the key-on wakeup func- tion which can be switched by software. INT0 pin and INT1 pin are also used as Ports P3 0 and P31, respectively. A/D converter analog input pins. AIN0–AIN7 are also used as ports P60–P63 and P40– P43, respectively. Serial I/O data transfer synchronous clock I/O pin. SCK pin is also used as port P20.. Serial I/O data output pin. SOUT pin is also used as port P21. Serial I/O data input pin. SIN pin is also used as port P22.

Rev.3.01 2005.06.15 page 5 of 160 REJ03B0007-0301 DEFINITION OF CLOCK AND CYCLE G Operation source clock The operation source clock is the source clock to operate this product. In this product, the following clocks are used.

• Clock (f(X IN)) by the external ceramic resonator
• Clock (f(XIN)) by the external RC oscillation
• Clock (f(XIN)) by the external input
• Clock (f(RING)) of the on-chip oscillator which is the internal oscillator
• Clock (f(XIN)) by the external quartz-crystal oscillation Register MR System clock f(STCK) = f(XIN) f(STCK) = f(RING) f(STCK) = f(X IN)/2 f(STCK) = f(RING)/2 f(STCK) = f(X IN)/4 f(STCK) = f(RING)/4 f(STCK) = f(X IN)/8 f(STCK) = f(RING)/8 Table Selection of system clock ✕ : 0 or 1 Note: The f(RING)/8 is selected after system is released from reset. When on-chip oscillator clock is selected for main clock, set the on-chip oscillator to be operating state. MR 2 MR Operation mode X IN through mode On-chip oscillator through mode X IN divided by 2 mode On-chip oscillator divided by 2 mode X IN divided by 4 mode On-chip oscillator divided by 4 mode X IN divided by 8 mode On-chip oscillator divided by 8 mode G System clock (STCK) The system clock is the basic clock for controlling this product. The system clock is selected by the clock control register MR shown as the table below. G Instruction clock (INSTCK) The instruction clock is the basic clock for controlling CPU. The instruction clock (INSTCK) is a signal derived by dividing the system clock (STCK) by 3. The one instruction clock cycle gen- erates the one machine cycle. G Machine cycle The machine cycle is the standard cycle required to execute the instruction. MR 0 MR Notes 1: Pins except above have just single function. 2: The input/output of P30 and P31 can be used even when INT0 and INT1 are selected. 3: The input of ports P20–P2 2 can be used even when SIN, SOUT and SCK are selected. 4: The input/output of D6 can be used even when CNTR0 (input) is selected. 5: The input of D6 can be used even when CNTR0 (output) is selected. 6: The input/output of D7 can be used even when CNTR1 (input) is selected. 7: The input of D7 can be used even when CNTR1 (output) is selected. Pin D 6 D 7 P20 P21 P22 P30 P31 Multifunction CNTR0 CNTR1 S CK SOUT SIN INT0 INT1 MULTIFUNCTION Pin CNTR0 CNTR1 S CK SOUT SIN INT0 INT1 Multifunction D D 7 P20 P21 P22 P30 P31 Pin P60 P61 P62 P63 P40 P41 P42 P43 Multifunction AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 Pin AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 Multifunction P60 P61 P62 P63 P40 P41 P42 P43

Rev.3.01 2005.06.15 page 6 of 160 REJ03B0007-0301 SD, RD SZD CLD OP0A IAP0 OP1A IAP1 OP2A IAP2 OP3A IAP3 OP4A IAP4 OP5A IAP5 OP6A IAP6 Control registers FR1, FR2 FR0 PU0 K0, K1 FR0 PU1 I1, I2 FR3 Output structure N-channel open-drain/ CMOS N-channel open-drain/ CMOS N-channel open-drain/ CMOS N-channel open-drain N-channel open-drain N-channel open-drain N-channel open-drain/ CMOS N-channel open-drain Input Output I/O (8) I/O (4) I/O (4) I/O (3) I/O (4) I/O (4) I/O (4) I/O (4) RemarkPin D 0–D 5 D 6/CNTR0 D 7/CNTR1 P00–P03 P10–P13 P20/SCK , P21/SOUT P22/SIN P30/INT0, P31/INT1 P32, P33 P40/AIN4–P43/AIN7 P50–P53 P60/AIN0–P63/AIN3 Output structure selection function (programmable) Built-in programmable pull-up functions, key-on wakeup functions and output structure selection functions Built-in programmable pull-up functions, key-on wakeup functions and output structure selection functions Output structure selection function (programmable)

Rev.3.01 2005.06.15 page 7 of 160 REJ03B0007-0301 CONNECTIONS OF UNUSED PINS Connection Open. Open. Open. Connect to V SS . Open. Connect to V SS . Open. Connect to V SS . Open. Connect to V SS . Open. Connect to VSS . Open. Connect to VSS . Open. Connect to V SS . Open. Connect to V SS . Open. Connect to Vss. Open. Connect to Vss. Open. Connect to Vss. Open. Connect to Vss. Open. Connect to Vss. Open. Connect to Vss. Pin X IN XOUT D 0–D 5 D 6/CNTR0 D 7/CNTR1 P00–P03 P10–P13 P20/SCK P21/SOUT P22/SIN P30/INT0 P31/INT1 P32, P33 P40/AIN4–P43/AIN7 P50–P53 P60/AIN0–P63/AIN3 Usage condition Internal oscillator is selected. (Note 1) Internal oscillator is selected. (Note 1) RC oscillator is selected. (Note 2) External clock input is selected for main clock. (Note 3) N-channel open-drain is selected for the output structure. (Note 4) CNTR0 input is not selected for timer 1 count source. N-channel open-drain is selected for the output structure. (Note 4) CNTR1 input is not selected for timer 3 count source. N-channel open-drain is selected for the output structure. (Note 4) The key-on wakeup function is not selected. (Note 6) N-channel open-drain is selected for the output structure. (Note 5) The pull-up function is not selected. (Note 4) The key-on wakeup function is not selected. (Note 6) The key-on wakeup function is not selected. (Note 7) N-channel open-drain is selected for the output structure. (Note 5) The pull-up function is not selected. (Note 4) The key-on wakeup function is not selected. (Note 7) S CK pin is not selected. SIN pin is not selected. “0” is set to output latch. “0” is set to output latch. N-channel open-drain is selected for the output structure. Notes 1: After system is released from reset, the internal oscillation (on-chip oscillator) is selected for system clock (RG0=0, MR0=1). 2: When the CRCK instruction is executed, the RC oscillation circuit becomes valid. Be careful that the swich of system clock is not executed at oscilla- tion start only by the CRCK instruction execution. In order to start oscillation, setting the main clock f(X IN) oscillation to be valid (MR1=0) is required. (If necessary, generate the oscillation stabilizing wait time by software.) Also, when the main clock (f(X IN)) is selected as system clock, set the main clock f(XIN) oscillation (MR1=0) to be valid, and select main clock f(XIN) (MR 0=0). Be careful that the switch of system clock cannot be executed at the same time when main clock oscillation is started. 3: In order to use the external clock input for the main clock, select the ceramic resonance by executing the CMCK instruction at the beggining of soft- ware, and then set the main clock (f(XIN)) oscillation to be valid (MR1=0). Until the main clock (f(XIN)) oscillation becomes valid (MR1=0) after ceramic resonance becomes valid, XIN pin is fixed to “H ”. When an external clock is used, insert a 1 kΩ resistor to XIN pin in series for limits of current. 4: Be sure to select the output structure of ports D0–D 5 and the pull-up function of P00–P03 and P10–P13 with every one port. Set the corresponding bits of registers for each port. 5: Be sure to select the output structure of ports P00–P0 3 and P10–P1 3 with every two ports. If only one of the two pins is used, leave another one open. 6: The key-on wakeup function is selected with every two bits. When only one of key-on wakeup function is used, considering that the value of key-on wake-up control register K1, set the unused 1-bit to “H ” input (turn pull-up transistor ON and open) or “L” input (connect to VSS , or open and set the output latch to “0”). 7: The key-on wakeup function is selected with every two bits. When one of key-on wakeup function is used, turn pull-up transistor of unused one ON and open. (Note when connecting to VSS and VDD ) G Connect the unused pins to VSS and VDD using the thickest wire at the shortest distance against noise.

Rev.3.01 2005.06.15 page 8 of 160 REJ03B0007-0301 Port block diagram (1) D 0— D 3S RQ FR1 i T h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e o n t h e p o r t A p p l i e d p o t e n t i a l t o t h e s e p o r t s m u s t b e VD D o r l e s s i r e p r e s e n t s b i t s t o N o t e s R e g i s t e r YD e c o d e r S D i n s t r u c t i o n R D i n s t r u c t i o n Skip decision C L D i n s t r u c t i o n (Note 1) (Note 2) (Note 1) (Note 3) S Z D i n s t r u c t i o n D 4S RQ FR2 0 R e g i s t e r Y D e c o d e r S D i n s t r u c t i o n R D i n s t r u c t i o n Skip decision C L D i n s t r u c t i o n (Note 1) (Note 2) (Note 1) SZD instruction D 5S RQ FR2 1 R e g i s t e r Y D e c o d e r S D i n s t r u c t i o n R D i n s t r u c t i o n Skip decision CLD instruction (Note 1) (Note 2) (Note 1) SZD instruction

Rev.3.01 2005.06.15 page 9 of 160 REJ03B0007-0301 Port block diagram (2) This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. Notes 1: W1 0 W1 1 S RQ FR2 2 W6 0 D 6/CNTR0 Register Y Decoder SD instruction RD instruction Skip decision CLD instruction (Note 1) (Note 2) Timer 1 underflow signal W2 3 1/2Timer 2 underflow signal W6 2 Clock (input) for timer 1 event count or period measurement signal input W5 0 W5 1 W3 0 W3 1 S RQ FR2 3 W4 3 D 7/CNTR1 Register Y Decoder SD instruction RD instruction Skip decision CLD instruction (Note 1) (Note 2) W6 3 Clock (input) for timer 3 event count PWMOD SZD instruction SZD instruction

Rev.3.01 2005.06.15 page 10 of 160 REJ03B0007-0301 P00, P01 OP0A instruction Register A Aj Aj D (Note 2) (Note 1) FR0 0 IAP0 instruction PU0 j Pull-up transistor TQ This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: j represents bits 0 and 1. 4: k represents bits 2 and 3. Notes 1: (Note 1) K00Key-on wakeup Level detection circuit Edge detection circuit K11 K10 (Note 3) P02, P03 OP0A instruction Register A Ak Ak D (Note 2) (Note 1) FR0 1 IAP0 instruction PU0 k Pull-up transistor TQ (Note 1) K01Key-on wakeup Level detection circuit Edge detection circuit K13 K12 (Note 4) P10, P11 OP1A instruction Register A Aj Aj D (Note 2) (Note 1) FR0 2 IAP1 instruction PU1 j Pull-up transistor TQ (Note 1) K02 (Note 3) P12, P13 OP1A instruction Register A Ak Ak D (Note 2) (Note 1) FR0 3 IAP1 instruction PU1 k Pull-up transistor TQ (Note 1) K03 Key-on wakeup Level detection circuit (Note 4) (Note 3) (Note 4) (Note 3) (Note 4) Key-on wakeup Level detection circuit Port block diagram (3)

Rev.3.01 2005.06.15 page 11 of 160 REJ03B0007-0301 Port block diagram (4) J This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. Notes 1: P 20/ SC K S y n c h r o n o u s c l o c k o u t p u t f o r s e r i a l d a t a t r a n s f e r (Note 1) N o t e S y n c h r o n o u s c l o c k i n p u t f o r s e r i a l d a t a t r a n s f e r R e g i s t e r A IAP2 instruction J10 J11 J12 J13 D T Q OP2A instruction P 21/ SO U T (Note 1) (Note 2) R e g i s t e r A IAP2 instruction O A i n s t r u c t i o n D T Q S e r i a l d a t a o u t p u t P 22/ SI N (Note 1) (Note 2) Register A IAP2 instruction O A i n s t r u c t i o n D T Q S e r i a l d a t a i n p u t J11

Rev.3.01 2005.06.15 page 12 of 160 REJ03B0007-0301 Port block diagram (5) This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: As for details, refer to the external interrupt circuit structure. Notes 1: P32 (Note 1) (Note 2) Register A IAP3 instruction OP3A instruction D T Q P30/INT0 (Note 1) (Note 2) Register A IAP3 instruction OP3A instruction D T Q External 0 interrupt circuitExternal 0 interrupt Key-on wakeup input Timer 1 count start synchronous circuit input Period measurement circuit input P31/INT1 (Note 1) (Note 2) Register A IAP3 instruction OP3A instruction D T Q External 1 interrupt circuitExternal 1 interrupt Key-on wakeup input Timer 3 count start synchronous circuit input P33 (Note 1) (Note 2) Register A IAP3 instruction OP3A instruction D T Q (Note 3) (Note 3)

Rev.3.01 2005.06.15 page 13 of 160 REJ03B0007-0301 Port block diagram (6) P40/AIN4–P43/AIN7 Decoder OP4A instruction Register A Ai Ai D Analog input T Q IAP4 instruction Q2 3 (Note 3) (Note 1) (Note 2) This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: i represents bits 0 to 3. Notes 1: P50–P53 Register A Ai OP5A instruction Ai D T Q IAP5 instruction FR3 i (Note 3) (Note 1) (Note 2) (Note 3)

Rev.3.01 2005.06.15 page 14 of 160 REJ03B0007-0301 Port block diagram (7) P /AI N P 61/AI N Decoder O P A i n s t r u c t i o n R e g i s t e r A Aj Aj D A n a l o g i n p u t T Q I A P i n s t r u c t i o n Q Q N o t e N o t e N o t e T h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e o n t h e p o r t A p p l i e d p o t e n t i a l t o t h e s e p o r t s m u s t b e VD D o r l e s s j r e p r e s e n t s b i t s a n d k r e p r e s e n t s b i t s a n d N o t e s P62/AIN2, P63/AIN3 Decoder OP6A instruction R e g i s t e r A Ak Ak D A n a l o g i n p u t T Q I A P i n s t r u c t i o n Q Q N o t e N o t e (Note 2) N o t e

Rev.3.01 2005.06.15 page 15 of 160 REJ03B0007-0301 Port block diagram (8) Rising Falling One-sided edge detection circuit Key-on wakeup External 1 interrupt Timer 3 count start synchronous circuit Level detection circuit Edge detection circuit Skip decision (SNZI1 instruction) Both edges detection circuit I22 EXF1 I21 P31/INT1 K22 I23 K23 Rising Falling I12 One-sided edge detection circuit Key-on wakeup EXF0 External 0 interrupt I11 P30/INT0 K20 Timer 1 count start synchronous circuitI13 (Note 1) Level detection circuit Edge detection circuit K21 Skip decision (SNZI0 instruction) Both edges detection circuit This symbol represents a parasitic diode on the port.Notes 1: (Note 2) (Note 3) (Note 1) (Note 2) (Note 3) 2: I12 (I22) = 0: “L” level detected I12 (I22) = 1: “H ” level detected 3: I12 (I22) = 0: Falling edge detected I12 (I22) = 1: Rising edge detected Period measurement circuit input

Rev.3.01 2005.06.15 page 16 of 160 REJ03B0007-0301 (1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4- bit data addition, comparison, AND operation, OR operation, and bit manipulation. (2) Register A and carry flag Register A is a 4-bit register used for arithmetic, transfer, ex- change, and I/O operation. Carry flag CY is a 1-bit flag that is set to “1” when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A 0 is stored in carry flag CY with the RAR instruction (Fig- ure 2). Carry flag CY can be set to “1” with the SC instruction and cleared to “0” with the RC instruction. (3) Registers B and E Register B is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3). Register E is undefined after system is released from reset and re- turned from the RAM back-up. Accordingly, set the initial value. (4) Register D Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed. Also, when the TABP p instruction is executed, the high-order 2 bits of the reference data in ROM is stored to the low-order 2 bits of register D, and the con- tents of the high-order 1 bit of register D is “0”. (Figure 4). Register D is undefined after system is released from reset and re- turned from the RAM back-up. Accordingly, set the initial value. Fig. 1 AMC instruction execution example Fig. 2 RAR instruction execution example Fig. 3 Registers A, B and register E Fig. 4 TABP p instruction execution example (CY) ( M ( D P ) ) ( A ) Addition A L U <Carry> < R e s u l t > CY A 3 A2 A1 A0 A0 CY A 3 A2 A1 <Rotation> RAR instruction <Set> SC instruction < C l e a r > R C i n s t r u c t i o n A3 A2 A1 A0B3 B2 B1 B0 E7 E6 E5 E4 E3 E2 E1 E0 A3 A2 A1 A0B3 B2 B1 B0 TAB instruction T E A B i n s t r u c t i o n T A B E i n s t r u c t i o n TBA instruction R e g i s t e r BR e g i s t e r A Register B Register A Register E Specifying address TABP p instruction p6 p5 p4 p3 p2 p1 p0 PC H DR 2 DR 1DR 0 A3 A2 A1 A0 PC L Immediate field value p The contents of register D ROM 840 Middle-order 4 bits Low-order 4bits Register A (4) Register B (4) The contents of register A High-order 2 bits Register D (3) High-order 1 bit of register D is“0”.

Rev.3.01 2005.06.15 page 17 of 160 REJ03B0007-0301 (5) Stack registers (SKS) and stack pointer (SP) Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when;

• branching to an interrupt service routine (referred to as an inter- rupt service routine),
• performing a subroutine call, or
• executing the table reference instruction (TABP p). Stack registers (SKs) are eight identical registers, so that subrou- tines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be care- ful not to over the stack when performing these operations together. The contents of registers SKs are destroyed when 8 lev- els are exceeded. The register SK nesting level is pointed automatically by 3-bit stack pointer (SP). The contents of the stack pointer (SP) can be transferred to register A with the TASP instruction. Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call. (6) Interrupt stack register (SDP) Interrupt stack register (SDP) is a 1-stage register. When an inter- rupt occurs, this register (SDP) is used to temporarily store the contents of data pointer, carry flag, skip flag, register A, and regis- ter B just before an interrupt until returning to the original routine. Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table refer- ence instruction. (7) Skip flag Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. When an interrupt oc- curs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained. Fig. 5 Stack registers (SKs) structure Fig. 6 Example of operation at subroutine call S K0 S K1 S K2 S K3 S K4 S K5 S K6 S K7 ( S P ) = 0 ( S P ) = 1 ( S P ) = 2 ( S P ) = 3 ( S P ) = 4 ( S P ) = 5 ( S P ) = 6 ( S P ) = 7 Program counter (PC) E x e c u t i n g R T i n s t r u c t i o n E x e c u t i n g B M i n s t r u c t i o n S t a c k p o i n t e r ( S P ) p o i n t s “ 7 ” a t r e s e t o r r e t u r n i n g f r o m R A M b a c k u p m o d e I t p o i n t s b y e x e c u t i n g t h e f i r s t B M i n s t r u c t i o n a n d t h e c o n t e n t s o f p r o g r a m c o u n t e r i s s t o r e d i n S K0. W h e n t h e B M i n s t r u c t i o n i s e x e c u t e d a f t e r e i g h t s t a c k r e g i s t e r s a r e u s e d S P S P a n d t h e c o n t e n t s o f S i s d e s t r o y e d Returning to the BM instruction execution address with the RT instruction, and the BM instruction becomes the NOP instruction. (SP) ← 0 (SK0) ← 000116 (PC) ← SUB1 Main program 0 0 0 21

6 N O P

000116 BM SUB1

S U B 1 : NOP R T (PC) ← (SK0) (SP) ← 7 Note :

Rev.3.01 2005.06.15 page 18 of 160 REJ03B0007-0301 (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table refer- ence instruction (TABP p) is executed. Program counter consists of PC H (most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which speci- fies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PC H does not specify after the last page of the built-in ROM. (9) Data pointer (DP) Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y. Register Z specifies a RAM file group, reg- ister X specifies a file, and register Y specifies a RAM digit (Figure 8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 9).

• Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the RAM back-up, set these registers. Fig. 7 Program counter (PC) structure Fig. 8 Data pointer (DP) structure Fig. 9 SD instruction execution example p5 p4 p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0 P r o g r a m c o u n t e r P C H S p e c i f y i n g p a g e PC L Specifying address Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0 D a t a p o i n t e r ( D P ) R e g i s t e r Z ( 2 ) R e g i s t e r X ( 4 ) R e g i s t e r Y ( 4 ) Specifying RAM digit Specifying RAM file Specifying RAM file group 0 01 1 S e t Specifying bit position P o r t D o u t p u t l a t c hR e g i s t e r Y ( 4 ) D 2D 3 D 1 D 0

Rev.3.01 2005.06.15 page 19 of 160 REJ03B0007-0301 PROGRAM MEMORY (ROM) The program memory is a mask ROM. 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Fig- ure 10 shows the ROM map of M34519M8/E8. Table 1 ROM size and pages Part number M34519M6 M34519M8/E8 ROM (PROM) size (✕ 10 bits) 6144 words 8192 words Pages 48 (0 to 47) 64 (0 to 63) A part of page 1 (addresses 008016 to 00FF16) is reserved for in- terrupt addresses (Figure 11). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is executed. When using an interrupt service routine, write the in- struction generating the branch to that routine at an interrupt address. Page 2 (addresses 0100 16 to 017F16) is the special page for sub- routine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM in- struction when it starts on page 2. ROM pattern (bits 9 to 0) of all addresses can be used as data ar- eas with the TABP p instruction. Fig. 10 ROM map of M34519M8/E8 Fig. 11 Page 1 (addresses 008016 to 00FF16) structure 90 87654321 Interrupt address page 000016 008016 017F16 Subroutine special page 007F16 00FF16 010016 1FFF 16 018016 Page 1 Page 2 Page 0 Page 3 Page 63 90 87654321 External 0 interrupt address008016 008216

008416 Timer 1 interrupt address

Timer 2 interrupt address008616 008816 008A16 008C 16 008E16 00FF16 A/D interrupt address External 1 interrupt address Timer 3 interrupt address Timer 4 interrupt address Serial I/O interrupt address

Rev.3.01 2005.06.15 page 20 of 160 REJ03B0007-0301 DATA MEMORY (RAM) 1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers Z, X, and Y. Set a value to the data pointer certainly when executing an instruction to access RAM (also, set a value after system returns from RAM back-up). Table 2 shows the RAM size. Figure 12 shows the RAM map.

• Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the RAM back-up, set these registers. Fig. 12 RAM map Table 2 RAM size Part number M34519M6 M34519M8/E8 RAM size 384 words ✕ 4 bits (1536 bits) M34519M8/E8 Z=0, X=0 to 15 Z=1, X=0 to 7 0 1 ... 7 384 words Register Y Register Z Register X RAM 384 words ✕ 4 bits (1536 bits)

Rev.3.01 2005.06.15 page 21 of 160 REJ03B0007-0301 INTERRUPT FUNCTION The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the following 3 conditions are satisfied.

• An interrupt activated condition is satisfied (request flag = “1”)
• Interrupt enable bit is enabled (“1”)
• Interrupt enable flag is enabled (INTE = “1”) Table 3 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.) (1) Interrupt enable flag (INTE) The interrupt enable flag (INTE) controls whether the every inter- rupt enable/disable. Interrupts are enabled when INTE flag is set to “1” with the EI instruction and disabled when INTE flag is cleared to “0” with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to “0,” so that other interrupts are disabled until the EI instruction is executed. (2) Interrupt enable bit Use an interrupt enable bit of interrupt control registers V1 and V2 to select the corresponding interrupt or skip instruction. Table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. Table 5 shows the interrupt enable bit function. (3) Interrupt request flag When the activated condition for each interrupt is satisfied, the cor- responding interrupt request flag is set to “1.” Each interrupt request flag is cleared to “0” when either;
• an interrupt occurs, or
• the next instruction is skipped with a skip instruction. Each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its in- terrupt enable bit. Once set, the interrupt request flag retains set until a clear condition is satisfied. Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. If more than one interrupt request flag is set when the interrupt dis- able state is released, the interrupt priority level is as follows shown in Table 3. Table 3 Interrupt sources Activated condition Level change of INT0 pin Level change of INT1 pin Timer 1 underflow Timer 2 underflow Timer 3 underflow Timer 4 underflow Completion of A/D conversion Completion of serial I/O transmit/receive Priority level Interrupt name External 0 interrupt External 1 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 4 interrupt A/D interrupt Serial I/O interrupt Interrupt request flag EXF0 EXF1 T1F T2F T3F T4F ADF SIOF Interrupt name External 0 interrupt External 1 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 4 interrupt A/D interrupt Serial I/O interrupt Table 5 Interrupt enable bit function Occurrence of interrupt Enabled Disabled Skip instruction Invalid Valid Interrupt enable bit Interrupt address Address 0 in page 1 Address 2 in page 1 Address 4 in page 1 Address 6 in page 1 Address 8 in page 1 Address A in page 1 Address C in page 1 Address E in page 1 Table 4 Interrupt request flag, interrupt enable bit and skip in- struction Skip instruction SNZ0 SNZ1 SNZT1 SNZT2 SNZT3 SNZT4 SNZAD SNZSI Interrupt enable bit V10 V11 V12 V13 V20 V21 V22 V23

Rev.3.01 2005.06.15 page 22 of 160 REJ03B0007-0301 (4) Internal state during an interrupt The internal state of the microcomputer during an interrupt is as fol- lows (Figure 14).

• Program counter (PC) An interrupt address is set in program counter. The address to be executed when returning to the main routine is automatically stored in the stack register (SK).
• Interrupt enable flag (INTE) INTE flag is cleared to “0” so that interrupts are disabled.
• Interrupt request flag Only the request flag for the current interrupt source is cleared to “0.”
• Data pointer, carry flag, skip flag, registers A and B The contents of these registers and flags are stored automatically in the interrupt stack register (SDP). (5) Interrupt processing When an interrupt occurs, a program at an interrupt address is ex- ecuted after branching a data store sequence to stack register. Write the branch instruction to an interrupt service routine at an in- terrupt address. Use the RTI instruction to return from an interrupt service routine. Interrupt enabled by executing the EI instruction is performed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction, interrupts are enabled after returning the main routine. (Refer to Figure 13) Fig. 13 Program example of interrupt processing
• Program counter (PC)
• Stack register (SK)
• Interrupt enable flag (INTE)
• Interrupt request flag (only the flag for the current interrupt
• Data pointer, carry flag, registers A and B, skip flag The address of main routine to be executed when returning Fig. 15 Interrupt system diagram Fig. 14 Internal state when interrupt occurs E I R T I I n t e r r u p t s e r v i c e r o u t i n e Interrupt occurs Interrupt is enabled M a i n r o u t i n e : I n t e r r u p t e n a b l e d s t a t e : I n t e r r u p t d i s a b l e d s t a t e V11 EXF0 V10 Address 2 in page 1 Address 4 in page 1 Address 0 in page 1 Timer 1 underflow Timer 2 underflow T1F V1 2 Request flag (state retained) Enable bit Enable flagActivated condition V13 Address 6 in page 1 A/D conversion completed INTE ADF T2F V20T3F V21 SIOF V2 3 T4F V22 INT0 pin interrupt waveform input Timer 3 underflow Timer 4 underflow Serial I/O transmit/ receive completed INT1 pin interrupt waveform input EXF1 Address 8 in page 1 Address A in page 1 Address C in page 1 Address E in page 1

Rev.3.01 2005.06.15 page 23 of 160 REJ03B0007-0301 (6) Interrupt control registers

• Interrupt control register V1 Interrupt enable bits of external 0, external 1, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A.
• Interrupt control register V2 The timer 3, timer 4, A/D and serial I/O interrupt enable bit is as- signed to register V2. Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction can be used to transfer the contents of register V2 to register A. Table 6 Interrupt control registers Note: “R ” represents read enabled, and “W ” represents write enabled. (7) Interrupt sequence Interrupts only occur when the respective INTE flag, interrupt en- able bits (V10–V1 3, V20–V2 3), and interrupt request flag are “1.” The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. The interrupt occurs after 3 machine cycles only when the three interrupt conditions are sat- isfied on execution of other than one-cycle instructions (Refer to Figure 16). Interrupt disabled (SNZSI instruction is valid) Interrupt enabled (SNZSI instruction is invalid) Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) Interrupt disabled (SNZT4 instruction is valid) Interrupt enabled (SNZT4 instruction is invalid) Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) V13 V12 V11 V10 V23 V22 V21 V20 Serial I/O interrupt enable bit A/D interrupt enable bit Timer 4 interrupt enable bit Timer 3 interrupt enable bit Interrupt control register V2 at RAM back-up : 00002at reset : 00002 Interrupt control register V1 Timer 2 interrupt enable bit Timer 1 interrupt enable bit External 1 interrupt enable bit External 0 interrupt enable bit Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) at RAM back-up : 0000 2at reset : 00002 R/W TAV1/TV1A R/W TAV2/TV2A

Rev.3.01 2005.06.15 page 24 of 160 REJ03B0007-0301 Fig. 16 Interrupt sequence T1F,T2F,T3F,T4F, ADF,SIOFINT0,INT1EXF0,EXF1 G When an interrupt request flag is set after its interrupt is enabled (Note 1) System clock (STCK) The program starts from the interrupt address. Interrupt enabled state 1 machine cycle EI instruction execution cycle Interrupt enable flag (INTE) Retaining level of system clock for 4 periods or more is necessary.Interrupt disabled state External interrupt Timer 1,Timer 2, Timer 3, Timer 4, A/D and Serial I/O interrupts Interrupt activated condition is satisfied. Notes 1: The address is stacked to the last cycle. 2: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied .Flag cleared 2 to 3 machine cycles (Notes 1, 2)

Rev.3.01 2005.06.15 page 25 of 160 REJ03B0007-0301 Table 7 External interrupt activated conditions Name External 0 interrupt External 1 interrupt Input pin P30/INT0 P31/INT1 Activated condition When the next waveform is input to P30/INT0 pin

• Falling waveform (“H ”→ “L”)
• Both rising and falling waveforms When the next waveform is input to P31/INT1 pin
• Falling waveform (“H ”→ “L”)
• Both rising and falling waveforms Valid waveform selection bit I11 I12 I21 I22 Fig. 17 External interrupt circuit structure EXTERNAL INTERRUPTS The 4519 Group has the external 0 interrupt and external 1 inter- rupt. An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). The external interrupt can be controlled with the interrupt control registers I1 and I2. Rising Falling One-sided edge detection circuit Key-on wakeup External 1 interrupt Timer 3 count start synchronous circuit Level detection circuit Edge detection circuit Skip decision (SNZI1 instruction) Both edges detection circuit I22 EXF1 I21 P31/INT1 K22 I23 K23 Rising Falling I12 One-sided edge detection circuit Key-on wakeup EXF0 External 0 interrupt I11 P30/INT0 K20 Timer 1 count start synchronous circuitI13 (Note 1) Level detection circuit Edge detection circuit K21 Skip decision (SNZI0 instruction) Both edges detection circuit This symbol represents a parasitic diode on the port.Notes 1: (Note 2) (Note 3) (Note 1) (Note 2) (Note 3) 2: I12 (I22) = 0: “L” level detected I12 (I22) = 1: “H ” level detected 3: I12 (I22) = 0: Falling edge detected I12 (I22) = 1: Rising edge detected Period measurement circuit input

Rev.3.01 2005.06.15 page 26 of 160 REJ03B0007-0301 (1) External 0 interrupt request flag (EXF0) External 0 interrupt request flag (EXF0) is set to “1” when a valid waveform is input to P30/INT0 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to “0” when an in- terrupt occurs or when the next instruction is skipped with the skip instruction.

• External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to P3 0/INT0 pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 0 interrupt is as follows. ➀ Set the bit 3 of register I1 to “1” for the INT0 pin to be in the in- put enabled state. ➁ Select the valid waveform with the bits 1 and 2 of register I1. ➂ Clear the EXF0 flag to “0” with the SNZ0 instruction. ➃ Set the NOP instruction for the case when a skip is performed with the SNZ0 instruction. ➄ Set both the external 0 interrupt enable bit (V1 0) and the INTE flag to “1.” The external 0 interrupt is now enabled. Now when a valid wave- form is input to the P30/INT0 pin, the EXF0 flag is set to “1” and the external 0 interrupt occurs. (2) External 1 interrupt request flag (EXF1) External 1 interrupt request flag (EXF1) is set to “1” when a valid waveform is input to P31/INT1 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF1 flag can be examined with the skip instruction (SNZ1). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF1 flag is cleared to “0” when an in- terrupt occurs or when the next instruction is skipped with the skip instruction.
• External 1 interrupt activated condition External 1 interrupt activated condition is satisfied when a valid waveform is input to P3 1/INT1 pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 1 interrupt is as follows. ➀ Set the bit 3 of register I2 to “1” for the INT1 pin to be in the in- put enabled state. ➁ Select the valid waveform with the bits 1 and 2 of register I2. ➂ Clear the EXF1 flag to “0” with the SNZ1 instruction. ➃ Set the NOP instruction for the case when a skip is performed with the SNZ1 instruction. ➄ Set both the external 1 interrupt enable bit (V1 1) and the INTE flag to “1.” The external 1 interrupt is now enabled. Now when a valid wave- form is input to the P31/INT1 pin, the EXF1 flag is set to “1” and the external 1 interrupt occurs.

Rev.3.01 2005.06.15 page 27 of 160 REJ03B0007-0301 (3) External interrupt control registers

• Interrupt control register I1 Register I1 controls the valid waveform for the external 0 inter- rupt. Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents of register I1 to register A. Table 8 External interrupt control register
• Interrupt control register I2 Register I2 controls the valid waveform for the external 1 inter- rupt. Set the contents of this register through register A with the TI2A instruction. The TAI2 instruction can be used to transfer the contents of register I2 to register A. I12 I11 I10 INT0 pin input control bit (Note 2) Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2) INT0 pin edge detection circuit control bit INT0 pin Timer 1 count start synchronous circuit selection bit Interrupt control register I1 R/W TAI1/TI1Aat RAM back-up : state retainedat reset : 00002 INT0 pin input disabled INT0 pin input enabled Falling waveform/“L” level (“L” level is recognized with the SNZI0 instruction) Rising waveform/“H ” level (“H ” level is recognized with the SNZI0 instruction) One-sided edge detected Both edges detected Timer 1 count start synchronous circuit not selected Timer 1 count start synchronous circuit selected I23 I22 I21 I20 INT1 pin input control bit (Note 2) Interrupt valid waveform for INT1 pin/ return level selection bit (Note 2) INT1 pin edge detection circuit control bit INT1 pin Timer 3 count start synchronous circuit selection bit Interrupt control register I2 R/W TAI2/TI2Aat RAM back-up : state retainedat reset : 00002 INT1 pin input disabled INT1 pin input enabled Falling waveform/“L” level (“L” level is recognized with the SNZI1 instruction) Rising waveform/“H ” level (“H ” level is recognized with the SNZI1 instruction) One-sided edge detected Both edges detected Timer 3 count start synchronous circuit not selected Timer 3 count start synchronous circuit selected Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: When the contents of I12, I13 I22 and I23 are changed, the external interrupt request flag (EXF0, EXF1) may be set.

Rev.3.01 2005.06.15 page 28 of 160 REJ03B0007-0301 (4) Notes on External 0 interrupt ➀ Note [1] on bit 3 of register I1 When the input of the INT0 pin is controlled with the bit 3 of reg- ister I1 in software, be careful about the following notes.

• Depending on the input state of the P3 0/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of regis- ter I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 18 ➀ ) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to Figure 18 ➁ ). Also, set the NOP instruction for the case when a skip is per- formed with the SNZ0 instruction (refer to Figure 18 ➂ ). LA 4 ; ( ✕✕✕ 0 LA 8 ; (1 ✕✕✕ 2) TI1A ; Control of INT0 pin input is changed SNZ0 ; The SNZ0 instruction is executed (EXF0 flag cleared) ✕ : these bits are not used here. Fig. 18 External 0 interrupt program example-1 ➁ Note [2] on bit 3 of register I1 When the bit 3 of register I1 is cleared to “0”, the RAM back-up mode is selected and the input of INT0 pin is disabled, be careful about the following notes.
• When the input of INT0 pin is disabled (register I1 3 = “0”), set the key-on wakeup function to be invalid (register K20 = “0”) before system enters to the RAM back-up mode. (refer to Figure 19➀ ).
• ••
• •• LA 0 ; ( ✕✕✕ 02) TK2A ; Input of INT0 key-on wakeup invalid..➀ DI EPOF POF ; RAM back-up ✕ : these bits are not used here. Fig. 19 External 0 interrupt program example-2
• ••
• •• ➂ Note on bit 2 of register I1 When the interrupt valid waveform of the P30/INT0 pin is changed with the bit 2 of register I1 in software, be careful about the following notes.
• Depending on the input state of the P3 0/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of regis- ter I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 20➀ ) and then, change the bit 2 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to Figure 20➁ ). Also, set the NOP instruction for the case when a skip is per- formed with the SNZ0 instruction (refer to Figure 20➂ ). LA 4 ; ( ✕✕✕ 0 LA 12 ; ( ✕ 1✕✕ 2) TI1A ; Interrupt valid waveform is changed SNZ0 ; The SNZ0 instruction is executed (EXF0 flag cleared) ✕ : these bits are not used here. Fig. 20 External 0 interrupt program example-3
• ••
• ••

Rev.3.01 2005.06.15 page 29 of 160 REJ03B0007-0301 (5) Notes on External 1 interrupt ➀ Note [1] on bit 3 of register I2 When the input of the INT1 pin is controlled with the bit 3 of reg- ister I2 in software, be careful about the following notes.

• Depending on the input state of the P3 1/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 3 of regis- ter I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 21➀ ) and then, change the bit 3 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to “0” after executing at least one instruction (refer to Figure 21➁ ). Also, set the NOP instruction for the case when a skip is per- formed with the SNZ1 instruction (refer to Figure 21➂ ). LA 4 ; ( ✕✕ 0✕ LA 8 ; (1 ✕✕✕ 2) TI2A ; Control of INT1 pin input is changed SNZ1 ; The SNZ1 instruction is executed (EXF1 flag cleared) ✕ : these bits are not used here. Fig. 21 External 1 interrupt program example-1 ➁ Note [2] on bit 3 of register I2 When the bit 3 of register I2 is cleared to “0”, the RAM back-up mode is selected and the input of INT1 pin is disabled, be careful about the following notes.
• When the input of INT1 pin is disabled (register I2 3 = “0”), set the key-on wakeup function to be invalid (register K22 = “0”) before system enters to the RAM back-up mode. (refer to Figure 22➀ ).
• ••
• •• LA 0 ; ( ✕ 0✕✕ 2) TK2A ; Input of INT1 key-on wakeup invalid ..➀ DI EPOF POF ; RAM back-up ✕ : these bits are not used here. Fig. 22 External 1 interrupt program example-2
• ••
• •• ➂ Note on bit 2 of register I2 When the interrupt valid waveform of the P31/INT1 pin is changed with the bit 2 of register I2 in software, be careful about the following notes.
• Depending on the input state of the P31/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 2 of regis- ter I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 23➀ ) and then, change the bit 2 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to “0” after executing at least one instruction (refer to Figure 23➁ ). Also, set the NOP instruction for the case when a skip is per- formed with the SNZ1 instruction (refer to Figure 23➂ ). LA 4 ; ( ✕✕ 0✕ LA 12 ; ( ✕ 1✕✕ 2) TI2A ; Interrupt valid waveform is changed SNZ1 ; The SNZ1 instruction is executed (EXF1 flag cleared) ✕ : these bits are not used here. Fig. 23 External 1 interrupt program example-3
• ••
• ••

Rev.3.01 2005.06.15 page 30 of 160 REJ03B0007-0301 The 4519 Group has the following timers.

• Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a set- ting value n. When it underflows (count to n + 1), a timer interrupt request flag is set to “1,” new data is loaded from the reload reg- ister, and count continues (auto-reload function).
• Fixed dividing frequency timer The fixed dividing frequency timer has the fixed frequency divid- ing ratio (n). An interrupt request flag is set to “1” after every n count of a count pulse. Fig. 24 Auto-reload function The 4519 Group timer consists of the following circuits.
• Prescaler : 8-bit programmable timer
• Timer 1 : 8-bit programmable timer
• Timer 2 : 8-bit programmable timer
• Timer 3 : 8-bit programmable timer
• Timer 4 : 8-bit programmable timer
• Watchdog timer : 16-bit fixed dividing frequency timer (Timers 1, 2, 3, and 4 have the interrupt function, respectively) Prescaler and timers 1, 2, 3, and 4 can be controlled with the timer control registers PA, W1 to W6. The watchdog timer is a free counter which is not controlled with the control register. Each function is described below. FF16 n 0016 n : C o u n t e r i n i t i a l v a l u e C o u n t s t a r t s R e l o a d Reload 1 s t u n d e r f l o w 2 n d u n d e r f l o w n+1 count n+1 count T i m e A n i n t e r r u p t o c c u r s o r a s k i p i n s t r u c t i o n i s e x e c u t e d Timer interrupt request flag T h e c o n t e n t s o f c o u n t e r “ 1 ” “ 0 ”

Rev.3.01 2005.06.15 page 31 of 160 REJ03B0007-0301 Count source

• Instruction clock (INSTCK)
• Instruction clock (INSTCK)
• Prescaler output (ORCLK)
• XIN input
• CNTR0 input
• System clock (STCK)
• Prescaler output (ORCLK)
• Timer 1 underflow (T1UDF)
• PWM output (PWMOUT)
• PWM output (PWMOUT)
• Prescaler output (ORCLK)
• Timer 2 underflow (T2UDF)
• CNTR1 input
• XIN input
• Prescaler output (ORCLK)
• Instruction clock (INSTCK) Structure 8-bit programmable binary down counter 8-bit programmable binary down counter (link to INT0 input) (period/pulse width measurement function) 8-bit programmable binary down counter 8-bit programmable binary down counter (link to INT1 input) 8-bit programmable binary down counter (PWM output function) 16-bit fixed dividing frequency Circuit Prescaler Timer 1 Timer 2 Timer 3 Timer 4 Watchdog timer Use of output signal
• Timer 1, 2, 3, amd 4 count sources
• Timer 2 count source
• CNTR0 output
• Timer 1 interrupt
• Timer 3 count source
• CNTR0 output
• Timer 2 interrupt
• CNTR1 output control
• Timer 3 interrupt
• Timer 2, 3 count source
• CNTR1 output
• Timer 4 interrupt
• System reset (count twice)
• WDF flag decision Frequency dividing ratio 1 to 256 1 to 256 1 to 256 1 to 256 1 to 256 65534 Control register PA Table 9 Function related timers

Rev.3.01 2005.06.15 page 32 of 160 REJ03B0007-0301 Fig. 25 Timer structure (1) System clock (STCK) Instruction clock (INSTCK) Multi- plexer (CMCK, CRCK, CYCK) (Note 1) MR 0 ORCLK Reload register RPS (8) Prescaler (8) Register B Register A (TABPS) (TABPS)(TPSAB) PA 0 MR 3, MR2 INSTCK W1 1, W10 (Note 3) ORCLK XIN T1F (TAB1)(TAB1) (T1AB) (T1AB) (T1AB) (TPSAB)(TPSAB) On-chip oscillator XIN Ceramic resonance RC oscillation Timer 1 (8) Timer 1 interrupt Reload register R1 (8) Register BRegister A Timer 1 underflow signal ( T1UDF) Internal clock generating circuit (divided by 3)Quartz-crystal oscillation W1 2 STCK W2 1, W20 ORCLK T1UDF PWMOUT T2F (TAB2) (TAB2)(T2AB)(T2AB) (T2AB) Timer 2 interrupt Timer 2 underflow signal (T2UDF) Timer 2 (8) Reload register R2 (8) Register BRegister A W2 2 W5 2 I12 P30/INT0 W1 3 T1UDF I10 I13 I11One-sided edge detection circuit Both edges detection circuit I10 S R Q W5 1, W50 W5 2 One-period generation circuit 1/16On-chip oscillator W6 2 D 6/CNTR0 W6 0 Port D6 output W2 3 1/2 T1UDF 1/2 T2UDF (Note 2) (TR1AB) TR1AB: PWMOUT: This instruction is used to transfer the contents of register A and register B to only reload register R1. PWM output signal (from timer 4 output unit) Data is set automatically from each reload register when timer underflows (auto-reload function). Notes 1: When CMCK instruction is executed, ceramic resonance is selected. When CRCK instruction is executed, RC oscillation is selected. When CYCK instruction is executed, quartz-crystal oscillator is selected. 2: Timer 1 count start synchronous circuit is set by the valid edge of P3 0/INT0 pin selected by bits 1 (I11) and 2 (I12) of register I1. 3: XIN cannot be used for the count source when bit 1 (MR1) of register MR is set to “1” and f(XIN) oscillation is stopped. W5 2 Divided by 4 Divided by 2 Divided by 8 Division circuit

Rev.3.01 2005.06.15 page 33 of 160 REJ03B0007-0301 Fig. 26 Timer structure (2) Watchdog timerINSTCK Q R S WDF1 WRST instruction Q R S WEF DWDT instruction WRST instruction RESET signal Q T D R RESET signal Watchdog reset signal PWMOUT I22 P31/INT1 W3 3 T3UDF I20 I23 I21 W3 1, W30 ORCLK T2UDF T3F (TAB3)(TAB3) (T3AB) (T3AB) (T3AB) Timer 3 (8) Timer 3 interrupt Reload register R3 (8) Register BRegister A Timer 3 underflow signal (T3UDF) One-sided edge detection circuit Both edges detection circuit W3 2 W6 3 I20 S R Q W4 3 PWMOD Q R D TW3 2 W6 1 T3UDF Port D7 output D 7/CNTR1 Register BRegister A Reload register R4H (8) (TAB4)(TAB4) (T4AB) (T4AB) (T4AB) Timer 4 (8) Reload register R4L (8) Register BRegister A Reload control circuit W4 1 W4 0 1/2ORCLK XIN “H ” interval expansion W4 2 T4F R QT W4 3 PWMOUT (T4HAB) (T4R4L) Timer 4 interrupt (Note 4) (TR3AB) (Note 3) (Note 5) (Note 6) TR3AB: T4R4L: INSTCK: ORCLK: This instruction is used to transfer the contents of register A and register B to only reload register R3. This instruction is used to transfer the contents of reload register R4L to timer 4. Instruction clock (system clock divided by 3) Prescaler output (instruction clock divided by 1 to 256) Data is set automatically from each reload register when timer underflows (auto-reload function). Notes 3: X IN cannot be used for the count source when bit 1 (MR1) of register MR is set to “1” and f(XIN) oscillation is stopped. 4: Timer 3 count start synchronous circuit is set by the valid edge of P31/INT1 pin selected by bits 1 (I21) and 2 (I22) of register I2. 5: Flag WDF1 is cleared to “0” and the next instruction is skipped when the WRST instruction is executed while flag WDF1 = “1”. The next instruction is not skipped even when the WRST instruction is executed while flag WDF1 = “0”. 6: Flag WEF is cleared to “0” and watchdog timer reset does not occur when the DWDT instruction and WRST instruction are executed continuously. 7: The WEF flag is set to “1” at system reset or RAM back-up mode. (Note 7)

Rev.3.01 2005.06.15 page 34 of 160 REJ03B0007-0301 Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”). 3: This function is valid only when the timer 3 count start synchronous circuit is selected (I20=“1”). Table 10 Timer related registers W2 1 Timer 1 underflow signal divided by 2 output Timer 2 underflow signal divided by 2 output Stop (state retained) Operating Count source System clock (STCK) Prescaler output (ORCLK) Timer 1 underflow signal (T1UDF) PWM signal (PWMOUT) CNTR0 output signal selection bit Timer 2 control bit Timer 2 count source selection bits Timer control register W2 at RAM back-up : state retainedat reset : 00002 W2 3 W2 2 W2 1 W2 0 W1 1 Timer 1 count auto-stop circuit not selected Timer 1 count auto-stop circuit selected Stop (state retained) Operating Count source Instruction clock (INSTCK) Prescaler output (ORCLK) X IN input CNTR0 input Timer 1 count auto-stop circuit selection bit (Note 2) Timer 1 control bit Timer 1 count source selection bits Timer control register W1 R/W TAW1/TW1Aat RAM back-up : state retainedat reset : 00002 W1 3 W1 2 W1 1 W1 0 R/W TAW2/TW2A W3 1 Timer 3 count auto-stop circuit not selected Timer 3 count auto-stop circuit selected Stop (state retained) Operating Count source PWM signal (PWMOUT) Prescaler output (ORCLK) Timer 2 underflow signal (T2UDF) CNTR1 input Timer 3 count auto-stop circuit selection bit (Note 3) Timer 3 control bit Timer 3 count source selection bits Timer control register W3 at RAM back-up : state retainedat reset : 00002 W3 3 W3 2 W3 1 W3 0 R/W TAW3/TW3A Stop (state initialized) Operating Prescaler control bit Timer control register PA W TPAAat RAM back-up : 02at reset : 02 PA 0

Rev.3.01 2005.06.15 page 35 of 160 REJ03B0007-0301 Falling edge Rising edge Falling edge Rising edge CNTR1 output auto-control circuit not selected CNTR1 output auto-control circuit selected D 6 (I/O) / CNTR0 (input) CNTR0 (I/O) /D6 (input) CNTR1 pin input count edge selection bit CNTR0 pin input count edge selection bit CNTR1 output auto-control circuit selection bit D 6/CNTR0 pin function selection bit Timer control register W6 at RAM back-up : state retainedat reset : 00002 W6 3 W6 2 W6 1 W6 0 D 7 (I/O) / CNTR1 (input) CNTR1 (I/O) / D7 (input) PWM signal “H ” interval expansion function invalid PWM signal “H ” interval expansion function valid Stop (state retained) Operating X IN input Prescaler output (ORCLK) divided by 2 D 7/CNTR1 pin function selection bit PWM signal “H ” interval expansion function control bit Timer 4 control bit Timer 4 count source selection bit W4 3 W4 2 W4 1 W4 0 W5 1 Not used Period measurement circuit control bit Signal for period measurement selection bits Timer control register W5 at RAM back-up : state retainedat reset : 00002 W5 3 W5 2 W5 1 W5 0 This bit has no function, but read/write is enabled. Stop Operating Count source On-chip oscillator (f(RING/16)) CNTR 0 pin input INT0 pin input Not available R/W TAW4/TW4A Timer control register W4 at RAM back-up : 00002at reset : 00002 R/W TAW5/TW5A R/W TAW6/TW6A Note: “R ” represents read enabled, and “W ” represents write enabled.

Rev.3.01 2005.06.15 page 36 of 160 REJ03B0007-0301 (1) Timer control registers

• Timer control register PA Register PA controls the count operation of prescaler. Set the contents of this register through register A with the TPAA instruc- tion.
• Timer control register W1 Register W1 controls the selection of timer 1 count auto-stop cir- cuit, and the count operation and count source of timer 1. Set the contents of this register through register A with the TW1A instruc- tion. The TAW1 instruction can be used to transfer the contents of register W1 to register A.
• Timer control register W2 Register W2 controls the selection of CNTR0 output, and the count operation and count source of timer 2. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A.
• Timer control register W3 Register W3 controls the selection of the count operation and count source of timer 3 count auto-stop circuit. Set the contents of this register through register A with the TW3A instruction. The TAW3 instruction can be used to transfer the contents of register W3 to register A.
• Timer control register W4 Register W4 controls the D 7/CNTR1 output, the expansion of “H ” interval of PWM output, and the count operation and count source of timer 4. Set the contents of this register through regis- ter A with the TW4A instruction. The TAW4 instruction can be used to transfer the contents of register W4 to register A.
• Timer control register W5 Register W5 controls the period measurement circuit and target signal for period measurement. Set the contents of this register through register A with the TW5A instruction. The TAW5 instruc- tion can be used to transfer the contents of register W5 to register A.
• Timer control register W6 Register W6 controls the count edges of CNTR0 pin and CNTR1 pin, selection of CNTR1 output auto-control circuit and the D CNTR0 pin function. Set the contents of this register through reg- ister A with the TW6A instruction. The TAW6 instruction can be used to transfer the contents of register W6 to register A.. (2) Prescaler Prescaler is an 8-bit binary down counter with the prescaler reload register PRS. Data can be set simultaneously in prescaler and the reload register RPS with the TPSAB instruction. Data can be read from reload register RPS with the TABPS instruction. Stop counting and then execute the TPSAB or TABPS instruction to read or set prescaler data. Prescaler starts counting after the following process; ➀ set data in prescaler, and ➁ set the bit 0 of register PA to “1.” When a value set in reload register RPS is n, prescaler divides the count source signal by n + 1 (n = 0 to 255). Count source for prescaler is the instruction clock (INSTCK). Once count is started, when prescaler underflows (the next count pulse is input after the contents of prescaler becomes “0”), new data is loaded from reload register RPS, and count continues (auto-reload function). The output signal (ORCLK) of prescaler can be used for timer 1, 2, 3, and 4 count sources. (3) Timer 1 (interrupt function) Timer 1 is an 8-bit binary down counter with the timer 1 reload reg- ister (R1). Data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. Data can be written to re- load register (R1) with the TR1AB instruction. Data can be read from timer 1 with the TAB1 instruction. Stop counting and then execute the T1AB or TAB1 instruction to read or set timer 1 data. When executing the TR1AB instruction to set data to reload regis- ter R1 while timer 1 is operating, avoid a timing when timer 1 underflows. Timer 1 starts counting after the following process; ➀ set data in timer 1 ➁ set count source by bits 0 and 1 of register W1, and ➂ set the bit 2 of register W1 to “1.” When a value set in reload register R1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes “0”), the timer 1 interrupt request flag (T1F) is set to “1,” new data is loaded from reload register R1, and count continues (auto-reload function). INT0 pin input can be used as the start trigger for timer 1 count op- eration by setting the bit 0 of register I1 to “1.” Also, in this time, the auto-stop function by timer 1 underflow can be performed by setting the bit 3 of register W1 to “1.” Timer 1 underflow signal divided by 2 can be output from CNTR0 pin by clearing bit 3 of register W2 to “0” and setting bit 0 of regis- ter W6 to “1”. The period measurement circuit starts operating by setting bit 2 of register W5 to “1” and timer 1 is used to count the one-period of the target signal for the period measurement. In this time, the timer 1 interrupt request flag (T1F) is not set by the timer 1 underflow sig- nal, it is the flag for detecting the completion of period measurement.

Rev.3.01 2005.06.15 page 37 of 160 REJ03B0007-0301 (4) Timer 2 (interrupt function) Timer 2 is an 8-bit binary down counter with the timer 2 reload reg- ister (R2). Data can be set simultaneously in timer 2 and the reload register (R2) with the T2AB instruction. Data can be read from timer 2 with the TAB2 instruction. Stop counting and then execute the T2AB or TAB2 instruction to read or set timer 2 data. Timer 2 starts counting after the following process; ➀ set data in timer 2, ➁ select the count source with the bits 0 and 1 of register W2, and ➂ set the bit 2 of register W2 to “1.” When a value set in reload register R2 is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes “0”), the timer 2 interrupt request flag (T2F) is set to “1,” new data is loaded from reload register R2, and count continues (auto-reload function). Timer 2 underflow signal divided by 2 can be output from CNTR0 pin by setting bit 3 of register W2 to “1” and setting bit 0 of register W6 to “1”. (5) Timer 3 (interrupt function) Timer 3 is an 8-bit binary down counter with the timer 3 reload reg- ister (R3). Data can be set simultaneously in timer 3 and the reload register (R3) with the T3AB instruction. Data can be written to re- load register (R3) with the TR3AB instruction. Data can be read from timer 3 with the TAB3 instruction. Stop counting and then execute the T3AB or TAB3 instruction to read or set timer 3 data. When executing the TR3AB instruction to set data to reload regis- ter R3 while timer 3 is operating, avoid a timing when timer 3 underflows. Timer 3 starts counting after the following process; ➀ set data in timer 3 ➁ set count source by bits 0 and 1 of register W3, and ➂ set the bit 2 of register W3 to “1.” When a value set in reload register R3 is n, timer 3 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 3 underflows (the next count pulse is input after the contents of timer 3 becomes “0”), the timer 3 interrupt request flag (T3F) is set to “1,” new data is loaded from reload register R3, and count continues (auto-reload function). INT1 pin input can be used as the start trigger for timer 3 count op- eration by setting the bit 0 of register I2 to “1.” Also, in this time, the auto-stop function by timer 3 underflow can be performed by setting the bit 3 of register W3 to “1.” (6) Timer 4 (interrupt function) Timer 4 is an 8-bit binary down counter with two timer 4 reload reg- isters (R4L, R4H). Data can be set simultaneously in timer 4 and the reload register R4L with the T4AB instruction. Data can be set in the reload register R4H with the T4HAB instruction. The contents of reload register R4L set with the T4AB instruction can be set to timer 4 again with the T4R4L instruction. Data can be read from timer 4 with the TAB4 instruction. Stop counting and then execute the T4AB or TAB4 instruction to read or set timer 4 data. When executing the T4HAB instruction to set data to reload regis- ter R4H while timer 4 is operating, avoid a timing when timer 4 underflows. Timer 4 starts counting after the following process; ➀ set data in timer 4 ➁ set count source by bit 0 of register W4, and ➂ set the bit 1 of register W4 to “1.” When a value set in reload register R4L is n, timer 4 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 4 underflows (the next count pulse is input after the contents of timer 4 becomes “0”), the timer 4 interrupt request flag (T4F) is set to “1,” new data is loaded from reload register R4L, and count continues (auto-reload function). The PWM signal generated by timer 4 can be output from CNTR1 pin by setting bit 3 of the timer control register W4 to “1”. Timer 4 can control the PWM output to CNTR1 pin with timer 3 by setting bit 1 of the timer control register W6 to “1”.

Rev.3.01 2005.06.15 page 38 of 160 REJ03B0007-0301 LA 0 ; ( ✕ 0✕✕ 2) LA 0 ; ( ✕ 0✕✕ 2) TW5A ; Period measurement circuit stop SNZT1 ; The SNZT1 instruction is executed (T1F flag cleared) ✕ : these bits are not used here. Fig. 27 Period measurement circuit program example

• ••
• •• (7) Period measurement function (Timer 1, period measurement circuit) Timer 1 has the period measurement circuit which performs timer count operation synchronizing with the one cycle of the signal di- vided by 16 of the on-chip oscillator, D 6/CNTR0 pin input, or P30/ INT0 pin input (one cycle, “H ”, or “L” pulse width at the case of a P30/INT0 pin input). When the target signal for period measurement is set by bits 0 and 1 of register W5, a period measurement circuit is started by setting the bit 2 of register W5 to “1”. Then, if a X IN input is set as the count source of a timer 1 and the bit 2 of register W1 is set to “1”, timer 1 starts operation. Timer 1 starts operation synchronizing with the falling edge of the target signal for period measurement, and stops count operation synchronizing with the next falling edge (one-period generation circuit). When selecting D 6/CNTR0 pin input as target signal for period measurement, the period measurement synchronous edge can be changed into a rising edge by setting the bit 2 of register W6 to “1”. When selecting P3 0/INT0 pin input as target signal for period measurement, period measurement synchronous edge can be changed into a rising edge by setting the bit 2 of register I1 to “1”. A timer 1 interrupt request flag (T1F) is set to “1” after completing measurement operation. When a period measurement circuit is set to be operating, timer 1 interrupt request flag (T1F) is not set by timer 1 underflow sig- nal, but turns into a flag which detects the completion of period measurement. In addition, a timer 1 underflow signal can be used as timer 2 count source. Once period measurement operation is completed, even if period measurement valid edge is input next, timer 1 is in a stop state and measurement data is held. When a period measurement circuit is used again, stop a period measurement circuit at once by setting the bit 2 of register W5 to “0”, and change a period measurement circuit into a state of op- eration by setting the bit 2 of register W5 to “1” again. When a period measurement circuit is used, clear bit 0 of regis- ter I1 to “0”, and set a timer 1 count start synchronous circuit to be “not selected”. Start timer operation immediately after operation of a period measurement circuit is started. When the target edge for measurement is input until timer opera- tion is started from the operation of period measurement circuit is started, the count operation is not executed until the timer opera- tion becomes valid. Accordingly, be careful of count data. When data is read from timer, stop the timer and clear bit 2 of register W5 to “0” to stop the period measurement circuit, and then execute the data read instruction. Depending on the state of timer 1, the timer 1 interrupt request flag (T1F) may be set to “1” when the period measurement cir- cuit is stopped by clearing bit 2 of register W5 to “0”. In order to avoid the occurrence of an unexpected interrupt, clear the bit 2 of register V1 to “0” (refer to Figure 27➀ ) and then, stop the bit 2 of register W5 to “0” to stop the period measurement circuit. In addition, execute the SNZT1 instruction to clear the T1F flag after executing at least one instruction (refer to Figure 27➁ ). Also, set the NOP instruction for the case when a skip is per- formed with the SNZT1 instruction (refer to Figure 27➂ ). When a period measurement circuit is used, select the suffi- ciently higher-speed frequency than the signal for measurement for the count source of a timer 1. When the target signal for period measurement is D 6/CNTR0 pin input, do not select D6/CNTR0 pin input as timer 1 count source. (The XIN input is recommended as timer 1 count source at the time of period measurement circuit use.) (8) Pulse width measurement function (timer 1, period measurement circuit) A period measurement circuit can measure “H ” pulse width (from rising to falling) or “L” pulse width (from falling to rising) of P30/ INT0 pin input (pulse width measurement function) when the fol- lowing is set;
• Set the bit 0 of register W5 to “0”, and set a bit 1 to “1” (target for period measurement circuit: 30/INT0 pin input).
• Set the bit 1 of register I1 to “1” (INT0 pin edge detection circuit: both edges detection) The measurement pulse width (“H ” or “L”) is decided by the pe- riod measurement circuit and the P3 0/INT0 pin input level at the start time of timer operation. At the time of the start of a period measurement circuit and timer operation, “L” pulse width (from falling to rising) when the input level of P3 0/INT0 pin is “H ” or “H ” pulse width (from rising to fall- ing) when its level is “L” is measured. When the input of P30/INT0 pin is selected as the target for mea- surement, set the bit 3 of register I1 to “1”, and set the input of INT0 pin to be enabled.

Rev.3.01 2005.06.15 page 39 of 160 REJ03B0007-0301 (11) Timer input/output pin (D6/CNTR0 pin, D7/CNTR1 pin) CNTR0 pin is used to input the timer 1 count source and output the timer 1 and timer 2 underflow signal divided by 2. CNTR1 pin is used to input the timer 3 count source and output the PWM signal generated by timer 4. The D 6/CNTR0 pin function can be selected by bit 0 of register W6. The selection of D7/CNTR1 output signal can be controlled by bit 3 of register W4. When the CNTR0 input is selected for timer 1 count source, timer 1 counts the rising or falling waveform of CNTR0 input. The count edge is selected by the bit 2 of register W6. When the CNTR1 input is selected for timer 3 count source, timer 3 counts the rising or falling waveform of CNTR1 input. The count edge is selected by the bit 3 of register W6. (12) PWM output function (D7/CNTR1, timer 3, timer 4) When bit 3 of register W4 is set to “1”, timer 4 reloads data from re- load register R4L and R4H alternately each underflow. Timer 4 generates the PWM signal (PWMOUT) of the “L” interval set as reload register R4L, and the “H ” interval set as reload regis- ter R4H. The PWM signal (PWMOUT) is output from CNTR1 pin. When bit 2 of register W4 is set to “1” at this time, the interval (PWM signal “H ” interval) set to reload register R4H for the counter of timer 4 is extended for a half period of count source. In this case, when a value set in reload register R4H is n, timer 4 divides the count source signal by n + 1.5 (n = 1 to 255). When this function is used, set “1” or more to reload register R4H. When bit 1 of register W6 is set to “1”, the PWM signal output to CNTR1 pin is switched to valid/invalid each timer 3 underflow. However, when timer 3 is stopped (bit 2 of register W3 is cleared to “0”), this function is canceled. Even when bit 1 of a register W4 is cleared to “0” in the “H ” interval of PWM signal, timer 4 does not stop until it next timer 4 underflow. When clearing bit 1 of register W4 to “0” to stop timer 4 while the PWM output function is used, avoid a timing when timer 4 underflows. (9) Count start synchronization circuit (timer 1, timer 3) Timer 1 and timer 3 have the count start synchronous circuit which synchronizes the input of INT0 pin and INT1 pin, and can start the timer count operation. Timer 1 count start synchronous circuit function is selected by set- ting the bit 0 of register I1 to “1” and the control by INT0 pin input can be performed. Timer 3 count start synchronous circuit function is selected by set- ting the bit 0 of register I2 to “1” and the control by INT1 pin input can be performed. When timer 1 or timer 3 count start synchronous circuit is used, the count start synchronous circuit is set, the count source is input to each timer by inputting valid waveform to INT0 pin or INT1 pin. The valid waveform of INT0 pin or INT1 pin to set the count start synchronous circuit is the same as the external interrupt activated condition. Once set, the count start synchronous circuit is cleared by clearing the bit I1 0 or I20 to “0” or reset. However, when the count auto-stop circuit is selected, the count start synchronous circuit is cleared (auto-stop) at the timer 1 or timer 3 underflow. (10) Count auto-stop circuit (timer 1, timer 3) Timer 1 has the count auto-stop circuit which is used to stop timer 1 automatically by the timer 1 underflow when the count start syn- chronous circuit is used. The count auto-stop cicuit is valid by setting the bit 3 of register W1 to “1”. It is cleared by the timer 1 underflow and the count source to timer 1 is stopped. This function is valid only when the timer 1 count start synchronous circuit is selected. Timer 3 has the count auto-stop circuit which is used to stop timer 3 automatically by the timer 3 underflow when the count start syn- chronous circuit is used. The count auto-stop cicuit is valid by setting the bit 3 of register W3 to “1”. It is cleared by the timer 3 underflow and the count source to timer 3 is stopped. This function is valid only when the timer 3 count start synchronous circuit is selected.

Rev.3.01 2005.06.15 page 40 of 160 REJ03B0007-0301 (13) Timer interrupt request flags (T1F, T2F, T3F, T4F) Each timer interrupt request flag is set to “1” when each timer underflows. The state of these flags can be examined with the skip instructions (SNZT1, SNZT2, SNZT3, SNZT4). Use the interrupt control register V1, V2 to select an interrupt or a skip instruction. An interrupt request flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with a skip instruction. The timer 1 interrupt request flag (T1F) is not set by the timer 1 under- flow signal, it is the flag for detecting the completion of period measurement. (14) Precautions Note the following for the use of timers.

• Prescaler Stop counting and then execute the TABPS instruction to read from prescaler data. Stop counting and then execute the TPSAB instruction to set prescaler data.
• Timer count source Stop timer 1, 2, 3 and 4 counting to change its count source.
• Reading the count value Stop timer 1, 2, 3 or 4 counting and then execute the data read instruction (TAB1, TAB2, TAB3, TAB4) to read its data.
• Writing to the timer Stop timer 1, 2, 3 or 4 counting and then execute the data write instruction (T1AB, T2AB, T3AB, T4AB) to write its data.
• Writing to reload register R1, R3, R4H When writing data to reload register R1, reload register R3 or re- load register R4H while timer 1, timer 3 or timer 4 is operating, avoid a timing when timer 1, timer 3 or timer 4 underflows.
• Timer 4 In order to stop timer 4 while the PWM output function is used, avoid a timing when timer 4 underflows. When “H” interval extension function of the PWM signal is set to be “valid”, set “1” or more to reload register R4H.
• Period measurement function When a period measurement circuit is used, clear bit 0 of regis- ter I1 to “0”, and set a timer 1 count start synchronous circuit to be “not selected”. Start timer operation immediately after operation of a period measurement circuit is started. When the target edge for measurement is input until timer opera- tion is started from the operation of period measurement circuit is started, the count operation is not executed until the timer opera- tion becomes valid. Accordingly, be careful of count data. When data is read from timer, stop the timer and clear bit 2 of register W5 to “0” to stop the period measurement circuit, and then execute the data read instruction. Depending on the state of timer 1, the timer 1 interrupt request flag (T1F) may be set to “1” when the period measurement cir- cuit is stopped by clearing bit 2 of register W5 to “0”. In order to avoid the occurrence of an unexpected interrupt, clear the bit 2 of register V1 to “0” (refer to Figure 28➀ ) and then, stop the bit 2 of register W5 to “0” to stop the period measurement circuit. In addition, execute the SNZT1 instruction to clear the T1F flag after executing at least one instruction (refer to Figure 28➁ ). Also, set the NOP instruction for the case when a skip is per- formed with the SNZT1 instruction (refer to Figure 28➂ ). LA 0 ; ( ✕ 0✕✕ LA 0 ; ( ✕ 0✕✕ 2) TW5A ; Period measurement circuit stop SNZT1 ; The SNZT1 instruction is executed (T1F flag cleared) ✕ : these bits are not used here. Fig. 28 Period measurement circuit program example While a period measurement circuit is operating, the timer 1 in- terrupt request flag (T1F) is not set by the timer 1 underflow signal, it is the flag for detecting the completion of period mea- surement. When a period measurement circuit is used, select the suffi- ciently higher-speed frequency than the signal for measurement for the count source of a timer 1. When the target signal for period measurement is D 6/CNTR0 pin input, do not select D6/CNTR0 pin input as timer 1 count source. (The XIN input is recommended as timer 1 count source at the time of period measurement circuit use.) When the input of P30/INT0 pin is selected for measurement, set the bit 3 of a register I1 to “1”, and set the input of INT0 pin to be enabled.
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Rev.3.01 2005.06.15 page 41 of 160 REJ03B0007-0301

• Prescaler, Timer 1, Timer 2 and Timer 3 count start timing and count time when operation starts Count starts from the first rising edge of the count source (2) af- ter Prescaler, Timer 1, Timer 2 and Timer 3 operations start (1). Time to first underflow (3) is shorter (for up to 1 period of the count source) than time among next underflow (4) by the timing to start the timer and count source operations after count starts. Fig. 29 Timer count start timing and count time when opera- tion starts (Prescaler, Timer 1, Timer 2 and Timer 3)
• Timer 4 count start timing and count time when operation starts Count starts from the rising edge (2) after the first falling edge of the count source, after Timer 4 operations start (1). Time to first underflow (3) is different from time among next un- derflow (4) by the timing to start the timer and count source operations after count starts. Fig. 30 Timer count start timing and count time when opera- tion starts (Timer 4) (1) Timer Start Count Source Timer value Timer Underflow signal 3 21032103 (4)(3) (2) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines (1) Timer Start Count Source Timer Value Timer Underflow Signal 3 21032103 (4)(3) (2) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

Rev.3.01 2005.06.15 page 42 of 160 REJ03B0007-0301 Fig. 31 Timer 4 operation (reload register R4L: “0316”, R4H: “0216”) G CNTR1 output: invalid (W43 = “0”) Timer 4 count source Timer 4 count value (Reload register) 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 00160316 (R4L) Timer 4 underflow signal PWM signal (output invalid) Timer 4 start PWM signal “L” fixed 02160316 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 (R4H) PWM period 7 clock PWM period 7 clock 0316 0116 00160216 0216 0116 0016 0216 0116 00160316 0216 0116 0016 0216 0116 00160316 0216 (R4L) (R4H) (R4L) (R4H) (R4L) (R4H) PWM period 7.5 clock PWM period 7.5 clock G CNTR1 output: valid (W43 = “1”) PWM signal “H ” interval extension function: invalid (W42 = “0”) Timer 4 count source Timer 4 count value (Reload register) Timer 4 underflow signal PWM signal Timer 4 count source Timer 4 count value (Reload register) Timer 4 underflow signal PWM signal Timer 4 start Timer 4 start G CNTR1 output: valid (W43 = “1”) PWM signal “H ” interval extension function: valid (W42 = “1”) (Note) Note: At PWM signal “H ” interval extension function: valid, set “0116” or more to reload register R4H. (R4L) (R4H) (R4L) (R4H) (R4L) (R4L) (R4L) (R4L)(R4L) 3 clock 3 clock 3.5 clock3.5 clock

Rev.3.01 2005.06.15 page 43 of 160 REJ03B0007-0301 Fig. 32 CNTR1 output auto-control function by timer 3 CNTR1 output auto-control circuit by timer 3 is selected. CNTR1 output Register W61 When the CNTR1 output auto-control function is set to be invalid while the CNTR1 output is invalid, the CNTR1 output invalid state is retained. When the CNTR1 output auto-control function is set to be invalid while the CNTR1 output is valid, the CNTR1 output valid state is retained. When timer 3 is stopped, the CNTR1 output auto-control function becomes invalid. G CNTR1 output: valid (W4 3 = “1”) CNTR1 output auto-control circuit selected (W61 = “1”) Timer 3 underflow signal PWM signal Timer 3 start CNTR1 output start G CNTR1 output auto-control function CNTR1 output Timer 3 underflow signal PWM signal Timer 3 start CNTR1 output start Timer 3 stop CNTR1 output stop ➀ ➁

Rev.3.01 2005.06.15 page 44 of 160 REJ03B0007-0301 Fig. 33 Timer 4 count start/stop timing (R4L) (R4H) (R4L) Timer 4 count start timing Waveform extension function of CNTR1 output “H ” interval: Invalid (W42 = “0”), CNTR1 output: valid (W43 = “1”), Count source: XIN input selected (W40 = “0”), Reload register R4L: “0316” Reload register R4H: “0216” Timer 4 count start timing TW4A instruction execution cycle (W41) ← 1 0216 0116 0016 021603160216 0116 00160316 021600160016 0216 0116 0016 0316 0216 01160216 (R4H)(R4L) 0116 (R4H) (Note 1) Notes 1: In order to stop timer 4 at CNTR1 output valid (W43 = “1”), avoid a timing when timer 4 underflows. If these timings overlap, a hazard may occur in a CNTR1 output waveform. 2: At CNTR1 output valid, timer 4 stops after “H ” interval of PWM signal set by reload register R4H is output. Mi Mi+1 Mi+2 Mi Mi+1 Mi+2 0116Timer 4 count value (Reload register) Timer 4 underflow signal PWM signal Machine cycle XIN input (count source selected) System clock f(STCK)=f(XIN)/4 Register W41 G Timer 4 count stop timing TW4A instruction execution cycle (W41) ← 0 Timer 4 count stop timing Timer 4 count value (Reload register) Timer 4 underflow signal PWM signal Machine cycle XIN input (count source selected) System clock f(STCK)=f(XIN)/4 Register W41

Rev.3.01 2005.06.15 page 45 of 160 REJ03B0007-0301 WATCHDOG TIMER Watchdog timer provides a method to reset the system when a pro- gram run-away occurs. Watchdog timer consists of timer WDT(16-bit binary counter), watchdog timer enable flag (WEF), and watchdog timer flags (WDF1, WDF2). The timer WDT downcounts the instruction clocks as the count source from “FFFF 16” after system is released from reset. After the count is started, when the timer WDT underflow occurs (after the count value of timer WDT reaches “0000 16,” the next count pulse is input), the WDF1 flag is set to “1.” If the WRST instruction is never executed until the timer WDT un- derflow occurs (until timer WDT counts 65534), WDF2 flag is set to “1,” and the RESET pin outputs “L” level to reset the microcom- puter. Execute the WRST instruction at each period of 65534 machine cycle or less by software when using watchdog timer to keep the microcomputer operating normally. When the WEF flag is set to “1” after system is released from reset, the watchdog timer function is valid. When the DWDT instruction and the WRST instruction are ex- ecuted continuously, the WEF flag is cleared to “0” and the watchdog timer function is invalid. The WEF flag is set to "1" at system reset or RAM back-up mode. The WRST instruction has the skip function. When the WRST in- struction is executed while the WDF1 flag is “1”, the WDF1 flag is cleared to “0” and the next instruction is skipped. When the WRST instruction is executed while the WDF1 flag is “0”, the next instruction is not skipped. The skip function of the WRST instruction can be used even when the watchdog timer function is invalid. Fig. 34 Watchdog timer function c o u n t N o t e V a l u e o f b i t t i m e r W D T W D F f l a g W R S T i n s t r u c t i o n e x e c u t e d s k i p e x e c u t e d R E S E T p i n o u t p u t W D F f l a g ➄ System reset➀ R e s e t r e l e a s e d A f t e r s y s t e m i s r e l e a s e d f r o m r e s e t a f t e r p r o g r a m i s s t a r t e d t i m e r W D T s t a r t s c o u n t d o w n W h e n t i m e r W D T u n d e r f l o w o c c u r s W D F f l a g i s s e t t o W h e n t h e W R S T i n s t r u c t i o n i s e x e c u t e d W D F f l a g i s c l e a r e d t o t h e n e x t i n s t r u c t i o n i s s k i p p e d W h e n t i m e r W D T u n d e r f l o w o c c u r s w h i l e W D F f l a g i s W D F f l a g i s s e t t o a n d t h e w a t c h d o g r e s e t s i g n a l i s o u t p u t T h e o u t p u t t r a n s i s t o r o f R E S E T p i n i s t u r n e d O N b y t h e w a t c h d o g r e s e t s i g n a l a n d s y s t e m r e s e t i s e x e c u t e d N o t e T h e n u m b e r o f c o u n t i s e q u a l t o t h e n u m b e r o f c y c l e b e c a u s e t h e c o u n t s o u r c e o f w a t c h d o g t i m e r i s t h e i n s t r u c t i o n c l o c k F F F ➁ ➁

Rev.3.01 2005.06.15 page 46 of 160 REJ03B0007-0301 Fig. 35 Program example to start/stop watchdog timer Fig. 36 Program example to enter the mode when using the watchdog timer WRST ; WDF1 flag cleared NOP DI ; Interrupt disabled EPOF ; POF instruction enabled POF Oscillation stop

• ••
• •• When the watchdog timer is used, clear the WDF1 flag at the pe- riod of 65534 machine cycles or less with the WRST instruction. When the watchdog timer is not used, execute the DWDT instruc- tion and the WRST instruction continuously (refer to Figure 35). The watchdog timer is not stopped with only the DWDT instruction. The contents of WDF1 flag and timer WDT are initialized at the RAM back-up mode. When using the watchdog timer and the RAM back-up mode, ini- tialize the WDF1 flag with the WRST instruction just before the microcomputer enters the RAM back-up state (refer to Figure 36). The watchdog timer function is valid after system is returned from the RAM back-up. When not using the watchdog timer function, ex- ecute the DWDT instruction and the WRST instruction continuously every system is returned from the RAM back-up, and stop the watchdog timer function. WRST ; WDF1 flag cleared DI DWDT ; Wat chdog timer function enabled/disabled WRST ; WEF and WDF1 flags cleared
• ••

Rev.3.01 2005.06.15 page 47 of 160 REJ03B0007-0301 VSS VDD IAP4 (P4 0–P43) IAP6 (P6 0–P63) OP4A (P4 0–P43) OP6A (P6 0–P63) TABAD Q1 3 Q2 1 Q2 0Q2 2 TADAB Q1 2 Q1 1 Q1 0 8 8 01 1 Q1 3 Q1 3 Q1 3 TALA Q1 3 Q2 3 TAQ2 TQ2A TAQ1 TQ1A ADF (1)P60/AIN0 P40/AIN4 P41/AIN5 P42/AIN6 P43/AIN7 P61/AIN1 P62/AIN2 P63/AIN3 4 4 Q3 1 Q3 0Q3 2Q3 3 TAQ3 TQ3A4 (Note 1) Register A (4) Register B (4) DAC operation signal Comparator 8-channel multi-plexed analog switch Instruction clock A/D control circuit Successive comparison register (AD) (10) A/D interrupt Comparator register (8) Notes 1: This switch is turned ON only when A/D converter is operating and generates the comparison voltage. 2: Writing/reading data to the comparator register is possible only in the comparator mode (Q13=1). The value of the comparator register is retained even when the mode is switched to the A/D conversion mode (Q1 3=0) because it is separated from the successive comparison register (AD). Also, the resolution in the comparator mode is 8 bits because the comparator register consists of 8 bits. (Note 2) Q3 1, Q30 Q3 2 On-chip oscillator clock A/D conversion clock (ADCK) Division circuit Divided by 48 Divided by 24 Divided by 12 Divided by 6 DA converter A/D CONVERTER (Comparator) The 4519 Group has a built-in A/D conversion circuit that performs conversion by 10-bit successive comparison method. Table 11 shows the characteristics of this A/D converter. This A/D converter can also be used as an 8-bit comparator to compare analog volt- ages input from the analog input pin with preset values. Table 11 A/D converter characteristics Characteristics Successive comparison method 10 bits Linearity error: ±2LSB (2.7 V ≤ V DD ≤ 5.5V) Differential non-linearity error: ±0.9LSB (2.2 V ≤ V DD ≤ 5.5V) 31 µs (f(XIN) = 6 MHz, STCK = f(XIN) (XIN through-mode), ADCK = INSTCK/6) Parameter Conversion format Resolution Relative accuracy Conversion speed Analog input pin Fig. 37 A/D conversion circuit structure

Rev.3.01 2005.06.15 page 48 of 160 REJ03B0007-0301 Table 12 A/D control registers Q1 2 A/D operation mode selection bit Analog input pin selection bits A/D control register Q1 at RAM back-up : state retainedat reset : 00002 Q1 3 A/D conversion mode Comparator mode R/W TAQ1/TQ1A Q1 0 Q1 2 Q1 1 Q1 0 Analog input pins AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 P40, P41, P42, P43 AIN4, AIN5, AIN6, AIN7 P62, P63 AIN2, AIN3 P61 AIN1 P60 AIN0 P40/AIN4, P41/AIN5, P42/AIN6, P43/AIN7 pin function selection bit P62/AIN2, P63/AIN3 pin function selection bit P61/AIN1 pin function selection bit P60/AIN0 pin function selection bit Q2 3 Q2 2 Q2 1 Q2 0 R/W TAQ2/TQ2A A/D control register Q2 at RAM back-up : state retainedat reset : 00002 Note: “R ” represents read enabled, and “W ” represents write enabled. Not used A/D converter operation clock selection bit A/D converter operation clock division ratio selection bits A/D control register Q3 Q3 3 Q3 2 Q3 1 Q3 0 at reset : 00002 at RAM back-up : state retained Division ratio Frequency divided by 6 Frequency divided by 12 Frequency divided by 24 Frequency divided by 48 This bit has no function, but read/write is enabled. Instruction clock (INSTCK) On-chip oscillator (f(RING)) R/W TAQ3/TQ3A

Rev.3.01 2005.06.15 page 49 of 160 REJ03B0007-0301 (1) A/D control register

• A/D control register Q1 Register Q1 controls the selection of A/D operation mode and the selection of analog input pins. Set the contents of this register through register A with the TQ1A instruction. The TAQ1 instruc- tion can be used to transfer the contents of register Q1 to register
• A/D control register Q2 Register Q2 controls the selection of P4 0/AIN4–P4 3/AIN7, P60/ AIN0–P63/AIN3. Set the contents of this register through register A with the TQ2A instruction. The TAQ2 instruction can be used to transfer the contents of register Q2 to register A.
• A/D control register Q3 Register Q3 controls the selection of A/D converter operation clock. Set the contents of this register through register A with the TQ3A instruction. The TAQ3 instruction can be used to transfer the contents of register Q3 to register A. (2) Operating at A/D conversion mode The A/D conversion mode is set by setting the bit 3 of register Q1 to “0.” (3) Successive comparison register AD Register AD stores the A/D conversion result of an analog input in 10-bit digital data format. The contents of the high-order 8 bits of this register can be stored in register B and register A with the TABAD instruction. The contents of the low-order 2 bits of this reg- ister can be stored into the high-order 2 bits of register A with the TALA instruction. However, do not execute these instructions dur- ing A/D conversion. When the contents of register AD is n, the logic value of the com- parison voltage V ref generated from the built-in D/A converter can be obtained with the reference voltage VDD by the following for- mula: Logic value of comparison voltage Vref Vref = ✕ n n: The value of register AD (n = 0 to 1023) V DD 1024 (4) A/D conversion completion flag (ADF) A/D conversion completion flag (ADF) is set to “1” when A/D con- version completes. The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction. The ADF flag is cleared to “0” when the interrupt occurs or when the next instruction is skipped with the skip instruction. (5) A/D conversion start instruction (ADST) A/D conversion starts when the ADST instruction is executed. The conversion result is automatically stored in the register AD. (6) Operation description A/D conversion is started with the A/D conversion start instruction (ADST). The internal operation during A/D conversion is as follows: ➀ When the A/D conversion starts, the register AD is cleared to “00016.” ➁ Next, the topmost bit of the register AD is set to “1,” and the com- parison voltage Vref is compared with the analog input voltage VIN. ➂ When the comparison result is Vref < VIN, the topmost bit of the register AD remains set to “1.” When the comparison result is Vref > VIN, it is cleared to “0.” The 4519 Group repeats this operation to the lowermost bit of the register AD to convert an analog value to a digital value. A/D con- version stops after 2 machine cycles + A/D conversion clock (31 µs when f(XIN) = 6.0 MHz in XIN through mode, f(ADCK) = f(INSTCK)/ 6) from the start, and the conversion result is stored in the register AD. An A/D interrupt activated condition is satisfied and the ADF flag is set to “1” as soon as A/D conversion completes (Figure 38). Table 13 Change of successive comparison register AD during A/D conversion Comparison voltage (Vref) valueChange of successive comparison register ADAt starting conversion ✼ 1: 1st comparison result ✼ 3: 3rd comparison result ✼ 9: 9th comparison result ✼ 2: 2nd comparison result ✼ 8: 8th comparison result ✼ A: 10th comparison result 1st comparison 2nd comparison 3rd comparison After 10th comparison completes ✼ 1 ✼ 1 ✼ 1 ----- ----- ----- ----- ✼ 2 ✼ 2 ✼ 3 ✼ 8 ✼ 9 ✼ A A/D conversion result V DD VDD VDD VDD VDD VDD VDD VDD 1024 ○○○ ○

Rev.3.01 2005.06.15 page 50 of 160 REJ03B0007-0301 Fig. 39 Setting registers A/D control register Q2 A IN0 pin function selected ✕✕✕ 1 (Bit 3) (Bit 0) (7) A/D conversion timing chart Figure 38 shows the A/D conversion timing chart. Fig. 38 A/D conversion timing chart (8) How to use A/D conversion How to use A/D conversion is explained using as example in which the analog input from P60/AIN0 pin is A/D converted, and the high- order 4 bits of the converted data are stored in address M(Z, X, Y) = (0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1), and the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM. The A/D interrupt is not used in this example. Instruction clock/6 is selected as the A/D converter operation clock. ➀ Select the A IN0 pin function with the bit 0 of the register Q2. Se- lect the AIN0 pin function and A/D conversion mode with the register Q1. Also, the instruction clock divided by 6 is selected with the register Q3. (refer to Figure 39) ➁ Execute the ADST instruction and start A/D conversion. ➂ Examine the state of ADF flag with the SNZAD instruction to de- termine the end of A/D conversion. ➃ Transfer the low-order 2 bits of converted data to the high-order 2 bits of register A (TALA instruction). ➄ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2). ➅ Transfer the high-order 8 bits of converted data to registers A and B (TABAD instruction). ➆ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1). ➇ Transfer the contents of register B to register A, and then, store into M(Z, X, Y) = (0, 0, 0). A/D control register Q1 A IN0 pin selected A/D conversion mode 0000 (Bit 3) (Bit 0) ✕ : Set an arbitrary value. ADST instruction A/D conversion completion flag (ADF) 2 machine cycles + 10/f(ADCK) DAC operation signal A/D control register Q3 Frequency divided by 6 Instruction clock ✕ 000 (Bit 3) (Bit 0)

Rev.3.01 2005.06.15 page 51 of 160 REJ03B0007-0301 (9) Operation at comparator mode The A/D converter is set to comparator mode by setting bit 3 of the register Q1 to “1.” Below, the operation at comparator mode is described. (10) Comparator register In comparator mode, the built-in D/A comparator is connected to the 8-bit comparator register as a register for setting comparison voltages. The contents of register B is stored in the high-order 4 bits of the comparator register and the contents of register A is stored in the low-order 4 bits of the comparator register with the TADAB instruction. When changing from A/D conversion mode to comparator mode, the result of A/D conversion (register AD) is undefined. However, because the comparator register is separated from regis- ter AD, the value is retained even when changing from comparator mode to A/D conversion mode. Note that the comparator register can be written and read at only comparator mode. If the value in the comparator register is n, the logic value of com- parison voltage V ref generated by the built-in D/A converter can be determined from the following formula: (11) Comparison result store flag (ADF) In comparator mode, the ADF flag, which shows completion of A/D conversion, stores the results of comparing the analog input volt- age with the comparison voltage. When the analog input voltage is lower than the comparison voltage, the ADF flag is set to “1.” The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the inter- rupt or the skip instruction. The ADF flag is cleared to “0” when the interrupt occurs or when the next instruction is skipped with the skip instruction. (12) Comparator operation start instruction (ADST instruction) In comparator mode, executing ADST starts the comparator oper- ating. The comparator stops 2 machine cycles + A/D conversion clock f(ADCK) 1 clock after it has started (4 µs at f(XIN) = 6.0 MHz in XIN through mode, f(ADCK) = f(INSTCK)/6). When the analog input voltage is lower than the comparison voltage, the ADF flag is set to “1.” (13) Notes for the use of A/D conversion

• TALA instruction When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-order 2 bits of register A, si- multaneously, the low-order 2 bits of register A is “0.”
• Operation mode of A/D converter Do not change the operating mode (both A/D conversion mode and comparator mode) of A/D converter with the bit 3 of register Q1 while the A/D converter is operating. Clear the bit 2 of register V2 to “0” to change the operating mode of the A/D converter from the comparator mode to A/D conver- sion mode. The A/D conversion completion flag (ADF) may be set when the operating mode of the A/D converter is changed from the com- parator mode to the A/D conversion mode. Accordingly, set a value to the register Q1, and execute the SNZAD instruction to clear the ADF flag. Logic value of comparison voltage Vref Vref = ✕ n n: The value of register AD (n = 0 to 255) Fig. 40 Comparator operation timing chart VDD 256 ADST instruction Comparison result store flag(ADF) 2 machine cycles + 1/f(ADCK) DAC operation signal Comparator operation completed. (The value of ADF is determined)

Rev.3.01 2005.06.15 page 52 of 160 REJ03B0007-0301 (14) Definition of A/D converter accuracy The A/D conversion accuracy is defined below (refer to Figure 41).

• Relative accuracy ➀ Zero transition voltage (V0T) This means an analog input voltage when the actual A/D con- version output data changes from “0” to “1.” ➁ Full-scale transition voltage (VFST ) This means an analog input voltage when the actual A/D con- version output data changes from “1023” to “1022.” ➂ Linearity error This means a deviation from the line between V0T and VFST of a converted value between V0T and VFST . ➃ Differential non-linearity error This means a deviation from the input potential difference re- quired to change a converter value between V0T and VFST by 1 LSB at the relative accuracy.
• Absolute accuracy This means a deviation from the ideal characteristics between 0 to VDD of actual A/D conversion characteristics. Fig. 41 Definition of A/D conversion accuracy VFST –V0T 1022 VDD 1024 Vn: Analog input voltage when the output data changes from “n” to
• 1LSB at relative accuracy → (V)
• 1LSB at absolute accuracy → (V) VDDV1022VnV1V0 Vn+1 n+1 n 1022 1023 b a c Output data Differential non-linearity error = Linearity error = [LSB] c a b–a a [LSB] Actual A/D conversion characteristics a: 1LSB by relative accuracy b: Vn+1–Vn c: Difference between ideal Vn and actual Vn Zero transition voltage (V0T) Analog voltage Full-scale transition voltage (VFST ) Ideal line of A/D conversion between V0–V1022

Rev.3.01 2005.06.15 page 53 of 160 REJ03B0007-0301 SERIAL INTERFACE The 4519 Group has a built-in clock synchronous serial I/O which can serially transmit or receive 8-bit data. Serial I/O consists of;

• serial I/O register SI
• serial I/O control register J1
• serial I/O transmit/receive completion flag (SIOF)
• serial I/O counter Registers A and B are used to perform data transfer with internal CPU, and the serial I/O pins are used for external data transfer. The pin functions of the serial I/O pins can be set with the register J1. Table 14 Serial I/O pins Pin P20/SCK P21/SOUT P22/SIN Pin function when selecting serial I/O Clock I/O (SCK ) Serial data output (SOUT ) Serial data input (SIN) Fig. 42 Serial I/O structure Table 15 Serial I/O control register Note: “R ” represents read enabled, and “W ” represents write enabled. Note: Even when the SCK , SOUT , SIN pin functions are used, the input of P2 0, P21, P22 are valid. Synchronous circuit Serial I/O counter (3) SIOF Serial I/O interrupt INSTCK P20/SCK SCK QS R MSB Serial I/O register (8) LSBSIN J11 J10 J13J12 Register B (4) Register A (4) TSIAB TABSITABSI SOUT P21/SOUT P22/SIN SST instruction Internal reset signal J13 Serial I/O synchronous clock selection bits Serial I/O port function selection bits Serial I/O control register J1 at RAM back-up : state retainedat reset : 00002 J13 J12 J11 J10 Synchronous clock Instruction clock (INSTCK) divided by 8 Instruction clock (INSTCK) divided by 4 Instruction clock (INSTCK) divided by 2 External clock (S CK input) Port function P20, P21,P22 selected/SCK , SOUT , SIN not selected SCK , SOUT , P22 selected/P20, P21, SIN not selected SCK , P21, SIN selected/P20, SOUT , P22 not selected SCK , SOUT , SIN selected/P20, P21,P22 not selected R/W TAJ1/TJ1A

Rev.3.01 2005.06.15 page 54 of 160 REJ03B0007-0301 Fig. 43 Serial I/O register state when transferring (1) Serial I/O register SI Serial I/O register SI is the 8-bit data transfer serial/parallel conver- sion register. Data can be set to register SI through registers A and B with the TSIAB instruction. The contents of register A is transmit- ted to the low-order 4 bits of register SI, and the contents of register B is transmitted to the high-order 4 bits of register SI. During transmission, each bit data is transmitted LSB first from the lowermost bit (bit 0) of register SI, and during reception, each bit data is received LSB first to register SI starting from the topmost bit (bit 7). When register SI is used as a work register without using serial I/O, do not select the S CK pin. (2) Serial I/O transmit/receive completion flag (SIOF) Serial I/O transmit/receive completion flag (SIOF) is set to “1” when serial data transmission or reception completes. The state of SIOF flag can be examined with the skip instruction (SNZSI). Use the in- terrupt control register V2 to select the interrupt or the skip instruction. The SIOF flag is cleared to “0” when the interrupt occurs or when the next instruction is skipped with the skip instruction. (3) Serial I/O start instruction (SST) When the SST instruction is executed, the SIOF flag is cleared to “0” and then serial I/O transmission/reception is started. (4) Serial I/O control register J1 Register J1 controls the synchronous clock, P20/SCK , P21/SOUT and P22/SIN pin function. Set the contents of this register through register A with the TJ1A instruction. The TAJ1 instruction can be used to transfer the contents of register J1 to register A. D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 At transmit (D7–D 0: transfer data) At receive D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 SI N p i n SO U T p i n SO U T p i n SI N p i n S e r i a l I O r e g i s t e r S I )Serial I/O register (SI) D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 7 D 6 D 5 D 4 D 3 D 2 D 0 D 1 D 0 Transfer data set T r a n s f e r s t a r t Transfer complete

Rev.3.01 2005.06.15 page 55 of 160 REJ03B0007-0301 (5) How to use serial I/O Figure 44 shows the serial I/O connection example. Serial I/O inter- rupt is not used in this example. In the actual wiring, pull up the wiring between each pin with a resistor. Figure 44 shows the data transfer timing and Table 16 shows the data transfer sequence. Fig. 44 Serial I/O connection example SOUT SR D Y s i g n a l SC K SIN D 3 SC K SO U T SI N D 3 M a s t e r c l o c k c o n t r o l S e r i a l I O i n t e r r u p t e n a b l e b i t S N Z S I i n s t r u c t i o n v a l i d Interrupt control register V2 S e r i a l I O c o n t r o l r e g i s t e r J S e r i a l I O p o r t SC K ,SO U T ,SI N Instruction clock/8 selected as synchronous clock S l a v e e x t e r n a l c l o c k S e r i a l I O i n t e r r u p t e n a b l e b i t S N Z S I i n s t r u c t i o n v a l i d (Bit 3) (Bit 0) 100 ✕0 ✕✕ ✕ : S e t a n a r b i t r a r y v a l u e Serial I/O control register J1 S e r i a l I O p o r t SC K ,SO U T ,SI N B i t ) ( B i t B i t ) ( B i t Interrupt control register V2 B i t ) ( B i t E x t e r n a l c l o c k s e l e c t e d a s s y n c h r o n o u s c l o c k

Rev.3.01 2005.06.15 page 56 of 160 REJ03B0007-0301 Fig. 45 Timing of serial I/O data transfer M 0– M 7: C o n t e n t s o f m a s t e r s e r i a l I O r e g i s t e r S0– S7: C o n t e n t s o f s l a v e s e r i a l I O r e g i s t e r R i s i n g o f SC S e r i a l i n p u t F a l l i n g o f SC S e r i a l o u t p u t SI N SO U T Master S l a v e SC K S S T i n s t r u c t i o n SO U T SI N S0S7’ S1 S2 S3 S4 S5 S6 S7 S S T i n s t r u c t i o n SR D Y s i g n a l S0S7’ S1 S3 S4 S5 S6 S7 M 0M 7’ M 1 M 2 M 3 M 4 M 5 M 6 M 7 M 0M 7’ M 1 M 2 M 3 M 4 M 5 M 6 M 7

Rev.3.01 2005.06.15 page 57 of 160 REJ03B0007-0301 Table 16 Processing sequence of data transfer from master to slave 1-byte data is serially transferred on this process. Subsequently, data can be transferred continuously by repeating the process from *. When an external clock is selected as a synchronous clock, the clock is not controlled internally. Control the clock externally be- cause serial transfer is performed as long as clock is externally input. (Unlike an internal clock, an external clock is not stopped when serial transfer is completed.) However, the SIOF flag is set to “1” when the clock is counted 8 times after executing the SST in- struction. Be sure to set the initial level of the external clock to “H.” Master (transmission) [Initial setting]

• Setting the serial I/O mode register J1 and inter- rupt control register V2 shown in Figure 44. TJ1A and TV2A instructions
• Setting the port received the reception enable signal (S RDY ) to the input mode. (Port D3 is used in this example) SD instruction * [Transmission enable state]
• Storing transmission data to serial I/O register SI. TSIAB instruction [Transmission]
• Check port D3 is “L” level. SZD instruction
• Serial transfer starts. SST instruction
• Check transmission completes. SNZSI instruction
• Wait (timing when continuously transferring) Slave (reception) [Initial setting]
• Setting serial I/O mode register J1, and interrupt control register V2 shown in Figure 44. TJ1A and TV2A instructions
• Setting the port transmitted the reception enable signal (SRDY ) and outputting “H ” level (reception impossible). (Port D3 is used in this example) SD instruction *[Reception enable state]
• The SIOF flag is cleared to “0.” SST instruction
• “L” level (reception possible) is output from port D RD instruction [Reception]
• Check reception completes. SNZSI instruction
• “H ” level is output from port D3. SD instruction [Data processing]

Rev.3.01 2005.06.15 page 58 of 160 REJ03B0007-0301 System reset is performed by applying “L” level to RESET pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions. Then when “H ” level is applied to RESET pin, software starts from address 0 in page 0. Fig. 46 Reset release timing Fig. 47 RESET pin input waveform and reset operation f(RING) RESET Program starts (address 0 in page 0) On-chip oscillator (internal oscillator) is counted 120 to 144 times. Note: The number of clock cycles depends on the internal state of the microcomputer when reset is performed. RESET 0.3VDD 0.85VDD (Note) Note: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. Reset input 1 machine cycle or more Program starts (address 0 in page 0) On-chip oscillator (internal oscillator) is counted 120 to 144 times.

Rev.3.01 2005.06.15 page 59 of 160 REJ03B0007-0301 Fig. 48 Structure of reset pin and its peripherals,, and power-on reset operation Name D 0–D 5 D 6/CNTR0 D 7/CNTR1 P00–P03 P10–P13 P20/SCK , P21/SOUT , P22/SIN P30/INT0, P31/INT1, P32, P33 P40/AIN4–P43/AIN7 P50–P53 P60/AIN0–P63/AIN3 Notes 1: Output latch is set to “1.” 2: Output structure is N-channel open-drain. 3: Pull-up transistor is turned OFF. Function D 0–D 5 D 6 D 7 P00–P03 P10–P13 P20–P22 P30–P33 P40–P43 P50–P53 P60–P63 State High-impedance (Notes 1, 2) High-impedance (Notes 1, 2) High-impedance (Notes 1, 2) High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2, 3) High-impedance (Note 1) High-impedance (Note 1) High-impedance (Note 1) High-impedance (Notes 1, 2) High-impedance (Note 1) (1) Power-on reset Reset can be automatically performed at power on (power-on re- set) by the built-in power-on reset circuit. When the built-in power-on reset circuit is used, the time for the supply voltage to rise from 0 V until the value of supply voltage reaches the minimum operating voltage must be set to 100 µs or less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and V SS at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage. Table 1 Port state at reset RESET pin WEF Watchdog reset signal (Note 1) Pull-up transistor (Note 1) Power-on reset circuit Voltage drop detection circuit VDD (Note 3)100 µs or less (Note 2) Internal reset signal Power-on Reset released Internal reset signal Reset state Notes 1: This symbol represents a parasitic diode. 2: Applied potential to RESET pin must be VDD or less. 3: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. Power-on reset circuit output SRST instruction

Rev.3.01 2005.06.15 page 60 of 160 REJ03B0007-0301 Address 0 in page 0 is set to program counter. “✕ ” represents undefined. Fig. 49 Internal state at reset 1 (2) Internal state at reset Figure 49 and 50 show internal state at reset (they are the same af- ter system is released from reset). The contents of timers, registers, flags and RAM except shown in Figure are undefined, so set the initial value to them. 00000000000000 0 (Interrupt disabled) 0 0 0 0 (Interrupt disabled) 0 0 0 0 (Interrupt disabled) 0000 0000 0 (Prescaler stopped) 0 0 0 0 (Timer 1 stopped) 0 0 0 0 (Timer 2 stopped) 0 0 0 0 (Timer 3 stopped) 0 0 0 0 (Timer 4 stopped) 0000( Period measurement circuit stopped) 0000 1111 0 (On-chip oscillator operating) 0 0 0 0 (External clock selected, serial I/O port not selected) 0000 0000 0000 0000 0000 0000 0000 0000 ✕ ✕✕✕

Rev.3.01 2005.06.15 page 61 of 160 REJ03B0007-0301 “✕ ” represents undefined. Fig. 50 Internal state at reset 2 0000 0000 0000 0000 0000 0000 ✕✕✕ 0000 0000 111

Rev.3.01 2005.06.15 page 62 of 160 REJ03B0007-0301 VOLTAGE DROP DETECTION CIRCUIT The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value. Fig. 51 Voltage drop detection reset circuit Fig. 52 Voltage drop detection circuit operation waveform Table 17 Voltage drop detection circuit operation state VDCE pin “L” “H ” At CPU operating Invalid Valid At RAM back-up Invalid Valid VRST VRST VDCE Voltage drop detection circuit Reset signal Voltage drop detection circuit VRST (reset release voltage)+ VDD Voltage drop detection circuit Reset signal Microcomupter starts operation after on-chip oscillator (internal oscillator) clock is counted 120 to 144 times. V RST (reset voltage) RESET pin Note: Detection voltage hysteresis of voltage drop detection circuit is 0.2 V (Typ).

Rev.3.01 2005.06.15 page 63 of 160 REJ03B0007-0301 RAM BACK-UP MODE The 4519 Group has the RAM back-up mode. When the EPOF and POF instructions are executed continuously, system enters the RAM back-up state. The POF instruction is equal to the NOP instruction when the EPOF instruction is not ex- ecuted before the POF instruction. As oscillation stops retaining RAM, the function of reset circuit and states at RAM back-up mode, current dissipation can be reduced without losing the contents of RAM. Table 18 shows the function and states retained at RAM back-up. Figure 53 shows the state transition. (1) Identification of the start condition Warm start (return from the RAM back-up state) or cold start (re- turn from the normal reset state) can be identified by examining the state of the RAM back-up flag (P) with the SNZP instruction. (2) Warm start condition When the external wakeup signal is input after the system enters the RAM back-up state by executing the EPOF and POF instruc- tions continuously, the CPU starts executing the program from address 0 in page 0. In this case, the P flag is “1.” (3) Cold start condition The CPU starts executing the program from address 0 in page 0 when;

• reset pulse is input to RESET pin, or
• reset by watchdog timer is performed, or
• voltage drop detection circuit detects the voltage drop, or
• SRST instruction is executed. In this case, the P flag is “0.” Table 18 Functions and states retained at RAM back-up Function Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2) Contents of RAM Interrupt control registers V1, V2 Interrupt control registers I1, I2 Selection of oscillation circuit Clock control register MR Timer 1 function Timer 2 function Timer 3 function Timer 4 function Watchdog timer function Timer control register PA, W4 Timer control registers W1 to W3, W5, W6 Serial I/O function Serial I/O mode register J1 A/D conversion function A/D control registers Q1 to Q3 Voltage drop detection circuit Port level Key-on wakeup control register K0 to K2 Pull-up control registers PU0, PU1 Port output direction registers FR0 to FR3 External 0 interrupt request flag (EXF0) External 1 interrupt request flag (EXF1) Timer 1 interrupt request flag (T1F) Timer 2 interrupt request flag (T2F) Timer 3 interrupt request flag (T3F) Timer 4 interrupt request flag (T4F) A/D conversion completion flag (ADF) Serial I/O transmission/reception completion flag (SIOF) Interrupt enable flag (INTE) Watchdog timer flags (WDF1, WDF2) Watchdog timer enable flag (WEF) RAM back-up O O O (Note 3) (Note 3) (Note 3) (Note 3) ✕ (Note 4) O O O O (Note 5) O O O O (Note 3) (Note 3) (Note 3) (Note 3) ✕ (Note 4) ✕ (Note 4) Notes 1:“O ” represents that the function can be retained, and “✕ ” repre- sents that the function is initialized. Registers and flags other than the above are undefined at RAM back-up, and set an initial value after returning. 2: The stack pointer (SP) points the level of the stack register and is initialized to “7” at RAM back-up. 3: The state of the timer is undefined. 4: Initialize the watchdog timer with the WRST instruction, and then execute the POF instruction. 5: The valid/invalid of the voltage drop detection circuit can be con- trolled only by VDCE pin.

Rev.3.01 2005.06.15 page 64 of 160 REJ03B0007-0301 (4) Return signal An external wakeup signal is used to return from the RAM back-up mode because the oscillation is stopped. Table 19 shows the return condition for each return source. (5) Related registers

• Key-on wakeup control register K0 Register K0 controls the ports P0 and P1 key-on wakeup func- tion. Set the contents of this register through register A with the TK0A instruction. In addition, the TAK0 instruction can be used to transfer the contents of register K0 to register A.
• Key-on wakeup control register K1 Register K1 controls the return condition and valid waveform/ level selection for port P0. Set the contents of this register through register A with the TK1A instruction. In addition, the TAK1 instruction can be used to transfer the contents of register K1 to register A.
• Key-on wakeup control register K2 Register K2 controls the INT0 and INT1 key-on wakeup functions and return condition function. Set the contents of this register through register A with the TK2A instruction. In addition, the TAK2 instruction can be used to transfer the contents of register K2 to register A. Table 19 Return source and return condition Remarks The key-on wakeup function can be selected with 2 port units. Select the re- turn level (“L” level or “H ” level), and return condition (return by level or edge) with the register K1 according to the external state before going into the RAM back-up state. The key-on wakeup function can be selected with 2 port units. Set the port using the key-on wakeup function to “H ” level before going into the RAM back-up state. Select the return level (“L” level or “H ” level) with the registers I1 and I2 ac- cording to the external state, and return condition (return by level or edge) with the register K2 before going into the RAM back-up state. Return condition Return by an external “H ” level or “L” level input, or rising edge (“L ”→ “H ”) or falling edge Return by an external “L” level in- put. Return by an external “H ” level or “L” level input, or rising edge (“L ”→ “H ”) or falling edge The external interrupt request flags (EXF0, EXF1) are not set. External wakeup signal Return source Ports P00–P0 3 Ports P10–P1 3 INT0 INT1
• Pull-up control register PU0 Register PU0 controls the ON/OFF of the port P0 pull-up transis- tor. Set the contents of this register through register A with the TPU0A instruction. In addition, the TAPU0 instruction can be used to transfer the contents of register PU0 to register A.
• Pull-up control register PU1 Register PU1 controls the ON/OFF of the port P1 pull-up transis- tor. Set the contents of this register through register A with the TPU1A instruction. In addition, the TAPU1 instruction can be used to transfer the contents of register PU0 to register A.
• External interrupt control register I1 Register I1 controls the valid waveform of external 0 interrupt, in- put control of INT0 pin, and return input level. Set the contents of this register through register A with the TI1A instruction. In addi- tion, the TAI1 instruction can be used to transfer the contents of register I1 to register A.
• External interrupt control register I2 Register I2 controls the valid waveform of external 1 interrupt, in- put control of INT1 pin, and return input level. Set the contents of this register through register A with the TI2A instruction. In addi- tion, the TAI2 instruction can be used to transfer the contents of register I2 to register A.

Rev.3.01 2005.06.15 page 65 of 160 REJ03B0007-0301 Fig. 53 State transition Fig. 54 Set source and clear source of the P flag Fig. 55 Start condition identified example using the SNZP in- struction A Operation state

• Operation source clock: f(RING)
• f(X IN): Stop Key-on wakeup POF instruction execution E RAM back-up mode D
• Operation source clock: f(XIN)
• f(RING): Stop POF instruction execution Operation state Notes 1: Microcomputer starts its operation after counting f(RING) 120 to 144 times. C POF instruction execution Operation state
• Operation source clock: f(XIN)
• f(RING): Operating B POF instruction execution Operation state
• Operation source clock: f(RING)
• f(X IN): Operating f(RING): stop f(XIN): stop MR 1← 1MR 1← 0 (Note 5) (Note 4) (Note 4) (Note 4) (Note 4) MR 0← 1MR 0← 0 RG 0← 0RG 0← 1 Reset (Note 1) (Note 2) (Note 3) However, the selected contents (CMCK, CRCK, CYCK instruction execution state) of f(XIN) oscillation circuit is retained. 5: System returns to state A certainly when returning from the RAM back-up mode. 4: Continuous execution of the EPOF instruction and the POF instruction is required to go into the RAM back-up state. 3: Generate the wait time by software until the oscillation is stabilized, and then, switch the system clock. MR 1 cannot be cleared to “0” when the oscillation circuit is not selected. Surely, select the f(XIN) oscillation circuit by executing the CMCK, CRCK or CYCK instruction before clearing MR1 to “0”. The start/stop of oscillation and the operation source is switched by register MR. instruction (the start of oscillation and the operation source clock is not switched by these instructions). 2: The f(XIN) oscillation circuit (ceramic resonance, RC oscillation or quartz-crystal oscillation) is selected by the CMCK, CRCK or CYCK S R Q Power down flag PPOF instruction Reset input G Set source G Clear source Reset input EPOF instruction + POF instructionEPOF instruction + Program start P = “1” Yes Warm start Cold start No

Rev.3.01 2005.06.15 page 66 of 160 REJ03B0007-0301 Table 20 Key-on wakeup control register, pull-up control register K03 K02 K01 K00 Key-on wakeup control register K0 Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Pins P1 2 and P13 key-on wakeup control bit Pins P1 0 and P11 key-on wakeup control bit Pins P02 and P03 key-on wakeup control bit Pins P0 0 and P01 key-on wakeup control bit at reset : 00002 at RAM back-up : state retained R/W TAK0/TK0A Note: “R ” represents read enabled, and “W ” represents write enabled. K13 K12 K11 K10 Key-on wakeup control register K1 Return by level Return by edge Falling waveform/“L” level Rising waveform/“H ” level Return by level Return by edge Falling waveform/“L” level Rising waveform/“H ” level Ports P0 2 and P03 return condition selection bit Ports P0 2 and P03 valid waveform/ level selection bit Ports P01 and P00 return condition selection bit Ports P0 1 and P00 valid waveform/ level selection bit at reset : 00002 at RAM back-up : state retained R/W TAK1/TK1A K23 K22 K21 K20 Key-on wakeup control register K2 Return by level Return by edge Key-on wakeup not used Key-on wakeup used Return by level Return by edge Key-on wakeup not used Key-on wakeup used INT1 pin return condition selection bit INT1 pin key-on wakeup contro bit INT0 pin return condition selection bit INT0 pin key-on wakeup contro bit at reset : 00002 at RAM back-up : state retained R/W TAK2/TK2A

Rev.3.01 2005.06.15 page 67 of 160 REJ03B0007-0301 Table 21 Key-on wakeup control register, pull-up control register PU0 3 PU0 2 PU0 1 PU0 0 Pull-up control register PU0 PU1 3 PU1 2 PU1 1 PU1 0 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON 3 pin pull-up transistor control bit 2 pin pull-up transistor control bit P01 pin pull-up transistor control bit 0 pin pull-up transistor control bit at reset : 00002 at RAM back-up : state retained Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON 3 pin pull-up transistor control bit P12 pin pull-up transistor control bit 1 pin pull-up transistor control bit 0 pin pull-up transistor control bit R/W TAPU0/ TPU0A Pull-up control register PU1 at reset : 00002 at RAM back-up : state retained R/W TAPU1/ TPU1A Note: “R ” represents read enabled, and “W ” represents write enabled.

Rev.3.01 2005.06.15 page 68 of 160 REJ03B0007-0301 The clock control circuit consists of the following circuits.

• On-chip oscillator (internal oscillator)
• Ceramic resonator
• RC oscillation circuit
• Quartz-crystal oscillation circuit
• Multi-plexer (clock selection circuit)
• Frequency divider
• Internal clock generating circuit The system clock and the instruction clock are generated as the source clock for operation by these circuits. Figure 56 shows the structure of the clock control circuit. The 4519 Group operates by the on-chip oscillator clock (f(RING)) which is the internal oscillator after system is released from reset. Also, the ceramic resonator, the RC oscillation or quartz-crystal os- cillator can be used for the main clock (f(X IN)) of the 4519 Group. The CMCK instruction, CRCK instruction or CYCK instruction is ex- ecuted to select the ceramic resonator, RC oscillator or quartz-crystal oscillator respectively. Fig. 56 Clock control circuit structure MR 3, MR 2 CMCK instruction QS R Internal reset signal Key-on wakeup signal EPOF instruction POF instruction+ QS R MR 0 Division circuit System clock (STCK) Instruction clock (INSTCK) Multi- plexer Quartz-crystal oscillation On-chip oscillator (internal oscillator) XOUT XIN Ceramic resonance RC oscillation Internal clock generating circuit (divided by 3) RG 0 MR 1 QS R QS R Q S R CRCK instruction CYCK instruction Divided by 2 Divided by 4 Divided by 8 The CMCK, CRCK, and CYCK instructions can be used only to se- lect main clock (f(XIN)). In this time, the start of oscillation and the switch of system clock are not performed. The oscillation start/stop of main clock f(X IN) is controlled by bit 1 of register MR. The system clock is selected by bit 0 of register MR. The oscillation start/stop of on-chip oscillator is controlled by register RG. The oscillation circuit by the CMCK, CRCK or CYCK instruction can be selected only at once. The oscillation circuit corresponding to the first executed one of these instructions is valid. Execute the main clock (f(X IN)) selection instruction (CMCK, CRCK or CYCK instruction) in the initial setting routine of program (ex- ecuting it in address 0 in page 0 is recommended). When the CMCK, CRCK, and CYCK instructions are never ex- ecuted, main clock (f(X IN)) cannot be used and system can be operated only by on-chip oscillator. The no operated clock source (f(RING)) or (f(X IN)) cannot be used for the system clock. Also, the clock source (f(RING) or f(XIN)) se- lected for the system clock cannot be stopped.

Rev.3.01 2005.06.15 page 69 of 160 REJ03B0007-0301 Fig. 57 Switch to ceramic resonance/RC oscillation/quartz-crystal oscillation Reset On-chip oscillator operation CMCK instruction CRCKinstruction

• Main clock: ceramic resonance
• On-chip oscillator: operating
• System clock: on-chip oscillator clock CYCK instruction
• Set the main clock (f(XIN)) oscillation by bit 1 of register MR.
• Switch the system clock by bit 0 of register MR. Also, when system clock is switched after main clock oscillation is started, generate the oscillation stabilizing wait time by program if necessary.
• Set the on-chip oscillator clock oscillation by register RG.
• Main clock: RC oscillation circuit
• On-chip oscillator: operating
• System clock: on-chip oscillator clock
• Main clock: Quartz-crystal circuit
• On-chip oscillator: operating
• System clock: on-chip oscillator clock (1) Main clock generating circuit (f(XIN)) The ceramic resonator, RC oscillation or quartz-crystal oscillator can be used for the main clock of this MCU. After system is released from reset, the MCU starts operation by the clock output from the on-chip oscillator which is the internal os- cillator. When the ceramic resonator is used, execute the CMCK instruc- tion. When the RC oscillation is used, execute the CRCK instruction. When the quartz-crystal oscillator is used, execute the CYCK instruction. The oscillation start/stop of main clock f(X IN) is controlled by bit 1 of register MR. The system clock is selected by bit 0 of register MR. The oscillation circuit by the CMCK, CRCK or CYCK instruction can be selected only at once. The oscillation cir- cuit corresponding to the first executed one of these instructions is valid. Execute the CMCK, CRCK or CYCK instruction in the initial setting routine of program (executing it in address 0 in page 0 is recom- mended). Also, when the CMCK, CRCK or CYCK instruction is not executed in program, this MCU operates by the on-chip oscillator.

Rev.3.01 2005.06.15 page 70 of 160 REJ03B0007-0301 Fig. 62 External clock input circuit Fig. 61 External quartz-crystal circuit Note: Externally connect a damping resistor Rd depending on the oscillation frequency. (A feedback resistor is built-in.) Use the quartz-crystal manu- facturer’s recommended value because constants such as ca- pacitance depend on the resonator. Fig. 58 Handling of XIN and XOUT when operating on-chip oscillator Fig. 59 Ceramic resonator external circuit Fig. 60 External RC oscillation circuit Execute the CMCK instruc- tion in program. Note: Externally connect a damping resistor Rd depending on the oscillation frequency. (A feedback resistor is built-in.) Use the resonator manu- facturer’s recommended value because constants such as ca- pacitance depend on the resonator. M34519 XIN XOUT Do not use the CMCK, CRCK and CYCK instructions in program. OpenOpen M34519 XIN XOUT Rd C IN C OUT M34519 XIN XOUTR C Execute the CRCK instruction in program. Open M34519 XIN XOUT Rd C IN C OUT Execute the CYCK instruction in program.* M34519 XIN XOUT External oscillation circuit VDD VSSR 1kΩ or more Open (2) On-chip oscillator operation When the MCU operates by the on-chip oscillator as the main clock (f(XIN)) without using the ceramic resonator, RC oscillator or quartz-crystal oscillation, leave XIN pin and XOUT pin open (Figure 58). The clock frequency of the on-chip oscillator depends on the sup- ply voltage and the operation temperature range. Be careful that the margin of frequencies when designing applica- tion products. (3) Ceramic resonator When the ceramic resonator is used as the main clock (f(XIN)), connect the ceramic resonator and the external circuit to pins XIN and XOUT at the shortest distance. Then, execute the CMCK in- struction. A feedback resistor is built in between pins XIN and XOUT (Figure 59). (4) RC oscillation When the RC oscillation is used as the main clock (f(XIN)), connect the XIN pin to the external circuit of resistor R and the capacitor C at the shortest distance and leave XOUT pin open. Then, execute the CRCK instruction (Figure 60). The frequency is affected by a capacitor, a resistor and a micro- computer. So, set the constants within the range of the frequency limits. (5) Quartz-crystal oscillator When a quartz-crystal oscillator is used as the main clock (f(XIN)), connect this external circuit and a quartz-crystal oscillator to pins XIN and XOUT at the shortest distance. Then, execute the CYCK in- struction. A feedback resistor is built in between pins XIN and XOUT (Figure 61). (6) External clock When the external clock signal for the main clock (f(XIN)) is used, connect the clock source to XIN pin and XOUT pin open. In program, after the CMCK instruction is executed, set main clock (f(XIN)) os- cillation start to be enabled (MR1=0). For this product, when RAM back-up mode and main clock (f(XIN)) stop (MR1=1), XIN pin is fixed to “H ” in order to avoid the through current by floating of internal logic. The XIN pin is fixed to “H ” until main clock (f(XIN)) oscillation starts to be valid (MR1=0) by the CMCK instruction from reset state. Accordingly, when an external clock is used, connect a 1 kΩ or more resistor to X IN pin in series to limit of current by competitive signal. Execute the CMCK instruction in program, and set the main clock f(X IN) to be enabled (MR1=0)

Rev.3.01 2005.06.15 page 71 of 160 REJ03B0007-0301 ROM ORDERING METHOD 1.Mask ROM Order Confirmation Form✽ 2.Mark Specification Form✽ ✽For the mask ROM confirmation and the mark specifications, refer to the “Renesas Technology Corp.” Homepage (http://www.renesas.com/en/rom). (7) Clock control register MR Register MR controls system clock. Set the contents of this register through register A with the TMRA instruction. In addition, the TAMR instruction can be used to transfer the contents of register MR to register A. Table 22 Clock control registers Note: “R ” represents read enabled, and “W ” represents write enabled. MR 3 Clock control register MR Operation mode Through mode (frequency not divided) Frequency divided by 2 mode Frequency divided by 4 mode Frequency divided by 8 mode Main clock (f(X IN)) oscillation enabled Main clock (f(XIN)) oscillation stop Main clock (f(XIN)) Main clock (f(RING)) at reset : 11112 at RAM back-up : 11112 MR 3 R/W TAMR/ TMRA Main clock f(XIN) oscillation circuit control bit System clock oscillation source selection bit Operation mode selection bits MR 2 MR 1 MR 0 MR 2 On-chip oscillator (f(RING)) oscillation enabled On-chip oscillator (f(RING)) oscillation stop On-chip oscillator (f(RING)) control bit Clock control register RG W TRGAat RAM back-up : 02at reset : 02 RG 0 (8) Clock control register RG Register RG controls start/stop of on-chip oscillator. Set the con- tents of this register through register A with the TRGA instruction.

Rev.3.01 2005.06.15 page 72 of 160 REJ03B0007-0301 ➃ Stack registers (SKS) Stack registers (SKs) are eight identical registers, so that subrou- tines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accord- ingly, be careful not to over the stack when performing these operations together. ➄ Multifunction

• The input/output of P30 and P31 can be used even when INT0 and INT1 are selected.
• The input of ports P20–P2 2 can be used even when SIN, SOUT and SCK are selected.
• The input/output of D6 can be used even when CNTR0 (input) is selected.
• The input of D6 can be used even when CNTR0 (output) is selected.
• The input/output of D7 can be used even when CNTR1 (input) is selected.
• The input of D7 can be used even when CNTR1 (output) is selected. ➅ Prescaler Stop counting and then execute the TABPS instruction to read from prescaler data. Stop counting and then execute the TPSAB instruction to set prescaler data. ➆ Timer count source Stop timer 1, 2, 3 and 4 counting to change its count source. ➇ Reading the count value Stop timer 1, 2, 3 or 4 counting and then execute the data read instruction (TAB1, TAB2, TAB3, TAB4) to read its data. ➈ Writing to the timer Stop timer 1, 2, 3 or 4 counting and then execute the data write instruction (T1AB, T2AB, T3AB, T4AB) to write its data. Writing to reload register R1, R3, R4H When writing data to reload register R1, reload register R3 or re- load register R4H while timer 1, timer 3 or timer 4 is operating, avoid a timing when timer 1, timer 3 or timer 4 underflows. Timer 4 In order to stop timer 4 while the PWM output function is used, avoid a timing when timer 4 underflows. When “H” interval extension function of the PWM signal is set to be “valid”, set “1” or more to reload register R4H. LIST OF PRECAUTIONS ➀ Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up;
• connect a bypass capacitor (approx. 0.1 µF) between pins VDD and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use relatively thick wire. In the One Time PROM version, CNV SS pin is also used as VPP pin. Accordingly, when using this pin, connect this pin to VSS through a resistor about 5 kΩ (connect this resistor to CNVSS / VPP pin as close as possible). ➁ Register initial values 1 The initial value of the following registers are undefined after sys- tem is released from reset. After system is released from reset, set initial values.
• Register Z (2 bits)
• Register D (3 bits)
• Register E (8 bits) ➂ Register initial values 2 The initial value of the following registers are undefined at RAM back- up. After system is returned from RAM back-up, set initial values.
• Register Z (2 bits)
• Register X (4 bits)
• Register Y (4 bits)
• Register D (3 bits)
• Register E (8 bits)

Rev.3.01 2005.06.15 page 73 of 160 REJ03B0007-0301

12 Watchdog timer

• The watchdog timer function is valid after system is released from reset. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously, and clear the WEF flag to “0” to stop the watchdog timer function.
• The watchdog timer function is valid after system is returned from the RAM back-up state. When not using the watchdog timer func- tion, execute the DWDT instruction and the WRST instruction continuously every system is returned from the RAM back-up state, and stop the watchdog timer function.
• When the watchdog timer function and RAM back-up function are used at the same time, execute the WRST instruction before sys- tem enters into the RAM back-up state and initialize the flag WDF1. Timer 4 count start timing and count time when operation starts Count starts from the rising edge (2) after the first falling edge of the count source, after Timer 4 operations start (1). Time to first underflow (3) is different from time among next un- derflow (4) by the timing to start the timer and count source operations after count starts. Fig. 64 Timer count start timing and count time when opera- tion starts (Timer 4) (1) Timer Start Count Source Timer Value Timer Underflow Signal 3 21032103 (4)(3) (2) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Fig. 63 Timer count start timing and count time when opera- tion starts (Prescaler, Timer 1, Timer 2 and Timer 3) (1) Timer Start Count Source Timer value Timer Underflow signal 3 21032103 (4)(3) (2) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Prescaler, Timer 1, Timer 2 and Timer 3 count start timing and count time when operation starts Count starts from the first rising edge of the count source (2) af- ter Prescaler, Timer 1, Timer 2 and Timer 3 operations start (1). Time to first underflow (3) is shorter (for up to 1 period of the count source) than time among next underflow (4) by the timing to start the timer and count source operations after count starts.

Rev.3.01 2005.06.15 page 74 of 160 REJ03B0007-0301 LA 0 ; ( ✕ 0✕✕ 2) LA 0 ; ( ✕ 0✕✕ 2) TW5A ; Period measurement circuit stop SNZT1 ; The SNZT1 instruction is executed (T1F flag cleared) ✕ : these bits are not used here. Fig. 65 Period measurement circuit program example

• ••
• •• Period measurement circuit When a period measurement circuit is used, clear bit 0 of regis- ter I1 to “0”, and set a timer 1 count start synchronous circuit to be “not selected”. Start timer operation immediately after operation of a period measurement circuit is started. When the edge for measurement is input until timer operation is started from the operation of period measurement circuit is started, the count operation is not executed until the timer opera- tion becomes valid. Accordingly, be careful of count data. When data is read from timer, stop the timer and clear bit 2 of register W5 to “0” to stop the period measurement circuit, and then execute the data read instruction. Depending on the state of timer 1, the timer 1 interrupt request flag (T1F) may be set to “1” when the period measurement cir- cuit is stopped by clearing bit 2 of register W5 to “0”. In order to avoid the occurrence of an unexpected interrupt, clear the bit 2 of register V1 to “0” (refer to Figure 65➀ ) and then, stop the bit 2 of register W5 to “0” to stop the period measurement circuit. In addition, execute the SNZT1 instruction to clear the T1F flag after executing at least one instruction (refer to Figure 65➁ ). Also, set the NOP instruction for the case when a skip is per- formed with the SNZT1 instruction (refer to Figure 65➂ ). While a period measurement circuit is operating, the timer 1 in- terrupt request flag (T1F) is not set by the timer 1 underflow signal, it is the flag for detecting the completion of period mea- surement. When a period measurement circuit is used, select the suffi- ciently higher-speed frequency than the signal for measurement for the count source of a timer 1. When the signal for period measurement is D 6/CNTR0 pin input, do not select D6/CNTR0 pin input as timer 1 count source. (The XIN input is recommended as timer 1 count source at the time of period measurement circuit use.) When the input of P3 0/INT0 pin is selected for measurement, set the bit 3 of a register I1 to “1”, and set the input of INT0 pin to be enabled.

Rev.3.01 2005.06.15 page 75 of 160 REJ03B0007-0301 P30/INT0 pin ❶ Note [1] on bit 3 of register I1 When the input of the INT0 pin is controlled with the bit 3 of reg- ister I1 in software, be careful about the following notes.

• Depending on the input state of the P30/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of regis- ter I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 66 ➀ ) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to Figure 66 ➁ ). Also, set the NOP instruction for the case when a skip is per- formed with the SNZ0 instruction (refer to Figure 66 ➂ ). LA 4 ; ( ✕✕✕ 0 LA 8 ; (1 ✕✕✕ 2) TI1A ; Control of INT0 pin input is changed SNZ0 ; The SNZ0 instruction is executed (EXF0 flag cleared) ✕ : these bits are not used here. ❷ Note [2] on bit 3 of register I1 When the bit 3 of register I1 is cleared to “0”, the RAM back-up mode is selected and the input of INT0 pin is disabled, be careful about the following notes.
• When the input of INT0 pin is disabled (register I1 3 = “0”), set the key-on wakeup function to be invalid (register K20 = “0”) before system enters to the RAM back-up mode. (refer to Figure 67➀ ).
• ••
• •• LA 0 ; ( ✕✕✕ 02) TK2A ; Input of INT0 key-on wakeup invalid..➀ DI EPOF POF ; RAM back-up ✕ : these bits are not used here. Fig. 67 External 0 interrupt program example-2
• ••
• •• ❸ Note on bit 2 of register I1 When the interrupt valid waveform of the P30/INT0 pin is changed with the bit 2 of register I1 in software, be careful about the following notes.
• Depending on the input state of the P3 0/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of regis- ter I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 68➀ ) and then, change the bit 2 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to Figure 68➁ ). Also, set the NOP instruction for the case when a skip is per- formed with the SNZ0 instruction (refer to Figure 68➂ ). LA 4 ; ( ✕✕✕ 0 LA 12 ; ( ✕ 1✕✕ 2) TI1A ; Interrupt valid waveform is changed SNZ0 ; The SNZ0 instruction is executed (EXF0 flag cleared) ✕ : these bits are not used here. Fig. 68 External 0 interrupt program example-3
• ••
• •• Fig. 66 External 0 interrupt program example-1

Rev.3.01 2005.06.15 page 76 of 160 REJ03B0007-0301 ❶ Note [1] on bit 3 of register I2 When the input of the INT1 pin is controlled with the bit 3 of reg- ister I2 in software, be careful about the following notes.

• Depending on the input state of the P31/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 3 of regis- ter I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 69➀ ) and then, change the bit 3 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to “0” after executing at least one instruction (refer to Figure 69➁ ). Also, set the NOP instruction for the case when a skip is per- formed with the SNZ1 instruction (refer to Figure 69➂ ). LA 4 ; ( ✕✕ 0✕ LA 8 ; (1 ✕✕✕ 2) TI2A ; Control of INT1 pin input is changed SNZ1 ; The SNZ1 instruction is executed (EXF1 flag cleared) ✕ : these bits are not used here. Fig. 69 External 1 interrupt program example-1 ❷ Note [2] on bit 3 of register I2 When the bit 3 of register I2 is cleared to “0”, the RAM back-up mode is selected and the input of INT1 pin is disabled, be careful about the following notes.
• When the input of INT1 pin is disabled (register I2 3 = “0”), set the key-on wakeup function to be invalid (register K22 = “0”) before system enters to the RAM back-up mode. (refer to Figure 70➀ ).
• ••
• •• LA 0 ; ( ✕ 0✕✕ 2) TK2A ; Input of INT1 key-on wakeup invalid ..➀ DI EPOF POF ; RAM back-up ✕ : these bits are not used here. Fig. 70 External 1 interrupt program example-2
• ••
• •• ❸ Note on bit 2 of register I2 When the interrupt valid waveform of the P31/INT1 pin is changed with the bit 2 of register I2 in software, be careful about the following notes.
• Depending on the input state of the P3 1/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 2 of regis- ter I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 71➀ ) and then, change the bit 2 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to “0” after executing at least one instruction (refer to Figure 71➁ ). Also, set the NOP instruction for the case when a skip is per- formed with the SNZ1 instruction (refer to Figure 71➂ ). LA 4 ; ( ✕✕ 0✕ LA 12 ; ( ✕ 1✕✕ 2) TI2A ; Interrupt valid waveform is changed SNZ1 ; The SNZ1 instruction is executed (EXF1 flag cleared) ✕ : these bits are not used here. Fig. 71 External 1 interrupt program example-3
• ••
• ••

Rev.3.01 2005.06.15 page 77 of 160 REJ03B0007-0301 POF instruction When the POF instruction is executed continuously after the EPOF instruction, system enters the RAM back-up state. Note that system cannot enter the RAM back-up state when ex- ecuting only the POF instruction. Be sure to disable interrupts by executing the DI instruction be- fore executing the EPOF instruction and the POF instruction continuously. Program counter Make sure that the PC does not specify after the last page of the built-in ROM. Power-on reset When the built-in power-on reset circuit is used, the time for the supply voltage to rise from 0 V to the value of supply voltage or more must be set to 100 µs or less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and V SS at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage. Clock control Execute the main clock (f(XIN)) selection instruction (CMCK, CRCK or CYCK instruction) in the initial setting routine of pro- gram (executing it in address 0 in page 0 is recommended). The oscillation circuit by the CMCK, CRCK or CYCK instruction can be selected only at once. The oscillation circuit correspond- ing to the first executed one of these instructions is valid. The CMCK, CRCK, and CYCK instructions can be used only to select main clock (f(X IN)). In this time, the start of oscillation and the switch of system clock are not performed. When the CMCK, CRCK, and CYCK instructions are never ex- ecuted, main clock (f(X IN)) cannot be used and system can be operated only by on-chip oscillator. The no operated clock source (f(RING)) or (f(X IN)) cannot be used for the system clock. Also, the clock source (f(RING) or f(XIN)) selected for the system clock cannot be stopped. On-chip oscillator The clock frequency of the on-chip oscillator depends on the sup- ply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. When considering the oscillation stabilize wait time at the switch of clock, be careful that the margin of frequencies of the on-chip oscillator clock. A/D converter-1

• When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-order 2 bits of register A, si- multaneously, the low-order 2 bits of register A is “0.”
• Do not change the operating mode (both A/D conversion mode and comparator mode) of A/D converter with the bit 3 of register Q1 while the A/D converter is operating.
• Clear the bit 2 of register V2 to “0” to change the operating mode of the A/D converter from the comparator mode to A/D conversion mode.
• The A/D conversion completion flag (ADF) may be set when the operating mode of the A/D converter is changed from the com- parator mode to the A/D conversion mode. Accordingly, set a value to the register Q1, and execute the SNZAD instruction to clear the ADF flag. LA 8 ; ( ✕ 0✕✕ LA 0 ; (0 ✕✕✕ 2) TQ1A ; Operation mode of A/D converter is changed from comparator mode to A/D conversion mode. SNZAD NOP ✕ : these bits are not used here. Fig. 72 A/D converter program example-3
• ••
• •• Fig. 73 Analog input external circuit example-1 A/D converter-2 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage. Accordingly, when the analog volt- age is input from the circuit with high-impedance and, charge/ discharge noise is generated and the sufficient A/D accuracy may not be obtained. Therefore, reduce the impedance or, connect a capacitor (0.01 µF to 1 µF) to analog input pins (Figure 73). When the overvoltage applied to the A/D conversion circuit may occur, connect an external circuit in order to keep the voltage within the rated range as shown the Figure 74. In addition, test the application products sufficiently. S e n s o r AI N A p p l y t h e v o l t a g e w i t h i i n t h e s p e c i f i c a t i o n s t o a n a n a l o g i n p u t p i n S e n s o r AIN About 1kΩ Fig. 74 Analog input external circuit example-2

Rev.3.01 2005.06.15 page 78 of 160 REJ03B0007-0301 When the external clock signal for the main clock (f(XIN)) is used, connect the clock source to XIN pin and XOUT pin open. In pro- gram, after the CMCK instruction is executed, set main clock (f(XIN)) oscillation start to be enabled (MR1=0). For this product, when RAM back-up mode and main clock (f(X IN)) stop (MR1=1), XIN pin is fixed to “H ” in order to avoid the through current by floating of internal logic. The XIN pin is fixed to “H ” until main clock (f(XIN)) oscillation start to be valid (MR1=0) by the CMCK instruction from reset state. Accordingly, when an external clock is used, connect a 1 kΩ or more resistor to XIN pin in series to limit of current by competitive signal. Electric Characteristic Differences Between Mask ROM and One Time PROM Version MCU There are differences in electric characteristics, operation mar- gin, noise immunity, and noise radiation between Mask ROM and One Time PROM version MCUs due to the difference in the manufacturing processes. When manufacturing an application system with the One time PROM version and then switching to use of the Mask ROM ver- sion, please perform sufficient evaluations for the commercial samples of the Mask ROM version. Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation.

Rev.3.01 2005.06.15 page 79 of 160 REJ03B0007-0301 CONTROL REGISTERS I13 I12 I11 I10 INT0 pin input control bit (Note 2) Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2) INT0 pin edge detection circuit control bit INT0 pin Timer 1 count start synchronous circuit selection bit Interrupt control register I1 R/W TAI1/TI1Aat RAM back-up : state retainedat reset : 00002 INT0 pin input disabled INT0 pin input enabled Falling waveform/“L” level (“L” level is recognized with the SNZI0 instruction) Rising waveform/“H ” level (“H ” level is recognized with the SNZI0 instruction) One-sided edge detected Both edges detected Timer 1 count start synchronous circuit not selected Timer 1 count start synchronous circuit selected Interrupt disabled (SNZSI instruction is valid) Interrupt enabled (SNZSI instruction is invalid) Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) Interrupt disabled (SNZT4 instruction is valid) Interrupt enabled (SNZT4 instruction is invalid) Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) V13 V12 V11 V10 V23 V22 V21 V20 Serial I/O interrupt enable bit A/D interrupt enable bit Timer 4 interrupt enable bit Timer 3 interrupt enable bit Interrupt control register V2 at RAM back-up : 00002at reset : 00002 Interrupt control register V1 Timer 2 interrupt enable bit Timer 1 interrupt enable bit External 1 interrupt enable bit External 0 interrupt enable bit Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) at RAM back-up : 0000 2at reset : 00002 R/W TAV1/TV1A I23 I22 I21 I20 INT1 pin input control bit (Note 2) Interrupt valid waveform for INT1 pin/ return level selection bit (Note 2) INT1 pin edge detection circuit control bit INT1 pin Timer 3 count start synchronous circuit selection bit Interrupt control register I2 R/W TAI2/TI2Aat RAM back-up : state retainedat reset : 00002 INT1 pin input disabled INT1 pin input enabled Falling waveform/“L” level (“L” level is recognized with the SNZI1 instruction) Rising waveform/“H ” level (“H ” level is recognized with the SNZI1 instruction) One-sided edge detected Both edges detected Timer 3 count start synchronous circuit not selected Timer 3 count start synchronous circuit selected Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: When the contents of I12, I13 I22 and I23 are changed, the external interrupt request flag (EXF0, EXF1) may be set to “1”. R/W TAV2/TV2A

Rev.3.01 2005.06.15 page 80 of 160 REJ03B0007-0301 Timer 1 underflow signal divided by 2 output Timer 2 underflow signal divided by 2 output Stop (state retained) Operating Count source System clock (STCK) Prescaler output (ORCLK) Timer 1 underflow signal (T1UDF) PWM signal (PWMOUT) CNTR0 output signal selection bit Timer 2 control bit Timer 2 count source selection bits Timer control register W2 at RAM back-up : state retainedat reset : 00002 Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”). W2 3 W2 2 W2 1 W2 0 MR 3 Clock control register MR Operation mode Through mode (frequency not divided) Frequency divided by 2 mode Frequency divided by 4 mode Frequency divided by 8 mode Main clock (f(X IN)) oscillation enabled Main clock (f(XIN)) oscillation stop Main clock (f(XIN)) Main clock (f(RING)) at reset : 11112 at RAM back-up : 11112 MR 3 R/W TAMR/ TMRA Main clock f(XIN) oscillation circuit control bit System clock oscillation source selection bit Operation mode selection bits MR 2 MR 1 MR 0 MR 2 On-chip oscillator (f(RING)) oscillation enabled On-chip oscillator (f(RING)) oscillation stop On-chip oscillator (f(RING)) control bit Clock control register RG W TRGAat RAM back-up : 02at reset : 02 RG 0 W1 1 Timer 1 count auto-stop circuit not selected Timer 1 count auto-stop circuit selected Stop (state retained) Operating Count source Instruction clock (INSTCK) Prescaler output (ORCLK) X IN input CNTR0 input Timer 1 count auto-stop circuit selection bit (Note 2) Timer 1 control bit Timer 1 count source selection bits Timer control register W1 R/W TAW1/TW1Aat RAM back-up : state retainedat reset : 00002 W1 3 W1 2 W1 1 W1 0 R/W TAW2/TW2A Stop (state initialized) Operating Prescaler control bit Timer control register PA W TPAAat RAM back-up : 02at reset : 02 PA 0

Rev.3.01 2005.06.15 page 81 of 160 REJ03B0007-0301 Falling edge Rising edge Falling edge Rising edge CNTR1 output auto-control circuit not selected CNTR1 output auto-control circuit selected D 6 (I/O) / CNTR0 (input) CNTR0 (I/O) /D6 (input) CNTR1 pin input count edge selection bit CNTR0 pin input count edge selection bit CNTR1 output auto-control circuit selection bit D 6/CNTR0 pin function selection bit Timer control register W6 at RAM back-up : state retainedat reset : 00002 W6 3 W6 2 W6 1 W6 0 D 7 (I/O) / CNTR1 (input) CNTR1 (I/O) / D7 (input) PWM signal “H ” interval expansion function invalid PWM signal “H ” interval expansion function valid Stop (state retained) Operating X IN input Prescaler output (ORCLK) divided by 2 D 7/CNTR1 pin function selection bit PWM signal “H ” interval expansion function control bit Timer 4 control bit Timer 4 count source selection bit W4 3 W4 2 W4 1 W4 0 W5 1 Not used Period measurement circuit control bit Signal for period measurement selection bits Timer control register W5 at RAM back-up : state retainedat reset : 00002 W5 3 W5 2 W5 1 W5 0 This bit has no function, but read/write is enabled. Stop Operating Count source On-chip oscillator (f(RING/16)) CNTR 0 pin input INT0 pin input Not available R/W TAW4/TW4A Timer control register W4 at RAM back-up : 00002at reset : 00002 R/W TAW5/TW5A R/W TAW6/TW6A W3 1 Timer 3 count auto-stop circuit not selected Timer 3 count auto-stop circuit selected Stop (state retained) Operating Count source PWM signal (PWMOUT) Prescaler output (ORCLK) Timer 2 underflow signal (T2UDF) CNTR1 input Timer 3 count auto-stop circuit selection bit (Note 2) Timer 3 control bit Timer 3 count source selection bits Timer control register W3 at RAM back-up : state retainedat reset : 00002 W3 3 W3 2 W3 1 W3 0 R/W TAW3/TW3A Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: This function is valid only when the timer 3 count start synchronous circuit is selected (I20=“1”).

Rev.3.01 2005.06.15 page 82 of 160 REJ03B0007-0301 Serial I/O synchronous clock selection bits Serial I/O port function selection bits Serial I/O control register J1 at RAM back-up : state retainedat reset : 00002 J13 J12 J11 J10 Synchronous clock Instruction clock (INSTCK) divided by 8 Instruction clock (INSTCK) divided by 4 Instruction clock (INSTCK) divided by 2 External clock (S CK input) Port function P20, P21,P22 selected/SCK , SOUT , SIN not selected SCK , SOUT , P22 selected/P20, P21, SIN not selected SCK , P21, SIN selected/P20, SOUT , P22 not selected SCK , SOUT , SIN selected/P20, P21,P22 not selected R/W TAJ1/TJ1A Q1 2 A/D operation mode selection bit Analog input pin selection bits A/D control register Q1 at RAM back-up : state retainedat reset : 00002 Q1 3 A/D conversion mode Comparator mode R/W TAQ1/TQ1A Q1 0 Q1 2 Q1 1 Q1 0 Analog input pins AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 P40, P41, P42, P43 AIN4, AIN5, AIN6, AIN7 P62, P63 AIN2, AIN3 P61 AIN1 P60 AIN0 P40/AIN4, P41/AIN5, P42/AIN6, P43/AIN7 pin function selection bit P62/AIN2, P63/AIN3 pin function selection bit P61/AIN1 pin function selection bit P60/AIN0 pin function selection bit Q2 3 Q2 2 Q2 1 Q2 0 R/W TAQ2/TQ2A A/D control register Q2 at RAM back-up : state retainedat reset : 00002 Note: “R ” represents read enabled, and “W ” represents write enabled. Not used A/D converter operation clock selection bit A/D converter operation clock division ratio selection bits A/D control register Q3 Q3 3 Q3 2 Q3 1 Q3 0 at reset : 00002 at RAM back-up : state retained Division ratio Frequency divided by 6 Frequency divided by 12 Frequency divided by 24 Frequency divided by 48 This bit has no function, but read/write is enabled. Instruction clock (INSTCK) On-chip oscillator (f(RING)) R/W TAQ3/TQ3A

Rev.3.01 2005.06.15 page 83 of 160 REJ03B0007-0301 K03 K02 K01 K00 Key-on wakeup control register K0 Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Pins P1 2 and P13 key-on wakeup control bit Pins P10 and P11 key-on wakeup control bit Pins P0 2 and P03 key-on wakeup control bit Pins P0 0 and P01 key-on wakeup control bit at reset : 00002 at RAM back-up : state retained R/W TAK0/TK0A Note: “R ” represents read enabled, and “W ” represents write enabled. K13 K12 K11 K10 Key-on wakeup control register K1 Return by level Return by edge Falling waveform/“L” level Rising waveform/“H ” level Return by level Return by edge Falling waveform/“L” level Rising waveform/“H ” level Ports P0 2 and P03 return condition selection bit Ports P02 and P03 valid waveform/ level selection bit Ports P0 1 and P00 return condition selection bit Ports P0 1 and P00 valid waveform/ level selection bit at reset : 00002 at RAM back-up : state retained R/W TAK1/TK1A K23 K22 K21 K20 Key-on wakeup control register K2 Return by level Return by edge Key-on wakeup not used Key-on wakeup used Return by level Return by edge Key-on wakeup not used Key-on wakeup used INT1 pin return condition selection bit INT1 pin key-on wakeup contro bit INT0 pin return condition selection bit INT0 pin key-on wakeup contro bit at reset : 00002 at RAM back-up : state retained R/W TAK2/TK2A

Rev.3.01 2005.06.15 page 84 of 160 REJ03B0007-0301 Pull-up control register PU0 PU1 3 PU1 2 PU1 1 PU1 0 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON 3 pin pull-up transistor control bit P02 pin pull-up transistor control bit 1 pin pull-up transistor control bit 0 pin pull-up transistor control bit at reset : 00002 at RAM back-up : state retained Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON 3 pin pull-up transistor control bit 2 pin pull-up transistor control bit 1 pin pull-up transistor control bit P10 pin pull-up transistor control bit R/W TAPU0/ TPU0A Pull-up control register PU1 at reset : 00002 at RAM back-up : state retained R/W TAPU1/ TPU1A Note: “R ” represents read enabled, and “W ” represents write enabled.

Rev.3.01 2005.06.15 page 85 of 160 REJ03B0007-0301 FR0 3 FR0 2 FR0 1 FR0 0 N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output Ports P1 2, P13 output structure selection bit Ports P1 0, P11 output structure selection bit Ports P02, P03 output structure selection bit Ports P0 0, P01 output structure selection bit Port output structure control register FR0 at reset : 00002 at RAM back-up : state retained FR1 3 FR1 2 FR1 1 FR1 0 N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output Port D 3 output structure selection bit Port D2 output structure selection bit Port D1 output structure selection bit Port D0 output structure selection bit Port output structure control register FR1 at reset : 00002 at RAM back-up : state retained FR2 3 FR2 2 FR2 1 FR2 0 N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output Port D7/CNTR1 output structure selection bit Port D6/CNTR0 output structure selection bit Port D5 output structure selection bit Port D4 output structure selection bit Port output structure control register FR2 at reset : 00002 at RAM back-up : state retained Note: “R ” represents read enabled, and “W ” represents write enabled. W TFR0A W TFR1A W TFR2A FR3 3 FR3 2 FR3 1 FR3 0 N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output Port P5 3 output structure selection bit Port P52 output structure selection bit Port P51 output structure selection bit Port P50 output structure selection bit Port output structure control register FR3 at reset : 00002 at RAM back-up : state retained W TFR3A

Rev.3.01 2005.06.15 page 86 of 160 REJ03B0007-0301 A B DR E MR RG PA PU0 PU1 FR0 FR1 FR2 FR3 X Y Z DP PC PC H PC L SK SP CY RPS R4L R4H

Contents

Register A (4 bits) Register B (4 bits) Register DR (3 bits) Register E (8 bits) Interrupt control register V1 (4 bits) Interrupt control register V2 (4 bits) Interrupt control register I1 (4 bits) Interrupt control register I2 (4 bits) Clock control register MR (4 bits) Clock control register RG (1 bit) Timer control register PA (1 bit) Timer control register W1 (4 bits) Timer control register W2 (4 bits) Timer control register W3 (4 bits) Timer control register W4 (4 bits) Timer control register W5 (4 bits) Timer control register W6 (4 bits) Serial I/O control register J1 (4 bits) A/D control register Q1 (4 bits) A/D control register Q2 (4 bits) A/D control register Q3 (4 bits) Pull-up control register PU0 (4 bits) Pull-up control register PU1 (4 bits) Port output format control register FR0 (4 bits) Port output format control register FR1 (4 bits) Port output format control register FR2 (4 bits) Port output format control register FR3 (4 bits) Key-on wakeup control register K0 (4 bits) Key-on wakeup control register K1 (4 bits) Key-on wakeup control register K2 (4 bits) Register X (4 bits) Register Y (4 bits) Register Z (2 bits) Data pointer (10 bits) (It consists of registers X, Y, and Z) Program counter (14 bits) High-order 7 bits of program counter Low-order 7 bits of program counter Stack register (14 bits ✕ 8) Stack pointer (3 bits) Carry flag Prescaler reload register (8 bits) Timer 1 reload register (8 bits) Timer 2 reload register (8 bits) Timer 3 reload register (8 bits) Timer 4 reload register (8 bits) Timer 4 reload register (8 bits) Timer 1 interrupt request flag Timer 2 interrupt request flag Timer 3 interrupt request flag Timer 4 interrupt request flag Watchdog timer flag Watchdog timer enable flag Interrupt enable flag External 0 interrupt request flag External 1 interrupt request flag Power down flag A/D conversion completion flag Serial I/O transmit/receive completion flag Port D (8 bits) Port P0 (4 bits) Port P1 (4 bits) Port P2 (3 bits) Port P3 (4 bits) Port P4 (4 bits) Port P5 (4 bits) Port P6 (4 bits) Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal constant Hexadecimal constant Hexadecimal constant Binary notation of hexadecimal variable A (same for others) Direction of data movement Data exchange between a register and memory Decision of state shown before “?” Contents of registers and memories Negate, Flag unchanged after executing instruction RAM address pointed by the data pointer Label indicating address a 6 a5 a4 a3 a2 a1 a0 Label indicating address a6 a5 a4 a3 a2 a1 a0 in page p5 p4 p3 p2 p1 p0 Hex. C + Hex. number x Symbol PS T1F T2F T3F T4F WDF1 WEF INTE EXF0 EXF1 P ADF SIOF D x y z p n i j A 3A2A1A0 ( ) M(DP) a p, a C + x INSTRUCTIONS The 4519 Group has the 153 instructions. Each instruction is de- scribed as follows; (1) Index list of instruction function (2) Machine instructions (index by alphabet) (3) Machine instructions (index by function) (4) Instruction code table Note : Some instructions of the 4519 Group has the skip function to unexecute the next described instruction. The 4519 Group just invalidates the next instruc- tion when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped. SYMBOL The symbols shown below are used in the following list of instruc- tion function and the machine instructions.

Rev.3.01 2005.06.15 page 87 of 160 REJ03B0007-0301 INDEX LIST OF INSTRUCTION FUNCTION Group- ing RAM addresses Mnemonic XAMI j TMA j LA n TABP p AM AMC A n AND OR SC RC SZC CMA RAR Function (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← n n = 0 to 15 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PC H ) ← p (PCL) ← (DR2–DR 0, A3–A0) (DR 2) ← 0 (DR 1, DR0) ← (ROM(PC))9, 8 (B) ← (ROM(PC))7–4 (A) ← (ROM(PC))3–0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (A) ← (A) + (M(DP)) (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry (A) ← (A) + n n = 0 to 15 (A) ← (A) AND (M(DP)) (A) ← (A) OR (M(DP)) (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → CY → A3A2A1A0 Mnemonic TAB TBA TAY TYA TEAB TABE TDA TAD TAZ TAX TASP LXY x, y LZ z INY DEY TAM j XAM j XAMD j Function (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) 7–E4) ← (B) (E3–E0) ← (A) (B) ← (E7–E4) (A) ← (E3–E0) (DR2–DR 0) ← (A2–A0) (A2–A0) ← (DR2–DR 0) (A3) ← 0 (A3, A2) ← 0 (A) ← (X) (A2–A0) ← (SP2–SP 0) (A3) ← 0 (X) ← x x = 0 to 15 (Y) ← y y = 0 to 15 (Z) ← z z = 0 to 3 (Y) ← (Y) + 1 (Y) ← (Y) – 1 (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) – 1 RAM to register transfer Arithmetic operation RAM to register transfer Register to register transfer Group- ing Note: p is 0 to 47 for M34519M6, p is 0 to 63 for M34519M8/E8.

Rev.3.01 2005.06.15 page 88 of 160 REJ03B0007-0301 INDEX LIST OF INSTRUCTION FUNCTION (continued) Group- ingFunction (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15 (PC L) ← a6–a0 (PCH ) ← p (PCL) ← a6–a0 (PCH ) ← p (PCL) ← (DR2–DR 0, A3–A0) (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← 2 (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← (DR2–DR 0, A3–A0) (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 Comparisonoperation Subroutine operation Branch operation Bit operation Return operation Mnemonic SB j RB j SZB j SEAM SEA n B a BL p, a BLA p BM a BML p, a BMLA p RTI RT RTS Group- ing Function (INTE) ← 0 (INTE) ← 1 After skipping, (EXF0) ← 0 V10 = 1: NOP After skipping, (EXF1) ← 0 V11 = 1: NOP (A) ← (V1) (V1) ← (A) (A) ← (V2) (V2) ← (A) (A) ← (I1) (I1) ← (A) (A) ← (I2) (I2) ← (A) (PA0) ← (A0) (A) ← (W1) (W1) ← (A) (A) ← (W2) (W2) ← (A) (A) ← (W3) (W3) ← (A) Interrupt operation Timer operation Note: p is 0 to 47 for M34519M6, p is 0 to 63 for M34519M8/E8. Mnemonic DI EI SNZ0 SNZ1 SNZI0 SNZI1 TAV1 TV1A TAV2 TV2A TAI1 TI1A TAI2 TI2A TPAA TAW1 TW1A TAW2 TW2A TAW3 TW3A

Rev.3.01 2005.06.15 page 89 of 160 REJ03B0007-0301 INDEX LIST OF INSTRUCTION FUNCTION (continued) Group- ing Group- ing Function (A) ← (W4) (W4) ← (A) (A) ← (W5) (W5) ← (A) (A) ← (W6) (W6) ← (A) (B) ← (TPS7–TPS 4) (A) ← (TPS3–TPS 0) (RPS 7–RPS 4) ← (B) (TPS7–TPS 4) ← (B) (RPS 3–RPS 0) ← (A) (TPS3–TPS 0) ← (A) (B) ← (T17–T14) (A) ← (T13–T10) (R17–R1 4) ← (B) (T17–T14) ← (B) (R13–R1 0) ← (A) (T13–T10) ← (A) (B) ← (T27–T24) (A) ← (T23–T20) (R27–R2 4) ← (B) (T27–T24) ← (B) (R23–R2 0) ← (A) (T23–T20) ← (A) (B) ← (T37–T34) (A) ← (T33–T30) (R37–R3 4) ← (B) (T37–T34) ← (B) (R33–R3 0) ← (A) (T33–T30) ← (A) (B) ← (T47–T44) (A) ← (T43–T40) (R4L7–R4L 4) ← (B) (T47–T44) ← (B) (R4L3–R4L 0) ← (A) (T43–T40) ← (A) Mnemonic TAW4 TW4A TAW5 TW5A TAW6 TW6A TABPS TPSAB TAB1 T1AB TAB2 T2AB TAB3 T3AB TAB4 T4AB Timer operation Input/Output operation Mnemonic T4HAB TR1AB TR3AB T4R4L SNZT1 SNZT2 SNZT3 SNZT4 IAP0 OP0A IAP1 OP1A IAP2 OP2A IAP3 OP3A IAP4 OP4A IAP5 OP5A IAP6 OP6A Function (R4H 7–R4H 4) ← (B) (R4H 3–R4H 0) ← (A) (T47–T44) ← (R4L7–R4L 4) After skipping, (T1F) ← 0 V12 = 1: NOP After skipping, (T2F) ← 0 V13 = 1: NOP After skipping, (T3F) ← 0 V20 = 1: NOP After skipping, (T4F) ← 0 V21 = 1: NOP (A) ← (P0) (P0) ← (A) (A) ← (P1) (P1) ← (A) (A) ← (P3) (P3) ← (A) (A) ← (P4) (P4) ← (A) (A) ← (P5) (P5) ← (A) (A) ← (P6) (P6) ← (A) Timer operation

Rev.3.01 2005.06.15 page 90 of 160 REJ03B0007-0301 INDEX LIST OF INSTRUCTION FUNCTION (continued) Group- ing Group- ing A/D operation Serial I/O operation Input/Output operation Function (D) ← 1 (D(Y)) ← 0 (Y) = 0 to 7 (D(Y)) ← 1 (Y) = 0 to 7 (D(Y)) = 0 ? (Y) = 0 to 7 (A) ← (PU0) (PU0) ← (A) (A) ← (PU1) (PU1) ← (A) (A) ← (K0) (K0) ← (A) (A) ← (K1) (K1) ← (A) (A) ← (K2) (K2) ← (A) (FR0) ← (A) (FR1) ← (A) (FR2) ← (A) (FR3) ← (A) Ceramic resonator selected RC oscillator selected Quartz-crystal oscillator selected (RG 0) ← (A0) (A) ← (MR) (MR) ← (A) Mnemonic CLD RD SD SZD TAPU0 TPU0A TAPU1 TPU1A TAK0 TK0A TAK1 TK1A TAK2 TK2A TFR0A TFR1A TFR2A TFR3A CMCK CRCK CYCK TRGA TAMR TMRA Function (B) ← (SI 7–SI4) (A) ← (SI3–SI0) (SI7–SI4) ← (B) (SI3–SI0) ← (A) (SIOF) ← 0 Serial I/O starting V23=0: (SIOF)=1? After skipping, (SIOF) ← 0 V23=1: NOP (A) ← (J1) (J1) ← (A) In A/D conversion mode , (B) ← (AD9–AD 6) (A) ← (AD5–AD 2) In comparator mode, (B) ← (AD7–AD 4) (A) ← (AD3–AD 0) (A3, A2) ← (AD1, AD0) (A1, A0) ← 0 (AD7–AD 4) ← (B) (AD3–AD 0) ← (A) (ADF) ← 0 A/D conversion starting After skipping, (ADF) ← 0 V21=1: NOP (A) ← (Q1) (Q1) ← (A) (A) ← (Q2) (Q2) ← (A) (A) ← (Q3) (Q3) ← (A) Mnemonic TABSI TSIAB SST SNZSI TAJ1 TJ1A TABAD TALA TADAB ADST SNZAD TAQ1 TQ1A TAQ2 TQ2A TAQ3 TQ3A Clock operation

Rev.3.01 2005.06.15 page 91 of 160 REJ03B0007-0301 Mnemonic NOP POF EPOF SNZP DWDT WRST SRST Function (PC) ← (PC) + 1 Transition to RAM back-up mode POF instruction valid (P) = 1 ? Stop of watchdog timer function enabled (WDF1) = 1 ? After skipping, (WDF1) ← 0 System reset occurrence Other operation INDEX LIST OF INSTRUCTION FUNCTION (continued) Group- ing

Rev.3.01 2005.06.15 page 92 of 160 REJ03B0007-0301 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) A n (Add n and accumulator) 000110nnnn 06n 11 – Overflow = 0 Grouping: Arithmetic operation Description:Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation. Operation: (A) ← (A) + n n = 0 to 15 ADST (A/D conversion STart) 1010011111 29F 11 – – Grouping: A/D conversion operation Description:Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q1 3 = 0) or the compara- tor operation at the comparator mode (Q13 = 1) is started. Operation: (ADF) ← 0 Q1 3 = 0: A/D conversion starting Q1 3 = 1: Comparator operation starting (Q13 : bit 3 of A/D control register Q1) AM (Add accumulator and Memory) 0000001010 00A 11 – – Grouping: Arithmetic operation Description:Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged. Operation: (A) ← (A) + (M(DP)) AMC (Add accumulator, Memory and Carry) 0000001011 00B 11 0/1 – Grouping: Arithmetic operation Description:Adds the contents of M(DP) and carry flag CY to register A. Stores the result in regis- ter A and carry flag CY. Operation: (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry

Rev.3.01 2005.06.15 page 93 of 160 REJ03B0007-0301 AND (logical AND between accumulator and memory) 0000011000 018 11 – – Grouping: Arithmetic operation Description:Takes the AND operation between the con- tents of register A and the contents of M(DP), and stores the result in register A. Operation: (A) ← (A) AND (M(DP)) B a (Branch to address a) 011a 6 a5 a4 a3 a2 a1 a0 1a 11 – – Grouping: Branch operation Description:Branch within a page : Branches to address a in the identical page. Note: Specify the branch address within the page including this instruction. Operation: (PCL) ← a6 to a0 BL p, a (Branch Long to address a in page p) 00111p 4 p3 p2 p1 p0 0p 22 – – Grouping: Branch operation Description:Branch out of a page : Branches to address a in page p. Note: p is 0 to 47 for M34519M6 and p is 0 to 63 for M34519M8E8. Operation: (PCH ) ← p (PCL) ← a6 to a0 BLA p (Branch Long to address (D) + (A) in page p) 0000010000 010 22 – – Grouping: Branch operation Description:Branch out of a page : Branches to address (DR 2 DR 1 DR 0 A3 A2 A1 A0)2 specified by registers D and A in page p. Note: p is 0 to 47 for M34519M6 and p is 0 to 63 for M34519M8E8. 2 1610p 5 a6 a5 a4 a3 a2 a1 a0 2a E Operation: (PCH ) ← p (PCL) ← (DR2–DR 0, A3–A0) 2 1610p 5 p4 00p 3 p2 p1 p0 2pp MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) p

Rev.3.01 2005.06.15 page 94 of 160 REJ03B0007-0301 BM a (Branch and Mark to address a in page 2) 010a 6 a5 a4 a3 a2 a1 a0 1aa 11 – – Grouping: Subroutine call operation Description:Call the subroutine in page 2 : Calls the subroutine at address a in page 2. Note: Subroutine extending from page 2 to an- other page can also be called with the BM instruction when it starts on page 2. Be careful not to over the stack because the maximum level of subroutine nesting is 8. Operation: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PC H ) ← 2 (PCL) ← a6–a0 BML p, a (Branch and Mark Long to address a in page p) 00110p 4 p3 p2 p1 p0 0p 22 – – Grouping: Subroutine call operation Description:Call the subroutine : Calls the subroutine at address a in page p. Note: p is 0 to 47 for M34519M6 and p is 0 to 63 for M34519M8E8. Be careful not to over the stack because the maximum level of subroutine nesting is 8. Operation: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PC H ) ← p (PCL) ← a6–a0 BMLA p (Branch and Mark Long to address (D) + (A) in page p) 0000110000 030 22 – – Grouping: Subroutine call operation Description:Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 speci- fied by registers D and A in page p. Note: p is 0 to 47 for M34519M6 and p is 0 to 63 for M34519M8E8. Be careful not to over the stack because the maximum level of subroutine nesting is 8. CLD (CLear port D) 0000010001 011 11 – – Grouping: Input/Output operation Description:Sets (1) to port D. Operation: (D) ← 1 2 1610p 5 a6 a5 a4 a3 a2 a1 a0 2a C Operation: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← (DR2–DR 0, A3–A0) 2 1610p 5 p4 00p 3 p2 p1 p0 2pp MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) p

Rev.3.01 2005.06.15 page 95 of 160 REJ03B0007-0301 CMA (CoMplement of Accumulator) 0000011100 01C 11 – – Grouping: Arithmetic operation Description:Stores the one’s complement for register A’s contents in register A. Operation: (A) ← (A) CMCK (Clock select: ceraMic oscillation ClocK) 1010011010 29A 11 – – Grouping: Clock control operation Description:Selects the ceramic oscillation circuit for main clock f(XIN). Operation: Ceramic oscillation circuit selected CRCK (Clock select: Rc oscillation ClocK) 1010011011 29B 11 – – Grouping: Clock control operation Description:Selects the RC oscillation circuit for main clock f(XIN). Operation: RC oscillation circuit selected MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) CYCK (Clock select: crYstal oscillation ClocK) 1010011101 29D 11 – – Grouping: Clock control operation Description:Selects the quartz-crystal oscillation circuit for main clock f(XIN). Operation: Quartz-crystal oscillation circuit selected

Rev.3.01 2005.06.15 page 96 of 160 REJ03B0007-0301 DI (Disable Interrupt) 0000000100 004 11 – – Grouping: Interrupt control operation Description:Clears (0) to interrupt enable flag INTE, and disables the interrupt. Note: Interrupt is disabled by executing the DI in- struction after executing 1 machine cycle. Operation: (INTE) ← 0 DWDT (Disable WatchDog Timer) 1010011100 29C 11 – – Grouping: Other operation Description:Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction. Operation: Stop of watchdog timer function enabled EI (Enable Interrupt) 0000000101 005 11 – – Grouping: Interrupt control operation Description:Sets (1) to interrupt enable flag INTE, and enables the interrupt. Note: Interrupt is enabled by executing the EI in- struction after executing 1 machine cycle. Operation: (INTE) ← 1 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) 0000010111 017 11 – (Y) = 15 Grouping: RAM addresses Description:Subtracts 1 from the contents of register Y. As a result of subtraction, when the con- tents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. Operation: (Y) ← (Y) – 1 DEY (DEcrement register Y)

Rev.3.01 2005.06.15 page 97 of 160 REJ03B0007-0301 IAP0 (Input Accumulator from port P0) 1001100000 260 11 – – Grouping: Input/Output operation Description:Transfers the input of port P0 to register A. IAP1 (Input Accumulator from port P1) 1001100001 261 11 – – Grouping: Input/Output operation Description:Transfers the input of port P1 to register A. Operation: (A) ← (P1) IAP2 (Input Accumulator from port P2) 1001100010 262 11 – – Grouping: Input/Output operation Description:Transfers the input of port P2 to register A. Operation: (A2–A0) ← (P22–P20) (A3) ← 0 Operation: (A) ← (P0) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) 0001011011 05B 11 –– Grouping: Other operation Description:Makes the immediate after POF instruction valid by executing the EPOF instruction. Operation: POF instruction valid EPOF (Enable POF instruction)

Rev.3.01 2005.06.15 page 98 of 160 REJ03B0007-0301 IAP4 (Input Accumulator from port P4) 1001100100 264 11 – – Grouping: Input/Output operation Description:Transfers the input of port P4 to register A. Operation: (A) ← (P4) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) IAP3 (Input Accumulator from port P3) 1001100011 263 11 – – Grouping: Input/Output operation Description:Transfers the input of port P3 to register A. Operation: (A) ← (P3) IAP6 (Input Accumulator from port P6) 1001100110 266 11 – – Grouping: Input/Output operation Description:Transfers the input of port P6 to register A. Operation: (A) ← (P6) IAP5 (Input Accumulator from port P5) 1001100101 265 11 – – Grouping: Input/Output operation Description:Transfers the input of port P5 to register A. Operation: (A) ← (P5)

Rev.3.01 2005.06.15 page 99 of 160 REJ03B0007-0301 LZ z (Load register Z with z) 00010010z 1 z0 04 11 –– Grouping: RAM addresses Description:Loads the value z in the immediate field to register Z. Operation: (Z) ← z z = 0 to 3 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) 11x 3 x2 x1 x0 y3 y2 y1 y0 3xy 11 – Continuous Grouping: RAM addresses Description:Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instruc- tions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continu- ously are skipped. Operation: (X) ← x x = 0 to 15 (Y) ← y y = 0 to 15 LXY x, y (Load register X and Y with x and y) INY (INcrement register Y) 0000010011 013 11 – (Y) = 0 Grouping: RAM addresses Description:Adds 1 to the contents of register Y . As a re- sult of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. Operation: (Y) ← (Y) + 1 LA n (Load n in Accumulator) 000111nnnn 07n 11 – Continuous Grouping: Arithmetic operation Description:Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA in- struction is executed and other LA instructions coded continuously are skipped. Operation: (A) ← n n = 0 to 15

Rev.3.01 2005.06.15 page 100 of 160 REJ03B0007-0301 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) NOP (No OPeration) 0000000000 000 11 – – Grouping: Other operation Description:No operation; Adds 1 to program counter value, and others remain unchanged. Operation: (PC) ← (PC) + 1 OP0A (Output port P0 from Accumulator) 1000100000 220 11 – – Grouping: Input/Output operation Description:Outputs the contents of register A to port P0. Operation: (P0) ← (A) OP1A (Output port P1 from Accumulator) 1000100001 221 11 – – Grouping: Input/Output operation Description:Outputs the contents of register A to port P1. Operation: (P1) ← (A) OP2A (Output port P2 from Accumulator) 1000100010 222 11 –– Grouping: Input/Output operation Description:Outputs the contents of register A to port P2. Operation: (P2) ← (A)

Rev.3.01 2005.06.15 page 101 of 160 REJ03B0007-0301 OP4A (Output port P4 from Accumulator) 1000100100 224 11 – – Grouping: Input/Output operation Description:Outputs the contents of register A to port P4. Operation: (P4) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) OP3A (Output port P3 from Accumulator) 1000100011 223 11 – – Grouping: Input/Output operation Description:Outputs the contents of register A to port P3. Operation: (P3) ← (A) OP5A (Output port P5 from Accumulator) 1000100101 225 11 – – Grouping: Input/Output operation Description:Outputs the contents of register A to port P5. Operation: (P5) ← (A) OP6A (Output port P6 from Accumulator) 1000100110 226 11 – – Grouping: Input/Output operation Description:Outputs the contents of register A to port P6. Operation: (P6) ← (A)

Rev.3.01 2005.06.15 page 102 of 160 REJ03B0007-0301 POF (Power OFf) 0000000010 002 11 –– Grouping: Other operation Description:Puts the system in RAM back-up state by executing the POF instruction after execut- ing the EPOF instruction. Note: If the EPOF instruction is not executed before executing this instruction, this instruction is equivalent to the NOP instruction. Operation: Transition to RAM back-up mode RAR (Rotate Accumulator Right) 0000011101 01D 1 1 0/1 – Grouping: Arithmetic operation Description:Rotates 1 bit of the contents of register A in- cluding the contents of carry flag CY to the right. Operation: → CY → A3A2A1A0 RB j (Reset Bit) 00010011j j 04 11 – – Grouping: Bit operation Description:Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Operation: (Mj(DP)) ← 0 j = 0 to 3 C MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) 0000011001 019 11 – – Grouping: Arithmetic operation Description:Takes the OR operation between the con- tents of register A and the contents of M(DP), and stores the result in register A. Operation: (A) ← (A) OR (M(DP)) OR (logical OR between accumulator and memory)

Rev.3.01 2005.06.15 page 103 of 160 REJ03B0007-0301 RD (Reset port D specified by register Y) 0000010100 014 11 – – Grouping: Input/Output operation Description:Clears (0) to a bit of port D specified by reg- ister Y. Operation: (D(Y)) ← 0 However, (Y) = 0 to 7 RC (Reset Carry flag) 0000000110 006 11 0 – Grouping: Arithmetic operation Description:Clears (0) to carry flag CY . Operation: (CY) ← 0 RTI (ReTurn from Interrupt) 0001000110 046 11 – – Grouping: Return operation Description:Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY in- struction, register A and register B to the states just before interrupt. Operation: (PC) ← (SK(SP)) (SP) ← (SP) – 1 RT (ReTurn from subroutine) 0001000100 044 12 – – Grouping: Return operation Description:Returns from subroutine to the routine called the subroutine. Operation: (PC) ← (SK(SP)) (SP) ← (SP) – 1 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

Rev.3.01 2005.06.15 page 104 of 160 REJ03B0007-0301 SD (Set port D specified by register Y) 0000010101 015 11 – – Grouping: Input/Output operation Description:Sets (1) to a bit of port D specified by regis- ter Y. Operation: (D(Y)) ← 1 (Y) = 0 to 7 SC (Set Carry flag) 0000000111 007 11 1 – Grouping: Arithmetic operation Description:Sets (1) to carry flag CY. Operation: (CY) ← 1 RTS (ReTurn from subroutine and Skip) 0001000101 045 12 – Skip at uncondition Grouping: Return operation Description:Returns from subroutine to the routine called the subroutine, and skips the next in- struction at uncondition. Operation: (PC) ← (SK(SP)) (SP) ← (SP) – 1 SB j (Set Bit) 00010111j j 05 11 – – Grouping: Bit operation Description:Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Operation: (Mj(DP)) ← 1 j = 0 to 3 C MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

Rev.3.01 2005.06.15 page 105 of 160 REJ03B0007-0301 SNZ0 (Skip if Non Zero condition of external 0 interrupt request flag) 0000111000 038 11 – V10 = 0: (EXF0) = 1 Grouping: Interrupt operation Description:When V1 0 = 0 : Skips the next instruction when external 0 interrupt request flag EXF0 is “1.” After skipping, clears (0) to the EXF0 flag. When the EXF0 flag is “0,” executes the next instruction. When V1 0 = 1 : This instruction is equiva- lent to the NOP instruction. Operation: V10 = 0: (EXF0) = 1 ? After skipping, (EXF0) ← 0 V10 = 1: SNZ0 = NOP (V10 : bit 0 of the interrupt control register V1) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SEA n (Skip Equal, Accumulator with immediate data n) 0000100101 025 22 – (A) = n Grouping: Comparison operation Description:Skips the next instruction when the con- tents of register A is equal to the value n in the immediate field. Executes the next instruction when the con- tents of register A is not equal to the value n in the immediate field. Operation: (A) = n ? n = 0 to 15 2 16000111nnnn 07n SEAM (Skip Equal, Accumulator with Memory) 0000100110 026 11 – (A) = (M(DP)) Grouping: Comparison operation Description:Skips the next instruction when the con- tents of register A is equal to the contents of M(DP). Executes the next instruction when the con- tents of register A is not equal to the contents of M(DP). Operation: (A) = (M(DP)) ? SNZ1 (Skip if Non Zero condition of external 1 interrupt request flag) 0000111001 039 11 – V11 = 0: (EXF1) = 1 Grouping: Interrupt operation Description:When V1 1 = 0 : Skips the next instruction when external 1 interrupt request flag EXF1 is “1.” After skipping, clears (0) to the EXF1 flag. When the EXF1 flag is “0,” executes the next instruction. When V1 1 = 1 : This instruction is equiva- lent to the NOP instruction. Operation: V11 = 0: (EXF1) = 1 ? After skipping, (EXF1) ← 0 V11 = 1: SNZ1 = NOP (V11 : bit 1 of the interrupt control register V1)

Rev.3.01 2005.06.15 page 106 of 160 REJ03B0007-0301 SNZP (Skip if Non Zero condition of Power down flag) 0000000011 003 11 – (P) = 1 Grouping: Other operation Description:Skips the next instruction when the P flag is “1”. After skipping, the P flag remains un- changed. Executes the next instruction when the P flag is “0.” Operation: (P) = 1 ? SNZAD (Skip if Non Zero condition of A/D conversion completion flag) 1010000111 287 Grouping: A/D conversion operation Description:When V2 2 = 0 : Skips the next instruction when A/D conversion completion flag ADF is “1.” After skipping, clears (0) to the ADF flag. When the ADF flag is “0,” executes the next instruction. When V2 2 = 1 : This instruction is equiva- lent to the NOP instruction. Operation: V22 = 0: (ADF) = 1 ? After skipping, (ADF) ← 0 V22 = 1: SNZAD = NOP (V22 : bit 2 of the interrupt control register V2) SNZI0 (Skip if Non Zero condition of external 0 Interrupt input pin) 0000111010 03A Grouping: Interrupt operation Description:When I1 2 = 0 : Skips the next instruction when the level of INT0 pin is “L.” Executes the next instruction when the level of INT0 pin is “H.” When I1 2 = 1 : Skips the next instruction when the level of INT0 pin is “H.” Executes the next instruction when the level of INT0 pin is “L.” Operation: I1 (I12 : bit 2 of the interrupt control register I1) SNZI1 (Skip if Non Zero condition of external 1 Interrupt input pin) 0000111011 03B Grouping: Interrupt operation Description:When I2 2 = 0 : Skips the next instruction when the level of INT1 pin is “L.” Executes the next instruction when the level of INT1 pin is “H.” When I2 2 = 1 : Skips the next instruction when the level of INT1 pin is “H.” Executes the next instruction when the level of INT1 pin is “L.” Operation: I22 = 0 : (INT1) = “L” ? (I22 : bit 2 of the interrupt control register I2) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

Rev.3.01 2005.06.15 page 107 of 160 REJ03B0007-0301 SNZT1 (Skip if Non Zero condition of Timer 1 interrupt request flag) 1010000000 280 Grouping: Timer operation Description:When V1 2 = 0 : Skips the next instruction when timer 1 interrupt request flag T1F is “1.” After skipping, clears (0) to the T1F flag. When the T1F flag is “0,” executes the next instruction. When V1 2 = 1 : This instruction is equiva- lent to the NOP instruction. Operation: V12 = 0: (T1F) = 1 ? After skipping, (T1F) ← 0 V12 = 1: SNZT1 = NOP (V12 = bit 2 of interrupt control register V1) SNZT2 (Skip if Non Zero condition of Timer 2 interrupt request flag) 1010000001 281 Grouping: Timer operation Description:When V1 3 = 0 : Skips the next instruction when timer 2 interrupt request flag T2F is “1.” After skipping, clears (0) to the T2F flag. When the T2F flag is “0,” executes the next instruction. When V1 3 = 1 : This instruction is equiva- lent to the NOP instruction. Operation: V13 = 0: (T2F) = 1 ? After skipping, (T2F) ← 0 V13 = 1: SNZT2 = NOP (V13 = bit 3 of interrupt control register V1) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SNZSI (Skip if Non Zero condition of Serial I/o interrupt request flag) SNZT3 (Skip if Non Zero condition of Timer 3 interrupt request flag) 1010000010 282 Grouping: Timer operation Description:When V2 0 = 0 : Skips the next instruction when timer 3 interrupt request flag T3F is “1.” After skipping, clears (0) to the T3F flag. When the T3F flag is “0,” executes the next instruction. When V2 0 = 1 : This instruction is equiva- lent to the NOP instruction. Operation: V20 = 0: (T3F) = 1 ? After skipping, (T3F) ← 0 V20 = 1: SNZT3 = NOP (V20 = bit 0 of interrupt control register V2) 1010001000 288 11 – V23 = 0: (SIOF) = 1 Grouping: Serial I/O operation Description:When V2 3 = 0 : Skips the next instruction when serial I/O interrupt request flag SIOF is “1.” After skipping, clears (0) to the SIOF flag. When the SIOF flag is “0,” executes the next instruction. When V2 3 = 1 : This instruction is equiva- lent to the NOP instruction. Operation: V23 = 0: (SIOF) = 1 ? After skipping, (SIOF) ← 0 V23 = 1: SNZSI = NOP (V23 = bit 3 of interrupt control register V2)

Rev.3.01 2005.06.15 page 108 of 160 REJ03B0007-0301 SNZT4 (Skip if Non Zero condition of Timer 4 inerrupt request flag) SRST (System ReSeT) SST (Serial i/o transmission/reception STart) 1010000011 283 Grouping: Timer operation Description:When V2 1 = 0 : Skips the next instruction when timer 4 interrupt request flag T4F is “1.” After skipping, clears (0) to the T4F flag. When the T4F flag is “0,” executes the next instruction. When V2 1 = 1 : This instruction is equiva- lent to the NOP instruction. Operation: V21 = 0: (T4F) = 1 ? After skipping, (T4F) ← 0 V21 = 1: SNZT4 = NOP (V21 = bit 1 of interrupt control register V2) 0000000001 001 11 – – Grouping: Other operation Description:System reset occurs. Operation: System reset occurrence 1010011110 29E 11 – – Grouping: Serial I/O operation Description:Clears (0) to SIOF flag and starts serial I/O. Operation: (SIOF) ← 0 Serial I/O transmission/reception start MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SZB j (Skip if Zero, Bit) 00001000j j 02j 11 – (Mj(DP)) = 0 j = 0 to 3 Grouping: Bit operation Description:Skips the next instruction when the con- tents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0.” Executes the next instruction when the con- tents of bit j of M(DP) is “1.” Operation: (Mj(DP)) = 0 ? j = 0 to 3

Rev.3.01 2005.06.15 page 109 of 160 REJ03B0007-0301 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SZC (Skip if Zero, Carry flag) 0000101111 02F 11 – (CY) = 0 Grouping: Arithmetic operation Description:Skips the next instruction when the con- tents of carry flag CY is “0.” After skipping, the CY flag remains un- changed. Executes the next instruction when the con- tents of the CY flag is “1.“ Operation: (CY) = 0 ? SZD (Skip if Zero, port D specified by register Y) 0000100100 024 22 – (D(Y)) = 0 (Y) = 0 to 7 Grouping: Input/Output operation Description:Skips the next instruction when a bit of port D specified by register Y is “0.” Executes the next instruction when the bit is “1.” T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B) 1000110000 230 11 – – Grouping: Timer operation Description:Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 re- load register R1. Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1. Operation: (T1 7–T14) ← (B) (R17–R1 4) ← (B) (T13–T10) ← (A) (R13–R1 0) ← (A) Operation: (D(Y)) = 0 ? (Y) = 0 to 7 2 160000101011 02B T2AB (Transfer data to timer 2 and register R2 from Accumulator and register B) 1000110001 231 11 – – Grouping: Timer operation Description:Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 re- load register R2. Transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2. Operation: (T2 7–T24) ← (B) (R27–R2 4) ← (B) (T23–T20) ← (A) (R23–R2 0) ← (A)

Rev.3.01 2005.06.15 page 110 of 160 REJ03B0007-0301 T3AB (Transfer data to timer 3 and register R3 from Accumulator and register B) T4AB (Transfer data to timer 4 and register R4L from Accumulator and register B) T4HAB (Transfer data to register R4H from Accumulator and register B) 1000110010 232 11 – – Grouping: Timer operation Description:Transfers the contents of register B to the high-order 4 bits of timer 3 and timer 3 re- load register R3. Transfers the contents of register A to the low-order 4 bits of timer 3 and timer 3 reload register R3. Operation: (T3 7–T34) ← (B) (R37–R3 4) ← (B) (T33–T30) ← (A) (R33–R3 0) ← (A) 1000110011 233 11 – – Grouping: Timer operation Description:Transfers the contents of register B to the high-order 4 bits of timer 4 and timer 4 re- load register R4L. Transfers the contents of register A to the low-order 4 bits of timer 4 and timer 4 reload register R4L. Operation: (T4 7–T44) ← (B) (R4L7–R4L 4) ← (B) (T43–T40) ← (A) (R4L3–R4L 0) ← (A) 1000110111 237 11 – – Grouping: Timer operation Description:Transfers the contents of register B to the high-order 4 bits of timer 4 and timer 4 re- load register R4H. Transfers the contents of register A to the low-order 4 bits of timer 4 and timer 4 reload register R4H. Operation: (R4H 7–R4H 4) ← (B) (R4H 3–R4H 0) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) T4R4L (Transfer data to timer 4 from register R4L) 1010010111 297 11 – – Grouping: Timer operation Description:Transfers the contents of reload register R4L to timer 4. Operation: (T47–T44) ← (R4L7–R4L 4) (T43–T40) ← (R4L3–R4L 0)

Rev.3.01 2005.06.15 page 111 of 160 REJ03B0007-0301 TAB (Transfer data to Accumulator from register B) 0000011110 01E 11 – – Grouping: Register to register transfer Description:Transfers the contents of register B to reg- ister A. TAB1 (Transfer data to Accumulator and register B from timer 1) 1001110000 270 11 – – Grouping: Timer operation Description:Transfers the high-order 4 bits (T17–T14) of timer 1 to register B. Transfers the low-order 4 bits (T13–T10) of timer 1 to register A. Operation: (B) ← (T17–T14) (A) ← (T13–T10) TAB2 (Transfer data to Accumulator and register B from timer 2) 1001110001 271 11 – – Grouping: Timer operation Description:Transfers the high-order 4 bits (T27–T24) of timer 2 to register B. Transfers the low-order 4 bits (T2 3–T20) of timer 2 to register A. Operation: (B) ← (T27–T24) (A) ← (T23–T20) Operation: (A) ← (B) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAB3 (Transfer data to Accumulator and register B from timer 3) 1001110010 272 11 – – Grouping: Timer operation Description:Transfers the high-order 4 bits (T37–T34) of timer 3 to register B. Transfers the low-order 4 bits (T33–T30) of timer 3 to register A. Operation: (B) ← (T37–T34) (A) ← (T33–T30)

Rev.3.01 2005.06.15 page 112 of 160 REJ03B0007-0301 TABP p (Transfer data to Accumulator and register B from Program memory in page p) 0010p 5 p4 p3 p2 p1 p0 0p 13 – – Grouping: Arithmetic operationOperation: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← (DR2–DR 0, A3–A0) (DR 2) ← 0 (DR 1, DR0) ← (ROM(PC))9, 8 (B) ← (ROM(PC))7–4 (A) ← (ROM(PC))3–0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 Description: Transfers bits 9 and 8 to register D, bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in ad- dress (DR2 DR 1 DR 0 A3 A2 A1 A0)2 specified by registers A and D in page p. Note: p is 0 to 47 for M34519M6, and p is 0 to 63 for M34519M8E8. When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. TABE (Transfer data to Accumulator and register B from register E) 0000101010 02A 11 –– Grouping: Register to register transfer Description:Transfers the high-order 4 bits (E7–E4) of register E to register B, and low-order 4 bits of register E to register A. Operation: (B) ← (E7–E4) (A) ← (E3–E0) TABAD (Transfer data to Accumulator and register B from register AD) 1001111001 279 11 –– Grouping: A/D conversion operation Description: In the A/D conversion mode (Q13 = 0), trans- fers the high-order 4 bits (AD9–AD 6) of register AD to register B, and the middle-or- der 4 bits (AD 5–AD 2) of register AD to register A. In the comparator mode (Q13 = 1), transfers the middle-order 4 bits (AD7–AD 4) of register AD to register B, and the low-order 4 bits (AD3–AD 0) of register AD to register A. Operation: In A/D conversion mode (Q13 = 0), (B) ← (AD9–AD 6) (A) ← (AD5–AD 2) In comparator mode (Q13 = 1), (B) ← (AD7–AD 4) (A) ← (AD3–AD 0) (Q13 : bit 3 of A/D control register Q1) TAB4 (Transfer data to Accumulator and register B from timer 4) 1001110011 273 11 – – Grouping: Timer operation Description:Transfers the high-order 4 bits (T47–T44) of timer 4 to register B. Transfers the low-order 4 bits (T4 3–T40) of timer 4 to register A. Operation: (B) ← (T47–T44) (A) ← (T43–T40) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

Rev.3.01 2005.06.15 page 113 of 160 REJ03B0007-0301 TAD (Transfer data to Accumulator from register D) 0001010001 051 11 – – Grouping: Register to register transfer Description:Transfers the contents of register D to the low-order 3 bits (A2–A0) of register A. Note: When this instruction is executed, “0” is stored to the bit 3 (A3) of register A. Operation: (A2–A0) ← (DR 2–DR 0) (A3) ← 0 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TABPS (Transfer data to Accumulator and register B from PreScaler) TABSI (Transfer data to Accumulator and register B from register SI) 1001111000 278 11 – – Grouping: Serial I/O operation Description:Transfers the high-order 4 bits (SI7–SI4) of serial I/O register SI to register B, and transfers the low-order 4 bits (SI3–SI0) of serial I/O register SI to register A. Operation: (B) ← (SI7–SI4) (A) ← (SI3–SI0) 1001110101 275 11 – – Grouping: Timer operation Description:Transfers the high-order 4 bits (TPS7– TPS 4) of prescaler to register B, and transfers the low-order 4 bits (TPS3–TPS 0) of prescaler to register A. Operation: (B) ← (TPS7–TPS 4) (A) ← (TPS3–TPS 0) TADAB (Transfer data to register AD from Accumulator from register B) 1000111001 239 11 – – Grouping: A/D conversion operation Description:In the A/D conversion mode (Q13 = 0), this in- struction is equivalent to the NOP instruction. In the comparator mode (Q13 = 1), trans- fers the contents of register B to the high-order 4 bits (AD 7–AD 4) of comparator register, and the contents of register A to the low-order 4 bits (AD3–AD 0) of compara- tor register. (Q13 = bit 3 of A/D control register Q1) Operation: (AD7–AD 4) ← (B) (AD3–AD 0) ← (A)

Rev.3.01 2005.06.15 page 114 of 160 REJ03B0007-0301 TAI1 (Transfer data to Accumulator from register I1) 1001010011 253 11 – – Grouping: Interrupt operation Description:Transfers the contents of interrupt control register I1 to register A. Operation: (A) ← (I1) TAI2 (Transfer data to Accumulator from register I2) 1001010100 254 11 – – Grouping: Interrupt operation Description:Transfers the contents of interrupt control register I2 to register A. Operation: (A) ← (I2) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAK0 (Transfer data to Accumulator from register K0) 1001010110 256 11 – – Grouping: Input/Output operation Description:Transfers the contents of key-on wakeup control register K0 to register A. Operation: (A) ← (K0) TAJ1 (Transfer data to Accumulator from register J1) 1001000010 242 11 – – Grouping: Serial I/O operation Description:Transfers the contents of serial I/O control register J1 to register A. Operation: (A) ← (J1)

Rev.3.01 2005.06.15 page 115 of 160 REJ03B0007-0301 TAK1 (Transfer data to Accumulator from register K1) 1001011001 259 11 – – Grouping: Input/Output operation Description:Transfers the contents of key-on wakeup control register K1 to register A. Operation: (A) ← (K1) TAK2 (Transfer data to Accumulator from register K2) 1001011010 25A 11 – – Grouping: Input/Output operation Description:Transfers the contents of key-on wakeup control register K2 to register A. Operation: (A) ← (K2) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TALA (Transfer data to Accumulator from register LA) 1001001001 249 11 – – Grouping: A/D conversion operation Description:Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (A3, A2) of register A. Note: After this instruction is executed, “0” is stored to the low-order 2 bits (A1, A0) of register A. Operation: (A3, A2) ← (AD1, AD0) (A1, A0) ← 0 TAM j (Transfer data to Accumulator from Memory) 101100 jjjj 2 C j 11 – – Grouping: RAM to register transfer Description:After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the re- sult in register X. Operation: (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15

Rev.3.01 2005.06.15 page 116 of 160 REJ03B0007-0301 TAQ1 (Transfer data to Accumulator from register Q1) 1001000100 244 11 – – Grouping: A/D conversion operation Description:Transfers the contents of A/D control regis- ter Q1 to register A. Operation: (A) ← (Q1) TAPU1 (Transfer data to Accumulator from register PU1) TAPU0 (Transfer data to Accumulator from register PU0) 1001010111 257 11 – – Grouping: Input/Output operation Description:Transfers the contents of pull-up control register PU0 to register A. Operation: (A) ← (PU0) 1001011110 25E 11 – – Grouping: Input/Output operation Description:Transfers the contents of pull-up control register PU1 to register A. Operation: (A) ← (PU1) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) 1001010010 252 11 – – Grouping: Clock operation Description:Transfers the contents of clock control reg- ister MR to register A. Operation: (A) ← (MR) TAMR (Transfer data to Accumulator from register MR)

Rev.3.01 2005.06.15 page 117 of 160 REJ03B0007-0301 TASP (Transfer data to Accumulator from Stack Pointer) 0001010000 050 11 – – Grouping: Register to register transfer Description:Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2–A0) of register A. Note: After this instruction is executed, “0” is stored to the bit 3 (A3) of register A. TAV1 (Transfer data to Accumulator from register V1) 0001010100 054 11 – – Grouping: Interrupt operation Description:Transfers the contents of interrupt control register V1 to register A. Operation: (A) ← (V1) Operation: (A2–A0) ← (SP2–SP 0) (A3) ← 0 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAQ3 (Transfer data to Accumulator from register Q3) 1001000110 246 11 – – Grouping: A/D conversion operation Description:Transfers the contents of A/D control regis- ter Q3 to register A. Operation: (A) ← (Q3) TAQ2 (Transfer data to Accumulator from register Q2) 1001000101 245 11 – – Grouping: A/D conversion operation Description:Transfers the contents of A/D control regis- ter Q2 to register A. Operation: (A) ← (Q2)

Rev.3.01 2005.06.15 page 118 of 160 REJ03B0007-0301 TAW2 (Transfer data to Accumulator from register W2) 1001001100 24C 11 – – Grouping: Timer operation Description:Transfers the contents of timer control reg- ister W2 to register A. Operation: (A) ← (W2) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAW1 (Transfer data to Accumulator from register W1) 1001001011 24B 11 – – Grouping: Timer operation Description:Transfers the contents of timer control reg- ister W1 to register A. Operation: (A) ← (W1) TAW3 (Transfer data to Accumulator from register W3) 1001001101 24D 11 – – Grouping: Timer operation Description:Transfers the contents of timer control reg- ister W3 to register A. Operation: (A) ← (W3) TAV2 (Transfer data to Accumulator from register V2) 0001010101 055 11 – – Grouping: Interrupt operation Description:Transfers the contents of interrupt control register V2 to register A. Operation: (A) ← (V2)

Rev.3.01 2005.06.15 page 119 of 160 REJ03B0007-0301 TAW5 (Transfer data to Accumulator from register W5) TAW6 (Transfer data to Accumulator from register W6) 1001010000 250 11 –– Grouping: Timer operation Description:Transfers the contents of timer control reg- ister W6 to register A. TAX (Transfer data to Accumulator from register X) 0001010010 052 11 – – Grouping: Register to register transfer Description:Transfers the contents of register X to reg- ister A. Operation: (A) ← (X) Operation: (A) ← (W6) 1001001111 24F 11 – – Grouping: Timer operation Description:Transfers the contents of timer control reg- ister W5 to register A. Operation: (A) ← (W5) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAW4 (Transfer data to Accumulator from register W4) 1001001110 24E 11 – – Grouping: Timer operation Description:Transfers the contents of timer control reg- ister W4 to register A. Operation: (A) ← (W4)

Rev.3.01 2005.06.15 page 120 of 160 REJ03B0007-0301 TBA (Transfer data to register B from Accumulator) 0000001110 00E 11 – – Grouping: Register to register transfer Description:Transfers the contents of register A to regis- ter B. TDA (Transfer data to register D from Accumulator) 0000101001 029 11 – – Grouping: Register to register transfer Description:Transfers the contents of the low-order 3 bits (A2–A0) of register A to register D. Operation: (DR 2–DR 0) ← (A2–A0) Operation: (B) ← (A) TAZ (Transfer data to Accumulator from register Z) 0001010011 053 11 – – Grouping: Register to register transfer Description:Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. Note: After this instruction is executed, “0” is stored to the high-order 2 bits (A3, A2) of register A. Operation: (A1, A0) ← (Z1, Z0) (A3, A2) ← 0 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAY (Transfer data to Accumulator from register Y) 0000011111 01F 11 – – Grouping: Register to register transfer Description:Transfers the contents of register Y to regis- ter A. Operation: (A) ← (Y)

Rev.3.01 2005.06.15 page 121 of 160 REJ03B0007-0301 TFR2A (Transfer data to register FR2 from Accumulator) TFR1A (Transfer data to register FR1 from Accumulator) TFR0A (Transfer data to register FR0 from Accumulator) 1000101000 228 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to the port output structure control register FR0. Operation: (FR0) ← (A) 1000101001 229 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to the port output structure control register FR1. Operation: (FR1) ← (A) 1000101010 22A 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to the port output structure control register FR2. Operation: (FR2) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TEAB (Transfer data to register E from Accumulator and register B) 0000011010 01A 11 – – Grouping: Register to register transfer Description:Transfers the contents of register B to the high-order 4 bits (E7–E4) of register E, and the contents of register A to the low-order 4 bits (E3–E0) of register E. Operation: (E7–E4) ← (B) (E3–E0) ← (A)

Rev.3.01 2005.06.15 page 122 of 160 REJ03B0007-0301 TI1A (Transfer data to register I1 from Accumulator) 1000010111 217 11 – – Grouping: Interrupt operation Description:Transfers the contents of register A to inter- rupt control register I1. Operation: (I1) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TI2A (Transfer data to register I2 from Accumulator) TJ1A (Transfer data to register J1 from Accumulator) 1000011000 218 11 – – Grouping: Interrupt operation Description:Transfers the contents of register A to inter- rupt control register I2. Operation: (I2) ← (A) 1000000010 202 11 – – Grouping: Serial I/O operation Description:Transfers the contents of register A to serial I/O control register J1. Operation: (J1) ← (A) TFR3A (Transfer data to register FR3 from Accumulator) 1000101011 22B 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to the port output structure control register FR3. Operation: (FR3) ← (A)

Rev.3.01 2005.06.15 page 123 of 160 REJ03B0007-0301 TK0A (Transfer data to register K0 from Accumulator) 1000011011 21B 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to key- on wakeup control register K0. Operation: (K0) ← (A) TK1A (Transfer data to register K1 from Accumulator) 1000010100 214 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to key- on wakeup control register K1. TK2A (Transfer data to register K2 from Accumulator) 1000010101 215 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to key- on wakeup control register K2. Operation: (K2) ← (A) Operation: (K1) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TMA j (Transfer data to Memory from Accumulator) 101011 jjjj 2 B j 11 – – Grouping: RAM to register transfer Description:After transferring the contents of register A to M(DP), an exclusive OR operation is per- formed between register X and the value j in the immediate field, and stores the result in register X. Operation: (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15

Rev.3.01 2005.06.15 page 124 of 160 REJ03B0007-0301 TPU0A (Transfer data to register PU0 from Accumulator) 1000101101 22D 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to pull- up control register PU0. Operation: (PU0) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TPAA (Transfer data to register PA from Accumulator) TPSAB (Transfer data to Pre-Scaler from Accumulator and register B) 1010101010 2AA 11 – – Grouping: Timer operation Description:Transfers the contents of lowermost bit (A0) register A to timer control register PA. Operation: (PA0) ← (A0) 1000110101 235 11 – – Grouping: Timer operation Description:Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS, and transfers the con- tents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS. Operation: (RPS 7–RPS 4) ← (B) (TPS7–TPS 4) ← (B) (RPS 3–RPS 0) ← (A) (TPS3–TPS 0) ← (A) TMRA (Transfer data to register MR from Accumulator) 1000010110 216 11 – – Grouping: Other operation Description:Transfers the contents of register A to clock control register MR. Operation: (MR) ← (A)

Rev.3.01 2005.06.15 page 125 of 160 REJ03B0007-0301 TQ2A (Transfer data to register Q2 from Accumulator) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TQ1A (Transfer data to register Q1 from Accumulator) 1000000100 204 11 – – Grouping: A/D conversion operation Description:Transfers the contents of register A to A/D control register Q1. Operation: (Q1) ← (A) TQ3A (Transfer data to register Q3 from Accumulator) 1000000101 205 11 – – Grouping: A/D conversion operation Description:Transfers the contents of register A to A/D control register Q2. Operation: (Q2) ← (A) 1000000110 206 11 –– Grouping: A/D conversion operation Description:Transfers the contents of register A to A/D control register Q3. Operation: (Q3) ← (A) TPU1A (Transfer data to register PU1 from Accumulator) 1000101110 22E 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to pull- up control register PU1. Operation: (PU1) ← (A)

Rev.3.01 2005.06.15 page 126 of 160 REJ03B0007-0301 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TR3AB (Transfer data to register R3 from Accumulator and register B) TSIAB (Transfer data to register SI from Accumulator and register B) 1000111011 23B 11 – – Grouping: Timer operation Description:Transfers the contents of register B to the high-order 4 bits (R37–R3 4) of reload regis- ter R3, and the contents of register A to the low-order 4 bits (R3 3–R3 0) of reload regis- ter R3. Operation: (R37–R3 4) ← (B) (R33–R3 0) ← (A) 1000111000 238 11 – – Grouping: Serial I/O operation Description:Transfers the contents of register B to the high-order 4 bits (SI7–SI4) of serial I/O reg- ister SI, and transfers the contents of register A to the low-order 4 bits (SI 3–SI0) of serial I/O register SI. Operation: (SI7–SI4) ← (B) (SI3–SI0) ← (A) TR1AB (Transfer data to register R1 from Accumulator and register B) 1000111111 23F 11 –– Grouping: Timer operation Description:Transfers the contents of register B to the high-order 4 bits (R17–R1 4) of reload regis- ter R1, and the contents of register A to the low-order 4 bits (R1 3–R1 0) of reload regis- ter R1. Operation: (R17–R1 4) ← (B) (R13–R1 0) ← (A) TRGA (Transfer data to register RG from Accumulator) 1000001001 209 11 – – Grouping: Clock control operation Description:Transfers the contents of register A to regis- ter RG. Operation: (RG 0) ← (A0)

Rev.3.01 2005.06.15 page 127 of 160 REJ03B0007-0301 TW1A (Transfer data to register W1 from Accumulator) 1000001110 20E 11 –– Grouping: Timer operation Description:Transfers the contents of register A to timer control register W1. Operation: (W1) ← (A) TW2A (Transfer data to register W2 from Accumulator) 1000001111 20F 11 – – Grouping: Timer operation Description:Transfers the contents of register A to timer control register W2. Operation: (W2) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) 0000111110 03E 11 – – Grouping: Interrupt operation Description:Transfers the contents of register A to inter- rupt control register V2. Operation: (V2) ← (A) TV2A (Transfer data to register V2 from Accumulator) TV1A (Transfer data to register V1 from Accumulator) 0000111111 03F 11 – – Grouping: Interrupt operation Description:Transfers the contents of register A to inter- rupt control register V1. Operation: (V1) ← (A)

Rev.3.01 2005.06.15 page 128 of 160 REJ03B0007-0301 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TW5A (Transfer data to register W5 from Accumulator) TW6A (Transfer data to register W6 from Accumulator) 1000010011 213 11 – – Grouping: Timer operation Description:Transfers the contents of register A to timer control register W6. Operation: (W6) ← (A) 1000010010 212 11 – – Grouping: Timer operation Description:Transfers the contents of register A to timer control register W5. Operation: (W5) ← (A) Grouping: Timer operation Description:Transfers the contents of register A to timer control register W4. TW4A (Transfer data to register W4 from Accumulator) 1000010001 211 11 – – Operation: (W4) ← (A) TW3A (Transfer data to register W3 from Accumulator) 1000010000 210 11 – – Grouping: Timer operation Description:Transfers the contents of register A to timer control register W3. Operation: (W3) ← (A)

Rev.3.01 2005.06.15 page 129 of 160 REJ03B0007-0301 TYA (Transfer data to register Y from Accumulator) 0000001100 00C 11 –– Grouping: Register to register transfer Description:Transfers the contents of register A to regis- ter Y . Operation: (Y) ← (A) WRST (Watchdog timer ReSeT) 1010100000 2A0 11 – (WDF1) = 1 Grouping: Other operation Description:Skips the next instruction when watchdog timer flag WDF1 is “1.” After skipping, clears (0) to the WDF1 flag. When the WDF1 flag is “0,” executes the next instruction. Also, stops the watchdog timer function when ex- ecuting the WRST instruction immediately after the DWDT instruction. Operation: (WDF1) = 1 ? After skipping, (WDF1) ← 0 XAM j (eXchange Accumulator and Memory data) 101101 jjjj 2 D j 11 – – Grouping: RAM to register transfer Description:After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between regis- ter X and the value j in the immediate field, and stores the result in register X. Operation: (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip) 101111 jjjj 2 F j 11 – (Y) = 15 Grouping: RAM to register transfer Description:After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between regis- ter X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the con- tents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. Operation: (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) – 1 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip) 101110 jjjj 2 E j 11 – (Y) = 0 Grouping: RAM to register transfer Description:After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between regis- ter X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y . As a re- sult of addition, when the contents of register Y is 0, the next instruction is skipped. when the contents of register Y is not 0, the next instruction is executed. Operation: (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 Instruction code 2 16 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) Skip conditionNumber of cycles Number of words Instruction code Flag CY 2 16 D 9 D 0 Rev.3.01 2005.06.15 page 130 of 160 REJ03B0007-0301

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.3.01 2005.06.15 page 131 of 160 REJ03B0007-0301 (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) (E7–E4) ← (B) (E3–E0) ← (A) (B) ← (E7–E4) (A) ← (E3–E0) (DR 2–DR 0) ← (A2–A0) (A2–A0) ← (DR2–DR 0) (A3) ← 0 (A3, A2) ← 0 (A) ← (X) (A2–A0) ← (SP2–SP 0) (A3) ← 0 (X) ← x x = 0 to 15 (Y) ← y y = 0 to 15 (Z) ← z z = 0 to 3 (Y) ← (Y) + 1 (Y) ← (Y) – 1 (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) – 1 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 TAB TBA TAY TYA TEAB TABE TDA TAD TAZ TAX TASP LXY x, y LZ z INY DEY TAM j XAM j XAMD j XAMI j TMA j MACHINE INSTRUCTIONS (INDEX BY TYPES) 0000011110 0000001110 0000011111 0000001100 0000011010 0000101010 0000101001 0001010001 0001010011 0001010010 0001010000 11x 3 x2 x1 x0 y3 y2 y1 y0 00010010z 1 z0 0000010011 0000010111 101100 jjjj 101101 jjjj 101111 jjjj 101110 jjjj 101011 jjjj 01E 00E 01F 00C 01A 02A 029 051 053 052 050 3xy 048 013 017 2C j 2D j 2Fj 2Ej 2Bj RAM addresses RAM to register transfer Register to register transfer

Skip condition Datailed description Carry flag CY Rev.3.01 2005.06.15 page 132 of 160 REJ03B0007-0301 (Y) = 0 (Y) = 15 (Y) = 15 (Y) = 0 Transfers the contents of register B to register A. Transfers the contents of register A to register B. Transfers the contents of register Y to register A. Transfers the contents of register A to register Y . Transfers the contents of register B to the high-order 4 bits (E 7–E4) of register E, and the contents of regis- ter A to the low-order 4 bits (E3–E0) of register E. Transfers the high-order 4 bits (E7–E4) of register E to register B, and low-order 4 bits (E3–E0) of register E to register A. Transfers the contents of the low-order 3 bits (A2–A0) of register A to register D. Transfers the contents of register D to the low-order 3 bits (A2–A0) of register A. Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. Transfers the contents of register X to register A. Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2–A0) of register A. Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. Loads the value z in the immediate field to register Z. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next in- struction is skipped. When the contents of register Y is not 0, the next instruction is executed. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between reg- ister X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per- formed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per- formed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per- formed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next in- struction is skipped. When the contents of register Y is not 0, the next instruction is executed. After transferring the contents of register A to M(DP), an exclusive OR operation is performed between reg- ister X and the value j in the immediate field, and stores the result in register X.

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.3.01 2005.06.15 page 133 of 160 REJ03B0007-0301 MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) 07n 08p 00A 00B 06n 018 019 007 006 02F 01C 01D 05C 04C 02j 026 025 07n 000111nnnn 0010p 5 p4 p3 p2 p1 p0 0000001010 0000001011 000110nnnn 0000011000 0000011001 0000000111 0000000110 0000101111 0000011100 0000011101 00010111j j 00010011j j 00001000j j 0000100110 0000100101 000111nnnn LA n TABP p AM AMC A n AND OR SC RC SZC CMA RAR SB j RB j SZB j SEAM SEA n Arithmetic operation Comparison operation Bit operation (A) ← n n = 0 to 15 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (Note) (PCL) ← (DR2–DR 0, A3–A0) (DR2) ← 0 (DR1, DR0) ← (ROM(PC))9, 8 (B) ← (ROM(PC))7–4 (A) ← (ROM(PC))3–0 (SK(SP)) ← (PC) (SP) ← (SP) – 1 (A) ← (A) + (M(DP)) (A) ← (A) + (M(DP)) +(CY) (CY) ← Carry (A) ← (A) + n n = 0 to 15 (A) ← (A) AND (M(DP)) (A) ← (A) OR (M(DP)) (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → CY → A 3A2A1A0 (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15 Note: p is 0 to 47 for M34519M6, p is 0 to 63 for M34519M8/E8.

Skip condition Datailed description Carry flag CY Rev.3.01 2005.06.15 page 134 of 160 REJ03B0007-0301 Overflow = 0 (CY) = 0 (Mj(DP)) = 0 j = 0 to 3 (A) = (M(DP)) (A) = n Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. Transfers bits 9 and 8 to register D, bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in ad-dress (DR 2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY re- mains unchanged. Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation. Takes the AND operation between the contents of register A and the contents of M(DP), and stores the re- sult in register A. Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A. Sets (1) to carry flag CY . Clears (0) to carry flag CY. Skips the next instruction when the contents of carry flag CY is “0.” Stores the one’s complement for register A’s contents in register A. Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0.” Executes the next instruction when the contents of bit j of M(DP) is “1.” Skips the next instruction when the contents of register A is equal to the contents of M(DP). Executes the next instruction when the contents of register A is not equal to the contents of M(DP). Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Executes the next instruction when the contents of register A is not equal to the value n in the immediate field.

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.3.01 2005.06.15 page 135 of 160 REJ03B0007-0301 B a BL p, a BLA p BM a BML p, a BMLA p RTI RT RTS 011a 6 a5 a4 a3 a2 a1 a0 00111p 4 p3 p2 p1 p0 10p 5 a6 a5 a4 a3 a2 a1 a0 0000010000 10p 5 p4 00p 3 p2 p1 p0 010a 6 a5 a4 a3 a2 a1 a0 00110p 4 p3 p2 p1 p0 10p 5 a6 a5 a4 a3 a2 a1 a0 0000110000 10p 5 p4 00p 3 p2 p1 p0 0001000110 0001000100 0001000101 18a 0Ep 2pa 010 2pp 1aa 0C p 2pa 030 2pp 046 044 045 Subroutine operation Return operation MACHINE INSTRUCTIONS (continued) (PCL) ← a6–a0 (PCH ) ← p (Note) (PCL) ← a6–a0 (PCH ) ← p (Note) (PCL) ← (DR2–DR 0, A3–A0) (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← 2 (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (Note) (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (Note) (PCL) ← (DR2–DR 0,A3–A0) (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 Branch operation Note: p is 0 to 47 for M34519M6, p is 0 to 63 for M34519M8/E8.

Skip condition Datailed description Carry flag CY Rev.3.01 2005.06.15 page 136 of 160 REJ03B0007-0301 Branch within a page : Branches to address a in the identical page. Branch out of a page : Branches to address a in page p. Branch out of a page : Branches to address (DR

2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in

page p. Call the subroutine in page 2 : Calls the subroutine at address a in page 2. Call the subroutine : Calls the subroutine at address a in page p. Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous de- scription of the LA/LXY instruction, register A and register B to the states just before interrupt. Returns from subroutine to the routine called the subroutine. Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.3.01 2005.06.15 page 137 of 160 REJ03B0007-0301 DI EI SNZ0 SNZ1 SNZI0 SNZI1 TAV1 TV1A TAV2 TV2A TAI1 TI1A TAI2 TI2A TPAA TAW1 TW1A TAW2 TW2A TAW3 TW3A TAW4 TW4A (INTE) ← 0 (INTE) ← 1 After skipping, (EXF0) ← 0 V10 = 1: SNZ0 = NOP After skipping, (EXF1) ← 0 V11 = 1: SNZ1 = NOP (A) ← (V1) (V1) ← (A) (A) ← (V2) (V2) ← (A) (A) ← (I1) (I1) ← (A) (A) ← (I2) (I2) ← (A) (PA0) ← (A0) (A) ← (W1) (W1) ← (A) (A) ← (W2) (W2) ← (A) (A) ← (W3) (W3) ← (A) (A) ← (W4) (W4) ← (A) 004 005 038 039 03A 03B 054 03F 055 03E 253 217 254 218 2AA 24B 20E 24C 20F 24D 210 24E 211 0000000100 0000000101 0000111000 0000111001 0000111010 0000111011 0001010100 0000111111 0001010101 0000111110 1001010011 1000010111 1001010100 1000011000 1010101010 1001001011 1000001110 1001001100 1000001111 1001001101 1000010000 1001001110 1000010001 Interrupt operation Timer operation Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)

Skip condition Datailed description Carry flag CY Rev.3.01 2005.06.15 page 138 of 160 REJ03B0007-0301 0 = 0: (EXF0) = 1 (INT0) = “H ” However, I12 = 1 (INT0) = “L” However, I12 = 0 (INT1) = “H ” However, I22 = 1 (INT1) = “L” However, I22 = 0 Skip condition Datailed description Carry flag CY Clears (0) to interrupt enable flag INTE, and disables the interrupt. Sets (1) to interrupt enable flag INTE, and enables the interrupt. When V1 0 = 0 : Skips the next instruction when external 0 interrupt request flag EXF0 is “1.” After skipping, clears (0) to the EXF0 flag. When the EXF0 flag is “0,” executes the next instruction. When V1 0 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register V1) When V1 1 = 0 : Skips the next instruction when external 1 interrupt request flag EXF1 is “1.” After skipping, clears (0) to the EXF1 flag. When the EXF1 flag is “0,” executes the next instruction. When V1 1 = 1 : This instruction is equivalent to the NOP instruction. (V11: bit 1 of interrupt control register V1) When I12 = 1 : Skips the next instruction when the level of INT0 pin is “H.” (I12: bit 2 of interrupt control reg- ister I1) When I12 = 0 : Skips the next instruction when the level of INT0 pin is “L.” When I22 = 1 : Skips the next instruction when the level of INT1 pin is “H.” (I22: bit 2 of interrupt control reg- ister I2) When I22 = 0 : Skips the next instruction when the level of INT1 pin is “L.” Transfers the contents of interrupt control register V1 to register A. Transfers the contents of register A to interrupt control register V1. Transfers the contents of interrupt control register V2 to register A. Transfers the contents of register A to interrupt control register V2. Transfers the contents of interrupt control register I1 to register A. Transfers the contents of register A to interrupt control register I1. Transfers the contents of interrupt control register I2 to register A. Transfers the contents of register A to interrupt control register I2. Transfers the contents of register A to timer control register PA. Transfers the contents of timer control register W1 to register A. Transfers the contents of register A to timer control register W1. Transfers the contents of timer control register W2 to register A. Transfers the contents of register A to timer control register W2. Transfers the contents of timer control register W3 to register A. Transfers the contents of register A to timer control register W3. Transfers the contents of timer control register W4 to register A. Transfers the contents of register A to timer control register W4.

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.3.01 2005.06.15 page 139 of 160 REJ03B0007-0301 1001001111 1000010010 1001010000 1000010011 1001110101 1000110101 1001110000 1000110000 1001110001 1000110001 1001110010 1000110010 1001110011 1000110011 1000110111 1000111111 1000111011 1010010111 24F 212 250 213 275 235 270 230 271 231 272 232 273 233 237 23F 23B 297 (A) ← (W5) (W5) ← (A) (A) ← (W6) (W6) ← (A) (B) ← (TPS 7–TPS 4) (A) ← (TPS3–TPS 0) (RPS 7–RPS 4) ← (B) (TPS7–TPS 4) ← (B) (RPS 3–RPS 0) ← (A) (TPS3–TPS 0) ← (A) (B) ← (T17–T14) (A) ← (T13–T10) (R17–R1 4) ← (B) (T17–T14) ← (B) (R13–R1 0) ← (A) (T13–T10) ← (A) (B) ← (T27–T24) (A) ← (T23–T20) (R27–R2 4) ← (B) (T27–T24) ← (B) (R23–R2 0) ← (A) (T23–T20) ← (A) (B) ← (T37–T34) (A) ← (T33–T30) (R37–R3 4) ← (B) (T37–T34) ← (B) (R33–R3 0) ← (A) (T33–T30) ← (A) (B) ← (T47–T44) (A) ← (T43–T40) (R4L7–R4L 4) ← (B) (T47–T44) ← (B) (R4L3–R4L 0) ← (A) (T43–T40) ← (A) (R4H 7–R4H 4) ← (B) (R4H 3–R4H 0) ← (A) (R17–R1 4) ← (B) (R13–R1 0) ← (A) (R37–R3 4) ← (B) (R33–R3 0) ← (A) (T47–T40) ← (R4L7–R4L 0) TAW5 TW5A TAW6 TW6A TABPS TPSAB TAB1 T1AB TAB2 T2AB TAB3 T3AB TAB4 T4AB T4HAB TR1AB TR3AB T4R4L Timer operation

Skip condition Datailed description Carry flag CY Rev.3.01 2005.06.15 page 140 of 160 REJ03B0007-0301 Transfers the contents of timer control register W5 to register A. Transfers the contents of register A to timer control register W5. Transfers the contents of timer control register W6 to register A. Transfers the contents of register A to timer control register W6. Transfers the high-order 4 bits of prescaler to register B, and transfers the low-order 4 bits of prescaler to register A. Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS, and transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS. Transfers the high-order 4 bits of timer 1 to register B, and transfers the low-order 4 bits of timer 1 to regis- ter A. Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1, and transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1. Transfers the high-order 4 bits of timer 2 to register B, and transfers the low-order 4 bits of timer 2 to regis- ter A. Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2, and transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2. Transfers the high-order 4 bits of timer 3 to register B, and transfers the low-order 4 bits of timer 3 to regis- ter A. Transfers the contents of register B to the high-order 4 bits of timer 3 and timer 3 reload register R3, and transfers the contents of register A to the low-order 4 bits of timer 3 and timer 3 reload register R3. Transfers the high-order 4 bits of timer 4 to register B, and transfers the low-order 4 bits of timer 4 to regis- ter A. Transfers the contents of register B to the high-order 4 bits of timer 4 and timer 4 reload register R4L, and transfers the contents of register A to the low-order 4 bits of timer 4 and timer 4 reload register R4L. Transfers the contents of register B to the high-order 4 bits of timer 4 reload register R4H, and transfers the contents of register A to the low-order 4 bits of timer 4 reload register R4H. Transfers the contents of register B to the high-order 4 bits of timer 1 reload register R1, and transfers the contents of register A to the low-order 4 bits of timer 1 reload register R1. Transfers the contents of register B to the high-order 4 bits of timer 3 reload register R3, and transfers the contents of register A to the low-order 4 bits of timer 3 reload register R3. Transfers the contents of timer 4 reload register R4L to timer 4.

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.3.01 2005.06.15 page 141 of 160 REJ03B0007-0301 1010000000 1010000001 1010000010 1010000011 1001100000 1000100000 1001100001 1000100001 1001100010 1000100010 1001100011 1000100011 1001100100 1000100100 1001100101 1000100101 1001100110 1000100110 0000010001 0000010100 0000010101 0000100100 0000101011 1001010111 1000101101 1001011110 1000101110 280 281 282 283 260 220 261 221 262 222 263 223 264 224 265 225 266 226 011 014 015 024 02B 257 22D 25E 22E SNZT1 SNZT2 SNZT3 SNZT4 IAP0 OP0A IAP1 OP1A IAP2 OP2A IAP3 OP3A IAP4 OP4A IAP5 OP5A IAP6 OP6A CLD RD SD SZD TAPU0 TPU0A TAPU1 TPU1A 2 = 0: (T1F) = 1 ? After skipping, (T1F) ← 0 V12 = 0: NOP V13 = 0: (T2F) = 1 ? After skipping, (T2F) ← 0 V13 = 0: NOP V20 = 0: (T3F) = 1 ? After skipping, (T3F) ← 0 V20 = 0: NOP V21 = 0: (T4F) = 1 ? After skipping, (T4F) ← 0 V21 = 0: NOP (A) ← (P0) (P0) ← (A) (A) ← (P1) (P1) ← (A) (A) ← (P4) (P4) ← (A) (A) ← (P5) (P5) ← (A) (A) ← (P6) (P6) ← (A) (D) ← 1 (D(Y)) ← 0 (Y) = 0 to 7 (D(Y)) ← 1 (Y) = 0 to 7 (D(Y)) = 0 ? (Y) = 0 to 7 (A) ← (PU0) (PU0) ← (A) (A) ← (PU1) (PU1) ← (A) Input/Output operation Timer operation

Skip condition Datailed description Carry flag CY Rev.3.01 2005.06.15 page 142 of 160 REJ03B0007-0301 Skips the next instruction when the contents of bit 2 (V12) of interrupt control register V1 is “0” and the con- tents of T1F flag is “1.” After skipping, clears (0) to T1F flag. Skips the next instruction when the contents of bit 3 (V13) of interrupt control register V1 is “0” and the con- tents of T2F flag is “1.” After skipping, clears (0) to T2F flag. Skips the next instruction when the contents of bit 0 (V20) of interrupt control register V2 is “0” and the con- tents of T3F flag is “1.” After skipping, clears (0) to T3F flag. Skips the next instruction when the contents of bit 1 (V21) of interrupt control register V2 is “0” and the con- tents of T4F flag is “1.” After skipping, clears (0) to T4F flag. Transfers the input of port P0 to register A. Outputs the contents of register A to port P0. Transfers the input of port P1 to register A. Outputs the contents of register A to port P1. Transfers the input of port P2 to register A. Outputs the contents of register A to port P2. Transfers the input of port P3 to register A. Outputs the contents of register A to port P3. Transfers the input of port P4 to register A. Outputs the contents of register A to port P4. Transfers the input of port P5 to register A. Outputs the contents of register A to port P5. Transfers the input of port P6 to register A. Outputs the contents of register A to port P6. Sets (1) to all port D. Clears (0) to a bit of port D specified by register Y. Sets (1) to a bit of port D specified by register Y . Skips the next instruction when a bit of port D specified by register Y is “0.” Executes the next instruction when a bit of port D specified by register Y is “1.” Transfers the contents of pull-up control register PU0 to register A. Transfers the contents of register A to pull-up control register PU0. Transfers the contents of pull-up control register PU1 to register A. Transfers the contents of register A to pull-up control register PU1. 2 = 0: (T1F) = 1 V13 = 0: (T2F) =1 V20 = 0: (T3F) = 1 V21 = 0: (T4F) =1 (D(Y)) = 0 However, (Y)=0 to 7

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.3.01 2005.06.15 page 143 of 160 REJ03B0007-0301 TAK0 TK0A TAK1 TK1A TAK2 TK2A TFR0A TFR1A TFR2A TFR3A TABSI TSIAB SST SNZSI TAJ1 TJ1A CMCK CRCK CYCK TRGA TAMR TMRA 256 21B 259 214 25A 215 228 229 22A 22B 278 238 29E 288 242 202 29A 29B 29D 209 252 216 1001010110 1000011011 1001011001 1000010100 1001011010 1000010101 1000101000 1000101001 1000101010 1000101011 1001111000 1000111000 1010011110 1010001000 1001000010 1000000010 1010011010 1010011011 1010011101 1000001001 1001010010 1000010110 Input/Output operation (A) ← (K0) (K0) ← (A) (A) ← (K1) (K1) ← (A) (A) ← (K2) (K2) ← (A) (FR0) ← (A) (FR1) ← (A) (FR2) ← (A) (FR3) ← (A) (B) ← (SI7–SI4) (A) ← (SI3–SI0) (SI7–SI4) ← (B) (SI3–SI0) ← (A) (SIOF) ← 0 Serial I/O starting V23=0: (SIOF)=1? After skipping, (SIOF) ← 0 V23 = 1: NOP (A) ← (J1) (J1) ← (A) Ceramic resonator selected RC oscillator selected Quartz-crystal oscillator selected (RG 0) ← (A0) (A) ← (MR) (MR) ← (A) MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Serial I/O operation Clock operation

Skip condition Datailed description Carry flag CY Rev.3.01 2005.06.15 page 144 of 160 REJ03B0007-0301 3 = 0: (SIOF) = 1 Transfers the contents of key-on wakeup control register K0 to register A. Transfers the contents of register A to key-on wakeup control register K0 . Transfers the contents of key-on wakeup control register K1 to register A. Transfers the contents of register A to key-on wakeup control register K1. Transfers the contents of key-on wakeup control register K2 to register A. Transfers the contents of register A to key-on wakeup control register K2. Transferts the contents of register A to port output format control register FR0. Transferts the contents of register A to port output format control register FR1. Transferts the contents of register A to port output format control register FR2. Transferts the contents of register A to port output format control register FR3. Transfers the high-order 4 bits of serial I/O register SI to register B, and transfers the low-order 4 bits of se- rial I/O register SI to register A. Transfers the contents of register B to the high-order 4 bits of serial I/O register SI, and transfers the con- tents of register A to the low-order 4 bits of serial I/O register SI. Clears (0) to SIOF flag and starts serial I/O. Skips the next instruction when the contents of bit 3 (V2 3) of interrupt control register V2 is “0” and contents of SIOF flag is “1.” After skipping, clears (0) to SIOF flag. Transfers the contents of serial I/O control register J1 to register A. Transfers the contents of register A to serial I/O control register J1. Selects the ceramic resonator for main clock f(X IN). Selects the RC oscillation circuit for main clock f(XIN). Selects the quartz-crystal oscillation circuit for main clock f(XIN). Transfers the contents of clock control regiser RG to register A. Transfers the contents of clock control regiser MR to register A. Transfers the contents of register A to clock control register MR.

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.3.01 2005.06.15 page 145 of 160 REJ03B0007-0301 279 249 239 29F 287 244 204 245 205 246 206 000 002 05B 003 2A0 29C 001 1001111001 1001001001 1000111001 1010011111 1010000111 1001000100 1000000100 1001000101 1000000101 1001000110 1000000110 0000000000 0000000010 0001011011 0000000011 1010100000 1010011100 0000000001 A/D conversion operation Other operation MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) TABAD TALA TADAB ADST SNZAD TAQ1 TQ1A TAQ2 TQ2A TAQ3 TQ3A NOP POF EPOF SNZP WRST DWDT SRST 3 = 0: (B) ← (AD9–AD 6) (A) ← (AD5–AD 2) Q1 3 = 1: (B) ← (AD7–AD 4) (A) ← (AD3–AD 0) (A3, A2) ← (AD1, AD0) (A1, A0) ← 0 (AD7–AD 4) ← (B) (AD3–AD 0) ← (A) (ADF) ← 0 A/D conversion starting After skipping, (ADF) ← 0 V22 = 1: NOP (A) ← (Q1) (Q1) ← (A) (A) ← (Q2) (Q2) ← (A) (A) ← (Q3) (Q3) ← (A) (PC) ← (PC) + 1 Transition to RAM back-up mode POF instruction valid (P) = 1 ? (WDF1) = 1 ? After skipping, (WDF1) ← 0 Stop of watchdog timer function enabled System reset occurrence

Skip condition Datailed description Carry flag CY Rev.3.01 2005.06.15 page 146 of 160 REJ03B0007-0301 V22 = 0: (ADF) = 1 (P) = 1 (WDF1) = 1 In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9–AD 6) of register AD to register B, and the middle-order 4 bits (AD5–AD 2) of register AD to register A. In the comparator mode (Q13 = 1), transfers the middle-order 4 bits (AD7–AD 4) of register AD to register B, and the low-order 4 bits (AD3–AD 0) of register AD to register A. (Q13: bit 3 of A/D control register Q1) Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (AD3, AD2) of register A. In the comparator mode (Q13 = 1), transfers the contents of register B to the high-order 4 bits (AD7–AD 4) of comparator register, and the contents of register A to the low-order 4 bits (AD3–AD 0) of comparator register. (Q13 = bit 3 of A/D control register Q1) Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q13 = 0) or the comparator operation at the comparator mode (Q13 = 1) is started. (Q13 = bit 3 of A/D control register Q1) When V2 2 = 0 : Skips the next instruction when A/D conversion completion flag ADF is “1.” After skipping, clears (0) to the ADF flag. When the ADF flag is “0,” executes the next instruction. (V22: bit 2 of interrupt con- trol register V2) Transfers the contents of A/D control register Q1 to register A. Transfers the contents of register A to A/D control register Q1. Transfers the contents of A/D control register Q2 to register A. Transfers the contents of register A to A/D control register Q2. Transfers the contents of A/D control register Q3 to register A. Transfers the contents of register A to A/D control register Q3. No operation; Adds 1 to program counter value, and others remain unchanged. Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruction. Makes the immediate after POF instruction valid by executing the EPOF instruction. Skips the next instruction when the P flag is “1”. After skipping, the P flag remains unchanged. Skips the next instruction when watchdog timer flag WDF1 is “1.” After skipping, clears (0) to the WDF1 flag. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction. Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction. System reset occurs.

Rev.3.01 2005.06.15 page 147 of 160 REJ03B0007-0301 INSTRUCTION CODE TABLE D 3–D 0 Hex. notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A B C D E F D 9–D 4 NOP SRST POF SNZP DI EI RC SC AM AMC TYA TBA 000001 BLA CLD INY RD SD DEY AND OR TEAB CMA RAR TAB TAY 000010 SZB SZB SZB SZB SZD SEAn SEAM TDA TABE SZC 000011 BMLA SNZ0 SNZ1 SNZI0 SNZI1 TV2A TV1A 000100 RT RTS RTI LZ LZ LZ LZ RB RB RB RB 000101 TASP TAD TAX TAZ TAV1 TAV2 EPOF SB SB SB SB 000110 A A A A A A A A A A A A A A A A 000111 LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA 001000 TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP 001001 TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP 001010 TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP 001011001100 001101 001110 001111 BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM 010000 010111 011000 011111 18–1F B B B B B B B B B B B B B B B B BL BML BLA BMLA SEA SZD The second word 1p paaa aaaa 1p paaa aaaa 1p pp00 pppp 1p pp00 pppp 00 0111 nnnn 00 0010 1011

• * cannot be used in the M34519M6. 10–17 000000 The above table shows the relationship between machine language codes and machine language instructions. D3–D 0 show the low-order 4 bits of the machine language code, and D9–D 4 show the high-order 6 bits of the machine language code. The hexadecimal representa- tion of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below. TABP 48* TABP 49* TABP 50* TABP 51* TABP 52* TABP 53* TABP 54* TABP 55* TABP 56* TABP 57* TABP 58* TABP 59* TABP 60* TABP 61* TABP 62* TABP 63* INSTRUCTION CODE TABLE

Rev.3.01 2005.06.15 page 148 of 160 REJ03B0007-0301 INSTRUCTION CODE TABLE (continued) TJ1A TQ1A TQ2A TQ3A TRGA TW1A TW2A TW3A TW4A TW5A TW6A TK1A TK2A TMRA TI1A TI2A TK0A T1AB T2AB T3AB T4AB TPSAB T4HAB TSIAB TADAB TR3AB TR1AB TAJ1 TAQ1 TAQ2 TAQ3 TALA TAW1 TAW2 TAW3 TAW4 TAW5 TAW6 TAMR TAI1 TAI2 TAK0 TAPU0 TAK1 TAK2 TAPU1 IAP0 IAP1 IAP2 IAP3 IAP4 IAP5 IAP6 TAB1 TAB2 TAB3 TAB4 TABPS TABSI TABAD SNZT1 SNZT2 SNZT3 SNZT4 SNZAD SNZSI T4R4L CMCK CRCK DWDT CYCK SST ADST WRST TPAA TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA BL BML BLA BMLA SEA SZD The second word 1p paaa aaaa 1p paaa aaaa 1p pp00 pppp 1p pp00 pppp 00 0111 nnnn 00 0010 1011 OP0A OP1A OP2A OP3A OP4A OP5A OP6A TFR0A TFR1A TFR2A TFR3A TPU0A TPU1A D 3–D 0 Hex. notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A B C D E F D 9–D 4 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 111111 30–3F 100000 The above table shows the relationship between machine language codes and machine language instructions. D3–D 0 show the low- order 4 bits of the machine language code, and D9–D 4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below. INSTRUCTION CODE TABLE

Rev.3.01 2005.06.15 page 149 of 160 REJ03B0007-0301 Parameter Supply voltage Input voltage P0, P1, P2, P3, P4, P5, P6, D 0–D 7, RESET, XIN, VDCE Input voltage SCK , SIN, CNTR0, CNTR1, INT0, INT1 Input voltage AIN0–AIN7 Output voltage P0, P1, P2, P3, P4, P5, P6, D0–D 7, RESET Output voltage SCK , SOUT , CNTR0, CNTR1 Output voltage XOUT Power dissipation Operating temperature range Storage temperature range Conditions Output transistors in cut-off state Output transistors in cut-off state Ta = 25 °C 42P2R-A Symbol V DD VI VI VI VO VO VO Pd Topr Tstg Unit V V V V V V V mW Ratings –0.3 to 6.5 –0.3 to VDD +0.3 –0.3 to VDD +0.3 –0.3 to VDD +0.3 –0.3 to VDD +0.3 –0.3 to VDD +0.3 –0.3 to VDD +0.3 300 –20 to 85 –40 to 125 Absolute maximum ratings

Rev.3.01 2005.06.15 page 150 of 160 REJ03B0007-0301 IOH (peak) IOH (avg) IOL (peak) IOL (peak) IOL (peak) IOL (peak) IOL (avg) IOL (avg) IOL (avg) IOL (avg) ΣIOH (avg) ΣIOL (avg) Parameter Supply voltage (when ceramic resonator/on-chip oscillator is used) Supply voltage (when RC oscillation is used) Supply voltage (when quartz-crystal oscillator is used) RAM back-up voltage Supply voltage “H ” level input voltage “H ” level input voltage “H ” level input voltage “L” level input voltage “L” level input voltage “L” level input voltage “H ” level peak output current “H ” level average output current (Note) “L” level peak output current “L” level peak output current “L” level peak output current “L” level peak output current “L” level average output current (Note) “L” level average output current (Note) “L” level average output current (Note) “L” level average output current (Note) “H ” level total average current “L” level total average current Note: The average output current is the average value during 100 ms. UnitConditions Mask ROM version One Time PROM version f(STCK) ≤ 4.4 MHz Mask ROM version One Time PROM version Mask ROM version One Time PROM version P0, P1, P2, P3, P4, P5, P6, D 0–D 7, VDCE, XIN RESET SCK , SIN, CNTR0, CNTR1, INT0, INT1 P0, P1, P2, P3, P4, P5, P6, D0–D 7, VDCE, XIN RESET SCK , SIN, CNTR0, CNTR1, INT0, INT1 P0, P1, P5, D0–D 7 CNTR0, CNTR1 P0, P1, P5, D0–D 7 CNTR0, CNTR1 P0, P1, P2, P4, P5, P6 SCK , SOUT P3, RESET D 0–D 5 D 6, D7 CNTR0, CNTR1 P0, P1, P2, P4, P5, P6 S CK , SOUT P3, RESET D 0–D 5 D 6, D7 CNTR0, CNTR1 P5, D0–D 7, CNTR0, CNTR1 P0, P1 P2, P5, D0–D 7, RESET , CNTR0, CNTR1 P0, P1, P3, P4, P6 Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 V DD VDD VDD 0.2VDD 0.3VDD 0.15VDD –20 –10 –10 –60 –60 Limits Min. 4.0 2.7 2.0 1.8 4.0 2.7 2.5 2.7 2.0 2.5 1.6 2.0 0.8V DD 0.85VDD 0.85VDD Typ. f(STCK) ≤ 6 MHz f(STCK) ≤ 4.4 MHz f(STCK) ≤ 2.2 MHz f(STCK) ≤ 1.1 MHz f(STCK) ≤ 6 MHz f(STCK) ≤ 4.4 MHz f(STCK) ≤ 2.2 MHz f(XIN) ≤ 50 kHz f(XIN) ≤ 50 kHz at RAM back-up mode at RAM back-up mode VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V V V V V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA Recommended operating conditions 1 (Mask ROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted)

Rev.3.01 2005.06.15 page 151 of 160 REJ03B0007-0301 f(XIN) f(XIN) f(XIN) Oscillation frequency (with a ceramic resonator) Oscillation frequency (at RC oscillation) (Note) Oscillation frequency (with a ceramic resonator selected, external clock input) Conditions MHz MHz MHz Max. 6.0 4.4 2.2 1.1 6.0 4.4 2.2 6.0 4.4 6.0 4.4 2.2 6.0 4.4 6.0 4.4 4.8 3.2 1.6 0.8 4.8 3.2 1.6 4.8 3.2 4.8 3.2 1.6 4.8 3.2 4.8 Limits Mask ROM version One Time PROM version VDD = 2.7 to 5.5 V Mask ROM version One Time PROM version Min. Typ. ParameterSymbol Unit Note: The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits. <System clock (STCK) operating condition map> VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.5 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.5 to 5.5 V VDD = 2.5 to 5.5 V VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.5 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.5 to 5.5 V VDD = 2.5 to 5.5 V Through mode Frequency/2 mode Frequency/4, 8 mode Through mode Frequency/2 mode Frequency/4, 8 mode Through mode Frequency/2 mode Frequency/4, 8 mode Through mode Frequency/2 mode Frequency/4, 8 mode 4.4 (2.5) 2.7 41.8 5.5 VDD [V] 2.2 1.1 f(STCK) [MHz] 3.2 4.8 (2.5) 2.7 41.8 5.5 VDD 1.6 0.8 When external clock is usedWhen RC oscillation is usedWhen ceramic resonance is used f(STCK) [MHz] 4.4 2.7 5.5 VDD [V] f(STCK) [MHz] ( ): One Time PROM version Recommended operating operation Recommended operating operation Recommended operating operation Recommended operating conditions 2 (Mask ROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted)

Rev.3.01 2005.06.15 page 152 of 160 REJ03B0007-0301 Conditions LimitsParameterSymbol Unit Mask ROM version V DD = 2.0 to 5.5 V One Time PROM version V DD = 2.5 to 5.5 V CNTR0, CNTR1 CNTR0, CNTR1 SCK SCK Mask ROM version V DD = 0 → 1.8 V One Time PROM version V DD = 0 → 2.5 V Oscillation frequency (with a quartz-crystal oscillator) Timer external input frequency Timer external input period (“H ” and “L” pulse width) Serial I/O external input frequency Serial I/O external input frequency (“H ” and “L“ pulse width) Power-on reset circuit valid supply voltage rising time f(X IN) f(CNTR) tw(CNTR) f(SCK ) tw(SCK ) TPON kHz Hz s Hz s µs f(STCK)/6 f(STCK)/6 100 100 3/f(STCK) 3/f(STCK) Typ. Max.Min. Recommended operating conditions 3 (Mask ROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted)

Rev.3.01 2005.06.15 page 153 of 160 REJ03B0007-0301 VOH VOL VOL VOL VOL IIH IIL R PU VT+ – VT– VT+ – VT– f(RING) ∆ f(XIN) “H ” level output voltage P0, P1, P5, D0–D 7, CNTR0, CNTR1 “L” level output voltage P0, P1, P2, P4, P5, P6 S CK , SOUT “L” level output voltage P3, RESET “L” level output voltage D 0–D 5 “L” level output voltage D 6, D7, CNTR0, CNTR1 “H ” level input current P0, P1, P2, P3, P4, P5, P6, D 0–D 7, VDCE, RESET, SCK , SIN, CNTR0, CNTR1, INT0, INT1 “L” level input current P0, P1, P2, P3, P4, P5, P6, D 0–D 7, VDCE, SCK , SIN, CNTR0, CNTR1, INT0, INT1 Pull-up resistor value P0, P1, RESET Hysteresis S CK , SIN, CNTR0, CNTR1, INT0, INT1 Hysteresis RESET On-chip oscillator clock frequency Frequency error (with RC oscillation, error of external R, C not included ) (Note) V V V V V µA µA kΩ V V kHz Test conditions VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VI = VDD Ports P4, P6 selected VI = 0 V P0, P1 No pull-up Ports P4, P6 selected V I = 0 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V Mask ROM version V DD = 1.8 V VDD = 5 V ± 10 %, Ta = 25 °C VDD = 3 V ± 10 %, Ta = 25 °C Limits Max. 0.9 0.9 0.6 0.9 0.9 0.9 1.4 0.9 0.9 0.9 125 250 700 400 200 ±17 ±17 IOH = –10 mA IOH = –3 mA IOH = –5 mA IOH = –1 mA IOL = 12 mA IOL = 4 mA IOL = 6 mA IOL = 2 mA IOL = 5 mA IOL = 1 mA IOL = 2 mA IOL = 15 mA IOL = 5 mA IOL = 9 mA IOL = 3 mA IOL = 30 mA IOL = 10 mA IOL = 15 mA IOL = 5 mA VDD = 5 V VDD = 3 V Min. 4.1 2.1 2.4 200 100 Typ. Symbol Parameter Unit 120 0.2 0.2 0.4 500 250 120 Note: When RC oscillation is used, use the external 30 pF or 33 pF capacitor (C). Electrical characteristics 1 (Mask ROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted)

Rev.3.01 2005.06.15 page 154 of 160 REJ03B0007-0301 IDD Supply currentat active mode (with a ceramic resonator, on-chip oscillator stop) at active mode (with a quartz-crystal oscillator, on-chip oscillator stop) at active mode (with an on-chip oscillator, f(X IN) stop) at RAM back-up mode (POF instruction execution) mA mA mA µA µA µA µA µA Test conditions VDD = 5 V f(XIN) = 6 MHz VDD = 5 V f(XIN) = 4 MHz VDD = 3 V f(XIN) = 4 MHz VDD = 5 V f(XIN) = 32 kHz VDD = 3 V f(XIN) = 32 kHz VDD = 5 V VDD = 3 V Ta = 25 °C VDD = 5 V VDD = 3 V Limits Max. 2.8 3.2 4.0 5.6 2.2 2.4 3.0 4.0 0.8 1.0 1.2 1.6 110 120 130 140 100 140 200 300 Min. Typ. 1.4 1.6 2.0 2.8 1.1 1.2 1.5 2.0 0.4 0.5 0.6 0.8 100 150 0.1 Symbol Parameter Unit f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(RING)/8 f(STCK) = f(RING)/4 f(STCK) = f(RING)/2 f(STCK) = f(RING) f(STCK) = f(RING)/8 f(STCK) = f(RING)/4 f(STCK) = f(RING)/2 f(STCK) = f(RING) Electrical characteristics 2 (Mask ROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted)

Rev.3.01 2005.06.15 page 155 of 160 REJ03B0007-0301 Symbol VDD VIA f(ADCK) Parameter Supply voltage Analog input voltage A/D conversion clock frequency (Note) Conditions Unit V V kHz Mask ROM version One Time PROM version Mask ROM version One Time PROM version Min. 2.0 3.0 0.8 0.8 0.8 0.8 0.8 0.8 Typ. Max. 5.5 5.5 VDD 334 245 3.9 1.8 334 123 Limits VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.2 to 5.5 V VDD = 2.0 to 5.5 V VDD = 4.0 to 5.5 V VDD = 3.0 to 5.5 V Note: Definition of A/D conversion clock (ADCK) <Operating condition map of A/D conversion clock (ADCK) > 334 245 (123) 2.2 ( ): One Time PROM version 2.7 (3.0) 42 5.5 VDD [V] 3.9 1.8 0.8 f(ADCK) [kHz] Recommended operating operation Instruction clock (INSTCK) On-chip oscillator clock(RING) A/D conversion clock (ADCK) Division circuit System clock (STCK) Instruction clock (INSTCK) Multi- plexer (CMCK, CRCK, CYCK) MR 0 MR 3, MR2 On-chip oscillator XIN Ceramic resonance RC oscillation Internal clock generating circuit (divided by 3) Quartz-crystal oscillation On-chip oscillator clock (RING) Q3 1, Q30 Q3 2 Divided by 2 Divided by 4 Divided by 8 Division circuit Divided by 12 Divided by 24 Divided by 48 Divided by 6 A/D converter recommended operating conditions (Comparator mode included, Ta = –20 °C to 85 °C, unless otherwise noted)

Rev.3.01 2005.06.15 page 156 of 160 REJ03B0007-0301 A/D converter characteristics (Ta = –20 °C to 85 °C, unless otherwise noted) Symbol V0T VFST IADD TCONV Parameter Resolution Linearity error Differential non-linearity error Zero transition voltage Full-scale transition voltage Absolute accuracy (Quantization error excluded) A/D operating current (Note 1) A/D conversion time Comparator resolution Comparator error (Note 2) Comparator comparison time Test conditions Unit 2.7 (3.0) V ≤ VDD ≤ 5.5 V((): One Time PROM version) Mask ROM version 2.2 V ≤ VDD < 2.7 V 2.2 (3.0) V ≤ VDD ≤ 5.5 V ((): One Time PROM version) Mask ROM version One Time PROM version Mask ROM version One Time PROM version Mask ROM version VDD = 5 V VDD = 3 V f(XIN) = 6 MHz f(STCK) = f(XIN) (XIN through mode) ADCK=INSTCK/6 Mask ROM version One Time PROM version f(XIN) = 6 MHz f(STCK) = f(XIN) (XIN through mode) ADCK=INSTCK/6 Min. 5105 3064.5 2552.5 5100 3065 Typ. 7.5 7.5 5115 3072 2560 5115 3075 150 Max. ±0.9 5125 3079.5 2567.5 5130 3085 450 225 ±20 ±15 ±15 ±30 ±23 Limits Notes 1: When the A/D converter is used, IADD is added to IDD (supply current). 2: As for the error from the ideal value in the comparator mode, when the contents of the comparator register is n, the logic value of the comparison voltage Vref which is generated by the built-in D/A converter can be obtained by the following formula. Logic value of comparison voltage Vref Vref = ✕ n n = Value of register AD (n = 0 to 255) VDD 256 bits LSB LSB mV mV LSB µA µs bits mV µs VDD = 5.12 V VDD = 3.072 V VDD = 2.56 V VDD = 5.12 V VDD = 3.072 V VDD = 5.12 V VDD = 3.072 V VDD = 2.56 V VDD = 5.12 V VDD = 3.072 V 2.0 V ≤ VDD < 2.2 V VDD = 5.12 V VDD = 3.072 V VDD = 2.56 V VDD = 5.12 V VDD = 3.072 V

Rev.3.01 2005.06.15 page 157 of 160 REJ03B0007-0301 Test conditions Ta = 25 °C Ta = 25 °C VDD = 5 V VDD = 3 V VDD → (VRST– – 0.1 V) (Note 4) Parameter Detection voltage (reset occurs) (Note 1) Detection voltage (reset release) (Note 2) Detection voltage hysteresis Operation current (Note 3) Detection time Symbol V RST – VRST+ VRST+ – VRST – IRST TRST Limits UnitMin. 3.3 2.7 2.6 3.5 2.9 2.8 Typ. 3.5 3.7 0.2 0.2 Max. 3.7 4.2 4.2 3.9 4.4 4.4 100 1.2 V V V µA ms Notes 1: The detected voltage (VRST –) is defined as the voltage when reset occurs when the supply voltage (VDD ) is falling. 2: The detected voltage (VRST+ ) is defined as the voltage when reset is released when the supply voltage (VDD ) is rising from reset occurs. 3: When the voltage drop detection circuit is used (VDCE pin = “H ”), IRST is added to IDD (power current). 4: The detection time (TRST ) is defined as the time until reset occurs when the supply voltage (VDD ) is falling to [VRST – – 0.1 V]. STCK Parameter Pin (signal) name Machine cycle Mi Mi+1 D 0–D 7 System clock Port D output Port D input Ports P0, P1, P2, P3, P4, P5, P6 output Ports P0, P1, P2, P3, P4, P5, P6 input D 0–D 7 INT0, INT1Interrupt input P00–P03 P10–P13 P00–P03 P10–P13 P20–P23 P30–P33 P20–P23 P30–P33 P40–P43 P40–P43 P50–P53 P60–P63 P50–P53 P60–P63 Basic timing diagram Voltage drop detection circuit characteristics (Ta = –20 °C to 85 °C, unless otherwise noted)

Rev.3.01 2005.06.15 page 158 of 160 REJ03B0007-0301 Table 23 Product of built-in PROM version PROM size (✕ 10 bits) 8192 words RAM size (✕ 4 bits) 384 wordsM34519E8FP One Time PROM [shipped in blank]42P2R-A BUILT-IN PROM VERSION In addition to the mask ROM versions, the 4519 Group has the One Time PROM versions whose PROMs can only be written to and not be erased. The built-in PROM version has functions similar to those of the mask ROM versions, but it has PROM mode that enables writing to built-in PROM. Table 23 shows the product of built-in PROM version. Figure 75 shows the pin configurations of built-in PROM versions. The One Time PROM version has pin-compatibility with the mask ROM version. ROM typePackagePart number Fig. 75 Pin configuration of built-in PROM version PIN CONFIGURATION (TOP VIEW) M34519E8FP8 P12 P11 P10 P03 P02 P01 P00 P43/AIN7 P42/AIN6 P41/AIN5 P40/AIN4 P63/AIN3 P62/AIN2 P61/AIN1 P60/AIN0 P33 P32 P31/INT1 P30/INT0 VDCE V DD P13 D 0 D 1 D 2 D 3 D 4 D 5 D 6/CNTR 0 D 7/CNTR 1 P50 P51 P52 P53 P20/SCK P21/SOUT P22/SIN RESET CNV SS XOUT XIN VSS

Rev.3.01 2005.06.15 page 159 of 160 REJ03B0007-0301 (1) PROM mode The built-in PROM version has a PROM mode in addition to a nor- mal operation mode. The PROM mode is used to write to and read from the built-in PROM. In the PROM mode, the programming adapter can be used with a general-purpose PROM programmer to write to or read from the built-in PROM as if it were M5M27C256K. Programming adapter is listed in Table 24. Contact addresses at the end of this data sheet for the appropriate PROM programmer.

• Writing and reading of built-in PROM Programming voltage is 12.5 V. Write the program in the PROM of the built-in PROM version as shown in Figure 76. (2) Notes on handling ➀ A high-voltage is used for writing. Take care that overvoltage is not applied. Take care especially at turning on the power. ➁ For the One Time PROM version shipped in blank, Renesas Technology Corp. does not perform PROM writing test and screening in the assembly process and following processes. In order to improve reliability after writing, performing writing and test according to the flow shown in Figure 77 before using is rec- ommended (Products shipped in blank: PROM contents is not written in factory when shipped). (3) Electric Characteristic Differences Between Mask ROM and One TIme PROM Version MCU There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between Mask ROM and One Time PROM version MCUs due to the difference in the manufactur- ing processes. When manufacturing an application system with the One Time PROM version and then switching to use of the Mask ROM ver- sion, please perform sufficient evaluations for the commercial samples of the Mask ROM version. Fig. 76 PROM memory map Fig. 77 Flow of writing and test of the product shipped in blank Microcomputer M34519E8FP Name of Programming Adapter PCA7441 Table 24 Programming adapter Address 000016

3 F F F1

H i g h - o r d e r 5 b i t s 1 11 D 4 D 3 D 2 D 1 D 0 L o w - o r d e r 5 b i t s 4 0 0 01

1 F F F1

Writing with PROM programmer Screening (Leave at 150 °C for 40 hours) (Note) Verify test with PROM programmer F u n c t i o n t e s t i n t a r g e t d e v i c e S i n c e t h e s c r e e n i n g t e m p e r a t u r e i s h i g h e r t h a n s t o r a g e t e m p e r a t u r e n e v e r e x p o s e t h e m i c r o c o m p u t e r t o C e x c e e d i n g h o u r s Note:

Rev.3.01 2005.06.15 page 160 of 160 REJ03B0007-0301 SSOP42-P-450-0.80 Weight(g) JEDEC Code 0.63 Alloy 42/Cu Alloy 42P2R-A Plastic 42pin 450mil SSOP Symbol Min Nom Max A b c D E L y Dimension in Millimeters H E .350 .050 .130 .317 .28 .6311 .30 .271 .02 .40 .150 .517 .48 .80 .9311 .50 .7651 .4311 .42 .50 .20 .717 .68 .2312 .70 .150 b2 –. 5 0– 0° –1 0 ° e 42 22 211 H E E D e y F A A2 A1 L c e b2 Recommended Mount Pad Detail F z Z1 Detail G –Z1 0.75 0.9 z b G Recommended

REVISION HISTORY

Rev. Date Description Page Summary (1/1)

4519 Group Data Sheet

1.00 Jan. 14, 2003 2.00 Apr. 15, 2003 3.00 Jul. 27, 2004 First edition issued Some values of the following table are revised. RECOMMENDED OPERATING CONDITIONS 1;

• Supply voltage (when quartz-crystal oscillator is used)
• RAM back voltage RECOMMENDED OPERATING CONDITIONS 3;
• Oscillation frequency (with a quartz-crystal oscillator) A/D CONVERTER RECOMMENDED OPERATING CONDITIONS;
• Supply voltage
• A/D conversion clock frequency A/D CONVERTER CHARACTERISTCS;
• Linearity error
• Differential non-linearity error
• Zero transition voltage
• Full-scale transition voltage
• Comparator error VOLTAGE DROP DETECTION CIRCUIT;
• Detection voltage (reset occurs)
• Detection voltage (reset release) Words standardized: On-chip oscillator, A/D converter PERFORMANCE OVERVIEW: Power dissipation revised. PIN DESCRIPTION: Description of RESET pin revised. Port block diagram (8): Period measurement circuit added. Fig.17: Period measurement circuit added. Fig.20 revised. Fig.23 revised. Fig.26: Note added. Table 10 W1 3: (Note 2) added, W23: (Note 2) eliminated. (12): Some description added. (14): Some description added. Some description added. Fig.33: “DI” instruction added. Table 11: Relative accuracy revised. Fig.46: SRST instruction added. 11 Timer 4: Some description added. Fig.64 revised. Fig.67 revised. Note on Power Source Voltage added. 3, I12: (Note 2) added. W1 3: (Note 2) added, and Note 2 added. SNZ0, SNZ1 revised. Fig.73 revised. 149 151 154 155 156 All pages 157 3.01 Jun.15, 2005All pages Delete the following: “PRELIMINARY ”. 41 •Prescaler, Timer 1, Timer 2 and Timer 3 count start timing and count time when operation starts, •Timer 4 count start timing and count time when operation starts added. 73 13 Prescaler, Timer 1, Timer 2 and Timer 3 count start timing and count time when operation starts, 14 Timer 4 count start timing and count time when opera- tion starts added.

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