4515B

CD4514BC FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

I Wide supply voltage range: 3.0V to 15V I High noise immunity: 0.45 VDD (typ.) I Low power TTL: fan out of 2 compatibility: driving 74L I Low quiescent power dissipation: 0.025 µW/package @ 5.0 VDC I Single supply operation I Input impedance = 1012Ω typically I Plug-in replacement for MC14514, MC14515 Ordering Code: Devices also available in T ape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Top View Order Number Package Number Package Diagram CD4514BCWM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide CD4514BCN N24A 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide CD4515BCWM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide CD4515BCN N24A 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide

www.fairchildsemi.com 2 CD4514BC  CD4515BC Truth Table Decode Truth Table (Strobe = 1) X = Don’t Care Logic Diagram Data Inputs Selected Output I n h i b i t D C B A C D 4 5 1 4 = Logic “1” CD4515 = Logic “0” 0 0 0 0 0 S 0 0 0 0 0 1 S 1 0 0 0 1 0 S 2 0 0 0 1 1 S 3 0 0 1 0 0 S 4 0 0 1 0 1 S 5 0 0 1 1 0 S 6 0 0 1 1 1 S 7 0 1 0 0 0 S 8 0 1 0 0 1 S 9 0 1 0 1 0 S 1 0 0 1 0 1 1 S 1 1 0 1 1 0 0 S 1 2 0 1 1 0 1 S 1 3 0 1 1 1 0 S 1 4 0 1 1 1 1 S 1 5

1 X X X X All Outputs

= 0, CD4514 All Outputs = 1, CD4515

3 www.fairchildsemi.com CD4514BC CD4515BC Absolute Maximum Ratings(Note 1) (Note 2) Recommended Operating Conditions (Note 2) Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Tempera- ture Range” they are not meant to imply that the devices should be oper- ated at these limits. The tables of “Recommended Operating Conditions” and “Electrical Characteristics” provide conditions for actual device opera- tion. Note 2: VSS = 0V unless otherwise specified. CD4514BC, CD4515BC Note 3: IOH and IOL are tested one output at a time. DC Supply Voltage (VDD ) −0.5V to +18V Input Voltage (VIN) −0.5V to VDD + 0.5V Storage Temperature Range (TS) −65°C to +150°C Power Dissipation (PD ) Dual-In-Line 700 mW Small Outline 500 mW Lead Temperature (T (Soldering, 10 seconds) 260 °C DC Supply Voltage (VDD ) 3V to 15V Input Voltage (VIN) 0V to V DD Operating Temperature Range (TA) CD4514BC, CD4515BC −40°C to +85°C Symbol Parameter Conditions −40°C +25°C +85°C Units Min Max Min Typ Max Min Max IDD Quiescent Device V DD = 5V, VIN = VDD or V SS 20 0.005 20 150 µA Current V DD = 10V, VIN = VDD or V SS 40 0.010 40 300 µA VDD = 15V, VIN = VDD or V SS 80 0.015 80 600 µA VOL LOW Level V IL = 0V, VIH = VDD , Output Voltage |I O | < 1 µA VDD = 5V 0.05 0 0.05 0.05 V VDD = 10V 0.05 0 0.05 0.05 V VDD = 15V 0.05 0 0.05 0.05 V VOH HIGH Level V IL = 0V, VIH = VDD , Output Voltage |I O | < 1 µA VDD = 5V 4.95 4.95 5.0 4.95 V VDD = 10V 9.95 9.95 10.0 9.95 V VDD = 15V 14.95 14.95 15.0 14.95 V VIL LOW Level |I O | < 1 µA VIH HIGH Level |I O | < 1 µA IIN Input Current V DD = 15V, VIN = 0V −0.3 −10−5 −0.3 −1.0 µA VDD = 15V, VIN = 15V 0.3 10 −5 0.3 1.0 µA

www.fairchildsemi.com 4 CD4514BC  CD4515BC All types CL = 50 pF, TA = 25°C, tr = tf = 20 ns unless otherwise specified Note 4: AC Parameters are guaranteed by DC correlated testing. Note 5: C PD determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics application note, AN-90. Note 6: Capacitance is guaranteed by periodic testing. Symbol Parameter Conditions Min Typ Max Units tTHL , tTLH Transition Times V DD = 5V 100 200 ns VDD = 10V 50 100 ns VDD = 15V 40 80 ns tPLH , tPHL Propagation Delay Times V DD = 5V 550 1100 ns VDD = 10V 225 450 ns VDD = 15V 150 300 ns tPLH , tPHL Inhibit Propagation V DD = 5V 400 800 ns Delay Times V DD = 10V 150 300 ns VDD = 15V 100 200 ns tSU Setup Time V DD = 5V 125 250 ns VDD = 10V 50 100 ns VDD = 15V 38 75 ns tWH Strobe Pulse Width V DD = 5V 175 350 ns VDD = 10V 50 100 ns VDD = 15V 38 75 ns CPD Power Dissipation Capacitance Per Package (Note 5) 150 pF CIN Input Capacitance Any Input (Note 6) 5 7.5 pF

5 www.fairchildsemi.com CD4514BC CD4515BC AC Test Circuit and Switching Time Waveforms FIGURE 1.

www.fairchildsemi.com 6 CD4514BC  CD4515BC

Applications

Two CD4512 8-channel data selectors are used here with the CD4514B 4-bit latch/decoder to effect a complex data routing system. A total of 16 inputs from data registers are selected and transferred via a 3-STATE data bus to a data distributor for rearrangement and entry into 16 output regis- ters. In this way sequential data can be re-routed or inter- mixed according to patterns determined by data select and distribution inputs. Data is placed into the routing scheme via the 8 inputs on both CD4512 data selectors. One register is assigned to each input. The signals on A0, A1 and A2 choose 1-of-8 inputs for transfer out to the 3-STATE data bus. A fourth signal, labelled Dis, disables one of the CD4512 selectors, assuring transfer of data from only one register. In addition to a choice of input registers, 1–16, the rate of transfer of the sequential information can also be varied. That is, if the CD4512 were addressed at a rate that is 8 times faster than the shift frequency of the input registers, the most significant bit (MSB) from each register could be selected for transfer to the data bus. Therefore, all of the most significant bits from all of the registers can be trans- ferred to the data bus before the next most significant bit is presented for transfer by the input registers. Information from the 3-STATE bus is redistributed by the CD4514B 4-bit latch/decoder. Using the 4-bit address, INA–IND, the information on the inhibit line can be trans- ferred to the addressed output line to the desired output registers, A–P. This distribution of data bits to the output registers can be made in many complex patterns. For example, all of the most significant bits from the input regis- ters can be routed into output register A, all of the next most significant bits into register B, etc. In this way horizon- tal, vertical, or other methods of data slicing can be imple- mented.

7 www.fairchildsemi.com CD4514BC CD4515BC Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B

www.fairchildsemi.com 8 CD4514BC  CD4515BC 4-Bit Latched/4-to-16 Line Decoders Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide Package Number N24A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com