4509

4509 RENESAS | Alldatasheet

Document overview

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Technical content

DESCRIPTION

The 4509 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with two 8-bit timers (each timer has two reload registers), interrupts, 10-bit A/D converter, Serial interface and oscillation circuit switch function.

FEATURES

(at 6 MHz oscillation frequency, in through-mode) (It depends on operation source clock, oscillation frequency and operating mode.) G Timers Part number M34509G4FP ( Note) M34509G4-XXXFP M34509G4HFP ( Note) M34509G4H-XXXFP ROM type QzROM QzROM QzROM QzROM Package PRSP0024GA-A PRSP0024GA-A PRSP0024GA-A PRSP0024GA-A RAM size (✕ 4 bits) 256 words 256 words 256 words 256 words ROM (PROM) size (✕ 10 bits) 4096 words 4096 words 4096 words 4096 words G A/D converter G Voltage drop detection circuit (only for H version) G Power-on reset circuit (only for H version) G Watchdog timer G Clock generating circuit (on-chip oscillator/ceramic resonator/RC oscillation) G LED drive directly enabled (port D) APPLICATION Electrical household appliance, consumer electronic products, office automation equipment, etc. Note: Shipped in blank. Rev.1.02 2006.12.22 page 1 of 140 REJ03B0147-0102

4509 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER REJ03B0147-0102 Rev.1.02 2006.12.22 PIN CONFIGURATION Pin configuration (top view) (4509 Group) VDD P10 P11/CNTR1 P12/CNTR0 P13/INT P03 VSS D 4 D 5 XIN XOUT CNV SS P21/AIN1 P20/AIN0 RESET D 1 D 0 P31/AIN3 P30/AIN2 Outline PRSP0024GA-A (24P2Q-A) M34509G4-XXXFPM34509G4FPM34509G4H-XXXFPM34509G4HFP P02/SCK P01/SOUT P00/SIN D 3/AIN5 D 2/AIN4

Rev.1.02 2006.12.22 page 2 of 140 REJ03B0147-0102 Block diagram (4509 Group) RAMROMMemory I/O port Internal peripheral functions Timer Timer 1 (8 bits)Timer 2 (8 bits) 256 words ✕ 4 bits 4096 words ✕ 10 bits

4500 SeriesCPU core

Register B (4 bits) Register A (4 bits)Register D (3 bits) Register E (8 bits) Stack register SK (8 levels) Interrupt stack register SDP (1level) ALU (4 bits) Watchdog timer (16 bits) (10 bits ✕ 6 ch) A/D converter Port P0 Port P1 Port P2 Port D Port P3 System clock generating circuit X IN OUT (Ceramic/RC) On-chip oscillator Voltage drop detection circuit (Note) Note: These circuits are equipped with only H version. (8 bits ✕ 1) Serial I/O Power-on reset circuit (Note)

Rev.1.02 2006.12.22 page 3 of 140 REJ03B0147-0102 PERFORMANCE OVERVIEW Function 134 135 0.5 µs (at 6 MHz oscillation frequency, in through mode) 4096 words ✕ 10 bits 256 words ✕ 4 bits Six independent I/O ports. Input is examined by skip decision. Ports D 2 and D 3 are equipped with a pull-up function and a key-on wakeup function. Both functions can be switched by software. Ports D 2 and D3 are also used as AIN4, and AIN5, respectively. 4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both functions and output structure can be switched by software. Ports P0 0, P01 and P02 are also used as SIN, SOUT and SCK , respectively. 4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both functions and output structure can be switched by software. Ports P1 1, P12 and P13 are also used as CNTR1, CNTR0 and INT, respectively. 2-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both functions and output structure can be switched by software. Ports P2 0 and P21 are also used as AIN0 and AIN1, respectively. 2-bit I/O port; The output structure can be switched by software. Ports P30 and P31 are also used as AIN2 and AIN3, respectively. Two independent I/O; CNTR1 and CNTR0 pins are also used as ports P11 and P12, respectively. 1-bit input; INT pin is also used as port P13. Three independent I/O; S IN, SOUT , and SCK are also used as ports P00, P01, and P02, respectively. Six independent input; AIN0–AIN5 are also used as P20, P21, P30, P31, D2 and D3, respectively. 8-bit programmable timer/event counter with two reload registers and PWM output function. 8-bit programmable timer/event counter with two reload registers and PWM output function. 16-bit timer (fixed dividing frequency) (for watchdog) 10-bit wide, This is equipped with an 8-bit comparator function. 6 channel (A IN0–AIN5 pins) 8-bit ✕ 1 Typ. 2.6 V (Ta = 25 °C) Typ. 2.7 V (Ta = 25 °C) Built-in type 5 (one for external, two for timer, one for A/D, one for Serial interface) 1 level 8 levels CMOS silicon gate 24-pin plastic molded SSOP (PRSP0024GA-A) –20 °C to 85 °C 1.8 V to 5.5 V (It depends on operation source clock, oscillation frequency and operating mode.) 2.2 mA (Ta = 25°C, VDD = 5.0 V, f(XIN) = 6.0 MHz, f(STCK) = f(XIN)/1) 0.1 µA (Ta = 25°C, VDD = 5.0 V, output transistors in the cut-off state) Parameter Number of basic instructions Minimum instruction execution time Memory sizes Input/Output ports Timers A/D converter Serial interface Voltage drop detection circuit (Note) Power-on reset circuit (Note) Interrupt Subroutine nesting Device structure Package Operating temperature range Supply voltage Power dissipation (typical value) Note: These circuits are equipped with only the H version. ROM RAM D 0–D 5 P00–P03 P10–P13 P20, P21 P30, P31 CNTR0, CNTR1 INT SIN, SOUT , SCK AIN0–AIN5 Timer 1 Timer 2 Watchdog timer function Analog input Reset occurrence Reset release Sources Nesting Active mode RAM back-up mode M34509G4 M34509G4H I/O I/O I/O I/O I/O Timer I/O Interrupt input Serial interface input/output Analog input

Rev.1.02 2006.12.22 page 4 of 140 REJ03B0147-0102 skip decision. I/O port P0 I/O port P1 I/O port P2 I/O port P3 Timer input/output Timer input/output Interrupt input Analog input Serial interface clock I/O Serial interface data output Serial interface data input Pin V DD VSS CNV SS RESET XIN D 0–D 5 P00–P03 P10–P13 P20, P21 P30, P31 CNTR0 CNTR1 INT A IN0–AIN5 SCK SOUT SIN Input/Output I/O Input I/O I/O I/O I/O I/O I/O I/O Input Input I/O Output Input Function Connected to a plus power supply. Connected to a 0 V power supply. Connect CNV SS to VSS and apply “L” (0V) to CNVSS certainly. An N-channel open-drain I/O pin for a system reset. When the SRST instruction, watchdog timer, the voltage drop detection circuit (only for H version) or the built-in power-on reset (only for H version) causes the system to be reset, the RESET pin out- puts “L” level. I/O pins of the main clock generating circuit. When using a ceramic resonator, connect it between pins XIN and XOUT . A feedback resistor is built-in between them. When using the RC oscillation, connect a resistor and a capacitor to XIN, and leave XOUT pin open. Each pin of port D has an independent 1-bit wide I/O function. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Ports D2 and D3 are equipped with a pull-up function and a key-on wakeup function. Both functions can be switched by software. Ports D 2 and D3 are also used as AIN4 and AIN5, respectively. Port P0 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Port P0 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Ports P0 0, P01 and P02 are also used as SIN, SOUT and SCK , respectively. Port P1 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Port P1 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Ports P1 1, P12 and P13 are also used as CNTR1, CNTR0 and INT, respectively. Port P2 serves as a 2-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Port P2 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Ports P20 and P21 are also used as AIN0 and AIN1, respectively. Port P3 serves as a 2-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Ports P30 and P31 are also used as AIN2 and AIN3, respectively. CNTR0 pin has the function to input the clock for the timer 2 event counter, and to output the PWM signal generated by timer 1. This pin is also used as port P1 CNTR1 pin has the function to input the clock for the timer 1 event counter, and to output the PWM signal generated by timer 2. This pin is also used as port P1 INT pin accepts external interrupts. It has the key-on wakeup function which can be switched by software. This pin is also used as port P1 A/D converter analog input pins. AIN0–AIN5 are also used as ports P20, P21, P30, P31, D2 and D3, respectively. Serial interface data transfer synchronous clock I/O pin. SCK pin is also used as port P02. Serial interface data output pin. SOUT pin is also used as port P01. Serial interface data input pin. SIN pin is also used as port P00. XOUT System clock output Output

Rev.1.02 2006.12.22 page 5 of 140 REJ03B0147-0102 PORT FUNCTION Port Port D Port P0 Port P1 Port P2 Port P3 I/O unit Control instructions SD, RD SZD, CLD OP0A IAP0 OP1A IAP1 OP2A IAP2 OP3A IAP3 Control registers FR3, C1 FR3, PU2 FR0, PU0 FR1, PU1 K1, L1, I1 W1, W2 W5, W6 FR2, PU2 Output structure N-channel open-drain/ CMOS N-channel open-drain/ CMOS N-channel open-drain/ CMOS N-channel open-drain/ CMOS N-channel open-drain/ CMOS Input Output I/O (6) I/O (4) I/O (4) I/O (2) I/O (2) RemarkPin D 0, D1, D4, D5 D 2/AIN4 D 3/AIN5 P00/SIN, P01/SOUT , P02/SCK , P03 P10, P11/CNTR1, P12/CNT0, P13/INT P20/AIN0 P21/AIN1 P30/AIN2 P31/AIN3 Programmable output structure selection function Programmable pull-up function Programmable key-on wakeup function Programmable output structure selection function Programmable pull-up function Programmable key-on wakeup function Programmable output structure selection function Programmable pull-up function Programmable key-on wakeup function Programmable output structure selection function Programmable pull-up function Programmable key-on wakeup function Programmable output structure selection function Programmable output structure selection functions Notes 1: Pins except above have just single function. 2: The input/output of P00 can be used even when SIN is used. Be careful when using inputs of both SIN and P00 since the input threshold value of SIN pin is different from that of port P00. 3: The input of P01 can be used even when SOUT is used. 4: The input of P02 can be used even when SCK is used. Be careful when using inputs of both SCK and P02 since the input threshold value of SCK pin is different from that of port P02. 5: The input of P11 can be used even when CNTR1 (output) is selected. The input/output of P11 can be used even when CNTR1 (input) is selected. Be careful when using inputs of both CNTR1 and P11 since the input thresh- old value of CNTR1 pin is different from that of port P11. 6: The input of P12 can be used even when CNTR0 (output) is selected. The input/output of P12 can be used even when CNTR0 (input) is selected. Be careful when using inputs of both CNTR0 and P12 since the input thresh- old value of CNTR0 pin is different from that of port P12. 7: The input/output of P13 can be used even when INT is used. Be careful when using inputs of both INT and P13 since the input threshold value of INT pin is different from that of port P13. 8: The input/output of P20, P21, P30, P31, D2, D3 can be used even when AIN0–AIN5 are used. Pin P00 P01 P02 P11 P12 P13 Multifunction SIN SOUT SCK CNTR1 CNTR0 INT MULTIFUNCTION Pin SIN SOUT SCK CNTR1 CNTR0 INT Multifunction P01 P02 P11 P12 P13 Pin P20 P21 P30 P31 D 2 D 3 Multifunction AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 Pin AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 Multifunction P20 P21 P30 P31 D 2 D 3

Rev.1.02 2006.12.22 page 6 of 140 REJ03B0147-0102 DEFINITION OF CLOCK AND CYCLE G Operation source clock The operation source clock is the source clock to operate this product. In this product, the following clocks are used.

• Clock (f(XIN)) by the external ceramic resonator
• Clock (f(XIN)) by the external RC oscillation
• Clock (f(XIN)) by the external input
• Clock (f(RING)) of the on-chip oscillator which is the internal os- cillator. G System clock The system clock is the basic clock for controlling this product. The system clock is selected by the register MR and register RG. G Instruction clock The instruction clock is a signal derived by dividing the system clock by 3. The one instruction clock cycle generates the one ma- chine cycle. G Machine cycle The machine cycle is the standard cycle required to execute the instruction. Register MR, RG System clock f(STCK) = f(RING)/8 f(STCK) = f(RING)/4 f(STCK) = f(RING)/2 f(STCK) = f(RING) f(STCK) = f(X IN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) Table Selection of system clock Note: The internal frequency divided by 8 is selected after system is released from reset. MR 2 MR Operation mode Internal frequency divided by 8 mode Internal frequency divided by 4 mode Internal frequency divided by 2 mode Internal frequency through mode High-speed frequency divided by 8 mode High-speed frequency divided by 4 mode High-speed frequency divided by 2 mode High-speed through mode MR 0 MR RG 0

Rev.1.02 2006.12.22 page 7 of 140 REJ03B0147-0102 Usage condition RC oscillation circuit is not selected. (CRCK instruction is not executed.) N-channel open-drain is selected for the output structure (FR30, FR31, C12, C13 = “0”). The key-on wakeup function is invalid (K22, K23 = “0”). N-channel open-drain is selected for the output structure (FR32, FR33 = “0”). Pull-up transistor is OFF (PU22, PU23 = “0”). The key-on wakeup function is invalid (K22, K23 = “0”). SIN pin is not selected (J11 = “0”). The key-on wakeup function is invalid (K00 = “0”). N-channel open-drain is selected for the output structure (FR00 = “0”). Pull-up transistor is OFF (PU00 = “0”). The key-on wakeup function is invalid (K00 = “0”). The key-on wakeup function is invalid (K01 = “0”). N-channel open-drain is selected for the output structure (FR01 = “0”). Pull-up transistor is OFF (PU01 = “0”). The key-on wakeup function is invalid (K01 = “0”). SCK pin is not selected (J11J10 = “00”). The key-on wakeup function is invalid (K02 = “0”). N-channel open-drain is selected for the output structure (FR02 = “0”). Pull-up transistor is OFF (PU02 = “0”). The key-on wakeup function is invalid (K02 = “0”). The key-on wakeup function is invalid (K03 = “0”). N-channel open-drain is selected for the output structure (FR03 = “0”). Pull-up transistor is OFF (PU03 = “0”). The key-on wakeup function is invalid (K03 = “0”). The key-on wakeup function is invalid (K10 = “0”). N-channel open-drain is selected for the output structure (FR10 = “0”). Pull-up transistor is OFF (PU10 = “0”). The key-on wakeup function is invalid (K10 = “0”). CNTR1 input is not selected for the timer 1 count source (W11, W10 ≠ “10”). The key-on wakeup function is invalid (K11 = “0”). N-channel open-drain is selected for the output structure (FR11 = “0”). Pull-up transistor is OFF (PU11 = “0”). The key-on wakeup function is invalid (K11 = “0”). CNTR0 input is not selected for the timer 2 count source (W21, W20 ≠ “10”). The key-on wakeup function is invalid (K12 = “0”). N-channel open-drain is selected for the output structure (FR12 = “0”). Pull-up transistor is OFF (PU12 = “0”). The key-on wakeup function is invalid (K12 = “0”). INT pin input is disabled (I13 = “0”). The key-on wakeup function is invalid (K13 = “0”). N-channel open-drain is selected for the output structure (FR13 = “0”). Pull-up transistor is OFF (PU13 = “0”). The key-on wakeup function is invalid (K13 = “0”). The key-on wakeup function is invalid (K20, K21 = “0”). N-channel open-drain is selected for the output structure (FR20, FR21 = “0”). Pull-up transistor is OFF (PU20, PU21 = “0”). The key-on wakeup function is invalid (K20, K21 = “0”). N-channel open-drain is selected for the output structure (C11, C10 = “0”). (Note when connecting to VSS or VDD ) G Connect the unused pins to VSS using the thickest wire at the shortest distance against noise. CONNECTIONS OF UNUSED PINS Connection Connect to VSS . Open. Open. Connect to V SS . Open. Connect to V SS . Open. Connect to VSS . Open. Connect to VSS . Open. Connect to VSS . Open. Connect to VSS . Open. Connect to VSS . Open. Connect to VSS . Open. Connect to VSS . Open. Connect to VSS . Open. Connect to VSS . Open. Connect to VSS . Pin XIN XOUT D 0, D1, D4, D5 D 2/AIN4, D3/AIN5 P00/SIN P01/SOUT P02/SCK P03 P10 P11/CNTR1 P12/CNTR0 P13/INT P20/AIN0, P21/AIN1 P30/AIN2, P31/AIN3

Rev.1.02 2006.12.22 page 8 of 140 REJ03B0147-0102 Port block diagram (1) This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: j represents bits 0 or 1. 4: k represents bits 2 or 3. Notes 1: D 0, D 1S RQ FR3 j Register Y Decoder SD instruction RD instruction Skip decision CLD instruction (Note 1) (Note 2) (Note 1) (Note 3) SZD instruction D 4, D 5S RQ C1 k Register Y Decoder SD instruction RD instruction Skip decision CLD instruction (Note 1) (Notes 2) (Note 1) SZD instruction (Note 4) (Note 2) D 2/AIN4, D 3/AIN5 (Note 1) Analog input Decoder (Note 1) PU2 k Pull-up transistor (Note 4) K2k “L” level detection circuitKey-on wakeup input (Note 4) Register Y Decoder SZD instruction Skip decision S RQ FR3 K SD instruction RD instruction CLD instruction (Note 4)

Rev.1.02 2006.12.22 page 9 of 140 REJ03B0147-0102 Port block diagram (2) (Note 2)P00/SIN N o t e S e r i a l i n t e r f a c e d a t a i n p u t N o t e P U K Level detection circuit Key-on wakeup input D TQ F R OP0A instruction R e g i s t e r A J I A P i n s t r u c t i o n (Note 2)P01/SOUT N o t e N o t e P U K Level detection circuit K e y - o n w a k e u p i n p u t D TQ FR0 1 O P 0 A i n s t r u c t i o n R e g i s t e r A IAP0 instruction J10 S e r i a l i n t e r f a c e d a t a o u t p u t N o t e )P02/SCK (Note 1) (Note 1) PU0 2 K02 L e v e l d e t e c t i o n c i r c u i t K e y o n w a k e u p i n p u t D TQ F R OP0A instruction Register A I A P i n s t r u c t i o n S y n c h r o n o u s c l o c k ( o u t p u t ) f o r s e r i a l i n t e r f a c e d a t a t r a n s f e r Synchronous clock (input) for serial interface data transfer J10 J11 T h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e o n t h e p o r t A p p l i e d p o t e n t i a l t o t h e s e p o r t s m u s t b e VD D o r l e s s N o t e s

Rev.1.02 2006.12.22 page 10 of 140 REJ03B0147-0102 Port block diagram (3) (Note 2)P03 (Note 1) (Note 1) PU0 3 K03 Level detection circuitKey-on wakeup input D TQ FR0 3 OP0A instruction Register A IAP0 instruction (Note 2)P10 (Note 1) (Note 1) PU1 0 K10 Edge detection circuit Key-on wakeup input D TQ FR1 0 OP1A instruction Register A IAP1 instruction L13 Level detection circuit L12 (Note 2)P11/CNTR1 (Note 1) (Note 1) PU1 1 K11 Key-on wakeup input D TQ FR1 1 OP1A instruction Register A IAP1 instruction L13 L12 Clock (input) for timer 1 event count W1 0 W1 1 W6 3 1PWMOD2 W6 0 Edge detection circuit Level detection circuit This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. Notes 1:

Rev.1.02 2006.12.22 page 11 of 140 REJ03B0147-0102 Port block diagram (4) P13/INT FR1 3 (Note 1) (Note 2) (Note 1) External 0 interrupt circuit (Notes 3, 4) External 0 interrupt Key-on wakeup input Timer 1 count start synchronous circuit input (Note 2)P12/CNTR0 (Note 1) (Note 1) PU1 2 K12 Level detection circuitKey-on wakeup input D TQ FR1 2 OP1A instruction Register A IAP1 instruction L13

1 Edge detection circuit

Clock (input) for timer 2 event count W2 0 W2 1 W5 3 1PWM1 W5 0 PU1 3 K13 Key-on wakeup input L13 L12 D TQOP1A instruction Register A IAP1 instruction Level detection circuit Edge detection circuit This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: As for details, refer to the external interrupt structure. 4: The threshold value of port input is different from that of external interrupt input. Notes 1:

Rev.1.02 2006.12.22 page 12 of 140 REJ03B0147-0102 D T Q (Note 2) PU2 j P20/AIN0, P21/AIN1 K2j Analog input Register A IAP2 instruction OP2A instruction (Note 1) Level detection circuitKey-on wakeup input Decoder This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: j represents 0 or 1. Notes 1: (Note 3) (Note 1) FR2 j Aj Aj D T Q (Notes 2)P30/AIN2, P31/AIN3 Analog input Register A IAP3 instruction OP3A instruction (Note 1) Decoder (Note 1) C1 j (Note 3) (Note 3) (Note 3) Port block diagram (5)

Rev.1.02 2006.12.22 page 13 of 140 REJ03B0147-0102 External interrupt circuit structure I12 EXF0 I11 SNZI0 instructionI13 P13/INT (Note 1) Rising Falling One-sided edge detection circuit Both edges detection circuit External 0 interrupt This symbol represents a parasitic diode on the port.• Timer 1 count start synchronization circuit input Skip L10 Level detection circuit Edge detection circuit L11 Key-on wakeup input (Note 2) (Note 3) Note 1: 2: When I12 is 0, “L” level is detected. When I12 is 1, “H ” level is detected. 3: When I12 is 0, falling edge is detected. When I12 is 1, rising edge is detected.

Rev.1.02 2006.12.22 page 14 of 140 REJ03B0147-0102 (1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-bit data addition, comparison, AND operation, OR operation, and bit manipulation. (2) Register A and carry flag Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to “1” when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A 0 is stored in carry flag CY with the RAR instruction (Figure 2). Carry flag CY can be set to “1” with the SC instruction and cleared to “0” with the RC instruction. (3) Registers B and E Register B is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3). Register E is undefined after system is released from reset and re- turned from the RAM back-up. Accordingly, set the initial value. (4) Register D Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 4). Also, when the TABP p instruction is executed at UPTF flag = “1”, the high-order 2 bits of ROM reference data is stored to the low-or- der 2 bits of register D, the high-order 1 bit of register D is “0”. When the TABP p instruction is executed at UPTF flag = “0”, the contents of register D remains unchanged. The UPTF flag is set to “1” with the SUPT instruction and cleared to “0” with the RUPT instruction. The initial value of UPTF flag is “0”. Register D is undefined after system is released from reset and re- turned from the RAM back-up. Accordingly, set the initial value. Fig. 1 AMC instruction execution example Fig. 2 RAR instruction execution example Fig. 3 Registers A, B and register E Fig. 4 TABP p instruction execution example ( C Y ) ( M ( D P ) ) (A) Addition A L U < C a r r y > < R e s u l t > A3 A2 A1 A0B3 B2 B1 B0 E7 E6 E5 E4 E3 E2 E1 E0 A3 A2 A1 A0B3 B2 B1 B0 TAB instruction TEAB instruction TABE instruction TBA instruction R e g i s t e r BR e g i s t e r A Register B Register A Register E CY A 3 A2 A1 A0 A0 CY A 3 A2 A1 <Rotation> RAR instruction <Set> SC instruction < C l e a r > R C i n s t r u c t i o n Specifying address TABP p instruction p6 p5 p4 p3 p2 p1 p0 PC H DR 2DR 1DR 0 A3 A2 A1 A0 PC L Immediate field value p The contents of register D ROM 840 Middle-order 4 bits Low-order 4bits Register A (4) Register B (4) The contents of register A High-order 2 bits Register D (3) * Flag UPTF = 1; High-order 2 bits of reference data is transferred to the low-order 2 bits of register D. “0” is stored to the high-order 1 bit of register D. Flag UPTF = 0; Data is not transferred to register D.

Rev.1.02 2006.12.22 page 15 of 140 REJ03B0147-0102 (5) Stack registers (SKS) and stack pointer (SP) Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when;

• branching to an interrupt service routine (referred to as an interrupt service routine),
• performing a subroutine call, or
• executing the table reference instruction (TABP p). Stack registers (SKs) are eight identical registers, so that subrou- tines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. The con- tents of registers SKs are destroyed when 8 levels are exceeded. The register SK nesting level is pointed automatically by 3-bit stack pointer (SP). The contents of the stack pointer (SP) can be trans- ferred to register A with the TASP instruction. Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call. (6) Interrupt stack register (SDP) Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (SDP) is used to temporarily store the contents of data pointer, carry flag, skip flag, register A, and register B just be- fore an interrupt until returning to the original routine. Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table reference in- struction. (7) Skip flag Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. When an interrupt oc- curs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained. Fig. 5 Stack registers (SKs) structure Fig. 6 Example of operation at subroutine call S K0 S K1 S K2 S K3 S K4 S K5 S K6 S K7 ( S P ) = 0 ( S P ) = 1 ( S P ) = 2 ( S P ) = 3 ( S P ) = 4 ( S P ) = 5 ( S P ) = 6 ( S P ) = 7 Program counter (PC) E x e c u t i n g R T i n s t r u c t i o n E x e c u t i n g B M i n s t r u c t i o n S t a c k p o i n t e r ( S P ) p o i n t s “ 7 ” a t r e s e t o r r e t u r n i n g f r o m R A M b a c k u p m o d e I t p o i n t s b y e x e c u t i n g t h e f i r s t B M i n s t r u c t i o n a n d t h e c o n t e n t s o f p r o g r a m c o u n t e r i s s t o r e d i n S K0. W h e n t h e B M i n s t r u c t i o n i s e x e c u t e d a f t e r e i g h t s t a c k r e g i s t e r s a r e u s e d S P S P a n d t h e c o n t e n t s o f S i s d e s t r o y e d Returning to the BM instruction execution address with the RT instruction, and the BM instruction becomes the NOP instruction. (SP) ← 0 (SK0) ← 000116 (PC) ← SUB1 Main program 0 0 0 21

6 N O P

000116 BM SUB1

S U B 1 : NOP R T (PC) ← (SK0) (SP) ← 7 Note :

Rev.1.02 2006.12.22 page 16 of 140 REJ03B0147-0102 (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table refer- ence instruction (TABP p) is executed. Program counter consists of PC H (most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which speci- fies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PC H does not specify after the last page of the built-in ROM. (9) Data pointer (DP) Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y. Register Z specifies a RAM file group, reg- ister X specifies a file, and register Y specifies a RAM digit (Figure 8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 9).

• Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the RAM back-up, set these registers. Fig. 7 Program counter (PC) structure Fig. 8 Data pointer (DP) structure Fig. 9 SD instruction execution example p5 p4 p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0 P r o g r a m c o u n t e r PC H Specifying page PC L Specifying address Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0 D a t a p o i n t e r ( D P ) R e g i s t e r Z ( 2 ) R e g i s t e r X ( 4 ) R e g i s t e r Y ( 4 ) Specifying RAM digit Specifying RAM file Specifying RAM file group 0 01 1 S e t Specifying bit position P o r t D o u t p u t l a t c hR e g i s t e r Y ( 4 ) D 2D 3 D 1 D 0

Rev.1.02 2006.12.22 page 17 of 140 REJ03B0147-0102 PROGRAM MEMOY (ROM) 1 word of program memory is composed of 10 bits. ROM is sepa- rated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 10 shows the ROM map of M34509G4. Table 1 ROM size and pages Part number M34509G4 M34509G4H ROM (PROM) size (✕ 10 bits) 4096 words 4096 words Pages 32 (0 to 31) 32 (0 to 31) A part of page 1 (addresses 008016 to 00FF16) is reserved for inter- rupt addresses (Figure 11). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the pro- gram counter, and the instruction at the interrupt address is executed. When using an interrupt service routine, write the instruc- tion generating the branch to that routine at an interrupt address. Page 2 (addresses 0100 16 to 017F16) is the special page for subrou- tine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern (bits 7 to 0) of all addresses can be used as data areas with the TABP p instruction. ROM Code Protect Address When selecting the protect bit write by using a serial programmer or selecting protect enabled for writing shipment by Renesas Technol- ogy corp., reading or writing from/to QzROM is disabled by a serial programmer. As for the QzROM product in blank, the ROM code is protected by selecting the protect bit write at ROM writing with a serial pro- grammer. As for the QzROM product shipped after writing, whether the ROM code protect is used or not can be selected as ROM option setup (“MASK option” written in the mask file converter) when ordering. Fig. 10 ROM map of M34509G4 Fig. 11 Page 1 (addresses 008016 to 00FF16) structure 087654321 0 0 0 01 0 0 8 01 0 1 7F1 Subroutine special page 0 0 7F1 0 0F 0 1 0 01 0 1 8 01 P a g e 1 P a g e 2 P a g e 0 P a g e 3 P a g e 3 10F F I n t e r r u p t a d d r e s s p a g e 90 87654321 External 0 interrupt address008016 008216 Timer 1 interrupt address008416 Timer 2 interrupt address008616 008816 008A16 00FF16 A/D interrupt address008C 16 008E16 Serial interface interrupt address

Rev.1.02 2006.12.22 page 18 of 140 REJ03B0147-0102 DATA MEMORY (RAM) 1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers Z, X, and Y. Set a value to the data pointer certainly when executing an instruction to access RAM. Table 2 shows the RAM size. Figure 12 shows the RAM map.

• Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the RAM back-up, set these registers. Fig. 12 RAM map Table 2 RAM size Part number M34509G4 M34509G4H RAM size 256 words ✕ 4 bits (1024 bits) 256 words ✕ 4 bits (1024 bits) Register Y Register Z Register X RAM 256 words ✕ 4 bits (1024 bits)

Rev.1.02 2006.12.22 page 19 of 140 REJ03B0147-0102 INTERRUPT FUNCTION The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the following 3 conditions are satisfied.

• An interrupt activated condition is satisfied (request flag = “1”)
• Interrupt enable bit is enabled (“1”)
• Interrupt enable flag is enabled (INTE = “1”) Table 3 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.) (1) Interrupt enable flag (INTE) The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to “1” with the EI instruction and disabled when INTE flag is cleared to “0” with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to “0,” so that other interrupts are disabled un- til the EI instruction is executed. (2) Interrupt enable bit Use an interrupt enable bit of interrupt control registers V1 and V2 to select the corresponding interrupt or skip instruction. Table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. Table 5 shows the interrupt enable bit function. (3) Interrupt request flag When the activated condition for each interrupt is satisfied, the corre- sponding interrupt request flag is set to “1.” Each interrupt request flag is cleared to “0” when either;
• an interrupt occurs, or
• the next instruction is skipped with a skip instruction. Each interrupt request flag is set when the activated condition is sat- isfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set until a clear condition is satisfied. Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. If more than one interrupt request flag is set when the interrupt dis- able state is released, the interrupt priority level is as follows shown in Table 3. Table 3 Interrupt sources Activated condition Level change of INT pin Timer 1 underflow Timer 2 underflow Completion of A/D conversion Completion of serial interface transmit/ recieve Priority level Interrupt name External 0 interrupt Timer 1 interrupt Timer 2 interrupt A/D interrupt Serial interface interrupt Table 5 Interrupt enable bit function Occurrence of interrupt Enabled Disabled Skip instruction Invalid Valid Interrupt enable bit Interrupt address Address 0 in page 1 Address 4 in page 1 Address 6 in page 1 Address C in page 1 Address E in page 1 Table 4 Interrupt request flag, interrupt enable bit and skip in- struction Interrupt request flag EXF0 T1F T2F ADF SIOF Interrupt name External 0 interrupt Timer 1 interrupt Timer 2 interrupt A/D interrupt Serial interface interrupt Skip instruction SNZ0 SNZT1 SNZT2 SNZAD SNZSI Interrupt enable bit V12 V13 V22 V23

Rev.1.02 2006.12.22 page 20 of 140 REJ03B0147-0102 (4) Internal state during an interrupt The internal state of the microcomputer during an interrupt is as fol- lows (Figure 14).

• Program counter (PC) An interrupt address is set in program counter. The address to be executed when returning to the main routine is automatically stored in the stack register (SK).
• Interrupt enable flag (INTE) INTE flag is cleared to “0” so that interrupts are disabled.
• Interrupt request flag Only the request flag for the current interrupt source is cleared to “0.”
• Data pointer, carry flag, skip flag, registers A and B The contents of these registers and flags are stored automatically in the interrupt stack register (SDP). (5) Interrupt processing When an interrupt occurs, a program at an interrupt address is ex- ecuted after branching a data store sequence to stack register. Write the branch instruction to an interrupt service routine at an interrupt address. Use the RTI instruction to return from an interrupt service routine. Interrupt enabled by executing the EI instruction is performed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction, interrupts are enabled after returning the main routine. (Refer to Figure 13) Fig. 13 Program example of interrupt processing
• Program counter (PC)
• Stack register (SK)
• Interrupt enable flag (INTE)
• Interrupt request flag (only the flag for the current interrupt
• Data pointer, carry flag, registers A and B, skip flag The address of main routine to be executed when returning Fig. 15 Interrupt system diagram Fig. 14 Internal state when interrupt occurs T1F V1 2 EXF0 V10 Address 4 in page 1 Address 0 in page 1 T2F V1 3 Address 6 in page 1 ADF V2 2 Timer 1 underflow Timer 2 underflow Completion of A/D conversion Address C in page 1 INT pin (L→H or H→L input) SIOF V2 3 Serial interface transmit/receive completed Address E in page 1 Request flag (state retained) Enable bit Enable flag INTE Activated condition E I R T I Interrupt service routine Interrupt occurs Interrupt is enabled M a i n r o u t i n e : I n t e r r u p t e n a b l e d s t a t e : Interrupt disabled state

Rev.1.02 2006.12.22 page 21 of 140 REJ03B0147-0102 (6) Interrupt control registers

• Interrupt control register V1 Interrupt enable bits of external 0, timer 1 and timer 2 are as- signed to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A.
• Interrupt control register V2 The A/D interrupt enable bit and serial interface interrupt enable bit are assigned to register V2. Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction can be used to transfer the contents of register V2 to register A. Table 6 Interrupt control registers Note: “R ” represents read enabled, and “W ” represents write enabled. (7) Interrupt sequence Interrupts only occur when the respective INTE flag, interrupt enable bits (V10, V12, V13, V22, V23), and interrupt request flag are “1.” The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. The interrupt occurs after 3 machine cycles only when the three interrupt conditions are satisfied on execution of other than one-cycle instructions (Refer to Figure 16). Interrupt disabled (SNZSI instruction is valid) Interrupt enabled (SNZSI instruction is invalid) Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. R/W TAV2/TV2A V13 V12 V11 V10 V23 V22 V21 V20 Serial interface interrupt enable bit A/D interrupt enable bit Not used Not used Interrupt control register V2 at RAM back-up : 00002at reset : 00002 Interrupt control register V1 Timer 2 interrupt enable bit Timer 1 interrupt enable bit Not used External 0 interrupt enable bit Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) This bit has no function, but read/write is enabled. Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) at RAM back-up : 0000 2at reset : 00002 R/W TAV1/TV1Aat RAM back-up : 00002at reset : 00002

Rev.1.02 2006.12.22 page 22 of 140 REJ03B0147-0102 Fig. 16 Interrupt sequence T1F, T2F ADF, SIOF INTEXF0 System clock The program starts from the interrupt address. Interrupt enabled state G When an interrupt request flag is set after its interrupt is enabled 1 machine cycle EI instruction execution cycle Interrupt enable flag (INTE) Retaining level of system clock for 4 periods or more is necessary.Interrupt disabled state External interrupt Timer 1,Timer 2, A/D and serial interface interrupts Interrupt activated condition is satisfied. 2: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied Notes 1: The address is stacked to the last cycle. Flag cleared 2 to 3 machine cycles (Notes 1, 2)

Rev.1.02 2006.12.22 page 23 of 140 REJ03B0147-0102 Table 7 External interrupt activated conditions Name External 0 interrupt Input pin P13/INT Activated condition When the next waveform is input to P13/INT pin

• Both rising and falling waveforms Valid waveform selection bit I11 I12 Fig. 17 External interrupt circuit structure EXTERNAL INTERRUPTS The 4509 Group has the external 0 interrupt. An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). The external interrupt can be controlled with the interrupt control register I1. 0 I12 EXF0 I11 SNZI0 instructionI13 P13/INT (Note 1) Rising Falling One-sided edge detection circuit Both edges detection circuit External 0 interrupt This symbol represents a parasitic diode on the port.• Timer 1 count start synchronization circuit input Skip L10 Level detection circuit Edge detection circuit L11 Key-on wakeup input (Note 2) (Note 3) Note 1: 2: When I12 is 0, “L” level is detected. When I12 is 1, “H ” level is detected. 3: When I12 is 0, falling edge is detected. When I12 is 1, rising edge is detected. (1) External 0 interrupt request flag (EXF0) External 0 interrupt request flag (EXF0) is set to “1” when a valid waveform is input to P13/INT pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip instruc- tion.
• External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to P1 3/INT pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 0 interrupt is as follows. ➀ Set the bit 3 of register I1 to “1” for the INT pin to be in the input enabled state. ➁ Select the valid waveform with the bits 1 and 2 of register I1. ➂ Clear the EXF0 flag to “0” with the SNZ0 instruction. ➃ Set the NOP instruction for the case when a skip is performed with the SNZ0 instruction. ➄ Set both the external 0 interrupt enable bit (V1 0) and the INTE flag to “1.” The external 0 interrupt is now enabled. Now when a valid wave- form is input to the P13/INT pin, the EXF0 flag is set to “1” and the external 0 interrupt occurs.

Rev.1.02 2006.12.22 page 24 of 140 REJ03B0147-0102 (2) External interrupt control registers

• Interrupt control register I1 Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the TI1A in- struction. The TAI1 instruction can be used to transfer the contents of register I1 to register A. Table 8 External interrupt control registerNotes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. I13 I12 I11 I10 INT pin input control bit (Note 2) Interrupt valid waveform for INT pin/ return level selection bit (Note 2) INT pin edge detection circuit control bit INT pin timer 1 control enable bit Interrupt control register I1 R/W TAI1/TI1Aat RAM back-up : state retainedat reset : 00002 INT pin input disabled INT pin input enabled Falling waveform (“L” level of INT pin is recognized with the SNZI0 instruction)/“L” level Rising waveform (“H ” level of INT pin is recognized with the SNZI0 instruction)/“H ” level One-sided edge detected Both edges detected Disabled Enabled

Rev.1.02 2006.12.22 page 25 of 140 REJ03B0147-0102 (3) Notes on interrupts ➀ Note [1] on bit 3 of register I1 When the input of the INT pin is controlled with the bit 3 of register I1 in software, be careful about the following notes.

• Depending on the input state of the P1 3/INT pin, the external 0 in- terrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected in- terrupt, clear the bit 0 of register V1 to “0” (refer to Figure 18➀ ) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to Figure 18➁ ). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 18➂ ). LA 4 ; ( ✕✕✕ 0 LA 8 ; (1 ✕✕✕ 2) TI1A ; Control of INT pin input is changed SNZ0 ; The SNZ0 instruction is executed (EXF0 flag cleared) ✕ : these bits are not used here. Fig. 18 External 0 interrupt program example-1 ➁ Note [2] on bit 3 of register I1 When the bit 3 of register I1 is cleared to “0”, the RAM back-up mode is selected and the input of INT pin is disabled, be careful about the following notes.
• When the INT pin input is disabled (register I1 3 = “0”), set the key- on wakeup of INT pin to be invalid (register L10 = “0”) before system enters to the RAM back-up mode. (refer to Figure 19➀ ).
• ••
• •• LA 0 ; ( ✕✕✕ 02) DI EPOF POF ; RAM back-up ✕ : these bits are not used here. Fig. 19 External 0 interrupt program example-2
• ••
• •• ➂ Note [3] on bit 2 of register I1 When the interrupt valid waveform of the P13/INT pin is changed with the bit 2 of register I1 in software, be careful about the follow- ing notes.
• Depending on the input state of the P1 3/INT pin, the external 0 in- terrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected in- terrupt, clear the bit 0 of register V1 to “0” (refer to Figure 20➀ ) and then, change the bit 2 of register I1 is changed. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to Figure 20➁ ). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 20➂ ). LA 4 ; ( ✕✕✕ 0 LA 12 ; (1 ✕✕✕ 2) TI1A ; Interrupt valid waveform is changed SNZ0 ; The SNZ0 instruction is executed (EXF0 flag cleared) ✕ : these bits are not used here. Fig. 20 External 0 interrupt program example-3
• ••
• ••

Rev.1.02 2006.12.22 page 26 of 140 REJ03B0147-0102 The 4509 Group has the following timers.

• Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt re- quest flag is set to “1,” new data is loaded from the reload register, and count continues (auto-reload function).
• Fixed dividing frequency timer The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to “1” after every n count of a count pulse. Fig. 21 Auto-reload function Count source
• Instruction clock (INSTCK)
• PWM2 signal (PWMOD2)
• Prescaler output (ORCLK)
• CNTR1 input
• On-chip oscillator clock (f(RING))
• Timer 1 underflow (T1UDF)
• Prescaler output (ORCLK)
• CNTR0 input
• System clock (STCK)
• Instruction clock (INSTCK) Structure 8-bit programmable binary down counter 8-bit programmable binary down counter (link to INT input) (with PWM output function) 8-bit programmable binary down counter (INT input period count function) (with PWM output function) 16-bit fixed dividing frequency Circuit Prescaler Timer 1 Timer 2 Watchdog timer Use of output signal
• Timer 1 and 2 count sources
• Timer 2 count source
• CNTR0 output
• Timer 1 interrupt
• Timer 1 count source
• CNTR1 output
• Timer 2 interrupt
• System reset (counting twice)
• Decision of flag WDF1 Frequency dividing ratio 1 to 256 1 to 256 1 to 256 65536 Control register PA The 4509 Group timer consists of the following circuits.
• Prescaler : 8-bit programmable timer
• Timer 1 : 8-bit programmable timer
• Timer 2 : 8-bit programmable timer (Timers 1 and 2 have the interrupt function, respectively)
• 16-bit timer Prescaler and timers 1 and 2 can be controlled with the timer control registers PA, W1, W2 , W5 and W6. The 16-bit timer is a free counter which is not controlled with the control register. Each function is described below. Table 9 Function related timers F F1 n 0 01 n : C o u n t e r i n i t i a l v a l u e Count starts Reload R e l o a d 1st underflow 2nd underflow n+1 count n+1 count T i m e An interrupt occurs or a skip instruction is executed. Timer interrupt request flag T h e c o n t e n t s o f c o u n t e r “1” “0”

Rev.1.02 2006.12.22 page 27 of 140 REJ03B0147-0102 Fig. 22 Timers structure (1) Watchdog timer (16)INSTCK Q R S WDF1 WRST instruction Q R S WEF DWDT instruction WRST instruction RESET signal Q T D R RESET signal Watchdog reset signal (Note 4) (Note 3) (Note 2) Division circuit System clock (STCK) Instruction clock (INSTCK) Multi- plexer (CRCK) MR 0 ORCLK Reload register RPS (8) Prescaler (8) Register B Register A(TABPS) (TABPS)(TPSAB) PA 0 MR 3, MR2 (TPSAB)(TPSAB) On-chip oscillator XIN Ceramic resonance RC oscillation Internal clock generating circuit (divided by 3) Divided by 2 Divided by 4 Divided by 8 (Note 1) Data is set automatically from each reload register when timer underflows (auto-reload function). Notes 1: When CRCK instruction is executed, RC oscillation is selected. When CRCK instruction is not executed, ceramic resonance is selected. 2: Flag WDF1 is cleared to “0” and the next instruction is skipped when the WRST instruction is executed while flag WDF1 = “1”. The next instruction is not skipped even when the WRST instruction is executed while flag WDF1 = “0”. 3: Flag WEF is cleared to “0” and watchdog timer reset does not occur when the DWDT instruction and WRST instruction are executed continuously. 4: The WEF flag is set to “1” at system reset or RAM back-up mode.

Rev.1.02 2006.12.22 page 28 of 140 REJ03B0147-0102 Fig. 23 Timers structure (2) PWM2 W1 1, W10 ORCLK f(RING) T1F(TAB1)(TAB1) (T1AB)(T1AB) (T1AB) Timer 1 (8) Timer 1 interrupt Reload register R1L (8) Register BRegister A Timer 1 underflow signal W1 2 P11/CNTR 1 (T1UDF) Reload register R1H (8) (T1HAB) Register BRegister A (T1R1L) Reload control circuit (Note 3) Q R T W1 3 W5 1 Q R S I12 P13/INT I13 I11One-sided edge detection circuit Both edges detection circuit INTSNC W6 0 INTSNC I10 W5 2 T1UDF (Note 1) T1UDF W2 1, W20 ORCLK STCK T2F(TAB2)(TAB2) (T2AB) (T2AB) (T2AB) Timer 2 (8) Timer 2 interrupt Reload register R2L (8) Register BRegister A W2 2 Reload register R2H (8) (T2HAB) Register BRegister A (T2R2L) Reload control circuit (Note 4) Q R T W2 3 W6 1 W5 0 W6 1 I13 (Note 2) Q R D T INTSNC PWM1 PWM2 W5 3 P12/CNTR 0 P12/CNTR 0 Port P12 output PWM1 W6 3 Port P11 output Q R D T P11/CNTR 1 PWM2 W1 2 W6 2 T1UDFPWMOD2 T1R1L: T2R2L: STCK: ORCLK: This instruction is used to transfer the contents of reload register R1L to timer 1. This instruction is used to transfer the contents of reload register R2L to timer 2. System clock Prescaler output Data is set automatically from each reload register when timer underflows (auto-reload function). Notes 1: Timer 1 count start synchronous circuit is synchronized with the valid edge of INT pin selected by bits 1 (I1 1) and 2 (I12) of register I1. 2: Timer 2 INT input period count circuit is used to count the valid edge period of INT pin selected by bits 1 (I11) and 2 (I12) of register I1. 3: When the PWM1 function is valid (W13=“1”), the value is auto-reloaded alternately from reload register R1L and R1H every timer 1 underflow. When the PWM1 function is invalid (W1 3=“0”), the value is auto-reloaded from reload register R1L only. 4: When the PWM2 function is valid (W23=“1”), the value is auto-reloaded alternately from reload register R2L and R2H every timer 2 underflow. When the PWM2 function is invalid (W2 3=“0”), the value is auto-reloaded from reload register R2L only.

Rev.1.02 2006.12.22 page 29 of 140 REJ03B0147-0102 Table 10 Timer control registers PWM1 function invalid PWM1 function valid Stop (state retained) Operating Count source PWM2 signal Prescaler output (ORCLK) CNTR1 input On-chip oscillator clock (f(RING)) PWM1 function control bit Timer 1 control bit PWM2 function invalid PWM2 function valid Stop (state retained) Operating Count source Timer 1 underflow signal (T1UDF) Prescaler output (ORCLK) CNTR0 input System clock (STCK) PWM2 function control bit Timer 2 control bit Timer 2 count source selection bits Timer control register W1 R/W TAW1/TW1Aat reset : 00002 at RAM back-up : 00002at reset : 00002 Timer control register W2 R/W TAW2/TW2Aat RAM back-up : 00002at reset : 00002 W2 3 W2 2 W2 1 W2 0 Stop (state initialized) Operating Prescaler control bit Timer control register PA W TPAAat RAM back-up : 02at reset : 02 PA 0 P12 (I/O) / CNTR0 (input) P12 (input) /CNTR0 (I/O) Count auto-stop circuit not selected Count auto-stop circuit selected Count start synchronous circuit not selected Count start synchronous circuit selected Falling edge Rising edge 2/CNTR0 pin function selection bit Timer 1 count auto-stop circuit selection bit (Note 2) Timer 1 count start synchronous circuit selection bit (Note 3) CNTR0 pin input count edge selection bit Timer control register W5 at RAM back-up : state retainedat reset : 00002 W5 3 W5 2 W5 1 W5 0 R/W TAW5/TW5A P11 (I/O) / CNTR1 (input) P11 (input) /CNTR1 (I/O) Output auto-control circuit not selected Output auto-control circuit selected INT pin input period count circuit not selected INT pin input period count circuit selected Falling edge Rising edge 1/CNTR1 pin function selection bit CNTR 1 pin output auto-control circuit selection bit Timer 2 INT pin input period count circuit selection bit CNTR1 pin input count edge selection bit Timer control register W6 at RAM back-up : state retainedat reset : 00002 W6 3 W6 2 W6 1 W6 0 R/W TAW6/TW6A Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: This function is valid only when the INT pin/timer 1 control is enabled (I10=“1”) and the timer 1 count start synchronous circuit is selected (W51=“1”). 3: This function is valid only when the INT pin/timer 1 control is enabled (I10=“1”). W1 3 W1 2 W1 1 W1 0 W1 1 Timer 1 count source selection bits

Rev.1.02 2006.12.22 page 30 of 140 REJ03B0147-0102 (1) Timer control registers

• Timer control register PA Register PA controls the count operation of prescaler. Set the con- tents of this register through register A with the TPAA instruction.
• Timer control register W1 Register W1 controls the count operation and count source of timer 1, and PWM1 function. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A.
• Timer control register W2 Register W2 controls the count operation and count source of timer 2, and PWM2 function. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A.
• Timer control register W5 Register W5 controls the input count edge of CNTR0 pin, timer 1 count start synchronous circuit, timer 1 auto-stop circuit and P1 CNTR0 pin function. Set the contents of this register through reg- ister A with the TW5A instruction. The TAW5 instruction can be used to transfer the contents of register W5 to register A.
• Timer control register W6 Register W6 controls the input count edge of CNTR1 pin, the INT pin input count start synchronous circuit and CNTR1 pin output auto-control circuit and the P1 1/CNTR1 pin function. Set the con- tents of this register through register A with the TW6A instruction. The TAW6 instruction can be used to transfer the contents of reg- ister W6 to register A. (2) Prescaler Prescaler is an 8-bit binary down counter with the prescaler reload register RPS. Data can be set simultaneously in prescaler and the reload register RPS with the TPSAB instruction. Data can be read from reload register RPS with the TABPS instruction. Stop counting and then execute the TPSAB or TABPS instruction to read or set prescaler data. Prescaler starts counting after the following process; ➀ set data in prescaler, and ➁ set the bit 0 of register PA to “1.” When a value set in reload register RPS is n, prescaler divides the count source signal by n + 1 (n = 0 to 255). Count source for prescaler is the instruction clock (INSTCK). Once count is started, when prescaler underflows (the next count pulse is input after the contents of prescaler becomes “0”), new data is loaded from reload register RPS, and count continues (auto-reload function). The output signal (ORCLK) of prescaler can be used for timer 1 and 2 count sources. (3) Timer 1 (interrupt function) Timer 1 is an 8-bit binary down counter with two timer 1 reload regis- ters (R1L, R1H). Data can be set simultaneously in timer 1 and the reload register R1L with the T1AB instruction. Data can be set in the reload register R1H with the T1HAB instruction. The contents of re- load register R1L set with the T1AB instruction can be set to timer 1 again with the T1R1L instruction. Data can be read from timer 1 with the TAB1 instruction. Stop counting and then execute the T1AB or TAB1 instruction to read or set timer 1 data. When executing the T1HAB instruction to set data to reload register R1H while timer 1 is operating, avoid a timing when timer 1 underflows. Timer 1 starts counting after the following process; ➀ set data in timer 1 ➁ set count source by bits 0 and 1 of register W1, and ➂ set the bit 2 of register W1 to “1.” When a value set in reload register R1L is n and a value set in re- load register R1H is m, timer 1 divides the count source signal by n + 1 or m + 1 (n = 0 to 255, m = 0 to 255). <Bit 3 of register W1 = “0” (PWM1 function invalid)> Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes “0”), the timer 1 inter- rupt request flag (T1F) is set to “1,” new data is loaded from reload register R1L, and count continues (auto-reload function). <Bit 3 of register W1 = “1” (PWM1 function valid)> Timer 1 generates the PWM1 signal of the “L” interval set as reload register R1L, and the “H ” interval set as reload register R1H. The PWM1 signal generated by timer 1 is output from CNTR0 pin by set- ting “1” to bit 3 of register W5. After timer 1 control by INT pin is enabled by setting the bit 0 of reg- ister I1 to “1”, INT pin input can be used as the start trigger for timer 1 count operation by setting the bit 1 of register W5 to “1”. Also, in this time, the auto-stop function by timer 1 underflow can be performed by setting the bit 2 of register W5 to “1.”

Rev.1.02 2006.12.22 page 31 of 140 REJ03B0147-0102 (5) Count start synchronization circuit (timer 1) Timer 1 has the count start synchronous circuit which synchronizes the input of INT pin, and can start the timer count operation. Timer 1 count start synchronous circuit function can be selected af- ter timer 1 control by INT pin is enabled by setting the bit 0 of register I1 to “1” and its function is selected by setting the bit 1 of register W5 to “1”. When timer 1 count start synchronous circuit is used, the count start synchronous circuit is set, the count source is input to timer by input- ting valid waveform to INT pin. The valid waveform of INT pin to set the count start synchronous cir- cuit is the same as the external interrupt activated condition. Once set, the count start synchronous circuit is cleared by clearing the bit I1 0 to “0” or system reset. However, when the count auto-stop circuit is selected (W22 = “1”), the count start synchronous circuit is cleared (auto-stop) at the timer 1 underflow. (6) Count auto-stop circuit (timer 1) Timer 1 has the count auto-stop circuit which is used to stop timer 1 automatically by the timer 1 underflow when the count start synchro- nous circuit is used. The count auto-stop circuit is valid by setting the bit 2 of register W5 to “1”. It is cleared by the timer 1 underflow and the count source to timer 1 is stopped. This function is valid only when the timer 1 count start synchronous circuit is selected. (7) INT pin input period count circuit (timer 2) Timer 2 has the INT pin input period count circuit to count the valid waveform input interval of the INT pin. When bit 1 of register W6 is set to “1”, the INT pin input period count circuit of timer 2 becomes valid, and the count source is input. The count source input is stopped by the next input of valid waveform to the INT pin. Then, every a valid waveform is input to the INT pin, start/stop of the count source input is alternately repeated. A valid waveform of the INT pin input is the same as the activated condition of an external interrupt. The INT pin input period count circuit set once is cleared by setting the INT pin input to be disabled state. The INT pin input can be dis- abled by clearing bit 3 of register I1 to “0”. (8) Timer input/output pin (P12/CNTR0 pin, P11/ CNTR1 pin) CNTR0 pin is used to input the timer 2 count source and output the PWM1 signal generated by timer 1. CNTR1 pin is used to input the timer 1 count source and output the PWM2 signal generated by timer 2. The P1 2/CNTR0 pin function can be selected by bit 3 of register W5. The P11/CNTR1 pin function can be selected by bit 3 of register W6. When the CNTR0 input is selected for timer 2 count source, timer 2 counts the falling or rising waveform of CNTR0 input. The count edge is selected by bit 0 of register W5. When the CNTR1 input is selected for timer 1 count source, timer 1 counts the falling or rising waveform of CNTR1 input. The count edge is selected by bit 0 of register W6. (4) Timer 2 (interrupt function) Timer 2 is an 8-bit binary down counter with two timer 2 reload regis- ters (R2L, R2H). Data can be set simultaneously in timer 2 and the reload register R2L with the T2AB instruction. Data can be set in the reload register R2H with the T2HAB instruction. The contents of re- load register R2L set with the T2AB instruction can be set to timer 2 again with the T2R2L instruction. Data can be read from timer 2 with the TAB2 instruction. Stop counting and then execute the T2AB or TAB2 instruction to read or set timer 2 data. When executing the T2HAB instruction to set data to reload register R2H while timer 2 is operating, avoid a timing when timer 2 underflows. Timer 2 starts counting after the following process; ➀ set data in timer 2 ➁ set count source by bits 0 and 1 of register W2, and ➂ set the bit 2 of register W2 to “1.” When a value set in reload register R2L is n and a value set in re- load register R2H is m, timer 2 divides the count source signal by n + 1 or m + 1 (n = 0 to 255, m = 0 to 255). Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes “0”), the timer 2 inter- rupt request flag (T2F) is set to “1,” new data is loaded from reload register R2L, and count continues (auto-reload function). <Bit 3 of register W2 = “0” (PWM2 function invalid)> Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes “0”), the timer 2 inter- rupt request flag (T2F) is set to “1,” new data is loaded from reload register R2L, and count continues (auto-reload function). <Bit 3 of register W2 = “1” (PWM2 function valid)> Timer 2 generates the PWM2 signal of the “L” interval set as reload register R2L, and the “H ” interval set as reload register R2H. The PWM2 signal generated by timer 2 is output from CNTR1 pin by set- ting “1” to bit 3 of register W6. PWM2 output to CNTR1 pin combined with timer 1 can be controlled by setting the bit 2 of register W6 to “1.” Input period of INT pin by timer 2 can be counted by setting the bit 1 of register W6 to “1.”

Rev.1.02 2006.12.22 page 32 of 140 REJ03B0147-0102 Fig. 24 Timer count start timing and count time when operation starts (9) PWM1 output function (P12/CNTR0, timer 1) When bit 3 of register W1 is set to “1”, the data is reloaded alter- nately from reload register R1L and R1H every timer 1 underflow. Timer 1 generates the PWM1 signal of the “L” interval set as reload register R1L, and the “H ” interval set as reload register R1H. In this time, the PWM1 signal generated by timer 1 is output from CNTR0 pin by setting “1” to bit 3 of register W5. When the TW1A instruction is executed while the PWM1 signal is “H ”, the contents of register W1 is changed after the “H ” interval of the PWM1 signal is ended. (10) PWM2 output function (P11/CNTR1, timer 1, timer 2) When bit 3 of register W2 is set to “1”, the data is reloaded alter- nately from reload register R2L and R2H every timer 2 underflow. Timer 2 generates the PWM2 signal of the “L” interval set as reload register R2L, and the “H ” interval set as reload register R2H. In this time, the PWM2 signal generated by timer 2 is output from CNTR1 pin by setting “1” to bit 3 of register W6. When bit 2 of register W6 is set to “1”, the PWM2 signal output to CNTR1 pin is switched to valid/invalid alternately each timer 1 un- derflow. However, when timer 1 is stopped (bit 2 of register W1 is cleared to “0”), this function is canceled. When the TW2A instruction is executed while the PWM2 signal is “H ”, the contents of register W2 is changed after the “H ” interval of the PWM2 signal is ended. (11) Timer interrupt request flags (T1F, T2F) Each timer interrupt request flag is set to “1” when each timer underflows. The state of these flags can be examined with the skip instructions (SNZT1, SNZT2). Use the interrupt control register V1, V2 to select an interrupt or a skip instruction. An interrupt request flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with a skip instruction. Timer start Count source Timer value Timer underflow signal 3 21032103 ➂ ➃ /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Count source (When falling edge of CNTR input is selected) (12) Precautions - Prescaler Stop prescaler counting and then execute the TABPS instruction to read its data. Stop prescaler counting and then execute the TPSAB instruction to write data to prescaler. - Timer count source Stop timer 1 or 2 counting to change its count source. - Reading the count value Stop timer 1 or 2 counting and then execute the TAB1 or TAB2 in- struction to read its data. - Writing to the timer Stop timer 1 or 2 counting and then execute the T1AB, T1R1L, T2AB or T2R2L instruction to write data to timer. - Writing to reload register In order to write a data to the reload register R1H while the timer 1 is operating, execute the T1HAB instruction except a timing of the timer 1 underflow. In order to write a data to the reload register R2H while the timer 2 is operating, execute the T2HAB instruction except a timing of the timer 2 underflow. - PWM signal (PWM1, PWM2) If the timer 1 count stop timing and the timer 1 underflow timing overlap during output of the PWM1 signal, a hazard may occur in the PWM1 output waveform. If the timer 2 count stop timing and the timer 2 underflow timing overlap during output of the PWM2 signal, a hazard may occur in the PWM2 output waveform. - Prescaler, timer 1 and timer 2 count start timing and count time when operation starts Count starts from the first rising edge of the count source (2) after prescaler and timer operations start (1). Time to first underflow (3) is shorter (for up to 1 period of the count source) than time among next underflow (4) by the timing to start the timer and count source operations after count starts. When selecting CNTR input as the count source of timer, timer operates synchronizing with the count edge (falling edge or rising edge) of CNTR input selected by software.

Rev.1.02 2006.12.22 page 33 of 140 REJ03B0147-0102 Fig. 25 Timer 1 operation example G PWM1 function invalid (W13 = “0”) Timer 1 count source Timer 1 count value (Reload register) 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 00160316 (R1L) (R1L) (R1L) (R1L) (R1L) Timer 1 underflow signal PWM1 signal Timer 1 start PWM1 signal “L” fixed 02160316 (R1L) (R1H) (R1L) (R1H) 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 (R1L) Timer 1 start (R1H) 3 clock 3 clock PWM period 7 clock PWM period 7 clock * : “0316” is set to reload register R1L and “0216” is set to reload register R1H. Timer 1 count source Timer 1 count value (Reload register) Timer 1 underflow signal PWM1 signal G PWM1 function valid (W13 = “1”) 4 clock 4 clock 4 clock → → → →

Rev.1.02 2006.12.22 page 34 of 140 REJ03B0147-0102 Fig. 26 CNTR1 output auto-control function by timer 1 CNTR1 output CNTR1 output start Register W62 Timer 1 stop * When the CNTR1 output auto-control circuit is selected, valid/invalid of CNTR1 output is repeated every timer 1 underflows. G CNTR1 output auto-control circuit operation example 1 (W23 = “1”, W63 = “1”, W62 = “1”) Timer 1 underflow signal PWM2 signal Timer 1 start Timer 1 underflow signal PWM2 signal Timer 1 start CNTR1 output CNTR1 output start→ CNTR1 output stop→ G CNTR1 output auto-control circuit operation example 2 (W23 = “1”, W63 = “1”) ➀ When the CNTR1 output auto-control function is not selected while the CNTR output is invalid, CNTR1 output invalid state is retained. ➁ When the CNTR1 output auto-control function is not selected while the CNTR output is valid, CNTR1 output valid state is retained. ➂ When the timer 1 is stopped, the CNTR1 output auto-control function becomes invalid.

Rev.1.02 2006.12.22 page 35 of 140 REJ03B0147-0102 Fig. 27 Timer count start/stop timing G Timer 2 count start timing (R2L = “0216”, R2H = ”0216”, W23 = “1”) G Timer 2 count stop timing (R2L = “0216”, R2H = ”0216”, W23 = “1”) Notes 1: If the timer count stop timing and the timer underflow timing overlap while the PWM function is valid (W13=“1” or W23=“1”), a hazard may occur in the PWM signal waveform. 2: When timer count is stopped during “H ” duration of the PWM signal, timer is stopped after the end of the “H ” output duration. TW2A instruction execution (W2 2←“1”) 0216 Timer 2 undeflow signal PWM2 signal 0116 0016 0216 0116 0016 0216 (R2L) (R2H) (R2L) Mi Mi + 1 Mi + 2 Mi + 3 Mi Mi + 1 Mi + 2 Mi + 3 Timer 2 count source (System clock (STCK)) Machine cycle Timer 2 count start timing Register W22 Timer 2 count value (Reload register) Timer 2 undeflow signal PWM2 signal Timer 2 count source (System clock (STCK)) Machine cycle Register W22 Timer 2 count value (Reload register) TW2A instruction execution (W22←“0”) 02160216 0116 0016 0216 0116 0016 (R2H) (R2L) Timer 2 count stop timing (R2H) (Note 1) →

Rev.1.02 2006.12.22 page 36 of 140 REJ03B0147-0102 Fig. 28 Watchdog timer function WATCHDOG TIMER Watchdog timer provides a method to reset the system when a pro- gram run-away occurs. Watchdog timer consists of timer WDT(16-bit binary counter), watchdog timer enable flag (WEF), and watchdog timer flags (WDF1, WDF2). The timer WDT downcounts the instruction clocks as the count source from “FFFF 16” after system is released from reset. After the count is started, when the timer WDT underflow occurs (after the count value of timer WDT reaches “FFFF 16,” the next count pulse is input), the WDF1 flag is set to “1.” If the WRST instruction is never executed until the timer WDT un- derflow occurs (until timer WDT counts 65534), WDF2 flag is set to “1,” and the RESET pin outputs “L” level to reset the microcom- puter. Execute the WRST instruction at each period of 65534 machine cycle or less by software when using watchdog timer to keep the microcomputer operating normally. When the WEF flag is set to “1” after system is released from reset, the watchdog timer function is valid. When the DWDT instruction and the WRST instruction are ex- ecuted continuously, the WEF flag is cleared to “0” and the watchdog timer function is invalid. The WEF flag is set to "1" at system reset or RAM back-up mode. The WRST instruction has the skip function. When the WRST in- struction is executed while the WDF1 flag is “1”, the WDF1 flag is cleared to “0” and the next instruction is skipped. When the WRST instruction is executed while the WDF1 flag is “0”, the next instruction is not skipped. The skip function of the WRST instruction can be used even when the watchdog timer function is invalid. 65534 count (Note) Value of 16-bit timer (WDT) WDF1 flag ➂ WRST instruction executed (skip executed) RESET pin output WDF2 flag ➄ System reset➀ Reset released ➀ After system is released from reset (= after program is started), timer WDT starts count down. ➁ When timer WDT underflow occurs, WDF1 flag is set to “1.” ➂ When the WRST instruction is executed while the WDF1 flag is “1”, WDF1 flag is cleared to “0,” the next instruction is skipped. ➃ When timer WDT underflow occurs while WDF1 flag is “1,” WDF2 flag is set to “1” and the watchdog reset signal is output. ➄ The output transistor of RESET pin is turned “ON ” by the watchdog reset signal and system reset is executed. Note: The number of count is equal to the number of machine cycle because the count source of watchdog timer is the instruction clock. FFFF 16 000016 ➁ ➁

Rev.1.02 2006.12.22 page 37 of 140 REJ03B0147-0102 Fig. 29 Program example to start/stop watchdog timer Fig. 30 Program example to enter the RAM back-up mode when using the watchdog timer WRST ; WDF1 flag cleared NOP DI ; Interrupt disabled EPOF ; POF instruction enabled POF ; RAM back-up mode Oscillation stop

• ••
• •• When the watchdog timer is used, clear the WDF1 flag at the period of 65534 machine cycles or less with the WRST instruction. When the watchdog timer is not used, execute the DWDT instruction and the WRST instruction continuously (refer to Figure 29). The watchdog timer is not stopped with only the DWDT instruction. The contents of WDF1 flag and timer WDT are initialized at the RAM back-up mode. When using the watchdog timer and the RAM back-up mode, initial- ize the WDF1 flag with the WRST instruction just before the microcomputer enters the RAM back-up state (refer to Figure 30) Also, set the NOP instruction after the WRST instruction, for the case when a skip is performed with the WRST instruction. WRST ; WDF1 flag cleared DI DWDT ; Wat chdog timer function enabled/disabled WRST ; WEF and WDF1 flags cleared
• ••

Rev.1.02 2006.12.22 page 38 of 140 REJ03B0147-0102 The 4509 Group has a built-in A/D conversion circuit that performs conversion by 10-bit successive comparison method. Table 11 shows the characteristics of this A/D converter. This A/D converter can also be used as an 8-bit comparator to compare analog voltages input from the analog input pin with preset values. Table 11 A/D converter characteristics Characteristics Successive comparison method 10 bits Linearity error: ±2LSB (V DD =2.7 to 5.5 V) Differential non-linearity error: ±0.9LSB (VDD =2.7 to 5.5 V) 31 µs (f(XIN)=6 MHz, f(STCK)=f(XIN)) Parameter Conversion format Resolution Relative accuracy Conversion speed Analog input pin Fig. 31 A/D conversion circuit structure VSS VDD DA converter TABAD Q1 3 Q1 1 Q1 0Q1 2 TADAB 8 8 01 1 Q1 3 Q1 3 Q1 3 (Note 1) TALAQ1 3 TAQ1 TQ1A ADF (1) P20/AIN0 P21/AIN1 P30/AIN2 P31/AIN3 Register A (4) Register B (4) DAC operation signal Comparator 6-channel multi-plexed analog switch Instruction clock A/D control circuit Successive comparison register (AD) (10) A/D interrupt Comparator register (8) Notes 1: This switch is turned ON only when A/D converter is operating and generates the comparison voltage. 2: Writing/reading data to the comparator register is possible only in the comparator mode (Q13=1). The value of the comparator register is retained even when the mode is switched to the A/D conversion mode (Q1 3=0) because it is separated from the successive comparison register (AD). Also, the resolution in the comparator mode is 8 bits because the comparator register consists of 8 bits. (Note 2) D 2/AIN4 D 3/AIN5

Rev.1.02 2006.12.22 page 39 of 140 REJ03B0147-0102 Note: “R ” represents read enabled, and “W ” represents write enabled. (1) A/D control register Q1 Register Q1 is used to select the operation mode and one of analog input pins. Set the contents of this register through register A with the TQ1A instruction. The TAQ1 instruction can be used to transfer the contents of register Q1 to register A. (2) Operating at A/D conversion mode The A/D conversion mode is set by setting the bit 3 of register Q1 to “0.” (3) Successive comparison register AD Register AD stores the A/D conversion result of an analog input in 10-bit digital data format. The contents of the high-order 8 bits of this register can be stored in register B and register A with the TABAD in- struction. The contents of the low-order 2 bits of this register can be stored into the high-order 2 bits of register A with the TALA instruc- tion. However, do not execute these instructions during A/D conversion. When the contents of register AD is n, the logic value of the compari- son voltage V ref generated from the built-in DA converter can be obtained with the reference voltage VDD by the following formula: Logic value of comparison voltage Vref Vref = ✕ n n: The value of register AD (n = 0 to 1023) V DD 1024 Table 12 A/D control registers (4) A/D conversion completion flag (ADF) A/D conversion completion flag (ADF) is set to “1” when A/D conver- sion completes. The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction. The ADF flag is cleared to “0” when the interrupt occurs or when the next instruction is skipped with the skip instruction. (5) A/D conversion start instruction (ADST) A/D conversion starts when the ADST instruction is executed. The conversion result is automatically stored in the register AD. (6) Operation description A/D conversion is started with the A/D conversion start instruction (ADST). The internal operation during A/D conversion is as follows: ➀ When the A/D conversion starts, the register AD is cleared to “000 16.” ➁ Next, the topmost bit of the register AD is set to “1,” and the com- parison voltage Vref is compared with the analog input voltage VIN. ➂ When the comparison result is Vref < VIN, the topmost bit of the register AD remains set to “1.” When the comparison result is Vref > VIN, it is cleared to “0.” The 4509 Group repeats this operation to the lowermost bit of the register AD to convert an analog value to a digital value. A/D conver- sion stops after 62 machine cycles (31 µs when f(XIN) = 6.0 MHz in high-speed mode) from the start, and the conversion result is stored in the register AD. An A/D interrupt activated condition is satisfied and the ADF flag is set to “1” as soon as A/D conversion completes (Figure 32). A/D control register Q1 A/D operation mode selection bit at reset : 00002 at RAM back-up : state retained Q1 2 A/D conversion mode Comparator mode Selected pins A IN0 AIN1 AIN2 AIN3 AIN4 AIN5 Not available Not available Q1 1 Q1 0 Q1 2 Q1 0 Analog input pin selection bits R/W TAQ1/TQ1A

Rev.1.02 2006.12.22 page 40 of 140 REJ03B0147-0102 Table 13 Change of successive comparison register AD during A/D conversion Comparison voltage (Vref) valueChange of successive comparison register ADAt starting conversion ✼ 1: 1st comparison result ✼ 3: 3rd comparison result ✼ 9: 9th comparison result ✼ 2: 2nd comparison result ✼ 8: 8th comparison result ✼ A: 10th comparison result 1st comparison 2nd comparison 3rd comparison After 10th comparison completes ✼ 1 ✼ 1 ✼ 1 ----- ----- ----- ----- ✼ 2 ✼ 2 ✼ 3 ✼ 8 ✼ 9 ✼ A A/D conversion result V DD VDD VDD VDD VDD VDD VDD VDD 1024 ○○○ ○ Fig. 33 Setting registers A/D control register Q1 A IN0 pin selected A/D conversion mode 0000 (Bit 3) (Bit 0) (7) A/D conversion timing chart Figure 32 shows the A/D conversion timing chart. Fig. 32 A/D conversion timing chart (8) How to use A/D conversion How to use A/D conversion is explained using as example in which the analog input from P20/AIN0 pin is A/D converted, and the high-or- der 4 bits of the converted data are stored in address M(Z, X, Y) = (0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1), and the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM. The A/ D interrupt is not used in this example. ➀ Select the A IN0 pin function and A/D conversion mode with the register Q1 (refer to Figure 33). ➁ Execute the ADST instruction and start A/D conversion. ➂ Examine the state of ADF flag with the SNZAD instruction to de- termine the end of A/D conversion. ➃ Transfer the low-order 2 bits of converted data to the high-order 2 bits of register A (TALA instruction). ➄ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2). ➅ Transfer the high-order 8 bits of converted data to registers A and B (TABAD instruction). ➆ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1). ➇ Transfer the contents of register B to register A, and then, store into M(Z, X, Y) = (0, 0, 0). A D S T i n s t r u c t i o n A / D c o n v e r s i o n c o m p l e t i o n f l a g A D F 6 2 m a c h i n e c y c l e s D A C o p e r a t i o n s i g n a l

Rev.1.02 2006.12.22 page 41 of 140 REJ03B0147-0102 (9) Operation at comparator mode The A/D converter is set to comparator mode by setting bit 3 of the register Q1 to “1.” Below, the operation at comparator mode is described. (10) Comparator register In comparator mode, the built-in DA comparator is connected to the 8-bit comparator register as a register for setting comparison volt- ages. The contents of register B is stored in the high-order 4 bits of the comparator register and the contents of register A is stored in the low-order 4 bits of the comparator register with the TADAB instruc- tion. When changing from A/D conversion mode to comparator mode, the result of A/D conversion (register AD) is undefined. However, because the comparator register is separated from register AD, the value is retained even when changing from comparator mode to A/D conversion mode. Note that the comparator register can be written and read at only comparator mode. If the value in the comparator register is n, the logic value of com- parison voltage V ref generated by the built-in DA converter can be determined from the following formula: (11) Comparison result store flag (ADF) In comparator mode, the ADF flag, which shows completion of A/D conversion, stores the results of comparing the analog input voltage with the comparison voltage. When the analog input voltage is lower than the comparison voltage, the ADF flag is set to “1.” The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the interrupt or the skip in- struction. The ADF flag is cleared to “0” when the interrupt occurs or when the next instruction is skipped with the skip instruction. (12) Comparator operation start instruction (ADST instruction) In comparator mode, executing ADST starts the comparator operat- ing. The comparator stops 8 machine cycles after it has started (6 µs at f(XIN) = 4.0 MHz in high-speed through mode). When the analog in- put voltage is lower than the comparison voltage, the ADF flag is set to “1.” (13) Notes for the use of A/D conversion 1

• TALA instruction When the TALA instruction is executed, the low-order 2 bits of reg- ister AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is “0.”
• Operating mode of A/D converter Do not change the operating mode (both A/D conversion mode and comparator mode) of A/D converter with the bit 3 of register Q1 while the A/D converter is operating. Clear the bit 2 of register V2 to “0” to change the operating mode from the comparator mode to A/D conversion mode. The A/D conversion completion flag (ADF) may be set when the operating mode of the A/D converter is changed from the compara- tor mode to the A/D conversion mode. Accordingly, set a value to the bit 3 of register Q1, and execute the SNZAD instruction to clear the ADF flag. Logic value of comparison voltage Vref Vref = ✕ n n: The value of register AD (n = 0 to 255) Fig. 34 Comparator operation timing chart VDD 256 ADST instruction C o m p a r i s o n r e s u l t s t o r e f l a g A D F 8 m a c h i n e c y c l e s D A C o p e r a t i o n s i g n a l C o m p a r a t o r o p e r a t i o n c o m p l e t e d . T h e v a l u e o f A D F i s d e t e r m i n e d

Rev.1.02 2006.12.22 page 42 of 140 REJ03B0147-0102 (14) Definition of A/D converter accuracy The A/D conversion accuracy is defined below (refer to Figure 35).

• Relative accuracy ➀ Zero transition voltage (V0T) This means an analog input voltage when the actual A/D con- version output data changes from “0” to “1.” ➁ Full-scale transition voltage (VFST ) This means an analog input voltage when the actual A/D con- version output data changes from “1023” to ”1022.” ➂ Linearity error This means a deviation from the line between V0T and VFST of a converted value between V0T and VFST . ➃ Differential non-linearity error This means a deviation from the input potential difference re- quired to change a converter value between V0T and VFST by 1 LSB at the relative accuracy.
• Absolute accuracy This means a deviation from the ideal characteristics between 0 to V DD of actual A/D conversion characteristics. Fig. 35 Definition of A/D conversion accuracy VFST –V0T 1022 VDD 1024 Vn: Analog input voltage when the output data changes from “n” to
• 1LSB at relative accuracy → (V)
• 1LSB at absolute accuracy → (V) VDDV1022VnV1V0 Vn+1 n+1 n 1023 b a c O u t p u t d a t a Differential non-linearity error = Linearity error = [ L S B ] c a b – a a [ L S B ] Actual A/D conversion characteristics a : 1 L S B b y r e l a t i v e a c c u r a c y b Vn Vn c D i f f e r e n c e b e t w e e n i d e a l Vn a n d a c t u a l Vn Zero transition voltage (V0T) Analog voltage Full-scale transition voltage (VFST ) I d e a l l i n e o f A / D c o n v e r s i o n b e t w e e n V0–

Rev.1.02 2006.12.22 page 43 of 140 REJ03B0147-0102 Synchronous circuit Serial interface counter (3)SIOF Serial interface interrupt INSTCK P02/SCK SCK QS R MSB Serial interface register (8) LSBSIN J11 J10 J13J12 Register B (4) Register A (4) TSIAB TABSITABSI SOUT P01/SOUT P00/SIN SST instruction Internal reset signal SERIAL INTERFACE The 4509 Group has a built-in clock synchronous serial interface which can serially transmit or receive 8-bit data. Serial interface consists of;

• Serial interface register SI
• Serial interface control register J1
• Serial interface transmit/receive completion flag (SIOF)
• Serial interface counter Registers A and B are used to perform data transfer with internal CPU. The pin functions of the serial interface pins can be set with the reg- ister J1. Table 14 Serial interface pins Pin P02/SCK P01/SOUT P03/SIN Pin function when selecting serial interface Clock I/O (SCK ) Serial data output (SOUT ) Serial data input (SIN) Fig. 36 Serial interface structure Table 15 Serial interface control register Note: “R ” represents read enabled, and “W ” represents write enabled. Note: Even when the SIN pin function is used, the I/O of port P00 is valid. Even when the SOUT pin function is used, the input of port P01 is valid. The input of P02 can be used even when SCK is used. Be careful when using inputs of both SCK and P02 since the input threshold value of SCK pin is different from that of port P02. J13 Serial interface synchronous clock selection bits Serial interface port function selection bits Serial interface control register J1 at RAM back-up : state retainedat reset : 00002 J13 J12 J11 J10 Synchronous clock Instruction clock (INSTCK) divided by 8 Instruction clock (INSTCK) divided by 4 Instruction clock (INSTCK) divided by 2 External clock (S CK input) Port function P00, P01,P02 selected/SIN, SOUT , SCK not selected P00, SOUT , SCK selected/SIN, P01, P02 not selected SIN, P01, SCK selected/P00, SOUT , P02 not selected SIN, SOUT , SCK selected/P00, P01,P02 not selected R/W TAJ1/TJ1A

Rev.1.02 2006.12.22 page 44 of 140 REJ03B0147-0102 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 At transmit (D7–D 0: transfer data) At receive D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 SIN pin SOUT pin SOUT pin SIN pin Serial interface register (SI)Serial interface register (SI) D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 7 D 6 D 5 D 4 D 3 D 2 D 0 D 1 D 0 Transfer data set Transfer start Transfer complete Fig. 37 Serial interface register state when transferring (1) Serial interface register SI Serial interface register SI is the 8-bit data transfer serial/parallel conversion register. Data can be set to register SI through registers A and B with the TSIAB instruction. The contents of register A is transmitted to the low-order 4 bits of register SI, and the contents of register B is transmitted to the high-order 4 bits of register SI. During transmission, each bit data is transmitted LSB first from the lowermost bit (bit 0) of register SI, and during reception, each bit data is received LSB first to register SI starting from the topmost bit (bit 7). When register SI is used as a work register without using serial in- terface, do not select the S CK pin. (2) Serial interface transmit/receive completion flag (SIOF) Serial interface transmit/receive completion flag (SIOF) is set to “1” when serial data transmission or reception completes. The state of SIOF flag can be examined with the skip instruction (SNZSI). Use the interrupt control register V2 to select the interrupt or the skip instruction. The SIOF flag is cleared to “0” when the interrupt occurs or when the next instruction is skipped with the skip instruction. (3) Serial interface start instruction (SST) When the SST instruction is executed, the SIOF flag is cleared to “0” and then serial interface transmission/reception is started. (4) Serial interface control register J1 Register J1 controls the synchronous clock, P02/SCK , P01/SOUT and P00/SIN pin function. Set the contents of this register through register A with the TJ1A instruction. The TAJ1 instruction can be used to transfer the contents of register J1 to register A.

Rev.1.02 2006.12.22 page 45 of 140 REJ03B0147-0102 SOUT SRDY signal SCK SIN D 3 SCK SOUT SIN D 3 Master (clock control) Serial interface interrupt enable bit (SNZSI instruction valid) Interrupt control register V2 Serial interface control register J1 Serial interface port S CK,SOUT, SIN Instruction clock/8 selected as synchronous clock Slave (external clock) Serial interface interrupt enable bit (SNZSI instruction valid) (Bit 3) (Bit 0) 100 ✕0 ✕✕ ✕ : Set an arbitrary value. Serial interface control register J1 Serial interface port SCK,SOUT, SIN (Bit 3) (Bit 0) (Bit 3) (Bit 0) Interrupt control register V2 (Bit 3) (Bit 0) External clock selected as synchronous clock (5) How to use serial interface Figure 38 shows the serial interface connection example. Serial in- terface interrupt is not used in this example. In the actual wiring, pull up the wiring between each pin with a resistor. Figure 38 shows the data transfer timing and Table 16 shows the data transfer sequence. Fig. 38 Serial interface connection example

Rev.1.02 2006.12.22 page 46 of 140 REJ03B0147-0102 M 0–M 7: Contents of master serial interface register S0–S7: Contents of slave serial interface register Rising of SCK : Serial input Falling of SCK : Serial output SIN SOUT Master Slave SCK SST instruction SOUT SIN S0S7’ S1 S2 S3 S4 S5 S6 S7 SST instruction SRDY signal S0S7’ S1 S3 S4 S5 S6 S7 M 0M 7’ M 1 M 2 M 3 M 4 M 5 M 6 M 7 M 0M 7’ M 1 M 2 M 3 M 4 M 5 M 6 M 7 Fig. 39 Timing of serial interface data transfer Table 16 Processing sequence of data transfer from master to slave 1-byte data is serially transferred on this process. Subsequently, data can be transferred continuously by repeating the process from *. When an external clock is selected as a synchronous clock, control the clock externally because serial transfer is performed as long as clock is externally input. (Unlike an internal clock, an external clock is not stopped when serial transfer is completed.) However, the Master (transmission) [Initial setting]

• Setting the serial interface control register J1 and inter- rupt control register V2 shown in Figure 38. TJ1A and TV2A instructions
• Setting the port received the reception enable signal RDY ) to the input mode. (Port D3 is used in this example) SD instruction * [Transmission enable state]
• Storing transmission data to serial interface register SI. TSIAB instruction [Transmission]
• Check port D3 is “L” level. SZD instruction
• Serial transfer starts. SST instruction
• Check transmission completes. SNZSI instruction
• Wait (timing when continuously transferring) Slave (reception) [Initial setting]
• Setting serial interface control register J1, and interrupt control register V2 shown in Figure 38. TJ1A and TV2A instructions
• Setting the port transmitted the reception enable signal (SRDY ) and output- ting “H ” level. (Port D3 is used in this example) SD instruction *[Reception enable state]
• The SIOF flag is cleared to “0.” SST instruction
• “L” level (reception possible) is output from port D3. RD instruction [Reception]
• Check reception completes. SNZSI instruction
• “H ” level is output from port D3. SD instruction [Data processing] SIOF flag is set to “1” when the clock is counted 8 times after ex- ecuting the SST instruction. Be sure to set the initial level of the external clock to “H.”

Rev.1.02 2006.12.22 page 47 of 140 REJ03B0147-0102 RESET FUNCTION System reset is performed by the followings:

• “L” level is applied to the RESET pin externally,
• System reset instruction (SRST) is executed,
• Reset occurs by watchdog timer,
• Reset occurs by built-in power-on reset (only for H version)
• Reset occurs by voltage drop detection circuit (only for H version) Then when “H ” level is applied to RESET pin, software starts from address 0 in page 0. Fig. 40 Structure of reset pin and its peripherals Fig. 41 RESET pin input waveform and reset release timing WEF This symbol represents a parasitic diode. 2: Applied potential to RESET pin must be VDD or less. (Note 1) (Note 2) Pull-up transistor RESET pin Notes 1: Voltage drop detection circuit Watchdog reset signal Power-on reset circuit SRST instruction (Note 3) (Note 3) 3: These are equipped with only H version. Internal reset signal RESET 0.3VDD 0.85VDD (Note 1) Notes 1: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. 2: It depends on the internal state at reset. Reset input 1 machine cycle or more Program starts (address 0 in page 0) On-chip oscillator (internal oscillator) is counted 120 to 144 times (Note 2). f(RING) (1) RESET pin input System reset is performed certainly by applying “L” level to RESET pin for 1 machine cycle or more when the following condition is sat- isfied; the value of supply voltage is the minimum value or more of the rec- ommended operating conditions.

Rev.1.02 2006.12.22 page 48 of 140 REJ03B0147-0102 Fig. 42 Power-on reset operation Name D 0, D1 D 2/AIN4, D3/AIN5 D 4, D5 P00/SIN, P01/SOUT , P02/SCK P03 P10 P11/CNTR1 P12/CNTR0 P13/INT P20/AIN0, P21/AIN1 P30/AIN2, P31/AIN3 Notes 1: Output latch is set to “1.” 2: The output structure is N-channel open-drain. 3: Pull-up transistor is turned OFF. Function D 0, D1 D 2, D3 D 4, D5 P00, P01, P02 P03 P10 P11 P12 P13 P20, P21 P30, P31 State High-impedance (Notes 1, 2) High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2) High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2) (2) Power-on reset (only for H version) Reset can be automatically performed at power on (power-on reset) by the built-in power-on reset circuit. When the built-in power-on re- set circuit is used, set the time for the supply voltage to rise from 0 V to the minimum voltage of recommended operating conditions to 100 µs or less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and Vss at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage. (3) System reset instruction (SRST) By executing the SRST instruction, “L” level is output to RESET pin and system reset is performed. Table 17 Port state at reset VDD Power-on Reset released Internal reset signal Reset state Power-on reset circuit output →←100 µs or less Reset state Note: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions.

Rev.1.02 2006.12.22 page 49 of 140 REJ03B0147-0102 Address 0 in page 0 is set to program counter. Fig. 43 Internal state at reset ✕✕✕✕ (4) Internal state at reset Figure 43 shows internal state at reset (they are the same after sys- tem is released from reset). The contents of timers, registers, flags and RAM except shown in Figure 43 are undefined, so set the initial value to them. 00000000000000 0 (Interrupt disabled) 0 0 0 0 (Interrupt disabled) 0 0 0 0 (Interrupt disabled) 0000 0 (Prescaler stopped) 0 0 0 0 (Timer 1 stopped) 0 0 0 0 (Timer 2 stopped) 0000 0000 1101 0 (On-chip oscillator operating) 0 0 0 0 (Serial interface port not selected) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ✕✕✕ 0000 0000 111

Rev.1.02 2006.12.22 page 50 of 140 REJ03B0147-0102 EPOF instruction +POF instruction Q S R SVDE instruction Internal reset signal Voltage drop detection circuit Reset signal VRS T Voltage drop detection circuit Internal reset signal Key-on wakeup signa QS R VRST (reset release voltage)+ VDD Voltage drop detection circuit Reset signal Microcomputer starts operation after on-chip oscillator (internal oscillator) clock is counted 120 to 144 times. V RST (reset occurrence voltage) RESET pin Note: Detection voltage hysteresis of voltage drop detection circuit is 0.2 V (Typ). VOLTAGE DROP DETECTION CIRCUIT (only for H version) The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer by outputting “L” level to RESET pin if the supply voltage drops below a set value. Fig. 44 Voltage drop detection reset circuit Fig. 45 Voltage drop detection circuit operation waveform Table 18 Voltage drop detection circuit operation state (1) SVDE instruction If the SVDE instruction is not executed (initial state), the voltage drop detection circuit becomes invalid at RAM back-up mode. When the SVDE instruction is executed, the voltage drop deteciton circuit is valid even after system enters into the RAM back-up mode. The SVDE instruction can be executed only once. In order to release the execution of the SVDE instruction, the system reset is required. At CPU operating Valid Valid At RAM back-up mode Invalid Valid SVDE instruction not executed SVDE instruction executed

Rev.1.02 2006.12.22 page 51 of 140 REJ03B0147-0102 RAM BACK-UP MODE The 4509 Group has the RAM back-up mode. When the POF instruction is executed continuously after the EPOF instruction, system enters the RAM back-up state. The POF instruction is equal to the NOP instruction when the EPOF instruction is not executed before the POF instruction. As oscillation stops retaining RAM, the function of reset circuit and states at RAM back-up mode, current dissipation can be reduced without losing the contents of RAM. Table 19 shows the function and states retained at RAM back-up. Figure 46 shows the state transition. (1) Identification of the start condition Warm start (return from the RAM back-up state) or cold start (return from the normal reset state) can be identified by examining the state of the power down flag (P) with the SNZP instruction. (2) Warm start condition When the external wakeup signal is input after the system enters the RAM back-up state by executing the EPOF instruction and POF in- struction continuously, the CPU starts executing the program from address 0 in page 0. In this case, the P flag is “1.” (3) Cold start condition The CPU starts executing the program from address 0 in page 0 when;

• “L” level is applied to RESET pin,
• system reset (SRST) is performed,
• reset by watchdog timer is performed,
• reset by the built-in power-on reset circuit is performed (only for H version), or
• reset by the voltage drop detection circuit is performed (only for H version). In this case, the P flag is “0.” Table 19 Functions and states retained at RAM back-up Function Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2) Contents of RAM Interrupt control registers V1, V2 Interrupt control register I1 Selected oscillation circuit (execution of CRCK) Clock control register MR Clock control register RG Timer 1, Timer 2 function Watchdog timer function Timer control register PA Timer control registers W1, W2 Timer control registers W5, W6 Serial interface function Serial interface control register J1 A/D conversion function A/D control register Q1 Voltage drop detection circuit Port level Key-on wakeup control registers K0 to K2, L1 Pull-up control registers PU0 to PU2 Port output structure control registers FR0 to FR3, C1 External interrupt request flag (EXF0) Timer interrupt request flags (T1F, T2F) A/D conversion completion flag (ADF) Serial interface transmit/receive completion flag (SIOF) Interrupt enable flag (INTE) Watchdog timer flags (WDF1, WDF2) Watchdog timer enable flag (WEF) RAM back-up O O O (Note 3) ✕ (Note 4) O O O (Note 5) O O O O (Note 3) ✕ (Note 4) ✕ (Note 4) Notes 1:“O ” represents that the function can be retained, and “✕ ” represents that the function is initialized. Registers and flags other than the above are undefined at RAM back-up, and set an initial value after returning. 2: The stack pointer (SP) points the level of the stack register and is initialized to “7” at RAM back-up. 3: The state of the timer is undefined. 4: Initialize the watchdog timer flag WDF1 with the WRST instruction, and then set the system to be in the RAM back-up mode. 5: The voltage drop detection circuit is equipped with only H version. In the RAM back-up mode, when the SVDE instruction is not ex- ecuted, the voltage drop detection circuit is invalid, and when the SVDE instruction is executed, the voltage drop detection circuit is valid.

Rev.1.02 2006.12.22 page 52 of 140 REJ03B0147-0102 (4) Return signal An external wakeup signal is used to return from the RAM back-up mode because the oscillation is stopped. Table 20 shows the return condition for each return source. (5) Control registers

• Key-on wakeup control register K0 Register K0 controls the port P0 key-on wakeup function. Set the contents of this register through register A with the TK0A instruc- tion. In addition, the TAK0 instruction can be used to transfer the contents of register K0 to register A.
• Key-on wakeup control register K1 Register K1 controls the port P1 key-on wakeup function. Set the contents of this register through register A with the TK1A instruc- tion. In addition, the TAK1 instruction can be used to transfer the contents of register K1 to register A.
• Key-on wakeup control register K2 Register K2 controls the ports P2, D 2 and D3 key-on wakeup func- tion. Set the contents of this register through register A with the TK2A instruction. In addition, the TAK2 instruction can be used to transfer the contents of register K2 to register A.
• Key-on wakeup control register L1 Register L1 controls the selection of the return condition and valid waveform/level of port P1, and the selection of the INT pin return condition and INT pin key-on wakeup function. Set the contents of this register through register A with the TL1A instruction. In addi- tion, the TAL1 instruction can be used to transfer the contents of register L1 to register A. Table 20 Return source and return condition Remarks The key-on wakeup function can be selected by one port unit. Set the port using the key-on wakeup function to “H ” level before going into the RAM back-up state. The key-on wakeup function can be selected by one port unit. Select the return level (“L” level or “H ” level) and return condition (level or edge) with the register L1 according to the external state before going into the RAM back-up state. Before going into the RAM backup state, set an opposite level of the selected return level (edge) to the port using the key-on wakeup function. The key-on wakeup function can be selected by one port unit. Select the return level (“L” level or “H ” level) with the register I1 and return condition (level or edge) with the register L1 according to the external state before going into the RAM back-up state. Return condition Return by an external “L” level in- put. Return by an external “H ” level or “L” level input, or falling edge Return by an external “H ” level or “L” level input, or falling edge When the return level is input, the EXF0 flag is not set. External wakeup signal Return source Port P00–P03 Port P20, P21 Port D2, D3 Port P1 0–P1 3 INT pin
• Pull-up control register PU0 Register PU0 controls the ON/OFF of the port P0 pull-up transis- tor. Set the contents of this register through register A with the TPU0A instruction. In addition, the TAK1 instruction can be used to transfer the contents of register K0 to register A.
• Pull-up control register PU1 Register PU1 controls the ON/OFF of the port P1 pull-up transis- tor. Set the contents of this register through register A with the TPU1A instruction. In addition, the TAPU1 instruction can be used to transfer the contents of register PU1 to register A.
• Pull-up control register PU2 Register PU2 controls the ON/OFF of the ports P2, D 2 and D3 pull- up transistor. Set the contents of this register through register A with the TPU2A instruction. In addition, the TAPU2 instruction can be used to transfer the contents of register PU2 to register A.
• Interrupt control register I1 Register I1 controls the valid waveform/level of the external 0 inter- rupt and the input control of INT pin. Set the contents of this register through register A with the TI1A instruction. In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A.

Rev.1.02 2006.12.22 page 53 of 140 REJ03B0147-0102 Fig. 46 State transition Fig. 47 Set source and clear source of the P flag Fig. 48 Start condition identified example using the SNZP in- struction R e s e t ( N o t e A O p e r a t i o n s o u r c e c l o c k f R I N G O n c h i p o s c i l l a t o r B O p e r a t i o n s o u r c e c l o c k f XI N ) C e r a m i c r e s o n a t o r o p e r a t i n g C O p e r a t i o n s o u r c e c l o c k f XI N ) R C o s c i l l a t i o n C R C K i n s t r u c t i o n n o e x e c u t i o n C R C K i n s t r u c t i o n e x e c u t i o n POF instruction execution (Note 5) P O F i n s t r u c t i o n e x e c u t i o n D R A M b a c k u p f R I N G s t o p f XI N ) s t o p P O F i n s t r u c t i o n e x e c u t i o n O p e r a t i n g s t a t e Key-on wakeup (Note 6) O p e r a t i n g s t a t e O p e r a t i n g s t a t e Operating state H i g h s p e e d m o d e N o t e (Note 5) I n t e r n a l m o d e N o t e N o t e N o t e M R 0)←0( M R 0)←1 Notes 1: Microcomputer starts its operation after counting f(RING) 120 to 144 times from system is released from reset. 2: When changing the operation source clock from f(RING) to f(XIN), first make the setting to enable f(XIN) oscillation (set MR1 to “0”), allow the oscillation stabilization time to elapse using software, and then set the operation source clock to f(XIN) (set MR0 to “0”). After this, stop f(RING) (set RG0 to “1”). (Do not start f(XIN) oscillation and change the operation source clock at the same time.) 3: When changing the operation source clock from f(XIN) to f(RING), first make the setting to enable f(RING) oscillation (set RG0 to “0”), allow the oscillation stabilization time to elapse using software, and then set the operation source clock to f(RING) (set MR0 to “1”). After this, stop f(XIN) (set MR1 to “1”). (Do not change the operation source clock and stop f(XIN) at the same time.) 4: After system is released from reset, the ceramic oscillation circuit is selected for the main clock f(XIN). When the RC oscillation circuit is used, execute the CRCK instruction. 5: Continuous execution of the EPOF instruction and the POF instruction is required to go into the RAM back-up state. 6: Microcomputer starts its operation after counting f(RING) 120 to 144 times. System returns to state A certainly when returning from the RAM back-up mode. The operation mode (system clock frequency divided) also returns to the initial state (internal frequency divided by 8 mode) (registers RG and MR initialized). However, the selected contents (CRCK instruction execution state) of f(X IN) oscillation circuit is retained. S R Q Power down flag PPOF instruction Reset input G Set source G Clear source Reset input EPOF instruction POF instructionEPOF instruction + + Program start P = “1” Yes Warm startCold start No SNTP

Rev.1.02 2006.12.22 page 54 of 140 REJ03B0147-0102 Table 21 Key-on wakeup control register K03 K02 K01 K00 Key-on wakeup control register K0 Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Port P0 3 key-on wakeup control bit Port P02 key-on wakeup control bit Port P0 1 key-on wakeup control bit Port P0 0 key-on wakeup control bit at reset : 00002 at RAM back-up : state retained K13 K12 K11 K10 Key-on wakeup control register K1 Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Port P1 3 key-on wakeup control bit Port P1 2 key-on wakeup control bit Port P11 key-on wakeup control bit Port P1 0 key-on wakeup control bit at reset : 00002 at RAM back-up : state retained K23 K22 K21 K20 Key-on wakeup control register K2 Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Port D 3 key-on wakeup control bit Port D2 key-on wakeup control bit Port P2 1 key-on wakeup control bit Port P2 0 key-on wakeup control bit at reset : 00002 at RAM back-up : state retained R/W TAK0/TK0A R/W TAK1/TK1A R/W TAK2/TK2A L13 L12 L11 L10 Key-on wakeup control register L1 Return by level Return by edge Falling waveform/“L” level Rising waveform/“H ” level Return by level Return by edge Key-on wakeup not used Key-on wakeup used Ports P1 0–P13 return condition selection bit Ports P1 0–P13 valid waveform/ level selection bit INT pin return condition selection bit INT pin key-on wakeup control bit at reset : 00002 at RAM back-up : state retained R/W TAL1/TL1A Notes 1: “R ” represents read enabled, and “W ” represents write enabled.

Rev.1.02 2006.12.22 page 55 of 140 REJ03B0147-0102 Table 22 Pull-up control register and interrupt control register PU0 3 PU0 2 PU0 1 PU0 0 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Port P0 3 pull-up transistor control bit Port P02 pull-up transistor control bit Port P0 1 pull-up transistor control bit Port P0 0 pull-up transistor control bit Pull-up control register PU0 at reset : 00002 at RAM back-up : state retained R/W TAPU0/TPU0A PU1 3 PU1 2 PU1 1 PU1 0 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Port P1 3 pull-up transistor control bit Port P1 2 pull-up transistor control bit Port P1 1 pull-up transistor control bit Port P10 pull-up transistor control bit Pull-up control register PU1 at reset : 00002 at RAM back-up : state retained PU2 3 PU2 2 PU2 1 PU2 0 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Port D 3 pull-up transistor control bit Port D2 pull-up transistor control bit Port P2 1 pull-up transistor control bit Port P2 0 pull-up transistor control bit Pull-up control register PU2 at reset : 00002 at RAM back-up : state retained Notes 1: “R ” represents read enabled, and “W ” represents write enabled. R/W TAPU1/TPU1A R/W TAPU2/TPU2A

Rev.1.02 2006.12.22 page 56 of 140 REJ03B0147-0102 The clock control circuit consists of the following circuits.

• On-chip oscillator (internal oscillator)
• Ceramic oscillation circuit
• RC oscillation circuit
• Multi-plexer (clock selection circuit)
• Frequency divider
• Internal clock generating circuit Fig. 49 Clock control circuit structure The system clock and the instruction clock are generated as the source clock for operation by these circuits. Figure 49 shows the structure of the clock control circuit. The 4509 Group operates by the on-chip oscillator clock (f(RING)) which is the internal oscillator after system is released from reset. Also, the ceramic resonator or the RC oscillation can be used for the source oscillation (f(X IN)) of the 4509 Group. MR 3, MR 2 QS R CRCK instruction QS R XOUT XIN Key-on wakeup signal Instruction clock (INSTCK) RC oscillation circuit Division circuit Internal clock generation circuit (divided by 3) System clock On-chip oscillator Multiplexer Ceramic resonator circuit EPOF instruction + POF instruction MR 1 Q RG 0 Internal reset signal MR 0 1f(RING) f(XIN) divided by 2 divided by 4 divided by 8

Rev.1.02 2006.12.22 page 57 of 140 REJ03B0147-0102 Fig. 50 Switch to ceramic oscillation/RC oscillation Fig. 51 Handling of XIN and XOUT when main clock is not used Fig. 52 Ceramic resonator external circuit Fig. 53 External RC circuit Do not execute the CRCK instruction in program. Note: Externally connect a damping resistor Rd depending on the oscillation frequency. (A feedback resistor is built-in.) Use the resonator manu- facturer’s recommended value because constants such as ca- pacitance depend on the resonator. (1) On-chip oscillator operation After system is released from reset, the MCU starts operation by the clock output from the on-chip oscillator which is the internal oscilla- tor. The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. (2) Main clock generating circuit (f(XIN)) The ceramic resonator or RC oscillation can be used for the main clock of this product. After system is released from reset, the ceramic oscillation is active for main clock. The ceramic oscillation is invalid and the RC oscillation circuit is valid with the CRCK instruction. Execute the CRCK instruction in the initial setting routine of program (executing it in address 0 in page 0 is recommended). The execution of the CRCK instruction can be valid only once. Register MR controls the enable/disable of the oscillation and the selection of the operation source clock. Also, when the MCU operates only by the on-chip oscillator without using main clock f(X IN), connect XIN pin to Vss and leave XOUT pin open, and do not execute the CRCK instruction (Figure 51). (3) Ceramic resonator When the ceramic resonator is used as the main clock (f(XIN)), con- nect the ceramic resonator and the external circuit to pins XIN and XOUT at the shortest distance. A feedback resistor is built in between pins XIN and XOUT (Figure 52). Do not execute the CRCK instruction. Set “0” to bit 0 of register MR after the oscillation stabilizing wait time is generated by software to select the clock generated by the ceramic oscillation circuit for the source oscillation clock. (4) RC oscillation When the RC oscillation is used as the main clock (f(XIN)), connect the XIN pin to the external circuit of resistor R and the capacitor C at the shortest distance and leave XOUT pin open. Then, execute the CRCK instruction (Figure 53). The frequency is affected by a capacitor, a resistor and a microcom- puter. So, set the constants within the recommended operating condition of the frequency limits. Reset CRCK instruction

• Ceramic oscillation invalid
• RC oscillation valid
• Ceramic oscillation valid
• RC oscillation invalid Main clock f(XIN) 4509 XIN XOUT Do not execute the CRCK instruction in program. 4509 XIN XOUTR C Execute the CRCK instruction in program. 4509 XIN XOUT Rd C IN C OUT

Rev.1.02 2006.12.22 page 58 of 140 REJ03B0147-0102 (5) External clock When the external signal clock is used for the main clock (f(XIN)), connect the XIN pin to the clock source and leave XOUT pin open (Figure 54). Do not execute the CRCK instruction in program. Be careful that the maximum value of the oscillation frequency when using the external clock differs from the value when using the ce- ramic resonator (refer to the recommended operating condition). Also, note that the RAM back-up mode (POF instruction) cannot be used when using the external clock. (6) Clock control register MR Register MR controls the selection of operation mode and the opera- tion source clock, and enable/stop of main clock. Set the contents of this register through register A with the TMRA instruction. In addition, the TAMR instruction can be used to transfer the contents of register MR to register A. (7) Clock control register RG Register RG controls the on-chip oscillator. Set the contents of this register through register A with the TRGA instruction. Table 23 Clock control register MR Fig. 54 External clock input circuit 4509 XIN XOUT External oscillation circuit VDD VSS Do not execute the CRCK instruction in program.* Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: Main clock cannot be stopped when the main clock is selected for the operation source clock. 3: The stopped clock cannot be selected for the operation source clock. In order to switch the operation source clock, generate the oscillation stabiliz- ing wait time by software first and set the oscillation of the destination clock to be enabled. 4: On-chip oscillator cannot be stopped when the on-chip oscillator is selected for the operation source clock. 5: When changing the setting of MR1 and MR0 from “00” to “11”, make settings in the sequence “00” → “01” → “11”. When changing the setting of MR1 and MR0 from “11” to “0”, make settings in the sequence “11” → “01” → “00”. MR 3 Clock control register MR Operation mode Through mode (frequency not divided) Frequency divided by 2 mode Frequency divided by 4 mode Frequency divided by 8 mode Main clock (f(X IN)) oscillation enabled Main clock (f(XIN)) oscillation stop Main clock (f(XIN)) On-chip oscillator clock (f(RING)) at reset : 11012 at RAM back-up : 11012 MR 3 R/W TAMR/TMRA Main clock f(XIN) control bit (Notes 2, 5) Operation source clock selection bit (Notes 3, 5) Operation mode selection bits MR MR 1 MR 0 MR 2 On-chip oscillator (f(RING)) oscillation enabled On-chip oscillator (f(RING)) oscillation stop On-chip oscillator (f(RING)) control bit (Note 4) Clock control register RG W TRGAat RAM back-up : 02at reset : 02 RG 0

Rev.1.02 2006.12.22 page 59 of 140 REJ03B0147-0102 QzROM Writing Mode In the QzROM writing mode, the user ROM area can be rewritten while the microcomputer is mounted on-board by using a serial pro- grammer which is applicable for this microcomputer. Table 24 lists the pin description (QzROM writing mode) and Figure 55 shows the pin connections. Refer to Figure 56 for examples of a connection with a serial pro- grammer. Contact the manufacturer of your serial programmer for serial pro- grammer. Refer to the user’s manual of your serial programmer for details on how to use it. Table 24 Pin description (QzROM writing mode)

• Power supply voltage pin.
• GND pin.
• QzROM programmable power source pin.
• V PP input is possible with VSS connected via a resistor of about 5 kΩ.
• QzROM serial data I/O pin.
• QzROM serial clock input pin.
• QzROM read/program pulse input pin.
• Reset input pin.
• Input “L” level signal.
• Either connect an oscillation circuit or connect XIN pin to VSS and leave the XOUT pin open.
• Input “H ” or “L” level signal or leave the pin open. VDD VSS CNV SS P20/AIN0 P21/AIN1 D 3/AIN5 RESET XIN XOUT D 0, D1, D2/AIN4, D4, D5, P00/SIN, P01/SOUT , P02/SCK , P03, P10, P11/CNTR1, P12/CNTR0, P13/INT, P30/AIN2, P31/AIN3 Power source GND V PP input SDA input/output SCLK input PGM input Reset input Clock input Clock output I/O port FunctionPin Name I/O Input Input Input I/O I/O

Rev.1.02 2006.12.22 page 60 of 140 REJ03B0147-0102 Fig. 55 Pin connection diagram 1kΩ P10 P11/CNTR1 P12/CNTR0 P13/INT D 0 D 1 P01/SOUT P00/SIN P31/AIN3 P30/AIN2 P03 P02/SCK 232 223 214 205 196 187 178 169 1510 1411 1312 P21/AIN1 XIN XOUT CNV SS (Note 2) VSS VDDVDD P20/AIN0 RESET D 3/AIN5 D 2/AIN4 D 5 D 4 M34509G4-XXXFPM34509G4FPM34509G4H-XXXFP M34509G4HFPVSS VPP SCLK SDA PGM (Note 1) : QzROM pin Note 1: Either connect an oscillation circuit or connect XIN pin to VSS and leave the XOUT pin open. 2: V PP input is possible with VSS connected via a resistor of about 5 kΩ.

Rev.1.02 2006.12.22 page 61 of 140 REJ03B0147-0102 Fig. 56 When using programmer of Suisei Electronics System Co., LTD, connection example T_VD D T_VP P T_RXD T_TXD T_SC LK T_BUSY N.C. T_PGM/OE/ MD T_RESE T GN D RESET circuit VDD CNV SS P20/AIN0 (SDA) P21/AIN1 (SCLK) D 3/AIN5 (PGM) RESET Vss XIN XOUT 1 kΩ Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF. Either connect an oscillation circuit or connect XIN pin to VSS and leave the XOUT pin open.

Rev.1.02 2006.12.22 page 62 of 140 REJ03B0147-0102 DATA REQUIRED FOR QzROM WRITING ORDERS The following are necessary when ordering a QzROM product shipped after writing: 1. QzROM Writing Confirmation Form* 2. Mark Specification Form* * For the QzROM writing confirmation form and the mark specifica- tion form, refer to the “Renesas Technology Corp.” Homepage (http:/ /www.renesas.com/homepage.jsp). Note that we cannot deal with special font marking (customer's trademark etc.) in QzROM microcomputer.

Rev.1.02 2006.12.22 page 63 of 140 REJ03B0147-0102 ➆ Multifunction - The input/output of P00 can be used even when SIN is used. Be careful when using inputs of both SIN and P00 since the input threshold value of SIN pin is different from that of port P00. - The input of P01 can be used even when SOUT is used. - The input of P02 can be used even when SCK is used. Be careful when using inputs of both SCK and P02 since the input threshold value of SCK pin is different from that of port P02. - The input of P11 can be used even when CNTR1 (output) is se- lected. The input/output of P1 1 can be used even when CNTR1 (input) is selected. Be careful when using inputs of both CNTR1 and P11 since the input threshold value of CNTR1 pin is different from that of port P11. - The input of P12 can be used even when CNTR0 (output) is se- lected. The input/output of P1 2 can be used even when CNTR0 (input) is selected. Be careful when using inputs of both CNTR0 and P12 since the input threshold value of CNTR0 pin is different from that of port P12. - The input/output of P13 can be used even when INT is used. Be careful when using inputs of both INT and P13 since the input threshold value of INT pin is different from that of port P13. - The input/output of P20, P21, P30, P31, D2, D3 can be used even when AIN0–AIN5 are used. ➇ Power-on reset (only for H version) When the built-in power-on reset circuit is used, set the time for the supply voltage to rise from 0 V to the minimum voltage of rec- ommended operating conditions to 100 µs or less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and Vss at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage. ➈ POF instruction When the POF instruction is executed continuously after the EPOF instruction, system enters the RAM back-up state. Note that system cannot enter the RAM back-up state when ex- ecuting only the POF instruction. Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction and the POF instruction continu- ously. LIST OF PRECAUTIONS ➀ Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up;

• connect a bypass capacitor (approx. 0.1 µF) between pins VDD and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use relatively thick wire. CNV SS pin is also used as VPP pin. Accordingly, when using this pin, connect this pin to VSS through a resistor about 5 kΩ (connect this resistor to CNVSS /VPP pin as close as possible). ➁ Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recom- mended operating conditions and design a system not to cause errors to the system by this unstable operation. ➂ Register initial values 1 The initial value of the following registers are undefined after sys- tem is released from reset. After system is released from reset, set initial values.
• Register Z (2 bits)
• Register D (3 bits)
• Register E (8 bits) ➃ Register initial values 2 The initial value of the following registers are undefined at RAM back-up. After system is returned from RAM back-up, set initial val- ues.
• Register Z (2 bits)
• Register X (4 bits)
• Register Y (4 bits)
• Register D (3 bits)
• Register E (8 bits) ➄ Program counter Make sure that the PC H does not specify after the last page of the built-in ROM. ➅ Stack registers (SKS) and stack pointer (SP) Stack registers (SKs) are eight identical registers, so that subrou- tines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be care- ful not to over the stack when performing these operations together.

Rev.1.02 2006.12.22 page 64 of 140 REJ03B0147-0102 ➁ Note [2] on bit 3 of register I1 When the bit 3 of register I1 is cleared to “0”, the RAM back-up mode is selected and the input of INT pin is disabled, be careful about the following notes.

• When the INT pin input is disabled (register I1 3 = “0”), set the key- on wakeup of INT pin to be invalid (register L10 = “0”) before system enters to the RAM back-up mode. (refer to Figure 58➀ ). LA 0 ; ( ✕✕✕ 02) DI EPOF POF2 ; RAM back-up ✕ : these bits are not used here. Fig. 58 External 0 interrupt program example-2
• ••
• •• Note [3] on bit 2 of register I1 When the interrupt valid waveform of the P13/INT pin is changed with the bit 2 of register I1 in software, be careful about the fol- lowing notes.
• Depending on the input state of the P1 3/INT pin, the external 0 in- terrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 59➀ ) and then, change the bit 2 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to Figure 59➁ ). Also, set the NOP instruction for the case when a skip is per- formed with the SNZ0 instruction (refer to Figure 59➂ ). LA 4 ; ( ✕✕✕ 0 LA 12 ; (1 ✕✕✕ 2) TI1A ; Interrupt valid waveform is changed SNZ0 ; The SNZ0 instruction is executed (EXF0 flag cleared) ✕ : these bits are not used here. Fig. 59 A/D conversion interrupt program example
• ••
• •• LA 4 ; ( ✕✕✕ 02) LA 8 ; (1 ✕✕✕ 2) TI1A ; Control of INT pin input is changed SNZ0 ; The SNZ0 instruction is executed (EXF0 flag cleared) ✕ : these bits are not used here.
• ••
• •• Fig. 57 External 0 interrupt program example-1 P13/INT pin Note [1] on bit 3 of register I1 When the input of the INT pin is controlled with the bit 3 of regis- ter I1 in software, be careful about the following notes.
• Depending on the input state of the P13/INT pin, the external 0 in- terrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 57➀ ) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to Figure 57➁ ). Also, set the NOP instruction for the case when a skip is per- formed with the SNZ0 instruction (refer to Figure 57➂ ).

Rev.1.02 2006.12.22 page 65 of 140 REJ03B0147-0102 Prescaler Stop prescaler counting and then execute the TABPS instruction to read its data. Stop prescaler counting and then execute the TPSAB instruction to write data to prescaler. Timer count source Stop timer 1 or 2 counting to change its count source. Reading the count value Stop timer 1 or 2 counting and then execute the TAB1 or TAB2 in- struction to read its data. Writing to the timer Stop timer 1 or 2 counting and then execute the T1AB, T1R1L, T2AB or T2R2L instruction to write data to timer. Writing to reload register In order to write a data to the reload register R1H while the timer 1 is operating, execute the T1HAB instruction except a timing of the timer 1 underflow. In order to write a data to the reload register R2H while the timer 2 is operating, execute the T2HAB instruction except a timing of the timer 2 underflow. Prescaler, timer 1 and timer 2 count start timing and count time when operation starts Count starts from the first rising edge of the count source (2) after prescaler and timer operations start (1). Time to first underflow (3) is shorter (for up to 1 period of the count source) than time among next underflow (4) by the timing to start the timer and count source operations after count starts. When selecting CNTR input as the count source of timer, timer operates synchronizing with the count edge (falling edge or rising edge) of CNTR input selected by software. Watchdog timer

• The watchdog timer function is valid after system is released from reset. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously, and clear the WEF flag to “0” to stop the watchdog timer function.
• The contents of WDF1 flag and timer WDT are initialized at the RAM back-up mode.
• When using the watchdog timer and the RAM back-up mode, ini- tialize the WDF1 flag with the WRST instruction just before the microcomputer enters the RAM back-up state. Also, set the NOP instruction after the WRST instruction, for the case when a skip is performed with the WRST instruction. Clock control When the RC oscillation is used as the main clock f(X IN), execute the CRCK instruction in the initial setting routine of program (ex- ecuting it in address 0 in page 0 is recommended). The oscillation circuit by the CRCK instruction can be selected only once. When the CRCK instruction is not executed, the ce- ramic oscillation is selected for the main clock f(X IN). Also, when the MCU operates only by the on-chip oscillator with- out using main clock f(XIN), connect XIN pin to Vss and leave XOUT pin open, and do not execute the CRCK instruction. In order to switch the operation source clock (f(RING)) or f(X IN)), generate the oscillation stabilizing wait time by software first and set the oscillation of the destination clock to be enabled. Registers RG and MR are initialized when system returns from RAM back-up mode. However, the selected contents (CRCK instruction execution state) of main clock (f(X IN)) oscillation circuit is retained. On-chip oscillator The clock frequency of the on-chip oscillator depends on the sup- ply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. Also, when considering the oscillation stabilize wait time for switch- ing clock, be careful that the variable frequency of the on-chip oscillator clock. External clock When the external clock is used for the main clock (f(X IN)), con- nect the XIN pin to the clock source and leave XOUT pin open. Do not execute the CRCK instruction in program. Be careful that the maximum value of the oscillation frequency when using the external clock differs from the value when using the ceramic resonator (refer to the recommended operating condi- tion). Also, note that the RAM back-up mode (POF instruction) cannot be used when using the external clock. PWM signal (PWM1, PWM2) If the timer 1 count stop timing and the timer 1 underflow timing overlap during output of the PWM1 signal, a hazard may occur in the PWM1 output waveform. If the timer 2 count stop timing and the timer 2 underflow timing overlap during output of the PWM2 signal, a hazard may occur in the PWM2 output waveform. Fig. 60 Timer count start timing and count time when operation starts Timer start Count source Timer value Timer underflow signal 3 21032103 ➂ ➃ /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Count source (When falling edge of CNTR input is selected)

Rev.1.02 2006.12.22 page 66 of 140 REJ03B0147-0102 Fig. 62 Analog input external circuit example-1 Fig. 63 Analog input external circuit example-2 LA 8 ; ( ✕ 0✕✕ 2) LA 0 ; (0 ✕✕✕ 2) TQ1A ; Operation mode of A/D converter is changed from comparator mode to A/D conversion mode. SNZAD NOP ✕ : this bit is not related to change the operation mode of A/D converter. Fig. 61 External 0 interrupt program example-3

• ••
• •• Notes for the use of A/D conversion 1
• TALA instruction When the TALA instruction is executed, the low-order 2 bits of reg- ister AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is “0.”
• Do not change the operating mode (both A/D conversion mode and comparator mode) of A/D converter with the bit 3 of register Q1 while the A/D converter is operating.
• Clear the bit 2 of register V2 to “0” to change the operating mode from the comparator mode to A/D conversion mode.
• The A/D conversion completion flag (ADF) may be set when the operating mode of the A/D converter is changed from the compara- tor mode to the A/D conversion mode. Accordingly, set a value to the bit 3 of register Q1, and execute the SNZAD instruction to clear the ADF flag. Sensor AIN A p p l y t h e v o l t a g e w i t h i i n t h e s p e c i f i c a t i o n s t o a n a n a l o g i n p u t p i n Sensor AIN A b o u t kΩ Notes for the use of A/D conversion 2 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage. Accordingly, when the analog voltage is input from the circuit with high-impedance and, charge/dis- charge noise is generated and the sufficient A/D accuracy may not be obtained. Therefore, reduce the impedance or, connect a ca- pacitor (0.01 µF to 1 µF) to analog input pins (Figure 60). When the overvoltage applied to the A/D conversion circuit may occur, connect an external circuit in order to keep the voltage within the rated range as shown the Figure 61. In addition, test the application products sufficiently. 22 23

24 QzROM

(1) Be careful not to apply overvoltage to MCU. The contents of QzROM may be overwritten because of overvoltage. Take care especially at turning on the power. (2) As for the product shipped in blank, Renesas does not perform the writing test to user ROM area after the assembly process though the QzROM writing test is performed enough before the assembly process. Therefore, a writing error of approx.0.1 % may occur. Moreover, please note the contact of cables and for- eign bodies on a socket, etc. because a writing environment may cause some writing errors. Notes On ROM Code Protect (QzROM product shipped after writing) As for the QzROM product shipped after writing, the ROM code protect is specified according to the ROM option setup data in the mask file which is submitted at ordering. The ROM option setup data in the mask file is “00 16” for protect enabled or “FF16” for protect disabled. Note that the mask file which has nothing at the ROM option data or has the data other than “00 16” and “FF16” can not be accepted.

Rev.1.02 2006.12.22 page 67 of 140 REJ03B0147-0102 NOTES ON NOISE Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 1. Shortest wiring length (1) Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the V SS pin with the shortest possible wiring. <Reason> In order to reset a microcomputer correctly, 1 machine cycle or more of the width of a pulse input into the RESET pin is required. If noise having a shorter pulse width than this is input to the RESET input pin, the reset is released before the internal state of the micro- computer is completely initialized. This may cause a program runaway. Fig. 64 Wiring for the RESET pin (2) Wiring for clock input/output pins

• Make the length of wiring which is connected to clock I/O pins as short as possible.
• Make the length of wiring across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcom- puter as short as possible.
• Separate the VSS pattern only for oscillation from other VSS pat- terns. <Reason> If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a po- tential difference is caused by the noise between the V SS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer. RESETReset circuit Noise VSSVSS Reset circuit VSS RESET VSS N.G. O.K. Noise XIN XOUT VSS XIN XOUT VSS N.G. O.K. (3) Wiring to CNVSS pin Connect CNVSS pin to a GND pattern at the shortest distance. The GND pattern is required to be as close as possible to the GND supplied to V SS . In order to improve the noise reduction, to connect a 5 kΩ resistor serially to the CNVSS pin - GND line may be valid. As well as the above-mentioned, in this case, connect to a GND pat- tern at the shortest distance. The GND pattern is required to be as close as possible to the GND supplied to V SS . <Reason> The CNV SS pin of the QzROM is the power source input pin for the built-in QzROM. When programming in the built-in QzROM, the im- pedance of the CNV SS pin is low to allow the electric current for writing flow into the QzROM. Because of this, noise can enter easily. If noise enters the CNV SS pin, abnormal instruction codes or data are read from the built-in QzROM, which may cause a program run- away. Fig. 66 Wiring for the CNVSS pin of the QzPROM About 5kΩ VSS The shortest The shortest CNV SS (Note) (Note) Note: This indicates pin. Fig. 65 Wiring for clock I/O pins

Rev.1.02 2006.12.22 page 68 of 140 REJ03B0147-0102 Fig. 67 Bypass capacitor across the VSS line and the VDD line 2. Connection of bypass capacitor across VSS line and VDD line Connect an approximately 0.1 µF bypass capacitor across the VSS line and the VDD line as follows:

• Connect a bypass capacitor across the VSS pin and the VDD pin at equal length.
• Connect a bypass capacitor across the VSS pin and the VDD pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS line and VDD line.
• Connect the power source wiring via a bypass capacitor to the VSS pin and the VDD pin. VSS VDD /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines VSS VDD /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines N.G. O.K. 3. Wiring to analog input pins
• Connect an approximately 100 Ω to 1 kΩ resistor to an analog sig- nal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible.
• Connect an approximately 1000 pF capacitor across the Vss pin and the analog input pin. Besides, connect the capacitor to the Vss pin as close as possible. Also, connect the capacitor across the analog input pin and the Vss pin at equal length. <Reason> Signals which is input in an analog input pin (such as an A/D con- verter/comparator input pin) are usually output signals from sensor. The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. This long wiring functions as an an- tenna which feeds noise into the microcomputer, which causes noise to an analog input pin. Fig. 68 Analog signal line and a resistor and a capacitor Analog input pin VSS Noise Thermistor Microcomputer N.G. O.K. (Note) Note : The resistor is used for dividing resistance with a thermistor.

Rev.1.02 2006.12.22 page 69 of 140 REJ03B0147-0102 5. Setup for I/O ports Setup I/O ports using hardware and software as follows: <Hardware>

• Connect a resistor of 100 Ω or more to an I/O port in series. <Software>
• As for an input port, read data several times by a program for checking whether input levels are equal or not.
• As for an output port or an I/O port, since the output data may re- verse because of noise, rewrite data to its port latch at fixed periods.
• Rewrite data to pull-up control registers at fixed periods. 6. Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The fol- lowing shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal opera- tion, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing. 4. Oscillator concerns Take care to prevent an oscillator that generates clocks for a micro- computer operation from being affected by other signals. (1) Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as pos- sible from signal lines where a current larger than the tolerance of current value flows. <Reason> In the system using a microcomputer, there are signal lines for con- trolling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs be- cause of mutual inductance. (2) Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. <Reason> Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a pro- gram runaway. Fig. 69 Wiring for a large current signal line XIN XO U T VS S M M i c r o c o m p u t e r Mutual inductance L a r g e c u r r e n t GND (3) Oscillator protection using Vss pattern As for a two-sided printed circuit board, print a Vss pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. Connect the Vss pattern to the microcomputer Vss pin with the shortest possible wiring. Besides, separate this Vss pattern from other Vss patterns. Fig. 71 Vss pattern on the underside of an oscillator /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines XIN XOUT VSS An example of VSS patterns on the underside of a printed circuit board Oscillator wiring pattern example Separate the V SS line for oscillation from other VSS lines XI N XO U T VS S C N T RDo not cross N.G. Fig. 70 Wiring to a signal line where potential levels change fre- quently

Rev.1.02 2006.12.22 page 70 of 140 REJ03B0147-0102 Fig. 72 Watchdog timer by software <The main routine>

• Assigns a single word of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition: N+1 ≥ (Counts of interrupt processing executed in each main rou- tine) As the main routine execution cycle may change because of an in- terrupt processing or others, the initial value N should have a margin.
• Watches the operation of the interrupt processing routine by com- paring the SWDT contents with counts of interrupt processing after the initial value N has been set.
• Detects that the interrupt processing routine has failed and deter- mines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents do not change after interrupt processing. <The interrupt processing routine>
• Decrements the SWDT contents by 1 at each interrupt processing.
• Determines that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents are not initialized to the initial value N but continued to decrement and if they reach 0 or less. Main routine (SWDT) ← N EI M a i n p r o c e s s i n g (SWDT) I n t e r r u p t p r o c e s s i n g r o u t i n e e r r o r s N Interrupt processing routine ( S W D T ) ← ( S W D T ) — 1 I n t e r r u p t p r o c e s s i n g ( S W D T ) M a i n r o u t i n e e r r o r s ≤0 R T I R e t u r n = N ? ≤0?

Rev.1.02 2006.12.22 page 71 of 140 REJ03B0147-0102 CONTROL REGISTERS I13 I12 I11 I10 INT pin input control bit (Note 2) Interrupt valid waveform for INT pin/ return level selection bit (Note 2) INT pin edge detection circuit control bit INT pin timer 1 control enable bit Interrupt control register I1 R/W TAI1/TI1Aat RAM back-up : state retainedat reset : 00002 INT pin input disabled INT pin input enabled Falling waveform (“L” level of INT pin is recognized with the SNZI0 instruction)/“L” level Rising waveform (“H ” level of INT pin is recognized with the SNZI0 instruction)/“H ” level One-sided edge detected Both edges detected Disabled Enabled Interrupt disabled (SNZSI instruction is valid) Interrupt enabled (SNZSI instruction is invalid) Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. R/W TAV2/TV2A V13 V12 V11 V10 V23 V22 V21 V20 Serial interface interrupt enable bit A/D interrupt enable bit Not used Not used Interrupt control register V2 at RAM back-up : 00002at reset : 00002 Interrupt control register V1 Timer 2 interrupt enable bit Timer 1 interrupt enable bit Not used External 0 interrupt enable bit Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) This bit has no function, but read/write is enabled. Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) at RAM back-up : 0000 2at reset : 00002 R/W TAV1/TV1Aat RAM back-up : 00002at reset : 00002 Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. 3: Main clock cannot be stopped when the main clock is selected for the operation source clock. 4: The stopped clock cannot be selected for the operation source clock. In order to switch the operation source clock, generate the oscillation stabiliz- ing wait time by software first and set the oscillation of the destination clock to be enabled. 5: On-chip oscillator cannot be stopped when the on-chip oscillator is selected for the operation source clock. MR 3 Clock control register MR Operation mode Through mode (frequency not divided) Frequency divided by 2 mode Frequency divided by 4 mode Frequency divided by 8 mode Main clock (f(X IN)) oscillation enabled Main clock (f(XIN)) oscillation stop Main clock (f(XIN)) On-chip oscillator clock (f(RING)) at reset : 11012 at RAM back-up : 11012 MR 3 R/W TAMR/TMRA Operation mode selection bits MR MR 1 MR 0 MR 2 On-chip oscillator (f(RING)) oscillation enabled On-chip oscillator (f(RING)) oscillation stop Clock control register RG W TRGAat RAM back-up : 02at reset : 02 RG 0 Main clock f(XIN) control bit (Note 3) Operation source clock selection bit (Note 4) On-chip oscillator (f(RING)) control bit (Note 5)

Rev.1.02 2006.12.22 page 72 of 140 REJ03B0147-0102 Stop (state retained) Operating Count source PWM2 signal Prescaler output (ORCLK) CNTR1 input On-chip oscillator clock (f(RING)) PWM1 function control bit Timer 1 control bit PWM2 function invalid PWM2 function valid Stop (state retained) Operating Count source Timer 1 underflow signal (T1UDF) Prescaler output (ORCLK) CNTR0 input System clock (STCK) PWM2 function control bit Timer 2 control bit Timer 2 count source selection bits Timer control register W1 R/W TAW1/TW1Aat reset : 00002 at RAM back-up : 00002at reset : 00002 Timer control register W2 R/W TAW2/TW2Aat RAM back-up : 00002at reset : 00002 W2 3 W2 2 W2 1 W2 0 Stop (state initialized) Operating Prescaler control bit Timer control register PA W TPAAat RAM back-up : 02at reset : 02 PA 0 P12 (I/O) / CNTR0 (input) P12 (input) /CNTR0 (I/O) Count auto-stop circuit not selected Count auto-stop circuit selected Count start synchronous circuit not selected Count start synchronous circuit selected Falling edge Rising edge 2/CNTR0 pin function selection bit Timer 1 count auto-stop circuit selection bit (Note 2) Timer 1 count start synchronous circuit selection bit (Note 3) CNTR0 pin input count edge selection bit Timer control register W5 at RAM back-up : state retainedat reset : 00002 W5 3 W5 2 W5 1 W5 0 R/W TAW5/TW5A P11 (I/O) / CNTR1 (input) P11 (input) /CNTR1 (I/O) Output auto-control circuit not selected Output auto-control circuit selected INT pin input period count circuit not selected INT pin input period count circuit selected Falling edge Rising edge 1/CNTR1 pin function selection bit CNTR 1 pin output auto-control circuit selection bit Timer 2 INT pin input period count circuit selection bit CNTR1 pin input count edge selection bit Timer control register W6 at RAM back-up : state retainedat reset : 00002 W6 3 W6 2 W6 1 W6 0 R/W TAW6/TW6A Notes 1: “R ” represents read enabled, and “W ” represents write enabled. 2: This function is valid only when the INT pin/timer 1 control is enabled (I10=“1”) and the timer 1 count start synchronous circuit is selected (W51=“1”). 3: This function is valid only when the INT pin/timer 1 control is enabled (I10=“1”). W1 3 W1 2 W1 1 W1 0 W1 1 Timer 1 count source selection bits

Rev.1.02 2006.12.22 page 73 of 140 REJ03B0147-0102 Q1 3 A/D control register Q1 A/D operation mode selection bit at reset : 00002 at RAM back-up : state retained Q1 2 A/D conversion mode Comparator mode Selected pins A IN0 AIN1 AIN2 AIN3 AIN4 AIN5 Not available Not available Q1 1 Q1 1 Q1 0 Q1 2 Q1 0 Analog input pin selection bits R/W TAQ1/TQ1A J13 Serial interface synchronous clock selection bits Serial interface port function selection bits Serial interface control register J1 at RAM back-up : state retainedat reset : 00002 J13 J12 J11 J10 Synchronous clock Instruction clock (INSTCK) divided by 8 Instruction clock (INSTCK) divided by 4 Instruction clock (INSTCK) divided by 2 External clock (S CK input) Port function P00, P01, P02 selected/SIN, SOUT , SCK not selected P00, SOUT , SCK selected/SIN, P01, P02 not selected SIN, P01, SCK selected/P00, SOUT , P02 not selected SIN, SOUT , SCK selected/P00, P01, P02 not selected R/W TAJ1/TJ1A Notes 1: “R ” represents read enabled, and “W ” represents write enabled.

Rev.1.02 2006.12.22 page 74 of 140 REJ03B0147-0102 Key-on wakeup control register K0 Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Port P0 3 key-on wakeup control bit Port P0 2 key-on wakeup control bit Port P0 1 key-on wakeup control bit Port P00 key-on wakeup control bit at reset : 00002 at RAM back-up : state retained K13 K12 K11 K10 Key-on wakeup control register K1 Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Port P1 3 key-on wakeup control bit Port P12 key-on wakeup control bit Port P1 1 key-on wakeup control bit Port P1 0 key-on wakeup control bit at reset : 00002 at RAM back-up : state retained K23 K22 K21 K20 Key-on wakeup control register K2 Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Port D 3 key-on wakeup control bit Port D 2 key-on wakeup control bit Port P2 1 key-on wakeup control bit Port P20 key-on wakeup control bit at reset : 00002 at RAM back-up : state retained R/W TAK0/TK0A R/W TAK1/TK1A R/W TAK2/TK2A L13 L12 L11 L10 Key-on wakeup control register L1 Return by level Return by edge Falling waveform/“L” level Rising waveform/“H ” level Return by level Return by edge Key-on wakeup not used Key-on wakeup used Ports P1 0–P13 return condition selection bit Ports P1 0–P13 valid waveform/ level selection bit INT pin return condition selection bit INT pin key-on wakeup control bit at reset : 00002 at RAM back-up : state retained R/W TAL1/TL1A Notes 1: “R ” represents read enabled, and “W ” represents write enabled.

Rev.1.02 2006.12.22 page 75 of 140 REJ03B0147-0102 PU0 3 PU0 2 PU0 1 PU0 0 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Port P0 3 pull-up transistor control bit Port P0 2 pull-up transistor control bit Port P01 pull-up transistor control bit Port P0 0 pull-up transistor control bit Pull-up control register PU0 at reset : 00002 at RAM back-up : state retained R/W TAPU0/TPU0A PU1 3 PU1 2 PU1 1 PU1 0 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Port P1 3 pull-up transistor control bit Port P1 2 pull-up transistor control bit Port P1 1 pull-up transistor control bit Port P10 pull-up transistor control bit Pull-up control register PU1 at reset : 00002 at RAM back-up : state retained PU2 3 PU2 2 PU2 1 PU2 0 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Port D 3 pull-up transistor control bit Port D2 pull-up transistor control bit Port P2 1 pull-up transistor control bit Port P2 0 pull-up transistor control bit Pull-up control register PU2 at reset : 00002 at RAM back-up : state retained Notes 1: “R ” represents read enabled, and “W ” represents write enabled. R/W TAPU1/TPU1A R/W TAPU2/TPU2A

Rev.1.02 2006.12.22 page 76 of 140 REJ03B0147-0102 N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output Port P0 3 output structure selection bit Port P02 output structure selection bit Port P01 output structure selection bit Port P00 output structure selection bit Port output structure control register FR0 at reset : 00002 at RAM back-up : state retained FR1 3 FR1 2 FR1 1 FR1 0 N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output Port P1 3 output structure selection bit Port P12 output structure selection bit Port P11 output structure selection bit Port P10 output structure selection bit Port output structure control register FR1 at reset : 00002 at RAM back-up : state retained FR3 3 FR3 2 FR3 1 FR3 0 N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output Port D 3 output structure selection bit Port D2 output structure selection bit Port D1 output structure selection bit Port D0 output structure selection bit Port output structure control register FR3 at reset : 00002 at RAM back-up : state retained Notes 1: “R ” represents read enabled, and “W ” represents write enabled. W TFR0A W TFR1A W TFR3A FR2 3 FR2 2 FR2 1 FR2 0 This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Not used Not used Port P21 output structure selection bit Port P20 output structure selection bit Port output structure control register FR2 at reset : 00002 at RAM back-up : state retained W TFR2A C1 3 C1 2 C11 C1 0 N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output Port D 5 output structure selection bit Port D4 output structure selection bit Port P31 output structure selection bit Port P30 output structure selection bit Port output structure control register C1 at reset : 00002 at power down : state retained W TC1A N-channel open-drain output CMOS output N-channel open-drain output CMOS output

Rev.1.02 2006.12.22 page 77 of 140 REJ03B0147-0102 Symbol A B DR E FR0 FR1 FR2 FR3 MR PU0 PU1 PU2 X Y Z DP PC PC H PC L SK SP CY

Contents

Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) A/D control register Q1 (4 bits) Interrupt control register V1 (4 bits) Interrupt control register V2 (4 bits) Interrupt control register I1 (4 bits) Timer control register W1 (4 bits) Timer control register W2 (4 bits) Timer control register W5 (4 bits) Timer control register W6 (4 bits) Port output structure control register FR0 (4 bits) Port output structure control register FR1 (4 bits) Port output structure control register FR2 (4 bits) Port output structure control register FR3 (4 bits) Port output structure control register C1 (4 bits) Serial interface control register J1 (4 bits) Clock control register MR (4 bits) Key-on wakeup control register K0 (4 bits) Key-on wakeup control register K1 (4 bits) Key-on wakeup control register K2 (4 bits) Key-on wakeup control register L1 (4 bits) Pull-up control register PU0 (4 bits) Pull-up control register PU1 (4 bits) Pull-up control register PU2 (4 bits) Register X (4 bits) Register Y (4 bits) Register Z (2 bits) Data pointer (10 bits) (It consists of registers X, Y, and Z) Program counter (14 bits) High-order 7 bits of program counter Low-order 7 bits of program counter Stack register (14 bits ✕ 8) Stack pointer (3 bits) Carry flag Prescaler reload register (8 bits) Timer 1 reload register (8 bits) Timer 1 reload register (8 bits) Timer 2 reload register (8 bits) Timer 2 reload register (8 bits) Prescaler Timer 1 Timer 2 Timer 1 interrupt request flag Timer 2 interrupt request flag Watchdog timer flag Watchdog timer enable flag Interrupt enable flag External 0 interrupt request flag Power down flag A/D conversion completion flag Serial interface transmit/receive completion flag Port D (6 bits) Port P0 (4 bits) Port P1 (4 bits) Port P2 (2 bits) Port P3 (2 bits) Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal constant Hexadecimal constant Hexadecimal constant Binary notation of hexadecimal variable A (same for others) Direction of data movement Data exchange between a register and memory Decision of state shown before “?” Contents of registers and memories Negate, Flag unchanged after executing instruction RAM address pointed by the data pointer Label indicating address a 6 a5 a4 a3 a2 a1 a0 Label indicating address a6 a5 a4 a3 a2 a1 a0 in page p6 p5 p4 p3 p2 p1 p0 Hex. C + Hex. number x (also same for others) Symbol RPS R1L R1H R2L R2H PS T1F T2F WDF1 WEF INTE EXF0 P ADF SIOF D x y z p n i j A 3A2A1A0 ( ) M(DP) a p, a C x Note :The 4509 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped. INSTRUCTIONS Each instruction is described as follows; (1) Index list of instruction function (2) Machine instructions (index by alphabet) (3) Machine instructions (index by function) (4) Instruction code table SYMBOL The symbols shown below are used in the following list of instruction function and the machine instructions.

Rev.1.02 2006.12.22 page 78 of 140 REJ03B0147-0102 INDEX LIST OF INSTRUCTION FUNCTION Group- ing RAM addresses Mnemonic XAMI j TMA j LA n TABP p AM AMC A n AND OR SC RC SZC CMA RAR Function (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← n n = 0 to 15 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PC H ) ← p (Note) (PCL) ← (DR2–DR 0, A3–A0) (UPTF) = 1, (DR 1, DR0) ← (ROM(PC))9, 8 (DR 2) ← 0 (B) ← (ROM(PC))7–4 (A) ← (ROM(PC))3–0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (A) ← (A) + (M(DP)) (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry (A) ← (A) + n n = 0 to 15 (A) ← (A) AND (M(DP)) (A) ← (A) OR (M(DP)) (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → CY → A 3A2A1A0 Mnemonic TAB TBA TAY TYA TEAB TABE TDA TAD TAZ TAX TASP LXY x, y LZ z INY DEY TAM j XAM j XAMD j Function (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) 7–E4) ← (B) (E3–E0) ← (A) (B) ← (E7–E4) (A) ← (E3–E0) (DR 2–DR 0) ← (A2–A0) (A2–A0) ← (DR2–DR 0) (A3) ← 0 (A3, A2) ← 0 (A) ← (X) (A2–A0) ← (SP2–SP 0) (A3) ← 0 (X) ← x x = 0 to 15 (Y) ← y y = 0 to 15 (Z) ← z z = 0 to 3 (Y) ← (Y) + 1 (Y) ← (Y) – 1 (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) – 1 RAM to register transfer Arithmetic operation RAM to register transfer Register to register transfer Group- ing Note: p is 0 to 31.

Rev.1.02 2006.12.22 page 79 of 140 REJ03B0147-0102 INDEX LIST OF INSTRUCTION FUNCTION (continued) Group- ingFunction (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15 (PCL) ← a6–a0 (PCH ) ← p (Note) (PCL) ← a6–a0 (PCH ) ← p (Note) (PCL) ← (DR2–DR 0, A3–A0) (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← 2 (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (Note) (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (Note) (PCL) ← (DR2–DR 0, A3–A0) (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 Comparisonoperation Subroutine operation Branch operation Bit operation Return operation Mnemonic SB j RB j SZB j SEAM SEA n B a BL p, a BLA p BM a BML p, a BMLA p RTI RT RTS Group- ing Function (INTE) ← 0 (INTE) ← 1 (EXF0) ← 0 V10 = 1: SNZ0 = NOP (A) ← (V1) (V1) ← (A) (A) ← (V2) (V2) ← (A) (A) ← (I1) (I1) ← (A) (PA) ← (A) (A) ← (W1) (W1) ← (A) (A) ← (W2) (W2) ← (A) (A) ← (W5) (W5) ← (A) (A) ← (W6) (W6) ← (A) (B) ← (TPS7–TPS 4) (A) ← (TPS3–TPS 0) (RPS 7–RPS 4) ← (B) (TPS7–TPS 4) ← (B) (RPS 3–RPS 0) ← (A) (TPS3–TPS 0) ← (A) (B) ← (T17–T14) (A) ← (T13–T10) Mnemonic DI EI SNZ0 SNZI0 TAV1 TV1A TAV2 TV2A TAI1 TI1A TPAA TAW1 TW1A TAW2 TW2A TAW5 TW5A TAW6 TW6A TABPS TPSAB TAB1 Interrupt operation Timer operation Note: p is 0 to 31.

Rev.1.02 2006.12.22 page 80 of 140 REJ03B0147-0102 INDEX LIST OF INSTRUCTION FUNCTION (continued) Group- ing Group- ing Function (R1L7–R1L 4) ← (B) (T17–T14) ← (B) (R1L3–R1L 0) ← (A) (T13–T10) ← (A) (R1H 7–R1H 4) ← (B) (R1H 3–R1H 0) ← (A) (B) ← (T27–T24) (A) ← (T23–T20) (R2L7–R2L 4) ← (B) (T27–T24) ← (B) (R2L3–R2L 0) ← (A) (T23–T20) ← (A) (R2H 7–R2H 4) ← (B) (R2H 3–R2H 0) ← (A) (T17–T10) ← (R1L7–R1L 0) (T27–T20) ← (R2L7–R2L 0) (T1F) ← 0 V12 = 1: SNZT1 = NOP (T2F) ← 0 V13 = 1: SNZT2 = NOP (A) ← (P0) (P0) ← (A) (A) ← (P1) (P1) ← (A) (A3, A2) ← 0 (A3, A2) ← 0 Mnemonic T1AB T1HAB TAB2 T2AB T2HAB T1R1L T2R2L SNZT1 SNZT2 IAP0 OP0A IAP1 OP1A IAP2 OP2A IAP3 OP3A Timer operation Function (D) ← 1 (D(Y)) ← 0 (Y) = 0 to 5 (D(Y)) ← 1 (Y) = 0 to 5 (D(Y)) = 0 ? (Y) = 0 to 5 (FR0) ← (A) (FR1) ← (A) (FR2) ← (A) (FR3) ← (A) (C1) ← (A) (K0) ← (A) (A) ← (K0) (K1) ← (A) (A) ← (K1) (K2) ← (A) (A) ← (K2) (PU0) ← (A) (A) ← (PU0) (PU1) ← (A) (A) ← (PU1) (PU2) ← (A) (A) ← (PU2) (L1) ← (A) (A) ← (L1) Mnemonic CLD RD SD SZD TFR0A TFR1A TFR2A TFR3A TC1A TK0A TAK0 TK1A TAK1 TK2A TAK2 TPU0A TAPU0 TPU1A TAPU1 TPU2A TAPU2 TL1A TAL1 Input/Output operation Input/Output operation

Rev.1.02 2006.12.22 page 81 of 140 REJ03B0147-0102 INDEX LIST OF INSTRUCTION FUNCTION (continued) Group- ingFunction (B) ← (SI7–SI4) (A) ← (SI3–SI0) (SI7–SI4) ← (B) (SI3–SI0) ← (A) (SIOF) ← 0 Serial interface transmit/receive starting V23=0: (SIOF)=1? (SIOF) ← 0 V23 = 1: SNZSI = NOP (A) ← (J1) (J1) ← (A) RC oscillator selected (RG 0) ← (A0) (A) ← (MR) (MR) ← (A) Q1 3 = 0, (B) ← (AD9–AD 6) (A) ← (AD5–AD 2) Q1 3 = 1, (B) ← (AD7–AD 4) (A) ← (AD3–AD 0) (A3, A2) ← (AD1, AD0) (A1, A0) ← 0 (AD3–AD 0) ← (A) Q1 3 = 0 : TABAD = NOP (A) ← (Q1) (Q1) ← (A) (ADF) ← 0 Q1 3 = 0 : A/D conversion starting Q1 3 = 1 : Comparator operation starting (ADF) ← 0 V22 = 1: SNZAD = NOP Clock operation Serial interface operation A/D conversion operation Mnemonic TABSI TSIAB SST SNZSI TAJ1 TJ1A CRCK TRGA TAMR TMRA TABAD TALA TADAB TAQ1 TQ1A ADST SNZAD Group- ing Function (PC) ← (PC) + 1 RAM back-up POF instruction valid (P) = 1 ? Stop of watchdog timer function enabled (WDF1) = 1 ?, (WDF1) ← 0 System reset (UPTF) ← 0 (UPTF) ← 1 Voltage drop detection circuit valid at RAM back- up Mnemonic NOP POF EPOF SNZP DWDT WRST SRST RUPT SUPT SVDE** Other operation Note: The SVDE instruction can be used only in the H version.

Rev.1.02 2006.12.22 page 82 of 140 REJ03B0147-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) A n (Add n and accumulator) 000110nnnn 06n 11 – Overflow = 0 Grouping: Arithmetic operation Description:Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation. Operation: (A) ← (A) + n n = 0 to 15 ADST (A/D conversion STart) 1010011111 29F 11 – – Grouping: A/D conversion operation Description:Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q13 = 0) or the compara- tor operation at the comparator mode (Q13 = 1) is started. Operation: (ADF) ← 0 Q1 3 = 0: A/D conversion starting Q1 3 = 1: Comparator operation starting (Q13 : bit 3 of A/D control register Q1) AM (Add accumulator and Memory) 0000001010 00A 11 – – Grouping: Arithmetic operation Description:Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged. Operation: (A) ← (A) + (M(DP)) AMC (Add accumulator, Memory and Carry) 0000001011 00B 11 0/1 – Grouping: Arithmetic operation Description:Adds the contents of M(DP) and carry flag CY to register A. Stores the result in regis- ter A and carry flag CY. Operation: (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry

Rev.1.02 2006.12.22 page 83 of 140 REJ03B0147-0102 AND (logical AND between accumulator and memory) 0000011000 018 11 – – Grouping: Arithmetic operation Description:Takes the AND operation between the con- tents of register A and the contents of M(DP), and stores the result in register A. Operation: (A) ← (A) AND (M(DP)) B a (Branch to address a) 011a 6 a5 a4 a3 a2 a1 a0 1a 11 – – Grouping: Branch operation Description:Branch within a page : Branches to address a in the identical page. Note: Specify the branch address within the page including this instruction. Operation: (PCL) ← a6 to a0 BL p, a (Branch Long to address a in page p) 00111p 4 p3 p2 p1 p0 0p 22 – – Grouping: Branch operation Description:Branch out of a page : Branches to address a in page p. Note: p is 0 to 31. Operation: (PCH ) ← p (PCL) ← a6 to a0 BLA p (Branch Long to address (D) + (A) in page p) 0000010000 010 22 – – Grouping: Branch operation Description:Branch out of a page : Branches to address (DR 2 DR 1 DR 0 A3 A2 A1 A0)2 specified by registers D and A in page p. Note: p is 0 to 31. 2 16100a 6 a5 a4 a3 a2 a1 a0 2aa E Operation: (PCH ) ← p (PCL) ← (DR2–DR 0, A3–A0) 2 16100p 4 00p 3 p2 p1 p0 2pp MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

Rev.1.02 2006.12.22 page 84 of 140 REJ03B0147-0102 BM a (Branch and Mark to address a in page 2) 010a 6 a5 a4 a3 a2 a1 a0 1aa 11 – – Grouping: Subroutine call operation Description:Call the subroutine in page 2 : Calls the subroutine at address a in page 2. Note: Subroutine extending from page 2 to an- other page can also be called with the BM instruction when it starts on page 2. Be careful not to over the stack because the maximum level of subroutine nesting is 8. Operation: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PC H ) ← 2 (PCL) ← a6–a0 BML p, a (Branch and Mark Long to address a in page p) 00110p 4 p3 p2 p1 p0 0p 22 – – Grouping: Subroutine call operation Description:Call the subroutine : Calls the subroutine at address a in page p. Note: p is 0 to 31. Be careful not to over the stack because the maximum level of subroutine nesting is 8. Operation: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← a6–a0 BMLA p (Branch and Mark Long to address (D) + (A) in page p) 0000110000 030 22 – – Grouping: Subroutine call operation Description:Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 speci- fied by registers D and A in page p. Note: p is 0 to 31. Be careful not to over the stack because the maximum level of subroutine nesting is 8. CLD (CLear port D) 0000010001 011 11 – – Grouping: Input/Output operation Description:Sets (1) to port D. Operation: (D) ← 1 2 16100a 6 a5 a4 a3 a2 a1 a0 2aa C Operation: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← (DR2–DR 0, A3–A0) 2 16100p 4 00p 3 p2 p1 p0 2pp MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

Rev.1.02 2006.12.22 page 85 of 140 REJ03B0147-0102 CMA (CoMplement of Accumulator) 0000011100 01C 11 – – Grouping: Arithmetic operation Description:Stores the one’s complement for register A’s contents in register A. Operation: (A) ← (A) CRCK (Clock select: Rc oscillation ClocK) 1010011011 29B 11 – – Grouping: Other operation Description:Selects the RC oscillation circuit for main clock f(XIN). Operation: RC oscillation circuit selected DEY (DEcrement register Y) 0000010111 017 11 – (Y) = 15 Grouping: RAM addresses Description:Subtracts 1 from the contents of register Y. As a result of subtraction, when the con- tents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. Operation: (Y) ← (Y) – 1 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) DI (Disable Interrupt) 0000000100 004 11 – – Grouping: Interrupt control operation Description:Clears (0) to interrupt enable flag INTE, and disables the interrupt. Note: Interrupt is disabled by executing the DI in- struction after executing 1 machine cycle. Operation: (INTE) ← 0

Rev.1.02 2006.12.22 page 86 of 140 REJ03B0147-0102 IAP0 (Input Accumulator from port P0) 1001100000 260 11 – – Grouping: Input/Output operation Description:Transfers the input of port P0 to register A. Operation: (A) ← (P0) DWDT (Disable WatchDog Timer) 1010011100 29C 11 –– Grouping: Other operation Description:Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction. Operation: Stop of watchdog timer function enabled EPOF (Enable POF instruction) 0001011011 05B 11 – – Grouping: Other operation Description:Makes the immediate after POF instruction valid by executing the EPOF instruction. Operation: POF instruction valid EI (Enable Interrupt) 0000000101 005 11 – – Grouping: Interrupt control operation Description:Sets (1) to interrupt enable flag INTE, and enables the interrupt. Note: Interrupt is enabled by executing the EI in- struction after executing 1 machine cycle. Operation: (INTE) ← 1 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

Rev.1.02 2006.12.22 page 87 of 140 REJ03B0147-0102 IAP1 (Input Accumulator from port P1) 1001100001 261 11 –– Grouping: Input/Output operation Description:Transfers the input of port P1 to register A. Operation: (A) ← (P1) IAP2 (Input Accumulator from port P2) 1001100010 262 11 – – Grouping: Input/Output operation Description:Transfers the input of port P2 to the low-or- der 2 bits (A1, A0) of register A. Note: After this instruction is executed, “0” is stored to the high-order 2 bits (A3, A2) of register A. Operation: (A1, A0) ← (P21, P20) (A3, A2) ← 0 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) INY (INcrement register Y) 0000010011 013 11 – (Y) = 0 Grouping: RAM addresses Description:Adds 1 to the contents of register Y. As a re- sult of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. Operation: (Y) ← (Y) + 1 IAP3 (Input Accumulator from port P3) 1001100011 263 11 – – Grouping: Input/Output operation Description:Transfers the input of port P3 to the low-or- der 2 bits (A1, A0) of register A. Note: After this instruction is executed, “0” is stored to the high-order 2 bits (A3, A2) of register A. Operation: (A1, A0) ← (P31, P30) (A3, A2) ← 0

Rev.1.02 2006.12.22 page 88 of 140 REJ03B0147-0102 LZ z (Load register Z with z) 00010010z 1 z0 04 11 – – Grouping: RAM addresses Description:Loads the value z in the immediate field to register Z. Operation: (Z) ← z z = 0 to 3 NOP (No OPeration) 0000000000 000 11 – – Grouping: Other operation Description:No operation; Adds 1 to program counter value, and others remain unchanged. Operation: (PC) ← (PC) + 1 LA n (Load n in Accumulator) 000111nnnn 07n 11 – Continuous Grouping: Arithmetic operation Description:Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA in- struction is executed and other LA instructions coded continuously are skipped. Operation: (A) ← n n = 0 to 15 LXY x, y (Load register X and Y with x and y) 11x 3 x2 x1 x0 y3 y2 y1 y0 3xy 11 – Continuous Grouping: RAM addresses Description:Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instruc- tions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continu- ously are skipped. Operation: (X) ← x x = 0 to 15 (Y) ← y y = 0 to 15 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

Rev.1.02 2006.12.22 page 89 of 140 REJ03B0147-0102 OP0A (Output port P0 from Accumulator) 1000100000 220 11 – – Grouping: Input/Output operation Description:Outputs the contents of register A to port P0. Operation: (P0) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) OP2A (Output port P2 from Accumulator) 1000100010 222 11 –– Grouping: Input/Output operation Description:Outputs the contents of the low-order 2 bits (A1, A0) of register A to port P2. Operation: (P21, P20) ← (A1, A0) OP1A (Output port P1 from Accumulator) 1000100001 221 11 – – Grouping: Input/Output operation Description:Outputs the contents of register A to port P1. Operation: (P1) ← (A) OP3A (Output port P3 from Accumulator) 1000100011 223 11 –– Grouping: Input/Output operation Description:Outputs the contents of the low-order 2 bits (A1, A0) of register A to port P3. Operation: (P31, P30) ← (A1, A0)

Rev.1.02 2006.12.22 page 90 of 140 REJ03B0147-0102 RAR (Rotate Accumulator Right) 0000011101 01D 11 0/1 – Grouping: Arithmetic operation Description:Rotates 1 bit of the contents of register A in- cluding the contents of carry flag CY to the right. Operation: → CY → A 3A2A1A0 RB j (Reset Bit) 00010011j j 04 11 – – Grouping: Bit operation Description:Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Operation: (Mj(DP)) ← 0 j = 0 to 3 C OR (logical OR between accumulator and memory) 0000011001 019 11 –– Grouping: Arithmetic operation Description:Takes the OR operation between the con- tents of register A and the contents of M(DP), and stores the result in register A. Operation: (A) ← (A) OR (M(DP)) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) POF (Power OFF) 0000000010 002 11 – – Grouping: Other operation Description:Puts the system in RAM back-up state by ex- ecuting the POF instruction after executing the EPOF instruction. Note: If the EPOF instruction is not executed just before this instruction, this instruction is equivalent to the NOP instruction. Operation: RAM back-up

Rev.1.02 2006.12.22 page 91 of 140 REJ03B0147-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) RC (Reset Carry flag) 0000000110 006 11 0 – Grouping: Arithmetic operation Description:Clears (0) to carry flag CY. Operation: (CY) ← 0 RTI (ReTurn from Interrupt) 0001000110 046 11 – – Grouping: Return operation Description:Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y , Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY in- struction, register A and register B to the states just before interrupt. Operation: (PC) ← (SK(SP)) (SP) ← (SP) – 1 RD (Reset port D specified by register Y) 0000010100 014 11 – – Grouping: Input/Output operation Description:Clears (0) to a bit of port D specified by register Y . Note: (Y) = 0 to 5. Do not execute this instruction if values ex- cept above are set to register Y. Operation: (D(Y)) ← 0 However, (Y) = 0 to 5RT (ReTurn from subroutine) 0001000100 044 12 – – Grouping: Return operation Description:Returns from subroutine to the routine called the subroutine. Operation: (PC) ← (SK(SP)) (SP) ← (SP) – 1

Rev.1.02 2006.12.22 page 92 of 140 REJ03B0147-0102 RTS (ReTurn from subroutine and Skip) 0001000101 045 12 – Skip at uncondition Grouping: Return operation Description:Returns from subroutine to the routine called the subroutine, and skips the next in- struction at uncondition. Operation: (PC) ← (SK(SP)) (SP) ← (SP) – 1 SB j (Set Bit) 00010111j j 05 11 – – Grouping: Bit operation Description:Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Operation: (Mj(DP)) ← 0 j = 0 to 3 SC (Set Carry flag) 0000000111 007 11 1 – Grouping: Arithmetic operation Description:Sets (1) to carry flag CY. Operation: (CY) ← 1 C MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) RUPT (Reset UPT flag) 0001011000 058 11 – – Grouping: Other operation Description:Clears (0) to the high-order bit reference enable flag UPTF. Operation: (UPTF) ← 0

Rev.1.02 2006.12.22 page 93 of 140 REJ03B0147-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SNZ0 (Skip if Non Zero condition of external 0 interrupt request flag) 0000111000 038 11 – V10 = 0: (EXF0) = 1 Grouping: Interrupt operation Description:When V1 0 = 0 : Clears (0) to the EXF0 flag and skips the next instruction when external 0 interrupt request flag EXF0 is “1.” When the EXF0 flag is “0,” executes the next in- struction. When V1 0 = 1 : This instruction is equiva- lent to the NOP instruction. Operation: V10 = 0: (EXF0) = 1 ? (EXF0) ← 0 V10 = 1: SNZ0 = NOP (V10 : bit 0 of the interrupt control register V1) SEA n (Skip Equal, Accumulator with immediate data n) 0000100101 025 22 – (A) = n Grouping: Comparison operation Description:Skips the next instruction when the con- tents of register A is equal to the value n in the immediate field. Executes the next instruction when the con- tents of register A is not equal to the value n in the immediate field. Operation: (A) = n ? n = 0 to 15 SEAM (Skip Equal, Accumulator with Memory) 0000100110 026 11 – (A) = (M(DP)) Grouping: Comparison operation Description:Skips the next instruction when the con- tents of register A is equal to the contents of M(DP). Executes the next instruction when the con- tents of register A is not equal to the contents of M(DP). Operation: (A) = (M(DP)) ? SD (Set port D specified by register Y) 0000010101 015 11 – – Grouping: Input/Output operation Description:Sets (1) to a bit of port D specified by register Y. Note: (Y) = 0 to 5. Do not execute this instruction if values ex- cept above are set to register Y. Operation: (D(Y)) ← 1 (Y) = 0 to 5 2 16000111nnnn 07n

Rev.1.02 2006.12.22 page 94 of 140 REJ03B0147-0102 SNZAD (Skip if Non Zero condition of A/D conversion completion flag) 1010000111 287 Grouping: A/D conversion operation Description:When V2 2 = 0 : Clears (0) to the ADF flag and skips the next instruction when A/D conversion completion flag ADF is “1.” After skipping, . When the ADF flag is “0,” ex- ecutes the next instruction. When V2 2 = 1 : This instruction is equiva- lent to the NOP instruction. Operation: V22 = 0: (ADF) = 1 ? (ADF) ← 0 V22 = 1: SNZAD = NOP (V22 : bit 2 of the interrupt control register V2) SNZI0 (Skip if Non Zero condition of external 0 Interrupt input pin) 0000111010 03A Grouping: Interrupt operation Description:When I12 = 0 : Skips the next instruction when the level of INT pin is “L.” Executes the next instruction when the level of INT pin is “H.” When I1 2 = 1 : Skips the next instruction when the level of INT pin is “H.” Executes the next instruction when the level of INT pin is “L.” Operation: I1 (I12 : bit 2 of the interrupt control register I1) SNZP (Skip if Non Zero condition of Power down flag) 0000000011 003 11 – (P) = 1 Grouping: Other operation Description:Skips the next instruction when the P flag is “1”. After skipping, the P flag remains un- changed. Executes the next instruction when the P flag is “0.” Operation: (P) = 1 ? MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SNZSI (Skip if Non Zero condition of Serial Interface interrupt request flag) 1010001000 288 Grouping: Serial interface operation Description:Clears (0) to SIOF flag and skips the next instruction when the contents of bit 3 (V23) of interrupt control register V2 is “0” and contents of SIOF flag is “1.” When V2 3 = 1: This instruction is equivalent to the NOP instruction. Operation: V23=0: (SIOF)=1? (SIOF) ← 0 V23 = 1: SNZSI = NOP

Rev.1.02 2006.12.22 page 95 of 140 REJ03B0147-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SNZT1 (Skip if Non Zero condition of Timer 1 interrupt request flag) 1010000000 280 Grouping: Timer operation Description:When V1 2 = 0 : Clears (0) to the T1F flag and skips the next instruction when timer 1 interrupt request flag T1F is “1.” When the T1F flag is “0,” executes the next instruc- tion. When V1 2 = 1 : This instruction is equiva- lent to the NOP instruction. Operation: V12 = 0: (T1F) = 1 ? (T1F) ← 0 V12 = 1: SNZT1 = NOP (V12 = bit 2 of interrupt control register V1) SNZT2 (Skip if Non Zero condition of Timer 2 interrupt request flag) 1010000001 281 Grouping: Timer operation Description:When V1 3 = 0 : Clears (0) to the T2F flag and skips the next instruction when timer 2 interrupt request flag T2F is “1.” When the T2F flag is “0,” executes the next instruc- tion. When V1 3 = 1 : This instruction is equiva- lent to the NOP instruction. Operation: V13 = 0: (T2F) = 1 ? (T2F) ← 0 V13 = 1: SNZT2 = NOP (V13 = bit 3 of interrupt control register V1) SRST (System ReSet) 0000000001 001 11 – – Grouping: Other operation Description:System reset occurs. Operation: System reset SST (Serial interface transmission/reception STart) 1010011110 29E 11 – – Grouping: Serial interface operation Description:Clears (0) to SIOF flag and starts serial in- terface. Operation: (SIOF) ← 0 Serial interface transmit/receive starting

Rev.1.02 2006.12.22 page 96 of 140 REJ03B0147-0102 SZC (Skip if Zero, Carry flag) 0000101111 02F 11 – (CY) = 0 Grouping: Arithmetic operation Description:Skips the next instruction when the con- tents of carry flag CY is “0.” After skipping, the CY flag remains un- changed. Executes the next instruction when the con- tents of the CY flag is “1.“ Operation: (CY) = 0 ? SZB j (Skip if Zero, Bit) 00001000j j 02j 11 – (Mj(DP)) = 0 j = 0 to 3 Grouping: Bit operation Description:Skips the next instruction when the con- tents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0.” Executes the next instruction when the con- tents of bit j of M(DP) is “1.” Operation: (Mj(DP)) = 0 ? j = 0 to 3 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SUPT (Set UPT flag) 0001011001 059 11 – – Grouping: Other operation Description:Sets (1) to the high-order bit reference en- able flag UPTF. When the table reference instruction (TABP p) is executed, the high- order 2 bits of ROM reference data is transferred to the low-order 2 bits of regis- ter D. Operation: (UPTF) ← 1 SVDE (Set Voltage Detector Enable flag) 1010010011 293 11 – – Grouping: Other operation Description:Validates the voltage drop detection circuit at RAM back-up. Note: This instruction can be executed only for the H version. Operation: Voltage drop detection circuit valid at RAM back-up

Rev.1.02 2006.12.22 page 97 of 140 REJ03B0147-0102 SZD (Skip if Zero, port D specified by register Y) 0000100100 024 22 – (D(Y)) = 0 (Y) = 0 to 5 Grouping: Input/Output operation Description:Skips the next instruction when a bit of port D specified by register Y is “0.” Executes the next instruction when the bit is “1.” Note: (Y) = 0 to 5. Do not execute this instruction if values ex- cept above are set to register Y . T1AB (Transfer data to timer 1 and register R1L from Accumulator and register B) 1000110000 230 11 – – Grouping: Timer operation Description:Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 re- load register R1L. Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1L. Operation: (R1L 7–R1L 4) ← (B) (T17–T14) ← (B) (R1L3–R1L 0) ← (A) (T13–T10) ← (A) Operation: (D(Y)) = 0 ? (Y) = 0 to 5 2 160000101011 02B MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) T1HAB (Transfer data to register R1H from Accumulator and register B) 1010010010 292 11 – – Grouping: Timer operation Description:Transfers the contents of register B to the high-order 4 bits of timer 1 reload register R1H. Transfers the contents of register A to the low-order 4 bits of timer 1 reload regis- ter R1H. Operation: (R1H 7–R1H 4) ← (B) (R1H 3–R1H 0) ← (A) T1R1L (Transfer data to timer 1 from register R1L) 1010100111 2A7 11 – – Grouping: Timer operation Description:Transfers the contents of timer 1 reload register R1L to timer 1. Operation: (T17–T10) ← (R1L7–R1L 0)

Rev.1.02 2006.12.22 page 98 of 140 REJ03B0147-0102 TAB (Transfer data to Accumulator from register B) 0000011110 01E 11 – – Grouping: Register to register transfer Description:Transfers the contents of register B to reg- ister A. Operation: (A) ← (B) T2HAB (Transfer data to register R2H from Accumulator and register B) 1010010100 294 11 – – Grouping: Timer operation Description:Transfers the contents of register B to the high-order 4 bits of timer 2 reload register R2H. Transfers the contents of register A to the low-order 4 bits of timer 2 reload regis- ter R2H. Operation: (R2H 7–R2H 4) ← (B) (R2H 3–R2H 0) ← (A) T2R2L (Transfer data to timer 2 from register R2L) 1010010101 295 11 – – Grouping: Timer operation Description:Transfers the contents of timer 2 reload register R2L to timer 2. Operation: (T27–T20) ← (R2L7–R2L 0) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) T2AB (Transfer data to timer 2 and register R2L from Accumulator and register B) 1000110001 231 11 – – Grouping: Timer operation Description:Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 re- load register R2L. Transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2L. Operation: (R2L 7–R2L 4) ← (B) (T27–T24) ← (B) (R2L3–R2L 0) ← (A) (T23–T20) ← (A)

Rev.1.02 2006.12.22 page 99 of 140 REJ03B0147-0102 TABE (Transfer data to Accumulator and register B from register E) 0000101010 02A 11 – – Grouping: Register to register transfer Description:Transfers the high-order 4 bits (E7–E4) of register E to register B, and low-order 4 bits of register E to register A. Operation: (B) ← (E7–E4) (A) ← (E3–E0) TAB1 (Transfer data to Accumulator and register B from timer 1) 1001110000 270 11 –– Grouping: Timer operation Description:Transfers the high-order 4 bits (T17–T14) of timer 1 to register B. Transfers the low-order 4 bits (T1 3–T10) of timer 1 to register A. Operation: (B) ← (T17–T14) (A) ← (T13–T10) TAB2 (Transfer data to Accumulator and register B from timer 2) 1001110001 271 11 – – Grouping: Timer operation Description:Transfers the high-order 4 bits (T27–T24) of timer 2 to register B. Transfers the low-order 4 bits (T2 3–T20) of timer 2 to register A. Operation: (B) ← (T27–T24) (A) ← (T23–T20) TABAD (Transfer data to Accumulator and register B from register AD) 1001111001 279 11 – – Grouping: A/D conversion operation Description: In the A/D conversion mode (Q13 = 0), trans- fers the high-order 4 bits (AD9–AD 6) of register AD to register B, and the middle-order 4 bits (AD 5–AD 2) of register AD to register A. In the comparator mode (Q13 = 1), transfers the high- order 4 bits (AD7–AD 4) of comparator register to register B, and the low-order 4 bits (AD3– AD 0) of comparator register to register A. Operation: In A/D conversion mode (Q13 = 0), (B) ← (AD9–AD 6) (A) ← (AD5–AD 2) In comparator mode (Q13 = 1), (B) ← (AD7–AD 4) (A) ← (AD3–AD 0) (Q13 : bit 3 of A/D control register Q1) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TABP p (Transfer data to Accumulator and register B from Program memory in page p) 00100p 4 p3 p2 p1 p0 0p 13 – – Grouping: Arithmetic operation Description:Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When UPTF is 1, Transfers bits 9, 8 to the low-order 2 bits (DR1, DR0) of register D, and “0” is stored to the least significant bit (DR2) of register D. When this instruction is executed, 1 stage of stack register (SK) is used. Note: p is 0 to 31. When this instruction is executed, be careful not to over the stack be- cause 1 stage of stack register is used. Operation: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PC H ) ← p (PCL) ← (DR2–DR 0, A3–A0) (B) ← (ROM(PC))7–4 (A) ← (ROM(PC))3–0 (UPTF) ← 1 (DR1, DR0) ← (ROM(PC))9, 8 (DR2) ← 0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 TAD (Transfer data to Accumulator from register D) 0001010001 051 11 – – Grouping: Register to register transfer Description:Transfers the contents of register D to the low-order 3 bits (A2–A0) of register A. Note: When this instruction is executed, “0” is stored to the bit 3 (A3) of register A. Operation: (A2–A0) ← (DR 2–DR 0) (A3) ← 0 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TABPS (Transfer data to Accumulator and register B from Pre-Scaler) 1001110101 275 11 – – Grouping: Timer operation Description:Transfers the high-order 4 bits of prescaler to register B. Transfers the low-order 4 bits of prescaler to register A. Operation: (B) ← (TPS 7–TPS 4) (A) ← (TPS3–TPS 0) TABSI (Transfer data to Accumulator and register B from register SI) 1001111000 278 11 – – Grouping: Serial interface operation Description:Transfers the high-order 4 bits of serial inter- face register SI to register B, and transfers the low-order 4 bits of serial interface regis- ter SI to register A. Operation: (B) ← (SI 7–SI4) (A) ← (SI3–SI0) Skip conditionNumber of cycles Number of words Instruction code D 9 D 0 Flag CY 2 16 Skip conditionNumber of cycles Number of words Instruction code D 9 D 0 Flag CY 2 16 Skip conditionNumber of cycles Number of words Instruction code D 9 D 0 Flag CY 2 16 Skip conditionNumber of cycles Number of words Instruction code D 9 D 0 Flag CY 2 16 Rev.1.02 2006.12.22 page 100 of 140 REJ03B0147-0102

Rev.1.02 2006.12.22 page 101 of 140 REJ03B0147-0102 TADAB (Transfer data to register AD from Accumulator from register B) 1000111001 239 11 – – Grouping: A/D conversion operation Description:In the comparator mode (Q13 = 1), transfers the contents of register B to the high-order 4 bits (AD 7–AD 4) of comparator register, and the contents of register A to the low-order 4 bits (AD 3–AD 0) of comparator register. In the A/D conversion mode (Q13 = 0), this in- struction is equivalent to the NOP instruction. (Q1 3 = bit 3 of A/D control register Q1) Operation: Q1 3 = 1: (AD7–AD 4) ← (B) (AD3–AD 0) ← (A) Q1 3 = 0: TADAB = NOP TAI1 (Transfer data to Accumulator from register I1) 1001010011 253 11 –– Grouping: Interrupt operation Description:Transfers the contents of interrupt control register I1 to register A. Operation: (A) ← (I1) TAJ1 (Transfer data to Accumulator from register J1) 1001000010 242 11 – – Grouping: Serial interface operation Description:Transfers the contents of serial interface control register J1 to register A. Operation: (A) ← (J1) TAK0 (Transfer data to Accumulator from register K0) 1001010110 256 11 – – Grouping: Input/Output operation Description:Transfers the contents of key-on wakeup control register K0 to register A. Operation: (A) ← (K0) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

Rev.1.02 2006.12.22 page 102 of 140 REJ03B0147-0102 TAK1 (Transfer data to Accumulator from register K1) 1001011001 259 11 – – Grouping: Input/Output operation Description:Transfers the contents of key-on wakeup control register K1 to register A. Operation: (A) ← (K1) TAK2 (Transfer data to Accumulator from register K2) 1001011010 25A 11 – – Grouping: Input/Output operation Description:Transfers the contents of key-on wakeup control register K2 to register A. Operation: (A) ← (K2) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TALA (Transfer data to Accumulator from register LA) 1001001001 249 11 – – Grouping: A/D conversion operation Description:Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (A3, A2) of register A. “0” is stored to the low-order 2 bits (A1, A0) of register A. Operation: (A3, A2) ← (AD1, AD0) (A1, A0) ← 0 TAL1 (Transfer data to Accumulator from register L1) 1010001010 24A 11 – – Grouping: Input/Output operation Description:Transfers the contents of key-on wakeup control register L1 to register A. Operation: (A) ← (L1)

Rev.1.02 2006.12.22 page 103 of 140 REJ03B0147-0102 TAM j (Transfer data to Accumulator from Memory) 101100 jjjj 2 C j 11 – – Grouping: RAM to register transfer Description:After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the re- sult in register X. TAMR (Transfer data to Accumulator from register MR) 1001010010 252 11 – – Grouping: Clock operation Description:Transfers the contents of clock control reg- ister MR to register A. Operation: (A) ← (MR) Operation: (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAPU0 (Transfer data to Accumulator from register PU0) 1001010111 257 11 – – Grouping: Input/Output operation Description:Transfers the contents of pull-up control register PU0 to register A. Operation: (A) ← (PU0) TAPU1 (Transfer data to Accumulator from register PU1) 1001011110 25E 11 – – Grouping: Input/Output operation Description:Transfers the contents of pull-up control register PU1 to register A. Operation: (A) ← (PU1)

Rev.1.02 2006.12.22 page 104 of 140 REJ03B0147-0102 TAV1 (Transfer data to Accumulator from register V1) 0001010100 054 11 – – Grouping: Interrupt operation Description:Transfers the contents of interrupt control register V1 to register A. Operation: (A) ← (V1) TAQ1 (Transfer data to Accumulator from register Q1) 1001000100 244 11 – – Grouping: A/D conversion operation Description:Transfers the contents of A/D control regis- ter Q1 to register A. Operation: (A) ← (Q1) TASP (Transfer data to Accumulator from Stack Pointer) 0001010000 050 11 – – Grouping: Register to register transfer Description:Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2–A0) of register A. “0” is stored to the bit 3 (A3) of register A. Operation: (A2–A0) ← (SP2–SP 0) (A3) ← 0 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAPU2 (Transfer data to Accumulator from register PU2) 1001011111 25F 11 – – Grouping: Input/Output operation Description:Transfers the contents of pull-up control register PU2 to register A. Operation: (A) ← (PU2)

Rev.1.02 2006.12.22 page 105 of 140 REJ03B0147-0102 TAV2 (Transfer data to Accumulator from register V2) 0001010101 055 11 – – Grouping: Interrupt operation Description:Transfers the contents of interrupt control register V2 to register A. Operation: (A) ← (V2) TAW1 (Transfer data to Accumulator from register W1) 1001001011 24B 11 – – Grouping: Timer operation Description:Transfers the contents of timer control reg- ister W1 to register A. Operation: (A) ← (W1) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAW2 (Transfer data to Accumulator from register W2) 1001001100 24C 11 – – Grouping: Timer operation Description:Transfers the contents of timer control reg- ister W2 to register A. Operation: (A) ← (W2) TAW5 (Transfer data to Accumulator from register W5) 1001001111 24F 11 – – Grouping: Timer operation Description:Transfers the contents of timer control reg- ister W5 to register A. Operation: (A) ← (W5)

Rev.1.02 2006.12.22 page 106 of 140 REJ03B0147-0102 TAW6 (Transfer data to Accumulator from register W6) 1001010000 250 11 – – Grouping: Timer operation Description:Transfers the contents of timer control reg- ister W6 to register A. TAX (Transfer data to Accumulator from register X) 0001010010 052 11 –– Grouping: Register to register transfer Description:Transfers the contents of register X to reg- ister A. Operation: (A) ← (X) Operation: (A) ← (W6) TAY (Transfer data to Accumulator from register Y) 0000011111 01F 11 –– Grouping: Register to register transfer Description:Transfers the contents of register Y to regis- ter A. Operation: (A) ← (Y) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAZ (Transfer data to Accumulator from register Z) 0001010011 053 11 – – Grouping: Register to register transfer Description:Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. “0” is stored to the high-order 2 bits (A3, A2) of register A. Operation: (A1, A0) ← (Z1, Z0) (A3, A2) ← 0

Rev.1.02 2006.12.22 page 107 of 140 REJ03B0147-0102 TBA (Transfer data to register B from Accumulator) 0000001110 00E 11 – – Grouping: Register to register transfer Description:Transfers the contents of register A to regis- ter B. TDA (Transfer data to register D from Accumulator) 0000101001 029 11 – – Grouping: Register to register transfer Description:Transfers the contents of the low-order 3 bits (A2–A0) of register A to register D. Operation: (DR 2–DR 0) ← (A2–A0) TEAB (Transfer data to register E from Accumulator and register B) 0000011010 01A 11 – – Grouping: Register to register transfer Description:Transfers the contents of register B to the high-order 4 bits (E3–E0) of register E, and the contents of register A to the low-order 4 bits (E 3–E0) of register E. Operation: (E7–E4) ← (B) (E3–E0) ← (A) Operation: (B) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TC1A (Transfer data to register C1 from Accumulator) 1010101000 2A8 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to port output structure control register C1. Operation: (C1) ← (A)

Rev.1.02 2006.12.22 page 108 of 140 REJ03B0147-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TFR0A (Transfer data to register FR0 from Accumulator) 1000101000 228 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to port output structure control register FR0. Operation: (FR0) ← (A) TFR1A (Transfer data to register FR1 from Accumulator) 1000101001 229 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to port output structure control register FR1. Operation: (FR1) ← (A) TFR2A (Transfer data to register FR2 from Accumulator) 1000101010 22A 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to port output structure control register FR2. Operation: (FR2) ← (A) TFR3A (Transfer data to register FR3 from Accumulator) 1000101011 22B 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to port output structure control register FR3. Operation: (FR3) ← (A)

Rev.1.02 2006.12.22 page 109 of 140 REJ03B0147-0102 TI1A (Transfer data to register I1 from Accumulator) 1000010111 217 11 – – Grouping: Interrupt operation Description:Transfers the contents of register A to inter- rupt control register I1. Operation: (I1) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TJ1A (Transfer data to register J1 from Accumulator) 1000000010 202 11 – – Grouping: Serial interface operation Description:Transfers the contents of register A to serial interface control register J1. Operation: (J1) ← (A) TK0A (Transfer data to register K0 from Accumulator) 1000011011 21B 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to key- on wakeup control register K0. Operation: (K0) ← (A) TK1A (Transfer data to register K1 from Accumulator) 1000010100 214 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to key- on wakeup control register K1. Operation: (K1) ← (A)

Rev.1.02 2006.12.22 page 110 of 140 REJ03B0147-0102 TK2A (Transfer data to register K2 from Accumulator) 1000010101 215 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to key- on wakeup control register K2. Operation: (K2) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TMA j (Transfer data to Memory from Accumulator) 101011 jjjj 2 B j 11 – – Grouping: RAM to register transfer Description:After transferring the contents of register A to M(DP), an exclusive OR operation is per- formed between register X and the value j in the immediate field, and stores the result in register X. Operation: (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 TL1A (Transfer data to register L1 from Accumulator) 1000001010 20A 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to key- on wakeup control register L1. Operation: (L1) ← (A) TMRA (Transfer data to register MR from Accumulator) 1000010110 216 11 – – Grouping: Clock operation Description:Transfers the contents of register A to clock control register MR. Operation: (MR) ← (A)

Rev.1.02 2006.12.22 page 111 of 140 REJ03B0147-0102 TPU0A (Transfer data to register PU0 from Accumulator) 1000101101 22D 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to pull- up control register PU0. Operation: (PU0) ← (A) TPU1A (Transfer data to register PU1 from Accumulator) 1000101110 22E 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to pull- up control register PU1. Operation: (PU1) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TPAA (Transfer data to register PA from Accumulator) 1010101010 2AA 11 – – Grouping: Timer operation Description:Transfers the least significant bit of register A to timer control register PA. Operation: (PA0) ← (A0) TPSAB (Transfer data to Pre-Scaler and register RPS from Accumulator and register B) 1000110101 235 11 – – Grouping: Timer operation Description:Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS. Transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS. Operation: (RPS 7–RPS 4) ← (B) (TPS7–TPS 4) ← (B) (RPS 3–RPS 0) ← (A) (TPS3–TPS 0) ← (A)

Rev.1.02 2006.12.22 page 112 of 140 REJ03B0147-0102 TQ1A (Transfer data to register Q1 from Accumulator) 1000000100 204 11 – – Grouping: A/D conversion operation Description:Transfers the contents of register A to A/D control register Q1. Operation: (Q1) ← (A) TPU2A (Transfer data to register PU2 from Accumulator) 1000101111 22F 11 – – Grouping: Input/Output operation Description:Transfers the contents of register A to pull- up control register PU2. Operation: (PU2) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TRGA (Transfer data to register RG from Accumulator) 1000001001 209 11 – – Grouping: Clock operation Description:Transfers the least significant bit (A0) of register A to clock control regiser RG. Operation: (RG 0) ← (A0) TSIAB (Transfer data to register SI from Accumulator) 1000111000 238 11 – – Grouping: Serial interface operation Description:Transfers the contents of register B to the high-order 4 bits of serial interface register SI, and transfers the contents of register A to the low-order 4 bits of serial interface register SI. Operation: (SI7–SI4) ← (B) (SI3–SI0) ← (A)

Rev.1.02 2006.12.22 page 113 of 140 REJ03B0147-0102 TV1A (Transfer data to register V1 from Accumulator) 0000111111 03F 11 – – Grouping: Interrupt operation Description:Transfers the contents of register A to inter- rupt control register V1. Operation: (V1) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TV2A (Transfer data to register V2 from Accumulator) 0000111110 03E 11 – – Grouping: Interrupt operation Description:Transfers the contents of register A to inter- rupt control register V2. Operation: (V2) ← (A) TW1A (Transfer data to register W1 from Accumulator) 1000001110 20E 11 –– Grouping: Timer operation Description:Transfers the contents of register A to timer control register W1. Operation: (W1) ← (A) TW2A (Transfer data to register W2 from Accumulator) 1000001111 20F 11 – – Grouping: Timer operation Description:Transfers the contents of register A to timer control register W2. Operation: (W2) ← (A)

Rev.1.02 2006.12.22 page 114 of 140 REJ03B0147-0102 WRST (Watchdog timer ReSeT) 1010100000 2A0 11 – (WDF1) = 1 Grouping: Other operation Description:Clears (0) to the WDF1 flag and skips the next instruction when watchdog timer flag WDF1 is “1.” When the WDF1 flag is “0,” ex- ecutes the next instruction. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction. Operation: (WDF1) = 1 ? (WDF1) ← 0 TW6A (Transfer data to register W6 from Accumulator) 1000010011 213 11 – – Grouping: Timer operation Description:Transfers the contents of register A to timer control register W6. Operation: (W6) ← (A) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TYA (Transfer data to register Y from Accumulator) 0000001100 00C 11 – – Grouping: Register to register transfer Description:Transfers the contents of register A to regis- ter Y . Operation: (Y) ← (A) TW5A (Transfer data to register W5 from Accumulator) 1000010010 212 11 – – Grouping: Timer operation Description:Transfers the contents of register A to timer control register W5. Operation: (W5) ← (A)

XAM j (eXchange Accumulator and Memory data) 101101 jjjj 2 D j 11 – – Grouping: RAM to register transfer Description:After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between regis- ter X and the value j in the immediate field, and stores the result in register X. XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip) 101111 jjjj 2 F j 11 – (Y) = 15 Grouping: RAM to register transfer Description:After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between regis- ter X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the con- tents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. Operation: (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) – 1 Operation: (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip) 101110 jjjj 2 E j 11 – (Y) = 0 Grouping: RAM to register transfer Description:After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between regis- ter X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a re- sult of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. Operation: (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 Instruction code Skip conditionNumber of cycles Number of words Instruction code Flag CY 2 16 Skip conditionNumber of cycles Number of words Instruction code Flag CY 2 16 Skip conditionNumber of cycles Number of words Instruction code Flag CY 2 16 D 9 D 0 D 9 D 0 D 9 D 0 Rev.1.02 2006.12.22 page 115 of 140 REJ03B0147-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.1.02 2006.12.22 page 116 of 140 REJ03B0147-0102 (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) (E7–E4) ← (B) (E3–E0) ← (A) (B) ← (E7–E4) (A) ← (E3–E0) (DR 2–DR 0) ← (A2–A0) (A2–A0) ← (DR2–DR 0) (A3) ← 0 (A3, A2) ← 0 (A) ← (X) (A2–A0) ← (SP2–SP 0) (A3) ← 0 (X) ← x x = 0 to 15 (Y) ← y y = 0 to 15 (Z) ← z z = 0 to 3 (Y) ← (Y) + 1 (Y) ← (Y) – 1 (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) – 1 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 TAB TBA TAY TYA TEAB TABE TDA TAD TAZ TAX TASP LXY x, y LZ z INY DEY TAM j XAM j XAMD j XAMI j TMA j MACHINE INSTRUCTIONS (INDEX BY TYPES) 0000011110 0000001110 0000011111 0000001100 0000011010 0000101010 0000101001 0001010001 0001010011 0001010010 0001010000 11x 3 x2 x1 x0 y3 y2 y1 y0 00010010z 1 z0 0000010011 0000010111 101100 jjjj 101101 jjjj 101111 jjjj 101110 jjjj 101011 jjjj 01E 00E 01F 00C 01A 02A 029 051 053 052 050 3xy 048 013 017 2C j 2D j 2Fj 2Ej 2Bj RAM addresses RAM to register transfer Register to register transfer

Rev.1.02 2006.12.22 page 117 of 140 REJ03B0147-0102 Skip condition Datailed description Carry flag CY Continuous (Y) = 0 (Y) = 15 (Y) = 15 (Y) = 0 Transfers the contents of register B to register A. Transfers the contents of register A to register B. Transfers the contents of register Y to register A. Transfers the contents of register A to register Y. Transfers the contents of register B to the high-order 4 bits (E 7–E4) of register E, and the contents of regis- ter A to the low-order 4 bits (E3–E0) of register E. Transfers the high-order 4 bits (E7–E4) of register E to register B, and low-order 4 bits of register E to regis- ter A. Transfers the contents of the low-order 3 bits (A2–A0) of register A to register D. Transfers the contents of register D to the low-order 3 bits (A2–A0) of register A. “0” is stored to the bit 3 (A3) of register A. Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. “0” is stored to the high-order 2 bits (A3, A2) of register A. Transfers the contents of register X to register A. Transfers the contents of stack pointer (SP) to the low-order 3 bits (A 2–A0) of register A. “0” is stored to the bit 3 (A3) of register A. Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. Loads the value z in the immediate field to register Z. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next in- struction is skipped. When the contents of register Y is not 0, the next instruction is executed. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between reg- ister X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per- formed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per- formed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per- formed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next in- struction is skipped. when the contents of register Y is not 0, the next instruction is executed. After transferring the contents of register A to M(DP), an exclusive OR operation is performed between reg- ister X and the value j in the immediate field, and stores the result in register X.

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.1.02 2006.12.22 page 118 of 140 REJ03B0147-0102 Note :p is 0 to 31. MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) 07n 08p 00A 00B 06n 018 019 007 006 02F 01C 01D 05C 04C 02j 026 025 07n 000111nnnn 00100p 4 p3 p2 p1 p0 0000001010 0000001011 000110nnnn 0000011000 0000011001 0000000111 0000000110 0000101111 0000011100 0000011101 00010111j j 00010011j j 00001000j j 0000100110 0000100101 000111nnnn LA n TABP p AM AMC A n AND OR SC RC SZC CMA RAR SB j RB j SZB j SEAM SEA n Arithmetic operation Comparison operation Bit operation (A) ← n n = 0 to 15 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (Note) (PCL) ← (DR2–DR 0, A3–A0) (B) ← (ROM(PC))7–4 (A) ← (ROM(PC))3–0 (UPTF) = 1 (DR1, DR0) ← (ROM(PC))9, 8 (DR 2) ← 0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (A) ← (A) + (M(DP)) (A) ← (A) + (M(DP)) +(CY) (CY) ← Carry (A) ← (A) + n n = 0 to 15 (A) ← (A) AND (M(DP)) (A) ← (A) OR (M(DP)) (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → CY → A 3A2A1A0 (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15

Rev.1.02 2006.12.22 page 119 of 140 REJ03B0147-0102 Skip condition Datailed description Carry flag CY Continuous Overflow = 0 (CY) = 0 (Mj(DP)) = 0 j = 0 to 3 (A) = (M(DP)) (A) = n n = 0 to 15 Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in ad- dress (DR 2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When UPTF is 1, Transfers bits 9, 8 to the low-order 2 bits (DR1, DR0) of register D, and “0” is stored to the least significant bit (DR2) of reg- ister D. When this instruction is executed, 1 stage of stack register (SK) is used. Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY re- mains unchanged. Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY . Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation. Takes the AND operation between the contents of register A and the contents of M(DP), and stores the re- sult in register A. Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A. Sets (1) to carry flag CY . Clears (0) to carry flag CY. Skips the next instruction when the contents of carry flag CY is “0.” Stores the one’s complement for register A’s contents in register A. Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0.” Executes the next instruction when the contents of bit j of M(DP) is “1.” Skips the next instruction when the contents of register A is equal to the contents of M(DP). Executes the next instruction when the contents of register A is not equal to the contents of M(DP). Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Executes the next instruction when the contents of register A is not equal to the value n in the immediate field.

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.1.02 2006.12.22 page 120 of 140 REJ03B0147-0102 BL p, a BLA p BM a BML p, a BMLA p RTI RT RTS 011a 6 a5 a4 a3 a2 a1 a0 00111p 4 p3 p2 p1 p0 100a 6 a5 a4 a3 a2 a1 a0 0000010000 100p 4 00p 3 p2 p1 p0 010a 6 a5 a4 a3 a2 a1 a0 00110p 4 p3 p2 p1 p0 100a 6 a5 a4 a3 a2 a1 a0 0000110000 100p 4 00p 3 p2 p1 p0 0001000110 0001000100 0001000101 18a 0Ep 2aa 010 2pp 1aa 0C p 2aa 030 2pp 046 044 045 Subroutine operation Return operation (PCL) ← a6–a0 (PCH ) ← p (Note) (PCL) ← a6–a0 (PCH ) ← p (Note) (PCL) ← (DR2–DR 0, A3–A0) (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← 2 (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (Note) (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (Note) (PCL) ← (DR2–DR 0,A3–A0) (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 Branch operation Note :p is 0 to 31. MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)

Rev.1.02 2006.12.22 page 121 of 140 REJ03B0147-0102 Skip condition Datailed description Carry flag CY Skip at uncondition Branch within a page : Branches to address a in the identical page. Branch out of a page : Branches to address a in page p. Branch out of a page : Branches to address (DR

2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in

page p. Call the subroutine in page 2 : Calls the subroutine at address a in page 2. Call the subroutine : Calls the subroutine at address a in page p. Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous de- scription of the LA/LXY instruction, register A and register B to the states just before interrupt. Returns from subroutine to the routine called the subroutine. Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.

(INTE) ← 0 (INTE) ← 1 (EXF0) ← 0 V10 = 1: SNZ0 = NOP (A) ← (V1) (V1) ← (A) (A) ← (V2) (V2) ← (A) (A) ← (I1) (I1) ← (A) (PA0) ← (A0) (A) ← (W1) (W1) ← (A) (A) ← (W2) (W2) ← (A) (A) ← (W5) (W5) ← (A) (A) ← (W6) (W6) ← (A) (B) ← (TPS7–TPS 4) (A) ← (TPS3–TPS 0) (RPS 7–RPS 4) ← (B) (TPS7–TPS 4) ← (B) (RPS 3–RPS 0) ← (A) (TPS3–TPS 0) ← (A) (B) ← (T17–T14) (A) ← (T13–T10) (R1L7–R1L 4) ← (B) (T17–T14) ← (B) (R1L3–R1L 0) ← (A) (T13–T10) ← (A) (R1H 7–R1H 4) ← (B) (R1H 3–R1H 0) ← (A) 004 005 038 03A 054 03F 055 03E 253 217 2AA 24B 20E 24C 20F 24F 212 250 213 275 235 270 230 292 0000000100 0000000101 0000111000 0000111010 0001010100 0000111111 0001010101 0000111110 1001010011 1000010111 1010101010 1001001011 1000001110 1001001100 1000001111 1001001111 1000010010 1001010000 1000010011 1001110101 1000110101 1001110000 1000110000 1010010010 Interrupt operation Timer operation Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Rev.1.02 2006.12.22 page 122 of 140 REJ03B0147-0102

0 = 0: (EXF0) = 1 (INT) = “L” However, I12 = 0 (INT) = “H ” However, I12 = 1 Skip condition Datailed description Carry flag CY Clears (0) to interrupt enable flag INTE, and disables the interrupt. Sets (1) to interrupt enable flag INTE, and enables the interrupt. When V1 0 = 0 : Clears (0) to the EXF0 flag and skips the next instruction when external 0 interrupt request flag EXF0 is “1.” When the EXF0 flag is “0,” executes the next instruction. When V1 0 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register V1) When I12 = 0 : Skips the next instruction when the level of INT pin is “L.” Executes the next instruction when the level of INT pin is “H.” When I12 = 1 : Skips the next instruction when the level of INT pin is “H.” Executes the next instruction when the level of INT pin is “L.” (I12: bit 2 of interrupt control register I1) Transfers the contents of interrupt control register V1 to register A. Transfers the contents of register A to interrupt control register V1. Transfers the contents of interrupt control register V2 to register A. Transfers the contents of register A to interrupt control register V2. Transfers the contents of interrupt control register I1 to register A. Transfers the contents of register A to interrupt control register I1. Transfers the contents of register A to timer control register PA. Transfers the contents of timer control register W1 to register A. Transfers the contents of register A to timer control register W1. Transfers the contents of timer control register W2 to register A. Transfers the contents of register A to timer control register W2. Transfers the contents of timer control register W5 to register A. Transfers the contents of register A to timer control register W5. Transfers the contents of timer control register W6 to register A. Transfers the contents of register A to timer control register W6. Transfers the high-order 4 bits of prescaler to register B. Transfers the low-order 4 bits of prescaler to register A. Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS. Transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS. Transfers the high-order 4 bits (T1 7–T14) of timer 1 to register B. Transfers the low-order 4 bits (T13–T10) of timer 1 to register A. Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1L. Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1L. Transfers the contents of register B to the high-order 4 bits of timer 1 reload register R1H. Transfers the contents of register A to the low-order 4 bits of timer 1 reload register R1H. Rev.1.02 2006.12.22 page 123 of 140 REJ03B0147-0102

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.1.02 2006.12.22 page 124 of 140 REJ03B0147-0102 (B) ← (T2 7–T24) (A) ← (T23–T20) (R2L7–R2L 4) ← (B) (T27–T24) ← (B) (R2L3–R2L 0) ← (A) (T23–T20) ← (A) (R2H 7–R2H 4) ← (B) (R2H 3–R2H 0) ← (A) (T1) ← (R1L) (T2) ← (R2L) (T1F) ← 0 V12 = 1: SNZT1 = NOP (T2F) ← 0 V13 = 1: SNZT2 = NOP (A) ← (P0) (P0) ← (A) (A) ← (P1) (P1) ← (A) (A3, A2) ← 0 (A3, A2) ← 0 (D) ← 1 (D(Y)) ← 0 (Y) = 0 to 5 (D(Y)) ← 1 (Y) = 0 to 5 (D(Y)) = 0 ? (Y) = 0 to 5 Timer operation Input/Output operation

Rev.1.02 2006.12.22 page 125 of 140 REJ03B0147-0102 Skip condition Datailed description Carry flag CY V12 = 0: (T1F) = 1 V13 = 0: (T2F) =1 (D(Y)) = 0 ? Transfers the high-order 4 bits (T2 7–T24) of timer 2 to register B. Transfers the low-order 4 bits (T23–T20) of timer 2 to register A. Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2L. Trans- fers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2L. Transfers the contents of register B to the high-order 4 bits of timer 2 reload register R2H. Transfers the con- tents of register A to the low-order 4 bits of timer 2 reload register R2H. Transfers the contents of timer 1 reload register R1L to timer 1. Transfers the contents of timer 2 reload register R2L to timer 2. When V1 2 = 0 : Clears (0) to the T1F flag and skips the next instruction when timer 1 interrupt request flag T1F is “1.” . When the T1F flag is “0,” executes the next instruction. When V1 2 = 1 : This instruction is equivalent to the NOP instruction. (V12: bit 2 of interrupt control register V1) When V1 3 = 0 : Clears (0) to the T2F flag and skips the next instruction when timer 2 interrupt request flag T2F is “1.” When the T2F flag is “0,” executes the next instruction. When V1 3 = 1 : This instruction is equivalent to the NOP instruction. (V13: bit 3 of interrupt control register V1) Transfers the input of port P0 to register A. Outputs the contents of register A to port P0. Transfers the input of port P1 to register A. Outputs the contents of register A to port P1. Transfers the input of port P2 to the low-order 2 bits (A 1, A0) of register A. “0” is stored to the bit 3 (A3) of register A. Outputs the contents of the low-order 2 bits (A1, A0) of register A to port P2. Transfers the input of port P3 to the low-order 2 bits (A1, A0) of register A. “0” is stored to the bit 3 (A3) of register A. Outputs the contents of the low-order 2 bits (A1, A0) of register A to port P3. Sets (1) to port D. Clears (0) to a bit of port D specified by register Y . Sets (1) to a bit of port D specified by register Y. Skips the next instruction when a bit of port D specified by register Y is “0.” Executes the next instruction when a bit of port D specified by register Y is “1.”

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.1.02 2006.12.22 page 126 of 140 REJ03B0147-0102 MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) TFR0A TFR1A TFR2A TFR3A TC1A TK0A TAK0 TK1A TAK1 TK2A TAK2 TPU0A TAPU0 TPU1A TAPU1 TPU2A TAPU2 TL1A TAL1 TABSI TSIAB SST SNZSI TAJ1 TJ1A CRCK TRGA TAMR TMRA 1000101000 1000101001 1000101010 1000101011 1010101000 1000011011 1001010110 1000010100 1001011001 1000010101 1001011010 1000101101 1001010111 1000101110 1001011110 1000101111 1001011111 1000001010 1001001010 1001111000 1000111000 1010011110 1010001000 1001000010 1000000010 1010011011 1000001001 1001010010 1000010110 228 229 22A 22B 2A8 21B 256 214 259 215 25A 22D 257 22E 25E 22F 25F 20A 24A 278 238 29E 288 242 202 29B 209 252 216 (FR0) ← (A) (FR1) ← (A) (FR2) ← (A) (FR3) ← (A) (C1) ← (A) (K0) ← (A) (A) ← (K0) (K1) ← (A) (A) ← (K1) (K2) ← (A) (A) ← (K2) (PU0) ← (A) (A) ← (PU0) (PU1) ← (A) (A) ← (PU1) (PU2) ← (A) (A) ← (PU2) (L1) ← (A) (A) ← (L1) (B) ← (SI 7–SI4) (A) ← (SI3–SI0) (SI7–SI4) ← (B) (SI3–SI0) ← (A) (SIOF) ← 0 Serial interface transmit/receive starting V23=0: (SIOF)=1? (SIOF) ← 0 V23 = 1: SNZSI = NOP (A) ← (J1) (J1) ← (A) RC oscillator selected (RG 0) ← (A0) (A) ← (MR) (MR) ← (A) Serial interface operation Input/Output operation Clock operation

Rev.1.02 2006.12.22 page 127 of 140 REJ03B0147-0102 Skip condition Datailed description Carry flag CY 3 = 0: (SIOF) =1 Transfers the contents of register A to port output structure control register FR0. Transfers the contents of register A to port output structure control register FR1. Transfers the contents of register A to port output structure control register FR2. Transfers the contents of register A to port output structure control register FR3. Transfers the contents of register A to port output structure control register C1. Transfers the contents of register A to key-on wakeup control register K0. Transfers the contents of key-on wakeup control register K0 to register A. Transfers the contents of register A to key-on wakeup control register K1. Transfers the contents of key-on wakeup control register K1 to register A. Transfers the contents of register A to key-on wakeup control register K2. Transfers the contents of key-on wakeup control register K2 to register A. Transfers the contents of register A to pull-up control register PU0. Transfers the contents of pull-up control register PU0 to register A. Transfers the contents of register A to pull-up control register PU1. Transfers the contents of pull-up control register PU1 to register A. Transfers the contents of register A to pull-up control register PU2. Transfers the contents of pull-up control register PU2 to register A. Transfers the contents of register A to key-on wakeup control register L1. Transfers the contents of key-on wakeup control register L1 to register A. Transfers the high-order 4 bits of serial interface register SI to register B, and transfers the low-order 4 bits of serial interface register SI to register A. Transfers the contents of register B to the high-order 4 bits of serial interface register SI, and transfers the contents of register A to the low-order 4 bits of serial interface register SI. Clears (0) to SIOF flag and starts serial interface transmit/receive. Clears (0) to SIOF flag and skips the next instruction when the contents of bit 3 (V2 3) of interrupt control reg- ister V2 is “0” and contents of SIOF flag is “1.” When V2 3 = 1: This instruction is equivalent to the NOP instruction. Transfers the contents of serial interface control register J1 to register A. Transfers the contents of register A to serial interface control register J1. Selects the RC oscillation circuit for main clock f(X IN). Transfers the least significant bit (A0) of register A to clock control regiser RG. Transfers the contents of clock control regiser MR to register A. Transfers the contents of register A to clock control register MR.

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Rev.1.02 2006.12.22 page 128 of 140 REJ03B0147-0102 SVDE** 279 249 239 244 204 29F 287 000 002 05B 003 29C 2A0 001 058 059 293 1001111001 1001001001 1000111001 1001000100 1000000100 1010011111 1010000111 0000000000 0000000010 0001011011 0000000011 1010011100 1010100000 0000000001 0001011000 0001011001 1010010011 A/D conversion operation Other operation Q1 3 = 0: (B) ← (AD9–AD 6) (A) ← (AD5–AD 2) Q1 3 = 1: (B) ← (AD7–AD 4) (A) ← (AD3–AD 0) (A3, A2) ← (AD1, AD0) (A1, A0) ← 0 Q1 3 = 0: (AD7–AD 4) ← (B) (AD3–AD 0) ← (A) Q1 3 = 1: TADAB = NOP (A) ← (Q1) (Q1) ← (A) (ADF) ← 0 Q1 3 = 0: A/D conversion starting Q1 3 = 1: Comparator operation starting (ADF) ← 0 V22 = 1: SNZAD = NOP (PC) ← (PC) + 1 RAM back-up POF instruction valid (P) = 1 ? Stop of watchdog timer function enabled (WDF1) = 1 ?, (WDF1) ← 0 System reset (UPTF) ← 0 (UPTF) ← 1 Voltage drop detection circuit valid at RAM back-up MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Note: The SVDE instruction can be used only in the H version.

Rev.1.02 2006.12.22 page 129 of 140 REJ03B0147-0102 Skip condition Datailed description Carry flag CY 2 = 0: (ADF) = 1 (P) = 1 (WDF1) = 1 In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9–AD 6) of register AD to register B, and the middle-order 4 bits (AD5–AD 2) of register AD to register A. In the comparator mode (Q13 = 1), transfers the high-order 4 bits (AD7–AD 4) of comparator register to reg- ister B, and the low-order 4 bits (AD3–AD 0) of comparator register to register A. (Q13: bit 3 of A/D control register Q1) Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (A3, A2) of register A. “0” is stored to the least significant bit (A0) of register A. In the comparator mode (Q13 = 1), transfers the contents of register B to the high-order 4 bits (AD7–AD 4) of comparator register, and the contents of register A to the low-order 4 bits (AD3–AD 0) of comparator register. In the A/D conversion mode (Q13 = 0), this instruction is equivalent to the NOP instruction. (Q13 = bit 3 of A/D control register Q1) Transfers the contents of A/D control register Q1 to register A. Transfers the contents of register A to A/D control register Q1. Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q1 = 0) or the comparator operation at the comparator mode (Q13 = 1) is started. (Q13 = bit 3 of A/D control register Q1) When V2 2 = 0 : Clears (0) to the ADF flag and skips the next instruction when A/D conversion completion flag ADF is “1.” When the ADF flag is “0,” executes the next instruction. When V2 2 = 1 : This instruction is equivalent to the NOP instruction. (V22: bit 2 of interrupt control register V2) No operation; Adds 1 to program counter value, and others remain unchanged. Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruction. Operations of all functions are stopped. Makes the immediate after POF instruction valid by executing the EPOF instruction. Skips the next instruction when the P flag is “1”. After skipping, the P flag remains unchanged. Executes the next instruction when the P flag is “0.” Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction. Clears (0) to the WDF1 flag and skips the next instruction when watchdog timer flag WDF1 is “1.” When the WDF1 flag is “0,” executes the next instruction. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction. System reset occurs. Clears (0) to the high-order bit reference enable flag UPTF. Sets (1) to the high-order bit reference enable flag UPTF. Validates the voltage drop detection circuit at RAM back-up (only for the H version).

Rev.1.02 2006.12.22 page 130 of 140 REJ03B0147-0102 D 3–D 0 Hex. notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A B C D E F D 9–D 4 NOP SRST POF SNZP DI EI RC SC AM AMC TYA TBA 000001 BLA CLD INY RD SD DEY AND OR TEAB CMA RAR TAB TAY 000010 SZB SZB SZB SZB SZD SEAn SEAM TDA TABE SZC 000011 BMLA SNZ0 SNZI0 TV2A TV1A 000100 RT RTS RTI LZ LZ LZ LZ RB RB RB RB 000101 TASP TAD TAX TAZ TAV1 TAV2 RUPT SUPT EPOF SB SB SB SB 000110 A A A A A A A A A A A A A A A A 000111 LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA 001000 TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP 001001 TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP 001010 001011 001100 001101 001110 001111 BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM 010000 010111 011000 011111 18–1F B B B B B B B B B B B B B B B B BL BML BLA BMLA SEA SZD The second word 10 0aaa aaaa 10 0aaa aaaa 10 0p00 pppp 10 0p00 pppp 00 0111 nnnn 00 0010 1011 10–17 000000 The above table shows the relationship between machine language codes and machine language instructions. D3–D 0 show the low-order 4 bits of the machine language code, and D9–D 4 show the high-order 6 bits of the machine language code. The hexadecimal representa- tion of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below.

Rev.1.02 2006.12.22 page 131 of 140 REJ03B0147-0102 INSTRUCTION CODE TABLE (continued) TJ1A TQ1A TRGA TL1A TW1A TW2A TW5A TW6A TK1A TK2A TMRA TI1A TK0A T1AB T2AB TPSAB TSIAB TADAB TAJ1 TAQ1 TALA TAL1 TAW1 TAW2 TAW5 TAW6 TAMR TAI1 TAK0 TAPU0 TAK1 TAK2 TAPU1 TAPU2 IAP0 IAP1 IAP2 IAP3 TAB1 TAB2 TABPS TABSI TABAD SNZT1 SNZT2 SNZAD SNZSI T1HAB SVDE* T2HAB T2R2L CRCK DWDT SST ADST WRST T1R1L TC1A TPAA TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA BL BML BLA BMLA SEA SZD The second word 10 0aaa aaaa 10 0aaa aaaa 10 0p00 pppp 10 0p00 pppp 00 0111 nnnn 00 0010 1011 OP0A OP1A OP2A OP3A TFR0A TFR1A TFR2A TFR3A TPU0A TPU1A TPU2A D 3–D 0 Hex. notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A B C D E F D 9–D 4 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 111111 30–3F 100000 The above table shows the relationship between machine language codes and machine language instructions. D3–D 0 show the low- order 4 bits of the machine language code, and D9–D 4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below.

• * can be used only in the H version.

Rev.1.02 2006.12.22 page 132 of 140 REJ03B0147-0102

Electrical characteristics

Input voltage P0, P1, P2, P3, D0–D 5, RESET , XIN Input voltage INT, CNTR0, CNTR1, SIN, SCK Input voltage AIN0–AIN5 Output voltage P0, P1, P2, P3, D0–D 5, RESET Output voltage CNTR0, CNTR1, SOUT , SCK Output voltage XOUT Power dissipation Operating temperature range Storage temperature range Conditions Output transistors in cut-off state Output transistors in cut-off state Ta = 25 °C Symbol VDD VI VI VI VO VO VO Pd Topr Tstg Unit V V V V V V V mW Ratings –0.3 to 6.5 –0.3 to VDD +0.3 –0.3 to VDD +0.3 –0.3 to VDD +0.3 –0.3 to VDD +0.3 –0.3 to VDD +0.3 –0.3 to VDD +0.3 300 –20 to 85 –40 to 125

Rev.1.02 2006.12.22 page 133 of 140 REJ03B0147-0102 Recommended operating conditions 1 (Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) Symbol VDD VDD VDD VRAM VSS VIH VIL IOH (peak) IOH (avg) IOL (peak) IOL (avg) ΣIOH (avg) ΣIOL (avg) Parameter Supply voltage (with a ceramic resonator) Supply voltage (with RC oscillation) Supply voltage (with an on-chip oscillator) RAM back-up voltage Supply voltage “H ” level input voltage “L” level input voltage “H ” level peak output current “H ” level average output current (Note) “L” level peak output current “L” level average output current “H ” level total average current “L” level total average current Notes 1: The average output current (IOH , IOL ) is the average value during 100 ms. UnitConditions f(STCK) ≤ 6 MHz f(STCK) ≤ 4.4 MHz f(STCK) ≤ 2.2 MHz f(STCK) ≤ 1.1 MHz f(STCK) ≤ 4.4 MHz (at RAM back-up) P0, P1, P2, P3, D0–D 5 XIN RESET INT, CNTR0, CNTR1, SIN, SCK P0, P1, P2, P3, D0–D 5 XIN RESET INT, CNTR0, CNTR1, SIN, SCK P0, P1, P2, P3, D0–D 5 CNTR0, CNTR1, S OUT , SCK P0, P1, P2, P3, D0–D 5 CNTR0, CNTR1, S OUT , SCK P0, P1 CNTR0, CNTR1, S OUT , SCK P2, P3, RESET D 0, D1, D4, D5 D 2, D3 P0, P1 CNTR0, CNTR1, S OUT , SCK P2, P3, RESET D 0, D1, D4, D5 D 2, D3 P0, P1, P3, CNTR0, CNTR1, SOUT , SCK P2, D0–D 5 P0, P1, P3, CNTR0, CNTR1, SOUT , SCK P2, D0–D 5, RESET Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 V DD VDD VDD VDD 0.2VDD 0.3VDD 0.3VDD 0.15VDD –20 –10 –10 4.0 6.0 5.0 2.0 7.0 –40 –40 Limits Min. 2.7 2.0 1.8 2.7 1.8 1.6 0.8V DD 0.7VDD 0.85VDD 0.85VDD Typ. V V V V V V V mA mA mA mA mA mA VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V

Rev.1.02 2006.12.22 page 134 of 140 REJ03B0147-0102 Recommended operating conditions 2 (Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) f(XIN) f(XIN) f(XIN) f(CNTR) tw(CNTR) f(SCK ) tw(SCK ) TPON Oscillation frequency (with a ceramic resonator) Oscillation frequency (with RC oscillation) (Note 1) Oscillation frequency (with a ceramic oscillation selected, external clock input) Timer external input frequency Timer external input period (“H ” and “L” pulse width) Serial interface external input period Serial interface external input period (“H ” and “L” pulse width) Power-on reset circuit valid supply voltage rising time (Note 2) Conditions MHz MHz MHz Hz s Hz s µs Max. 4.4 2.2 1.1 4.4 2.2 4.4 4.4 4.8 3.2 1.6 0.8 4.8 3.2 1.6 4.8 3.2 f(STCK)/6 f(STCK)/6 100 Limits Through mode Internal frequency divided by 2 Internal frequency divided by 4, 8 VDD = 2.7 V to 5.5 V Through mode Internal frequency divided by 2 Internal frequency divided by 4, 8 CNTR0, CNTR1 CNTR0, CNTR1 SCK SCK VDD = 0 → 1.8 V Min. Typ. 3/f(STCK) 3/f(STCK) ParameterSymbol Unit Notes 1: The frequency at RC oscillation is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits. 2: If the rising time exceeds the maximum rating value, connect a capacitor between the RESET pin and Vss at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage. VDD = 4.0 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 1.8 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 1.8 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 1.8 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 1.8 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 1.8 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 1.8 V to 5.5 V 21.8 2.7 45 . 5 VDD [V] 2.2 1.1 4.4 4.4 2.7 5.5 When RC oscillation is used 5.5 When ceramic resonator is used When external clock is used f(STCK) [MHz] VDD [V] f(STCK) [MHz] VDD [V] f(STCK) [MHz] Recommended operating condition 4.8 21.8 2.7 4 1.6 0.8 3.2 Recommended operating condition Recommended operating condition System clock (STCK) operating condition map

Rev.1.02 2006.12.22 page 135 of 140 REJ03B0147-0102 Electrical characteristics 1 (Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) VOH VOL VOL VOL VOL IIH IIL R PU VT+ – VT– VT+ – VT– f(RING) ∆ f(XIN) “H ” level output voltage P0, P1, P2, P3, D0–D 5 CNTR0, CNTR1, S OUT , SCK “L” level output voltage P0, P1 CNTR0, CNTR1, S OUT , SCK “L” level output voltage P2, P3, RESET “L” level output voltage D 0, D1, D4, D5 “L” level output voltage D 2, D3 “H ” level input current P0, P1, P2, P3, D0–D 5 RESET , INT CNTR0, CNTR1, S IN, SCK “L” level input current P0, P1, P2, P3, D0–D 5 RESET , INT CNTR0, CNTR1, S IN, SCK Pull-up resistor value P0, P1, P2, D2, D3, RESET Hysteresis RESET Hysteresis INT, CNTR0, CNTR1 SIN, SCK On-chip oscillator clock frequency Oscillation frequency error (Note 1) (at RC oscillation, error value of external R, C not included) V V V V V µA µA kΩ V V kHz Test conditions VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VI = VDD VI = 0 V P0, P1, P2, D2, D3 No pull-up VI = 0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 1.8 V VDD = 5.0 V ± 10 %, Ta = center 25 °C VDD = 3.0 V ± 10 %, Ta = center 25 °C Limits Max. 2.0 0.9 0.9 0.6 2.0 0.6 0.9 2.0 0.9 2.0 0.9 2.0 0.9 1.4 0.9 2.0 –2.0 125 250 700 400 200 ±17 ±17 IOH = –10 mA IOH = –3.0 mA IOH = –5.0 mA IOH = –1.0 mA IOL = 12 mA IOL = 4.0 mA IOL = 6.0 mA IOL = 2.0 mA IOL = 5.0 mA IOL = 1.0 mA IOL = 2.0 mA IOL = 30 mA IOL = 10 mA IOL = 15 mA IOL = 5.0 mA IOL = 15 mA IOL = 5.0 mA IOL = 9.0 mA IOL = 3.0 mA VDD = 5.0 V VDD = 3.0 V Min. 3.0 4.1 2.1 2.4 200 100 Typ. 120 1.0 0.4 0.2 0.2 500 250 120 Symbol Parameter Unit Notes 1: When the RC oscillation is used, use a 33 pF capacitor externally.

Rev.1.02 2006.12.22 page 136 of 140 REJ03B0147-0102 Electrical characteristics 2 (Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) IDD Supply current mA mA mA µA µA µA Test conditions VDD = 5.0 V f(XIN) = 6.0 MHz f(RING) = stop VDD = 5.0 V f(XIN) = 4.0 MHz f(RING) = stop VDD = 3.0 V f(XIN) = 2.0 MHz f(RING) = stop VDD = 5.0 V f(XIN) = stop f(RING) = operating VDD = 3.0 V f(XIN) = stop f(RING) = opertaing Ta = 25 °C VDD = 5.0 V VDD = 3.0 V Limits Max. 2.4 2.6 3.2 4.4 1.8 2.4 3.2 0.4 0.5 0.6 0.8 100 120 160 240 f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(RING)/8 f(STCK) = f(RING)/4 f(STCK) = f(RING)/2 f(STCK) = f(RING) f(STCK) = f(RING)/8 f(STCK) = f(RING)/4 f(STCK) = f(RING)/2 f(STCK) = f(RING) Min. Typ. 1.2 1.3 1.6 2.2 0.9 1.2 1.6 0.2 0.25 0.3 0.4 120 0.1 Symbol Parameter Unit Notes 1: When the A/D converter is used, the A/D operation current (IADD ) is included. 2: In the M34509G4H, the voltage drop detection circuit operation current (IRST ) is added. 3: In the M34509G4H, when the SVDE instruction is executed, the voltage drop detection circuit operation current (IRST ) is added. at active mode (with a ceramic resonator) (Notes 1, 2) at active mode (with an on-chip oscillator) (Notes 1, 2) at RAM back-up mode (POF instruction execution) (Note 3)

Rev.1.02 2006.12.22 page 137 of 140 REJ03B0147-0102 A/D converter recommended operating conditions (Comparator mode included, Ta = –20 °C to 85 °C, unless otherwise noted) Symbol VDD VIA f(ADCK) Parameter Supply voltage Analog input voltage A/D clock frequency (Note) Conditions Unit V V kHz Ta = 0 °C to 50 °C Ta = –20 °C to 85 °C VDD = 4.0 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2.2 V to 5.5 V VDD = 2.0 V to 5.5 V Min. 2.0 2.7 0.8 0.8 0.8 0.8 Typ. Max. 5.5 5.5 V DD 334 123 61.2 15.3 Limits Division circuit System clock (STCK) Instruction clock (INSTCK) Multi- plexer MR 0 MR 3, MR2 On-chip oscillator XIN Ceramic resonance RC oscillation Internal clock generating circuit (divided by 3) Divided by 2 Divided by 4 Divided by 8 A/D clock generating circuit (divided by 6) A/D conversion clock (ADCK) Note: Definition of A/D conversion clock (ADCK) A/D clock (ADCK) operating condition map 334 123 22 . 7 42.2 5.5 61.2 0.8 15.3 VDD [V] f(ADCK) [kHz] A/D clock recommended operating condition

Rev.1.02 2006.12.22 page 138 of 140 REJ03B0147-0102 A/D converter characteristcs (Ta = –20 °C to 85 °C, unless otherwise noted) Symbol V VFST IADD TCONV Parameter Resolution Linearity error Differential non-linearity error Zero transition voltage Full-scale transition voltage Absolute accuracy (Quantization error excluded) A/D operating current (Note 1) A/D conversion time Comparator resolution Comparator error (Note 2) Comparator comparison time Test conditions bits LSB LSB mV mV LSB µA µs bits mV µs Ta = 0 °C to 50 °C, 2.2 V ≤ VDD 0 °C 2.7 V Ta = –20 °C to 85 °C, 2.7 V ≤ VDD ≤ 5.5 V Ta = 0 °C to 50 °C, 2.2 V ≤ VDD < 2.7 V Ta = –20 °C to 85 °C, 2.7 V ≤ VDD ≤ 5.5 V VDD = 2.56 V VDD = 3.075 V VDD = 5.12 V VDD = 2.56 V VDD = 3.075 V VDD = 5.12 V Ta = 0 °C to 50 °C, 2.0 V ≤ VDD < 2.2 V VDD = 5.0 V VDD = 3.0 V f(ADCK) = 334 kHz f(ADCK) = 123 kHz f(ADCK) = 61.2 kHz f(ADCK) = 15.3 kHz V DD = 2.56 V VDD = 3.072 V VDD = 5.12 V f(ADCK) = 334 kHz f(ADCK) = 123 kHz f(ADCK) = 61.2 kHz f(ADCK) = 15.3 kHz Min. 2552.5 3064.5 5100 Typ. 7.5 7.5 2560 3072 5110 300 100 Max. ±4.0 ±2.0 ±0.9 ±0.9 2567.5 3079.5 5120 ±8.0 900 300 169 676 ± 15 ± 15 ± 20 Limits Notes 1: When the A/D converter is used, the IADD is included to IDD . 2: As for the error from the logic value in the comparator mode, when the contents of the comparator register is n, the logic value of the comparison voltage Vref which is generated by the built-in DA converter can be obtained by the following formula. Logic value of comparison voltage Vref Vref = ✕ n n = Value of register AD (n = 0 to 255) VDD 256 Unit

Rev.1.02 2006.12.22 page 139 of 140 REJ03B0147-0102 Basic timing diagram VOLTAGE DROP DETECTION CIRCUIT CHARACTERISTICS (Ta = –20 °C to 85 °C, unless otherwise noted) Test conditions Ta = 25 °C -20 °C ≤ Ta < 0 °C 0 °C ≤ Ta < 50 °C 50 °C ≤ Ta ≤ 85 °C Ta = 25 °C -20 °C ≤ Ta < 0 °C 0 °C ≤ Ta < 50 °C 50 °C ≤ Ta ≤ 85 °C VDD = 5 V VDD = 3 V VDD → (VRST – – 0.1 V) Parameter Detection voltage (reset occurs) (Note 2) Detection voltage (reset release) (Note 3) Detection voltage hysteresis Operation current (Note 4) Detection time (Note 5) Symbol V RST – VRST + VRST + – VRST – IRST TRST Limits UnitMin. 2.5 2.2 2.6 2.3 2.1 Typ. 2.6 2.7 0.1 0.2 Max. 3.1 2.7 3.2 3.1 2.8 100 1.2 V V V µA ms Notes 1: The voltage drop detection circuit is equipped with only the M34509G4H. 2: The detection voltage (VRST –) is defined as the voltage when reset occurs when the supply voltage (VDD ) is falling. 3: The detection voltage (VRST +) is defined as the voltage when reset is released when the supply voltage (VDD ) is rising from reset occurs. 4: In the M34509G4H, IRST is added to IDD (supply current). 5: The detection time (TRST ) is defined as the time until reset occurs when the supply voltage (VDD ) is falling to [VRST – – 0.1 V]. STCK Parameter Pin name Machine cycle Mi Mi+1 D 0–D 5 P00–P03 P10–P13 P00–P03 P10–P13 P20, P21 P20, P21 System clock Port output Port input D 0–D 5 INTInterrupt input P30, P31 P30, P31

Rev.1.02 2006.12.22 page 140 of 140 REJ03B0147-0102 F 1 12 1324 Index mark y E HE e bp D A c Detail F A1A2 L INCLUDE TRIM OFFSET. DIMENSION "*3" DOES NOT NOTE) DO NOT INCLUDE MOLD FLASH. A1 0 0.1 0.2 Previous CodeJEITA Package Code RENESAS Code PRSP0024GA-A 24P2Q-A MASS[Typ.] 0.2gP-SSOP24-5.3x10.1-0.80 0.250.20.18 0.450.350.3 MaxNomMin Dimension in Millimeters Symbol Reference 10.210.110.0D 5.45.35.2E 1.8A2 8.17.87.5 2.1A 0.80.60.4L 8°0° c 0.8e 0.10y HE bp 0.65 0. 95

REVISION HISTORY

Rev. Date Description Page Summary

4509 Group Data Sheet

1.00 Mar. 18, 2005 First edition issued – (1/1) 1.01 Aug. 12, 2005 17 ROM Code Protect Address added. 52 Table 20: Some description about Port P1 added. 57 Fig.52 revised. 58 Fig.54 revised. “DATA REQUIRED FOR QzROM WRITING ORDERS ” added. 62 Notes On ROM Code Protect added.

130 A/D converter characteristics:

Linearity error, Differential non-linearity error and Absolute accuracy → Parameters and Test conditions revised. 131 Voltage drop detection circuit characteristics: VRST -, VRST + → Test conditions revised. 1.02 Dec. 22, 2006 5 MULFUNCTION: Note 4 revised. 26 TIMER: Description revised and Structure of Timer 2 in Table 9 revised. 28 Fig.23: INSTCK (wrong) → INTSNC (correct) 30 (2) Prescaler: PRS → RPS (3) Timer 3 → Timer 1 43 SERIAL I/O: Table 14: Note revised. 53 Fig. 46: Notes revised. 58 Table 23: Changes referring ahead and note 5 added. 59 to 61 QzROM Writing Mode added. 63 LIST OF PRECAUTIONS: Mulfunction revised. 67 to 70 NOTES ON NOISE added. 76 Description of Port output structure control register FR2 and FR3 revised. 102 Instruction code of TAL1 revised. Description of TALA revised. 117 Detailed description of TEAB revised. 134 f(S CK ): Serial interface external input frequency → Serial interface external input period 135 ∆ f(XIN): Ta = around 25 °C → center 25 °C 137 Figure title revised, “When ceramic resonator is used” deleted.

139 Note 4: ( power current) → (supply current)

→ Pages 79–81, 93–95, 114, 122–129: Description of SNZ0, SNZT1, SNZT2, SNZAD, SNZSI and WRST instructions revised.

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