MC44608 ONSEMI | Alldatasheet
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Technical content
Semiconductor Components Industries, LLC, 1999 January, 2000 – Rev. 2
1 Publication Order Number:
/C0077/C0067/C0052/C0052/C0054/C0048/C0056 /C0070/C0101/C0119/C0069/C0120/C0116/C0101/C0114/C0110/C0097/C0108/C0067/C0111/C0109/C0112/C0111/C0110/C0101/C0110/C0116/C0115 /C0082/C0101/C0108/C0105/C0097/C0098/C0108/C0101/C0097/C0110/C0100/C0070/C0108/C0101/C0120/C0105/C0098/C0108/C0101 /C0071/C0114/C0101/C0101/C0110/C0076/C0105/C0110/C0101 /C0086/C0101/C0114/C0121/C0072/C0105/C0103/C0104/C0086/C0111/C0108/C0116/C0097/C0103/C0101 /C0080/C0087/C0077/C0067/C0111/C0110/C0116/C0114/C0111/C0108/C0108/C0101/C0114 The MC44608 is a high performance voltage mode controller designed for off–line converters. This high voltage circuit that integrates the start–up current source and the oscillator capacitor, requires few external components while offering a high flexibility and reliability. The device also features a very high efficiency stand–by management consisting of an effective Pulsed Mode operation. This technique enables the reduction of the stand–by power consumption to approximately 1W while delivering 300mW in a 150W SMPS.
- Integrated Start–Up Current Source
- Lossless Off–Line Start–Up
- Direct Off–Line Operation
- Fast Start–Up General Features
- Flexibility
- Duty Cycle Control
- Undervoltage Lockout with Hysteresis
- On Chip Oscillator Switching Frequency 40, or 75kHz
- Secondary Control with Few External Components Protections
- Maximum Duty Cycle Limitation
- Cycle by Cycle Current Limitation
- Demagnetization (Zero Current Detection) Protection
- “Over VCC Protection” Against Open Loop
- Programmable Low Inertia Over V oltage Protection Against Open Loop
- Internal Thermal Protection GreenLine Controller
- Pulsed Mode Techniques for a Very High Efficiency Low Power Mode
- Lossless Startup
- Low dV/dT for Low EMI Radiations Device Switching Frequency Shipping
ORDERING INFORMATION
DIP–8 P SUFFIX CASE 626 http://onsemi.com 1 8 (Top View) Demag Isense Control Input Vi PIN CONNECTIONS AND MARKING DIAGRAM Gnd Vcc Driver 44608Pxxx Package Plastic DIP–8 Plastic DIP–8 50 / Rail 50 / Rail AWL YYWW AWL = Manufacturing Code YYWW = Date Code
http://onsemi.com REPRESENTATIVE BLOCK DIAGRAM DMG Demag Logic Output Start–up PhaseSwitching Phase Latched off Phase
1 V 4 kHz Filter
&Latched off Phase Stand–by Thermal DMG OUT Disable OVP UVLO1 Switching Phase Start–up Phase Latched off Phase UVLO2 9 mA Start–up CC Buffer PWM QR S PWM VPWM& OSC OSC Clock Stand–by Leading Edge Stand–by Demag Vi Isense Control GND Driver V Input CC Shutdown Latch UVLO2 Management V Source Management Enable Blanking Output CS
2 S/C0109
120 A/C0109>24 A/C0109 50 mV /20 mV NOCOC
200 A/C0109
Start–up Phase MAXIMUM RATINGS Rating Symbol Value Unit Total Power Supply Current ICC 30 mA Output Supply Voltage with Respect to Ground VCC 16 V All Inputs except Vi Vinputs –1.0 to +16 V Line Voltage Vi 500 V Power Dissipation and Thermal Characteristics Maximum Power Dissipation at TA = 85°C PD 600 mW Thermal Resistance, Junction–to–Air R θJA 100 °C/W Operating Junction Temperature TJ 150 °C Operating Ambient Temperature TA –25 to +85 °C
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ELECTRICAL CHARACTERISTICS
Characteristic Symbol Min Typ Max Unit OUTPUT SECTION Output Resistor /C0087 Sink Resistance R OL 5.0 8.5 15 Source Resistance R OH 15 Output Voltage Rise Time (from 3 V up to 9 V) (1) tr 50 ns Output Voltage Falling Edge Slew–Rate (from 9 V down to 3 V) (1) tf 50 ns CONTROL INPUT SECTION Duty Cycle @ Ipin3 = 2.5 mA d2mA 2.0 % Duty Cycle @ Ipin3 = 1.0 mA d1mA 36 43 48 % Control Input Clamp Voltage (Switching Phase) @ Ipin3 = –1.0 mA 4.75 5.0 5.25 V Latched Phase Control Input Voltage (Stand–by) @ Ipin3 = +500 /C0109A VLP–stby 3.4 3.9 4.3 V Latched Phase Control Input Voltage (Stand–by) @ Ipin3 = +1.0 mA VLP–stby 2.4 3.0 3.7 V CURRENT SENSE SECTION Maximum Current Sense Input Threshold VCS–th 0.95 1.0 1.05 V Input Bias Current IB–cs –1.8 1.8 /C0109A Stand–By Current Sense Input Current ICS–stby 180 200 220 /C0109A Start–up Phase Current Sense Input Current ICS–stup 180 200 220 /C0109A Propagation Delay (Current Sense Input to Output @ VTH T MOS = 3 V) TPLH(In/Out) 220 ns Leading Edge Blanking Duration MC44608P40 TLEB 480 ns Leading Edge Blanking Duration MC44608P75 TLEB 250 ns Leading Edge Blanking Duration MC44608P100 TLEB 200 ns Leading Edge Blanking + Propagation Delay MC44608P40 TDLY 500 680 900 ns Leading Edge Blanking + Propagation Delay MC44608P75 TDLY 370 470 570 ns Leading Edge Blanking + Propagation Delay MC44608P100 TDLY 400 ns OSCILLATOR SECTION Normal Operation Frequency MC44608P40 fosc 36 40 44 kHz Normal Operation Frequency MC44608P75 fosc 68 75 82 kHz Normal Operation Frequency MC44608P100 fosc 100 kHz Maximum Duty Cycle @ f = fosc dmax 78 82 86 % OVERVOLTAGE SECTION Quick OVP Input Filtering (Rdemag = 100 k/C0087) Tfilt 250 ns Propagation Delay (Idemag > Iovp to output low) TPHL(In/Out) 2.0 µs Quick OVP Current Threshold IOVP 105 120 140 µA Protection Threshold Level on VCC VCC–OVP 14.8 15.3 15.8 V Minimum Gap Between VCC–OVP and Vstup–th VCC–OVP – Vstup 1.0 V NOTES: (1) This parameter is measured using 1.0 nF connected between the output and the ground.
http://onsemi.com ELECTRICAL CHARACTERISTICS (VCC = 12 V, for typical values TA = 25°C, for min/max values TA = –25°C to +85°C unless otherwise noted) (Note 1) Characteristic Symbol Min Typ Max Unit DEMAGNETIZATION DETECTION SECTION (Note 2) Demag Comparator Threshold (Vpin1 increasing) Vdmg–th 30 50 69 mV Demag Comparator Hysteresis (Note 3) H dmg 30 mV Propagation Delay (Input to Output, Low to High) tPHL(In/Out) 300 ns Input Bias Current (Vdemag = 50 mV) Idem–lb –0.6 /C0109A Negative Clamp Level (Idemag = –1 mA) Vcl–neg–dem –0.9 –0.7 –0.4 V Positive Clamp Level @ Idemag = 125 /C0109A Vcl–pos– dem–H 2.05 2.3 2.8 V Positive Clamp Level @ Idemag = 25 /C0109A Vcl–pos– dem–L 1.4 1.7 1.9 V OVERTEMPERATURE SECTION Trip Level Over Temperature Thigh 160 °C Hysteresis Thyst 30 °C STAND–BY MAXIMUM CURRENT REDUCTION SECTION Normal Mode Recovery Demag Pin Current Threshold Idem–NM 20 25 30 /C0109A K FACTORS SECTION FOR PULSED MODE OPERATION ICCS / Istup MC44608P40 10 x K1 2.4 2.9 3.8 – ICCS / Istup MC44608P75 10 x K1 2.8 3.3 4.2 – ICCS / Istup MC44608P100 10 x K1 3.5 – ICCL / Istup 103 x K2 46 52 63 – (Vstup – UVLO2) / (Vstup – UVLO1) 102 x Ksstup 1.8 2.2 2.6 – (UVLO1 – UVLO2) / (Vstup – UVLO1) 102 x Ksl 90 120 150 – ICS / Vcsth 106 x Ycstby 175 198 225 – Demag ratio Iovp / Idem NM Dmgr 3.0 4.7 5.5 – (V3 1 mA – V3 0.5 mA ) / (1 mA – 0.5 mA) R3 1800 /C0087 Vcontrol Latch–off V3 4.8 V SUPPLY SECTION Minimum Start–up Voltage Vilow 50 V VCC Start–up Voltage Vstup–th 12.5 13.1 13.8 V Output Disabling VCC Voltage After Turn On Vuvlo1 9.5 10 10.5 V Hysteresis (Vstup–th – Vuvlo1) H stup–uvlo1 3.1 V VCC Undervoltage Lockout Voltage Vuvlo2 6.2 6.6 7.0 V Hysteresis (Vuvlo1 – Vuvlo2) H uvlo1–uvlo2 3.4 V Absolute Normal Condition VCC Start Current @ (Vi = 100 V) and (VCC = 9 V) Switching Phase Supply Current (no load) MC44608P40 MC44608P75 MC44608P100 ICCS 2.0 2.4 2.6 3.2 3.4 3.6 4.0 mA Latched Off Phase Supply Current ICC–latch 0.3 0.5 0.68 mA Hiccup Mode Duty Cycle (no load) /C0100Hiccup 10 % NOTES: (1) Adjust VCC above the start–up threshold before setting to 12 V. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. (2) This function can be inhibited by connecting pin 1 to GND. (3) Guaranteed by design (non tested)
120µA level to detect an Over Voltage status called Quick OVP. 4 Ground This pin is the ground of the primary side of the SMPS. 5 Driver The current and slew rate capability of this pin are suited to drive Power MOSFETs. disabling condition called Latched Off phase. 7 This pin is to provide isolation between the Vi pin 8 and the VCC pin 6. VCC capacitor. As soon as the IC starts–up, this current source is disabled. Figure 1. Regulator
5 V 4 kHz
the shunt regulator represented by the zener diode is 20/C0087. section PULSED MODE DUTY CYCLE CONTROL). the block diagram on page 2).
Figure 2. Current Sense required to sense the current. to a reference that is typically equal to 50mV . the demagnetization detection even during start–up. signal which may alter the demagnetization detection. during the demagnetization phase. this current is detected as higher than 120µA. Figure 3. Demagnetization Block case, the quick and programmable OVP is also disabled. Figure 4. Oscillator Block working conditions (Refer to DMG signal in the Figure 5).
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- 2. Overload In the hiccup mode the 3 distinct phases are described as follows (refer to Figure 6): The SWITCHING PHASE: The SMPS output is low and the regulation block reacts by increasing the ON time (dmax = 80%). The OC is reached at the end of every switching cycle. The LW latch (Figure 7) is reset before the VPWM signal appears. The SMPS output voltage is low. The VCC voltage cannot be maintained at a normal level as the auxiliary winding provides a voltage which is also reduced in a ratio similar to the one on the output (i.e. V out nominal / V out short–circuit). Consequently the VCC voltage is reduced at an operating rate given by the combination VCC capacitor value together with the ICC working consumption (3.2mA) according to the equation 2. When VCC crosses 10V the WORKING PHASE gets terminated. The LW latch remains in the reset status. The LATCHED–OFF PHASE: The V CC capacitor voltage continues to drop. When it reaches 6.5V this phase is terminated. Its duration is governed by equation 3. The START–UP PHASE is reinitiated. The high voltage start–up current source (–ICC1 = 9mA) is activated and the MODE latch is reset. The VCC voltage ramps up according to the equation 1. When it reaches 13V , the IC enters into the SWITCHING PHASE. The NEXT SWITCHING PHASE: The high voltage current source is inhibited, the MODE latch (Q=0) activates the NORMAL mode of operation. Figure 2 shows that no current is injected out pin 2. The over current sense level corresponds to 1V . As long as the overload is present, this sequence repeats. The SWITCHING PHASE duty cycle is in the range of 10%.
- 3. Transition from Normal to Pulsed Mode In this sequence the secondary side is reconfigured (refer to the typical application schematic on page 13). The high voltage output value becomes lower than the NORMAL mode regulated value. The TL431 shunt regulator is fully OFF. In the SMPS stand–by mode all the SMPS outputs are lowered except for the low voltage output that supply the wake–up circuit located at the isolated side of the power supply. In that mode the secondary regulation is performed by the zener diode connected in parallel to the TL431. The secondary reconfiguration status can be detected on the SMPS primary side by measuring the voltage level present on the auxiliary winding Laux. (Refer to the Demagnetization Section). In the reconfigured status, the Laux voltage is also reduced. The VCC self–powering is no longer possible thus the SMPS enters in a hiccup mode similar to the one described under the Overload condition. In the SMPS stand–by mode the 3 distinct phases are: The SWITCHING PHASE: Similar to the Overload mode. The current sense clamping level is reduced according to the equation of the current sense section, page 5. The C.S. clamping level depends on the power to be delivered to the load during the SMPS stand–by mode. Every switching sequence ON/OFF is terminated by an OC as long as the secondary Zener diode voltage has not been reached. When the Zener voltage is reached the ON cycle is terminated by a true PWM action. The proper SWITCHING PHASE termination must correspond to a NOC condition. The LW latch stores this NOC status. The LATCHED OFF PHASE: The MODE latch is set. The START–UP PHASE is similar to the Overload Mode. The MODE latch remains in its set status (Q=1). The SWITCHING PHASE: The Stand–by signal is validated and the 200µA is sourced out of the Current Sense pin 2.
- 4. Transition from Stand–by to Normal The secondary reconfiguration is removed. The regulation on the low voltage secondary rail can no longer be achieved, thus at the end of the SWITCHING PHASE, no PWM condition can be encountered. The LW latch is reset. At the next WORKING PHASE a NORMAL mode status takes place. In order to become independent of the recovery time constant on the secondary side of the SMPS an additional reset input R2 is provided on the MODE latch. The condition Idemag<24µA corresponds to the activation of the secondary reconfiguration status. The R2 reset insures a return into the NORMAL mode following the first START–UP PHASE. Pulsed Mode Duty Cycle Control During the sleep mode of the SMPS the switch S3 is closed and the control input pin 3 is connected to a 4.6V voltage source thru a 500/C0087 resistor. The discharge rate of the V CC capacitor is given by ICC–latch (device consumption during the LATCHED OFF phase) in addition to the current drawn out of the pin 3. Connecting a resistor between the Pin 3 and GND (RDPULSED ) a programmable current is drawn from the VCC through pin 3. The duration of the LATCHED OFF phase is impacted by the presence of the resistor R DPULSED . The equation 3 shows the relation to the pin 3 current. Pulsed Mode Phases Equations 1 through 8 define and predict the effective behavior during the PULSED MODE operation. The equations 6, 7, and 8 contain K, Y , and D factors. These factors are combinations of measured parameters. They appear in the parameter section “Kfactors for pulsed mode operation” page 4. In equations 3 through 8 the pin 3 current is the current defined in the above section “Pulsed Mode Duty Cycle Control”.
http://onsemi.com EQUATION 1 Start–up Phase Duration: tstart–up/C0043 C Vcc /C0032(Vstup/C0042UVLO2) Istup where: Istup is the start–up current flowing through VCC pin C Vcc is the VCC capacitor value EQUATION 2 Switching Phase Duration: tswitch/C0043 C Vcc /C0032(Vstup/C0042UVLO1) IccS /C0041IG where: IccS is the no load circuit consumption in switching phase IG is the current consumed by the Power Switch EQUATION 3 Latched–off Phase Duration: tlatched/C0042off/C0043 C Vcc /C0032(UVLO1 /C0042UVLO2) IccL/C0041Ipin3 where: IccL is the latched off phase consumption Ipin3 is the current drawn from pin3 adding a resistor EQUATION 4 Burst Mode Duty Cycle: dBM /C0043 tswitch tstart/C0042up /C0041tswitch/C0041tlatched/C0042off EQUATION 5 dBM /C0043 C Vcc/C0032(Vstup/C0042UVLO1) IccS/C0041IG C Vcc/C0032(Vstup/C0042UVLO2) Istup /C0041 C Vcc/C0032(Vstup/C0042UVLO1) IccS/C0041IG /C0041 C Vcc/C0032(UVLO1 /C0042UVLO2) IccL/C0041Ipin3 EQUATION 6 dBM /C0043 1 1 /C0041/C0466kS/C0324Stup/C0032 IccS/C0041IG Istup /C0467/C0041/C0466kS/C0324L /C0032 IccS/C0041IG IccL/C0041Ipin3 /C0467 where: kS/Stup = (Vstup – UVLO2)/(Vstup – UVLO1) kS/L = (UVLO1 – UVLO2)/(Vstup – UVLO1)
http://onsemi.com EQUATION 7 dBM /C0043 1 1 /C0041/C0551/C0545 /C0546 IccS/C0041IG Istup /C0032/C0466kS/C0324Stup/C0041/C0466kS/C0324L /C0032 Istup IccL/C0041Ipin3 /C0467/C0467/C0551/C0547 /C0548 EQUATION 8 dBM /C0043 1 1 /C0041 /C0551 /C0551/C0549 /C0545 /C0546 /C0466k1 /C0041 IG Istup /C0467/C0032 /C0551/C0551/C0551/C0551 /C0545 /C0546 kS/C0324Stup/C0041(kS/C0324L /C0032 1 k2/C0041/C0466 Ipin3 Istup /C0467 /C0551/C0551/C0551/C0551 /C0547 /C0548/C0551 /C0551/C0550 /C0547 /C0548 where: k1 = Iccs/Istup k2 = IccL/Istup kS/Stup = (Vstup–UVLO2)/(Vstup–UVLO1) kS/L = (UVLO1–UVLO2)/(Vstup–UVLO1) PULSED MODE CURRENT SENSE CLAMPING LEVEL Equations 9, 10, 11 and 12 allow the calculation of the Rcs value for the desired maximum current peak value during the SMPS stand–by mode. EQUATION 9 Ipkstby/C0043 Vcs–th/C0042(Rcs/C0032Ics) R S where: Vcs–th is the CS comparator threshold Ics is the CS internal current source R S is the sensing resistor R cs is the resistor connected between pin 2 and RS EQUATION 10 Ipkstby/C0043Vcs–th/C0032 1 /C0042/C0466R cs/C0032 Ics Vcs–th /C0467 R S EQUATION 11 Ipkstby/C0043Vcs–th/C0032 1 /C0042(Rcs/C0032Ycs–stby) R S where: Ycs–stby = Ics/Vcs–th Taking into account the circuit propagation delay (/C0100tcs) and the Power Switch reaction time (/C0100tps): EQUATION 12 Ipkstby/C0043/C0426Vcs–th/C0032 1 /C0042(Rcs/C0032Ycs–stby) R S /C0427/C0041 Vin/C0032(/C0100tcs/C0041/C0100tps) Lp
Figure 8. Output Switching Speed Figure 9. Frequency Stability Figure 10. Duty Cycle Control
65.0 Frequency
Figure 11. Vpin3 During the Working Period Figure 12. Vpin3 During the Latched Off Period Figure 13. Device Consumption when Switching
3.00 Pin6 Current (mA)
The Figure 18 represents a complete power supply using the secondary reconfiguration. Figure 17. Typical Application
22 F/C0109+I
8 V/1 A
for the microProcessor supply. Figure 18. SMPS Pulsed Mode effective ton current flowing in the sensing resistor R11.
http://onsemi.com PACKAGE DIMENSIONS DIP–8 P SUFFIX PLASTIC PACKAGE CASE 626–05 ISSUE K NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. STYLE 1: PIN 1. AC IN 2. DC + IN 3. DC – IN 4. AC IN 5. GROUND 6. OUTPUT 7. AUXILIARY 8. V CC F NOTE 2 –A– –B– –T– SEATING PLANE H J G D K N C L M MAM0.13 (0.005) B MT DIM MIN MAX MIN MAX INCHESMILLIMETERS A 9.40 10.16 0.370 0.400 B 6.10 6.60 0.240 0.260 C 3.94 4.45 0.155 0.175 D 0.38 0.51 0.015 0.020 F 1.02 1.78 0.040 0.070 G 2.54 BSC 0.100 BSC H 0.76 1.27 0.030 0.050 J 0.20 0.30 0.008 0.012 K 2.92 3.43 0.115 0.135 L 7.62 BSC 0.300 BSC N 0.76 1.01 0.030 0.040 /C0095/C0095
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