AD7543 AD | Alldatasheet
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FEATURES FUNCTIONAL BLOCK DIAGRAM Resolution: 12 Bits Nonlinearity: +1/2LSB Tmin to Tmax Low Gain T.C.: 2ppm/°C typ, S5ppm/°C max (16) Ree Serial Load on Positive or Negative Strobe (1) our Asynchronous CLEAR Input for Initialization Vaer (15) | eroacomerren | 6 Full 4-Quadrant Multiplication am oure Low Multiplying Feedthrough: 1LSB max @ 10kHz ir oe OL Requires no Schottky Diode Output Protection aa (3) Low Power Dissipation: 40mW max +5V Supply 115) Small Size: 16-Pin DIP or 20-Terminal Surface Mount oan, “a Package ste (1) =@-J > Gre ste2 (8) (2) ono GENERAL DESCRIPTION The AD7543 is a precision 12-bit monolithic CMOS multi- | plying DAC designed for serial interface applications. Initialization is simplified by the use of the CLR input which Selo tes . a provides an asynchronous reset of Register B. The DAC’s logic circuitry consists of a 12-bit serial-in parallel- : out shift register (Register A) and a 12-bit DAC input register Packaged in 16-pin DIP and 20-pin LCCC and PLCC, the (Register B). Serial data at the AD7543 SRI pin is clocked into AD7543 features excellent gain T.C. (2ppm/°C typ; | Register A on the leading or trailing edge (user selected) of the Sppm/°C max), +5V operation and latch-free operation. strobe input. Once Register A is full its contents are loaded in- (No protection Schottky Diodes required.) | to Register B under control of the LOAD inputs. PIN CONFIGURATIONS DIP Lecce PLCC on Gl e [36] Fen 321 2019 BlalaipiD our 2] [15] Vnee A acno [a] Ge] vow AcNo 4 i Yoo acno [a] [ia] Veo ser Ge] apsas [2] aR srs Ap7543 von sve [5] [v2] err ii Fe rormiew FR ocno Nc 6 Tor view 16 Ne ne [a] AO7543 Fa] vc {Not to Seale) i? Not to Seale) 16 poND 7 ror EW ne [6] [mr] stes or [1s] cane Ne 8 te sre sai D} [10] STB3 ne [oe] [ia] stes oe swe [2] Sones gage E PIMIMIIL] NG = NOCONNECT c-woconmeer™ E SE 228 Nc = NoconNect REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices parties which may result from its use>No license is granted by implica- Tel: 617/329-4700 Fax: 617/326-8703 Twx: 710/394-6577 tion or otherwise under any patent or patent rights of Analog Devices. Telex: 924491 Cable: ANALOG NORWOODMASS,
AD7543 — SPECIFICATIONS (Von = +5V, Veer = +10V, Yours = Vourr = OV, unless otherwise noted.) Limit Ac’ Limit At’ Limit At Tras 40°C Ta = 535°C Parameter Tan #28°C 10 +85°C &+125°C Units Conditions/Comments RECURAGY Resolution n 2 2 Bits Relative Accuracy? JA, Versions Fn 41 41 LSB max K, B, T Versions 12 12 +12 LSB max GK, GB, GT Versions tz t1/2 t2 LSB max Differential Nonlinearity? J. A,S Versions 2 2 2 LSB max Monotonic to 11 bits from Tmin t© Tmax K, B, T Versions tl 41 41 LSB max Monotonic to 12 bits from Tmin t0 Tmax GK, GB, GT Versions H “ “4 LSB max ‘Monotonic to 12 bits from Trin t© Tmax Gain Error? J.K.A,B,S,T 412.3 2135 +145 LSB max ‘Using internal RFB only (gain error can be GK, G8, GT FS “1 2 LSB max trimmed to zero using citcuits of Figures 6 & 7) Gain Temperature Coefficient OGain/ATemperature 5 5 s ppm/°C max Typical value is 2ppm/°C Power Supply Rejection ‘AGain/AVpp 0.005 oor oor % per % max Vpp = +4.75V to +5.25V Output Leakage Current lout: (Pin 4) 1 10 200 nA max DAC Register loaded with all Os lourz (Pin 5) 1 10 200 nA max DAC Register loaded with all 15, DYNAMIC PERFORMANCE Current Seteling Time? 20 20 20 us max To 1/2LSB. OUT! load = 100, DAC output measured from falling edge of [D1 and LD2, see Figure 5. Multiplying Feedthrough Error” 2.5 25 28 mV p-pmax Vper = 210V, 10kHe sine wave “REFERENCE INPUT Input Resistance (pin 15) 8/15/25 8/15/25 8/15/25 kQmin/typ/max Typical cemperature coefficient 1s -J0Oppm/*C “aWALoGouTPUTS SOS Ovrput Capacitance Court 7 1 75 pF max Register B loaded to 0000 0000 0000 Couts? 260 260 260 pF max Register B loaded to 111 1111 1111 Cour? 15 75 1 pF max Register B loaded to 1111 1111 111 Cour?” 260 260 260 pf max Register B loaded to 0000 0000 0000 LOGIC INPUTS Vint (Logic HIGH Voltage) 3.0 +3.0 +30 V min Vet (Logic LOW Voltage) +08 +08 +08 V max tn* 1 1 1 WA max Vin = OV ot Vp Cpy (Input Capacitance)? 8 8 8 pF max Input Coding 12-Bit Unipolar Binary or 12-Bit Offset Binary (sce Figures 6 and 7), serial load (MSB First) ‘SWITCHING CHARACTERISTICS® ‘psi 50 100 100 ns min Serial Input STBI used as a strobe ost ° ° ° ns min fal inpet \\ STB4 used as a strobe ss o ° ° ns min setup Tow STB3 used as a strobe tps2 20 40 40 ns min STB2 used as a strobe ton 30 60 60 1s min STBI used as a strobe toi 80 160 160 as min Seral inpt) st¢ used asa strobe tore 80 160 160 1s min oe STB3 used as a strobe tH? 60 120 120 fs min wme STB2 used as a strobe tsRi 80 160 160 fs min SRI data pulse width tsrey 80 160 160 ns min STBI pulse width tst86 100 200 200 rns min STB4 pulse widch sta 100 200 200 as min STB3 pulse width ts182 80 160 160 ns min STB2 pulse width TLpr. (D2 150 300 300 ‘ns min Load pulse width 'ASB 0 ° o ns min ‘Min time between strobing LSB into Register A and loading Register B tar 200 400 400 1s min CLR pulse width POWER SUPPLY Vpp (Supply Voltage) +s 45 45 v Ipp (Supply Current) 2s 25 25 mA max Digital Inputs = Vinny oF Vine NOTES "Temperature ranges as follows: JN, KN, GKN Version; ~40°C 10 +85°C AQ, BQ, GBQ Versions: ~ 40°C to +85°C SQ. TQ, GTQ Versions: ~55°C to +125°C ‘Se Terminology on following page ‘Guaranteed but not tested. ‘Logic inputs are MOS gates. Typical input current (+25°C) is ess than In. “Sample tested at +25°C to ensure compliance. Specifications subject to change without notice -2- REV. B
AD7543 | ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE (T, = +25°C unless otherwise noted) Temperature Relative Gain Package yaa oe crrrrsssrrrss sess ov. oy AD7543JN —40°Cto +85°C + ILSB—-+12.3LSB_N-16 DENDAGND LLL ye TOSY aD7543KN —40°Cto 85°C F12LSB + 12.3LSBN-16 Digital Lape Vehage to DGND 21 Laay, WP TOBY AD7543GKN -40°C10+85°C ¥12LSB +ILSB_ N-I6 Vn Vee to AGND 7 93v, Von toay ADIS43JP —40°Ct0 +85°C = ILSB+12.3LSB_ P-20A Venn "AGND pets s SEAN: pp te e25y AD7543KP_ —40°Ct0 +85°C + 1/2LSB_+12.3LSB_ P-20A Yee OAGND LLL LIL LT TT, ERY ADzS3GKP —40°Ct0 +85°C = 12LSBFILSB 208 PamteDissipaton Package AD7543JR 40°C + 85°C Z1LSB-£12.3LSB_ R-16 eee AD7543KR -40°C10 +85°C |= 1/2LSB +12.3LSB_ R-16 ast oc cpomw AD7S#3GKR -40°C10+85°C +1/2LSB +1LSB R16 vee tee ee AD7543AQ_ —40°C10 +85°C +ILSB-+12.3LSB_ Q-16 Cerdip AD7543GBQ -40°Ct0 +85°C | +1/2LSB +1ILSB Q-16 To +75°C ows ee es 450MWa7s43gQ” —55°Ct0 +125°C +ILSB +123LSB Q-16 Operating Temperature Range oc AD7S43GTQ -55°Cto+125°C £1/2LSB =ILSB Q-16 Extended (S, T, GT Versions)... . ~59°C to +125°C anysa3GTE —S5°Cto+125°C +1/2LSB +1ILSB E-20A ‘*Stresses above those listed under “Absolute Maximum Ratings” may cause Chip Carrier (PLCC); Q = Cerdip; R = Small Outline IC (SOIC). permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION, ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protect- WARNING! _ ed; however, permanent damage may occur on unconnected devices subject to high energy <<, electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective i foam should be discharged to the destination socket before devices are removed. Let agin PIN_| MNEMONIC FUNCTION 1 ouT1 DAC current output bus. Normally terminated at op amp virtual ground 2 ouT2 DAC current output bus. Normally terminated at AGND
3 AGND ‘Analog Ground
4 STB1 Register A Strobe 1 input, see Table II
5 CDi DAC Register B Load 1 input. When LDi and LD2 go low the contents of Register A are loaded into DAC Register B
6 Nic No Connection
7 SRI Serial Data Input to Register A
8 sTB2 Register A Strobe 2 input, see Table II 9 LDz DAC Register B Load 2 input. When LD1 and LD2 go low the contents of Register A are loaded into DAC Register B
10 SBS Register A Strobe 3 input, see Table IT
u STB4 Register A Strobe 4 input, see Table II
12 DGND Digital Ground
13 CLR Register B CLEAR input (active LOW), can be used to asynchronously
reset Register B to 0000 0000 0000
14 Vp +5V Supply Input
15 VREF Reference input. Can be positive or negative dc voltage or ac signal
16 Rep DAC Feedback Resistor
Table |. Pin Function Description, DIP Configuration REV. B -3-
Relative accuracy or endpoint nonlinearity is a measure of the define scale factor. ppm of full-scale range or (sub) multiples of 1LSB. MULTIPLYING FEEDTHROUGH ERROR rent drain through the termination resistor on the R-2R ladder. a highly stable thin film R-2R ladder and twelve N-channel on terminal , 6 Z00pr are . Figure 1. AD7543 Functional Diagram ' Qe + Toor °
- CLR =0 Asynchronously resets Register B to 0000 0000 0000, but has no effeet gn Register A.
2, Serial data i toaded into Register A MSB first, on edges shown_A is positive edge Vis negative edge.
- O= Logic LOW, 1 = Logic HIGH, X = Don't Care
Figure 5. Timing Diagram Register B can be asynchronously reset to 0000 0000 0000 2-quadrant multiplication (digitally controlled attenuation). ar : : The input/output relationship is shown in Table III. circuit of Figure 7,a CLEAR causes the DAC output to equal magnitude. and output capacitance at OUT1).
- HIGH FREQUENCY CONSIDERATIONS: AD7543 out- AD7543 INTERFACE TO MC6800 put capacitance works in conjunction with the amplifier In this example, it is assumed that the 12-bit data is con- feedback resistance to add a pole to the open loop response. _tained in two memory locations (0000 and 0001). The four This not only reduces closed loop bandwidth, but can also _—most significant bits are assumed to occupy the lower half of cause ringing or oscillation if the spurious pole frequency is memory location 0000. The eight least significant bits occupy less than the amplifier’s OdB crossover frequency. Stability memory location 0001. The data is presented bit by bit on the can be restored by adding a phase compensation capacitor __D7 line and strobed into the AD7543 by executing memory in parallel with the feedback resistor. write instructions. In this case the strobe signal (STB1) is sup- 4. GAIN TEMPERATURE COEFFICIENTS: The gain temper-_Plied by decoding address 2000, R/W and $2. A memory write ature coefficient of the AD7543 has a maximum value of instruction to a different address (4000) loads the data from Sppm/°C and a typical value of 2ppm/°C, This corresponds Register A to the DAC register. to gain shifts of 2.0LSBs and 0.82LSBs respectively over 4 Figure 8 shows the interface circuitry and Table V gives a 100°C temperature range. When trim resistors are used to listing of the procedure. adjust full-scale range as shown in Figures 6 and 7 the temperature coefficient of R1 and R2 should be taken into account. It may be shown that the additional gain temperature coefficients introduced by R1 and R2 may ADDRESS BUS (16) AODRESS (16) be approximately expressed as follows: — Temperature Coefficient Ry ud d contribution due to RI ~~ Ry (71 * 300) eo [ee prcooer =+@ (72 + 300) comtibution due to RZ" * Rey 7? “ — a) oa o Where 7; and 72 are the temperature coefficients in ppm/°C === of R1 and R2 respectively and Ryy is the DAC input resist- seve Se ance at the Vegp terminal (pin 2). For high quality wire- [imi A754 wound resistors and trimming potentiometers 7 is of the order oe ane ee of 50ppm/°C. It will be seen that if R1 and R2 are small com- % pared with Ruy, their contribution to gain temperature coef- FROM SYSTEM RESET ficient will also be small. For the standard AD7543 gain error specification of +12.3LSBs it is recommended that R1 = 1202 Figure 8. AD7543—MC6800 Interface and R2 = 602. With y = 50 these values result in an overall maximum gain error temperature coefficient of: 5 +206 (50 + 300) = 8ppm/C LABEL MNEMONIC OPERAND COMMENT LDA B, 04 . . - LDA A,0000 Load 4 Most Significant Bi However, if the AD7543GTD is usad which has a specified LOOP ROL a Reposition inthe Dats gain error of t1LSB, then with R1 = 10Q and R2 = 5Q the DEC B in ACC A overall maximum gain temperature coefficient is increased by BNE Loop ° 3 , only 0.25ppm/°C, Where possible R1 should be a select on ten aot ourpue Daa test fixed resistor since the resulting gain temperature coeffi- LDA B, 08 efficient will be tighter in all cases. For further gain T.C. LDA A, 0001 Load 8 Least Significant Bits information refer to application note, “Gain Error and BSR SHIFT Output Data Gain Temperature Coefficients of CMOS Multiplying DACs”, STA 4.4000 Load DAG Register Publication Number E630—10—6/81 available from Analog RTs Return to Main Program ' SHIFT STA A,2000 Strobe Data Devices. ROL A into AD7543 . DEC 5. For additional information on multiplying DACS refer BNE Suier to “Application Guide to CMOS Multiplying D/A Con- RTS verters”, Publication Number G479—15—8/78, available —-—————_ from Analog Devices. Table V. Sample Routine for AD7543—MC6800 Interface AD7543 INTERFACE TO MCS-85 : Figure 9 shows the AD7543 interfaced to the 8085. This sys- tem makes use of the serial output facility (SOD) on the 8085. The data is presented serially on the SOD line and strobed into the AD7543 by executing memory write instructions. In this example the strobe signal (STB2) is supplied by decod- ing address 8000 and WR. A memory write instruction to a different address (A000) loads the DAC Register with Register REV. B -1-
A data. Table VI gives a listing of this procedure. Note, it is OUTLINE DIMENSIONS assumed that the required serial data is already present in Dimensions shown in inches and (mm). right-justified format in Registers H and L when this proce- . . dure is implemented. Note that the sample routine of Table VI 16-Pin Plastic DIP (N-16) Package can be speeded up by replacing the SHIFT routine with a DAD H instruction. —; ozereen cate @ AoOREES UST poness 11 Ht s 2708 pam see a7 8 t ara p89 accel t 8 mm q oe 1448) [T— ) DATA) ak 4b ove to308 200s 68) oz son owei2en 0008 (0203) a = doesn Oma Sora s0D SRI i02 stez LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH +5V0 sTe3 LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42 stB1 = AD7543 mH . - rit 16-Pin Ceramic DIP (D-16) Package V FROM SYSTEM RESET: + . e3 nen Figure 9, AD7643—8085 Interface pana. LABEL MNEMONIC OPERAND COMMENT oo 2088) or 3.08 MVI B, OS Shift Data Up to O77 19.66) ‘Doe nea LOOP CALL SHIFT Most Significant t —t DCR B Segment of HL with onaaai JNZ LOOP MSB as Carry Leal t MVI B,OC 1) 278 16.48) 2.012 (0.308) LUP MVI A, 80 SOD Enable in ACC O16 (3.10) ‘308 0.203) RAR Shift in MSB of H ol. | be U — SIM Set Interrupt Mask 008.083) 0.02 08) ows len (0.308 078) STA 8000 Strobe Data into AD7543 cassie) Om (o2ey O.088 (248) ease ran CALL SHIFT Get Next Bit into Carry 1, LEAD NO. 1 IDENTIFIED BY OOT OR NOTCH DCR B 2 LEADS wilv'BE EITHER GOLD OR FINLATED Iw ACCORDANCE WITH ILM 38610 REQUIREMENTS. JNZ LUP Go Back if Not Finished STA A000 Load DAC Register of AD7543 Cs 5 ‘ , a RET Return to Main Program 20-Pin Leadless Ceramic Chip Carrier (E-20A) Package SHIFT MOV AL Shift H and L Left ese = acta RAL One Place and . 0388 = 9008 5a of 00 MOV LA Leave Uppermost Bit 4 i: (aes + 0.20) wera pics MOV AH of Hin Carry COUN oo cons RAL t2 CHF 10895 = 0.075) MOV HLA J cf RET — a es L& = Table VI. Sample Routine for AD7543—8085 Interface re dogo oo oose . BONDING DIAGRAM ~ er orroM view coe 0.096 (2438) . ourz_ourt are 20-Pin Plastic Leaded Chip Carrier (P-20A) Package a ACN ar 1 ONL ee SSeS, z S mh A288 0 omg sars 3 sy ; eo ee fees eh u i, [| Bose 23008 9° | of fe 8228 sa z _ = i, an 4} ponoon Sy = wi 1\\/Pl ese = GND oss coco O No.1 IN 0 — laa (es t 0.134 (5 =08r6 JOENTIFIER E+ ozs -0003 . he q 0 Cosa fons Soares EWS IR i aoe d h | cob ete! dy oon q p ee a naan max i be —, d —) [2s ==rry beth oer ae _— ae Sh ae shi sez D8 STB3 (B22, max ame Lal TOMINIMIZE 260 HAZARD BOND BGNO FinsT -8- REV. B