UPD434016A NEC | Alldatasheet
Document overview
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Technical content
Features
© 262,144 words by 16 bits organization * Fast access time : 12, 15, 17, 20 ns (MAX.) © Byte data control : /LB (VO1 - /O8), /UB (/O9 - 1016) * Output Enable input for easy application * Single +5.0 V power supply
Ordering Information
[em [sso] ee [om [stoma | The information in this document is subject to change without notice. Document No. M12228EJ3VODS00 (3rd edition) The mark * shows major revised points. Date Published November 1997 NS Printed in Japan © NEC Corporation 1996
Pin Configurations (Marking Side) /xxx indicates active low signal. 44-pin plastic SOJ (400 mil) [ uPD434016ALE ] pC A0O 10 44 CO) A17 ATO 2 43 O AB A20 3 42 OAS AO 4 4 © /OE AAO 5 40 ©) /UB ICS © 6 39 O /LB vo1 © 7 38 O vote vo2 © 8 37 O vo1s vO3 © 9 36 O vo14 vo4 © 10 35 © VO13 Veo © "1 34 © GND GND © 12 33 O Voc Vvo5 © 13 32 O vo12 vos © 14 31 O vot vo7 © 15 30 © 010 vos © 16 29 © voe ME © 17 28 © NC ASO 18 27 O A14 ABO 19 26 O A13 a7 O 20 25 O A12 ABO at 24 O AI as O 22 23 O A10 AOQ-A17 _ : Address Inputs VO1 - 1/016: Data Inputs / Outputs ics : Chip Select WE : Write Enable /OE : Output Enable /LB,/UB _ : Byte data select Veo : Power supply GND : Ground NC : No connection
2 Preliminary Data Sheet
44-pin plastic TSOP (II) (400 mil) (Normal Bent) [ uPD434016AG5-7JF ] Ny AOC 10 44 O A17 ALO 2 43 OAs A2 0 3 42 O AIS A3 © 4 ra) © /OE ASO 5 40 © /UB ICS © 6 39 O /LB vo1 © 7 38 C) VO16 voz © 8 37 © vo1s vO3 © 9 36 O vo14
04 O 10 35 © vo13
Vee © cn 34 © GND GND © 12 33 ©) Voc vos © 13 32 © 012 voB © 14 31 OQ voit vo7 © 15 30 © 010 vos © 16 29 © 09 ME © 17 28 © NC AsO 18 27 OA14 As O 19 26 O A13 A7 © 20 25 O a2 As O 21 24 Oat Ag © 22 23 © A10 AOQ-A17 _ : Address Inputs 01 - /016: Data Inputs / Outputs /CS : Chip Select WE : Write Enable /OE : Output Enable /LB,/UB __: Byte data select Veo : Power supply GND : Ground NC : No connection Preliminary Data Sheet 3
3 . g 5 = 3 “ 2 8 Memory cell array 3 3 M7 3 g 4,194,304 bits | 3 a | 2 [4 01 - 08 O [| pate . I) Output data | | ee controller Sense/Switch /\\ controller "o9- 016 © > ICS 0 Hf) LB O-+-H+d JOE O—9 +04 < lb q d Voc O——— GND O——. Truth Table mes |e |] we] ae | we | woce Sippy curen Sapetaaatie | High mpednce | High mpedance Remark x : Don't care
4 Preliminary Data Sheet
Note -2.0 V (MIN.) (pulse width : 2 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions fowwetpavenge [we fia oe PY Note -2.0 V (MIN.) (pulse width : 2 ns) Preliminary Data Sheet 5
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Output leakage current ho Vivo = 0 V to Voo, /CS = Vix or /OE = Vin -2 +2 HA or /WE = Vi. or /LB = Vik or /UB = Vix Operating sup ouvert we [rose ve cycetme: ral | | a0] ma Mnmum eyeetme [Cyaoime:i7nal | | ara | Veo - 0.2 V </CS, Viv $0.2 V or Veo -0.2 V< Vin Remark Vi : Input voltage Capacitance (Ta=25 °C, f = 1 MHz) [reactance | ov [wav SiS Si | Remarks 1. Vin : Input voltage 2. These parameters are periodically sampled and not 100% tested.
6 Preliminary Data Sheet
[rf [an Jr ne farnacmine |» | [et fs] [ef [==]. jesacesine wm | pe | pf ep la | jocscentne st = | felt fr] [ef [ele jis wesc «| w | fel [rp [ef [of | loanivcttemasioncawe |» |a{ [a] fa] [| [| jesivausininmeine | «= [a{ |a{ a] ]*| [= ]e joctotntiniwinwane | = |e{ |e{ fo] }o| [| fis useovanoninwans [m= |e{ |e{ fe] ]o| [m= | festomunnininwane | ve | |e] [7] le] [e[ | foctotpanabinngnimesirce [we |e] [7] [@] |e] =| rs neiocuparoanrnineace| w= | [et tr] let [el «| Notes 1. See the output load shown in Figure 1. 2. Transition is measured at + 200 mV from steady-state voltage with the output load shown in Figure 2. 3. These parameters are periodically sampled and not 100% tested. Read Cycle Timing Chart 1 (Address Access) tre )_$ tas VO (Output) Previous data out (XX) Data out Remarks 1. In read cycle, /WE should be fixed to high level. 2. /CS =/OE = /LB (or /UB) = Vic
8 Preliminary Data Sheet
Read Cycle Timing Chart 2 (/CS Access) tac tan tacs /CS (Input) ToA\\\\\\\\ ee (TIT 71 FF JOE (| ocirou) AY ELLLLLL —=T 1 a touz : |_| /LB, /UB (I tea ELLLLLL ——an or fez = Caution Address valid prior to or coincident with /CS low level input. Remark In read cycle, /WE should be fixed to high level. Preliminary Data Sheet 9
Jwrtecycretime Te Pe Ts] Tw] fet fot | jicsioondorwio tem Pe T fof fut fet [oe [| jaccress vaistoendotwite | wm fe | fof fat fet [io [| jwitopusewan Tw Pet fof fut fet [oo] | [us iustoendotwie | tw fo | fot fut fet fst | fosavaisiowsstwe |» fs{ [7[ le] ls] [= |_| [oataroistime tm PoP fof fof fof fist | fasseessnupine |» fe| fe] [o| [oe] [=| | + [wiercowvine [| [+] [+] [+] [+] [=] | Fmevwouunnonmpnans | me | |e] [7] [el] [|| Fousnaciveromensstwie | taf fal le] le] [| Notes 1. Transition is measured at + 200 mV from steady-state voltage with the output load shown in Figure 2. 2. These parameters are periodically sampled and not 100% tested. Write Cycle Timing Chart 1 (/WE Controlled) two Address (Input) (SY JCS (Input) wo WITT on ae ep we TY ME (Input) /LB, /UB (Input) mo WO TTT tow twuz tow ton — High V \\ High ' W/O (Input / Output) Indefinite data out impe- iimpe- Indefinite data out dance dance Caution /CS or /WE should be fixed to high level during address transition. Remarks 1. Write operation is done during the overlap time of a low level /CS, a low level /WE and a low level /LB (or low level /UB) 2. During twuz, I/O pins are in the output state, therefore the input signals of opposite phase to the output must not be applied. 3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed, Therefore /OE should be at high level to make the I/O pins high impedance.
10 Preliminary Data Sheet
Write Cycle Timing Chart 2 (/CS Controlled) twc com TN a twe ME (Input) tow tow ton High impedance High impedance Caution /CS or /WE should be fixed to high level during address transition. Remark Write operation is done during the overlap time of a low level /CS, a low level /WE and a low level /LB (or low level /UB). Write Cycle Timing Chart 3 (/LB, /UB Controlled) two vestry NS LLLLLLLL ME (\\nput) tov So ee /LB, UB (Input) WX tow ton High impedance . High impedance Caution /CS or /WE should be fixed to high level during address transition. Remark Write operation is done during the overlap time of a low level /CS, a low level /WE and a low level /LB (or low level /UB). Preliminary Data Sheet 1
44 PIN PLASTIC SOu (400 mil)
B A ooooooooolnnonnnnonoont {—-— | SOOO T 22 F E a et) 5 ee ee eet I ae] P Moly @] [ely @| P44LE-400A NOTE ITEM) MILLIMETERS INCHES Each lead centerline Is located within 0.12 soe soos maximum material condition. c 10.16 0.400 D 11.18+0.20 0.440£0.008 E F 0.74 0.029 G 3.540.2 0.138£0.008 H 2.340.2 0.09173988 | 0.8 MIN. 0.031 MIN. N 0.12 0.005 P 9.440.20 0.370+0.008 oot T R 0.85 R 0.033 u
12 Preliminary Data Sheet
44 PIN PLASTIC TSOP(II) (400 mil)
l) uw D + w o 1 22 A H J ee ORR ctetsistatstststetstststatstatstatststststete, <h — i | iN | B L D NOTE ITEM MILLIMETERS INCHES E 0,120.05 0.00420.002 F 1.2 MAX. 0.048 MAX. G__097 0.038 H 11.7620.2 _0.46840.008 Il 10.1620.1 _0.40020.004 J 0.840.2 0.03148-609 L 0.520.1 0.02088 -804 M013 0.005 N_ 0.10 0.004 237° 47; Pp ain ott ‘S44G5-80-70F5, Preliminary Data Sheet 13
Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the .PD434016A. Type of Surface Mount Device HPD434016ALE : 44-pin plastic SOJ (400 mil) uPD434016AG5-7JF : 44-pin plastic TSOP (II) (400 mil) (Normal Bent)