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M24256-BW_12 STMICROELECTRONICS | Alldatasheet

Document overview

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• PDF pages: 41

Technical content

Datasheet sections

• 1 Description
• 2 Signal description
• 2.1 Serial Clock (SCL)
• 2.2 Serial Data (SDA)
• 2.3 Chip Enable (E2, E1, E0)
• 2.4 Write Control (WC
• 2.5 V SS (ground)
• 2.6 Supply voltage (V CC)
• 2.6.1 Operating supply voltage V CC
• 2.6.2 Power-up conditions
• 2.6.3 Device reset
• 2.6.4 Power-down conditions
• 3 Memory organization
• 4 Device operation
• 4.1 Start condition
• 4.2 Stop condition
• 4.3 Data input
• 4.4 Acknowledge bit (ACK)
• 4.5 Device addressing
• 5 Instructions
• 5.1 Write operations
• 5.1.1 Byte Write
• 5.1.2 Page Write
• 5.1.3 Write Identification Page (M24256-D only)
• 5.1.4 Lock Identification Page (M24256-D only)
• 5.1.5 ECC (Error Correction Code) and Write cycling
• 5.1.6 Minimizing Write delays by polling on ACK
• 5.2 Read operations
• 5.2.1 Random Address Read

Features

■ Compatible with all I2C bus modes: –1 M H z – 400 kHz – 100 kHz ■ Memory array: – 256 Kbit (32 Kbytes) of EEPROM – Page size: 64 bytes – Additional Write lockable page (M24256-D order codes) ■ Single supply voltage and high speed: – 1 MHz clock from 1.7 V to 5.5 V ■ Write: – Byte Write within 5 ms – Page Write within 5 ms ■ Operating temperature range: from -40 °C up to +85 °C ■ Random and sequential Read modes ■ Write protect of the whole memory array ■ Enhanced ESD/Latch-Up protection ■ More than 4 million Write cycles ■ More than 200-year data retention ■ Packages: – RoHS compliant and halogen-free (ECOPACK®) SO8 (MN) 150 mil width TSSOP8 (DW) 169 mil width UFDFPN8 (MC) WLCSP (CS)

M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Contents Doc ID 6757 Rev 28 3/41

Table 20. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead Table 21. M24256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package mechanical data. 37

1 Description

Memory) organized as 32 K × 8 bits. (later) permanently locked in Read-only mode. Figure 1. Logic diagram Table 1. Signal names

2 Signal description

2.1 Serial Clock (SCL)

output the data on SDA(out).

2.2 Serial Data (SDA)

indicates how to calculate the value of the pull-up resistor).

2.3 Chip Enable (E2, E1, E0)

Figure 4. Device select code

2.4 Write Control (WC )

driven low or left floating. acknowledged, Data bytes are not acknowledged.

2.5 V SS (ground)

VSS is the reference for the VCC supply voltage.

M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Signal description Doc ID 6757 Rev 28 9/41

2.6 Supply voltage (V CC)

2.6.1 Operating supply voltage V CC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 8: DC and AC parameters). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (t W).

2.6.2 Power-up conditions

The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage (see Operating conditions in Section 8: DC and AC parameters) and the rise time must not vary faster than 1 V/µs.

2.6.3 Device reset

In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until V CC has reached the internal reset threshold voltage. This threshold is lower than the minimum VCC operating voltage (see Operating conditions in Section 8: DC and AC parameters). When VCC passes over the POR threshold, the device is reset and enters the Standby Power mode; however, the device must not be accessed until V CC reaches a valid and stable DC voltage within the specified [VCC(min), VCC(max)] range (see Operating conditions in Section 8: DC and AC parameters). In a similar way, during power-down (continuous decrease in VCC), the device must not be accessed when VCC drops below VCC(min). When VCC drops below the power-on-reset threshold voltage, the device stops responding to any instruction sent to it.

2.6.4 Power-down conditions

During power-down (continuous decrease in VCC), the device must be in the Standby Power mode (mode reached after decoding a Stop condition, assuming that there is no internal write cycle in progress).

3 Memory organization

The memory is organized as shown below. Figure 5. Block diagram

4 Device operation

Figure 6. I

Device operation M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF 12/41 Doc ID 6757 Rev 28

4.1 Start condition

Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer instruction. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition.

4.2 Stop condition

Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master. A Read instruction that is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode. A Stop condition at the end of a Write instruction triggers the internal Write cycle.

4.3 Data input

During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven low.

4.4 Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9 th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits.

4.5 Device addressing

in Table 2(on Serial Data (SDA), most significant bit first). Address is the same as the value on the Chip Enable (E2, E1, E0) inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. the device select code, it deselects itself from the bus, and goes into Standby mode. Table 2. Device select code

1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared with the value read on input pins E0,E1,and E2.
3. For the 5-bump WLCSP package, (E0,E1,E2) i nputs are internally connected to (0,0,1)

1010 E 2 E 1 E 0 R W

1011 E 2 E 1 E 0 R W

5 Instructions

5.1 Write operations

not respond to any requests. accompanying data bytes are not acknowledged, as shown in Figure 8. Table 3. Most significant address byte Table 4. Least significant address byte

5.1.1 Byte Write

transfer by generating a Stop condition, as shown in Figure 7. Figure 7. Write mode sequences with WC

5.1.2 Page Write

The transfer is terminated by the bus master generating a Stop condition. Figure 8. Write mode sequences with WC

M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Instructions Doc ID 6757 Rev 28 17/41

5.1.3 Write Identificat ion Page (M24256-D only)

The Identification Page (64 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. It is written by issuing the Write Identification Page instruction. This instruction uses the same protocol and format as Page Write (into memory array), except for the following differences:

• Device type identifier = 1011b
• MSB address bits A15/A6 are don't care except for address bit A10 which must be ‘0’. LSB address bits A5/A0 define the byte address inside the Identification page. If the Identification page is locked, the data bytes transferred during the Write Identification Page instruction are not acknowledged (NoAck).

5.1.4 Lock Identificati on Page (M24256-D only)

The Lock Identification Page instruction (Lock ID) permanently locks the Identification page in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with the following specific conditions:

• Device type identifier = 1011b
• Address bit A10 must be ‘1’; all other address bits are don't care
• The data byte must be equal to the binary value xxxx xx1x, where x is don't care

Instructions M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF 18/41 Doc ID 6757 Rev 28

5.1.5 ECC (Error Correcti on Code) and Write cycling

The Error Correction Code (ECC) is an internal logic function which is transparent for the I2C communication protocol. The ECC logic is implemented on each group of four EEPROM bytes(a). Inside a group, if a single bit out of the four bytes happens to be erroneous during a Read operation, the ECC detects this bit and replaces it with the correct value. The read reliability is therefore much improved. Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently. In this case, the ECC function also writes/cycles the three other bytes located in the same group (a). As a consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the 4 bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined Table 11: Cycling performance by groups of four bytes. a. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.

5.1.6 Minimizing Write del ays by polling on ACK

• Initial condition: a Write cycle is in progress.
• Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction).
• Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1).

Figure 9. Write cycle polling flowchart using ACK

1. The seven most significant bits of the Device Se lect code of a Random Read (bottom right box in the

5.2 Read operations

Read operations are performed independently of the state of the Write Control (WC) signal. incremented by one, to point to the next byte address. Figure 10. Read mode sequences

M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Instructions Doc ID 6757 Rev 28 21/41

5.2.1 Random Address Read

A dummy Write is first performed to load the address into this address counter (as shown in Figure 10) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition.

5.2.2 Current Address Read

For the Current Address Read operation, following a Start condition, the bus master only sends a device select code with the R/W bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 10, without acknowledging the byte. Note that the address counter value is defined by instructions accessing either the memory or the Identification page. When accessing the Identification page, the address counter value is loaded with the byte location in the Identification page, therefore the next Current Address Read in the memory uses this new address counter value. When accessing the memory, it is safer to always use the Random Address Read instruction (this instruction loads the address counter with the byte location to read in the memory, see Section 5.2.1) instead of the Current Address Read instruction.

5.2.3 Sequential Read

This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 10. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter “rolls-over”, and the device continues to output data from memory address 00h.

5.3 Read Identification Page (M24256-D only)

The Identification Page (64 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. The Identification Page can be read by issuing an Read Identification Page instruction. This instruction uses the same protocol and format as the Random Address Read (from memory array) with device type identifier defined as 1011b. The MSB address bits A15/A6 are don't care, the LSB address bits A5/A0 define the byte address inside the Identification Page. The number of bytes to read in the ID page must not exceed the page boundary (e.g.: when reading the Identification Page from location 10d, the number of bytes should be less than or equal to 54, as the ID page boundary is 64 bytes).

Initial delivery state M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF 22/41 Doc ID 6757 Rev 28

5.4 Read the lock status (M24256-D only)

The locked/unlocked status of the Identification page can be checked by transmitting a specific truncated command [Identification Page Write instruction + one data byte] to the device. The device returns an acknowledge bit if the Identification page is unlocked, otherwise a NoAck bit if the Identification page is locked. Right after this, it is recommended to transmit to the device a Start condition followed by a Stop condition, so that:

• Start: the truncated command is not executed because the Start condition resets the device internal logic,
• Stop: the device is then set back into Standby mode by the Stop condition.

6 Initial delivery state

The device is delivered with all bits set to 1 (both in the memory array and in the Identification page - that is, each byte contains FFh).

7 Maximum rating

Table 5. Absolute maximum ratings

1. Compliant with JEDEC Std J-STD- 020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
2. Positive and negative pulses applied on different comb inations of pin connections, according to AEC-

Q100-002 (compliant with JEDEC Std JESD22-A114, C1=100 pF, R1=1500 Ω).

1. 3000 V for previous devices (process letters KA).

8 DC and AC parameters

characteristics of the device. Figure 11. AC measurement I/O waveform Table 6. Operating conditions (voltage range W) Table 7. Operating conditions (voltage range R) Table 8. Operating conditions (voltage range F) Table 9. AC measurement conditions

Table 10. Input parameters

1. Characterized only, not tested in production.
2. E2, E1, E0 input impedance when the memory is selected (after a Start condition).

Table 11. Cycling performance by groups of four bytes

1. Cycling performance for products identified by process letter KB.
2. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1,
3. A Write cycle is executed when ei ther a Page Write, a Byte Write, a Write Identification Page or a Lock

Identification Page, refer also to Section 5.1.5: ECC (Error Correction Code) and Write cycling. Table 12. Memory cell data retention

1. For products identified by process letter K. The data retention behavior is checked in production. The 200-

year limit is defined from characterization and qualification results.

Table 13. DC characteristics (M24256-BW, device grade 6)

1. Only for devices operating at f C max = 1 MHz (see Table 17).
2. Characterized value, not tested in production.
3. The device is not selected after power-up, after a R ead instruction (after the Stop condition), or after the

completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).

Table 14. DC characteristics (M24256-BR, M24256-DR, device grade 6)

1. If the application uses the voltage range R device with 2.5 V < V cc < 5.5 V and -40 °C < TA < +85 °C,

please refer to Table 13 instead of this table.

1. Only for devices identified with process letter K.
2. Characterized value, not tested in production.
3. The device is not selected after power-up, after a R ead instruction (after the Stop condition), or after the

completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).

Table 15. DC characteristics (M24256-BF, M24256-DF, device grade 6)

1. If the application uses the voltage range F device with 2.5 V < V CC < 5.5 V and -40 °C < TA < +85 °C,

please refer to Table 13 instead of this table.

1. Only for devices identified with process letter K.
2. Characterized value, not tested in production.
3. The device is not selected after power-up, after a R ead instruction (after the Stop condition), or after the

completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).

Table 16. 400 kHz AC characteristics

1. Characterized only, not tested in production.
2. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
4. t CLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or

0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 12.

1. WC =0 set up time condition to enable the execution of a WRITE command.
2. WC =0 hold time condition to enable the execution of a WRITE command.

Table 17. 1 MHz AC characteristics

1. Only for M24256 devices identif ied by the process letter K.
2. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the

I²C specification that the input signal rise and fall times be less than 120 ns when fC <1M H z .

1. Characterized only, not tested in production.
2. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
3. t CLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or

0.7 VCC, assuming that the Rbus × Cbus time constant is within the values specified in Figure 13.

1. 500 ns for the previous products.
2. WC =0 set up time condition to enable the execution of a WRITE command.
3. WC =0 hold time condition to enable the execution of a WRITE command.
4. 50100 ns for previous products.

Figure 14. AC waveforms

9 Package mechanical data

specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 15. TSSOP8 – 8-lead thin shrink small outline, package outline Table 18. TSSOP8 – 8-lead thin shrink small outline, package mechanical data

1. Values in inches are converted fr om mm and rounded to four decimal digits.

Figure 16. SO8N – 8 lead plastic small outli ne, 150 mils body width, package outline Table 19. SO8N – 8 lead plastic small outline, 150 mils body width, package data

1. Values in inches are converted fr om mm and rounded to four decimal digits.

Figure 17. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package

1. The central pad (area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be

connected to any other voltage or signal line on the PCB, for example during the soldering process.

1. Values in inches are converted fr om mm and rounded to four decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from

Figure 18. M24256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline

Table 21. M24256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package

1. Values in inches are converted fr om mm and rounded to four decimal digits.

10 Part numbering

Table 22. Ordering information scheme

1. RoHS-compliant and halogen-free (ECOPACK2 ®)
2. The process letters apply to WLCSP devices only. The process letters appear on the device package

(marking) and on the shipment box. Please contact your nearest ST Sales Office for further information.

Table 23. Document revision history 19-Jan-2010 20 Revision number co rrected at bottom of pages. 04-Mar-2010 21 Process description corrected in Table 23: Ordering information scheme. side, with balls on the underside). Added Table 12: Memory cell characteristics. Deleted all references to package SO8 (MW) 208 mils width.

flat package no lead 2 x 3 mm, mechanical data to add MC version. datasheet) for standard products (range 6). DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline. DFCS6TP/K (top view, marking side, with balls on the underside). Updated Section 5.2.2: Current Address Read. Table 23. Document revision history (continued)