4216800L | DigiCamel IC Datasheet

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UPD4216800L NEC | Alldatasheet

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NEC MOS INTEGRATED CIRCUIT uPD42S16800L, 4216800L, 42517800L, 4217800L

3.3 V OPERATION 16 M-BIT DYNAMIC RAM

2 M-WORD BY 8-BiT, FAST PAGE MODE

DESCRIPTION

The uPD42S16800L, 42168001, 42S17800L, 4217800L are 2 097 152 words by 8 bits dynamic CMOS RAMs. These differ in refresh cycle and the uPD42S16800L, 42S17800L can execute CAS before RAS self refresh (see the table below). ‘These are packed in 28-pin plastic TSOP(L1) (400 mil) and 28-pin plastic SOJ (400 mil).

FEATURES

© 2.097 152 words by 8 bits organization * Single +3.3 V+0.3 V power supply © Fast page mode © The uPD42S16800L, uPD42S17800L can execute CAS before RAS self refresh. Power consumption at standby [ menmon | mene | tam [Beret TAS before RAS refresh, AS only refresh, Hidden refresh (CMOS tev input) RAS only refresh, Hin eofesh {CMOS level nou © Fast access and cycle time Power consumption Access time RM cycle time Fast page mode Active (MAX.) (MAX.) (MIN.) cycle time (MIN.) eons t10n8 |wPD42S17@00L-A60, «217e00L-A60 | 360mW | |wrD4zs16800.-A70, ezresoo-a7o | aszmw | [wPb42s17@00L-A70,a217@00L-A70 | szkmw | [uPo«2s17@00.-A80, «217e001-a60 | 2a8mW The information in this document is subject to change without notice. 16 243 M@™ 6427525 O055073 4

NEC UPD42S16800L, 4216800L, 42S17800L, 4217800L

ORDERING INFORMATION

PD42S 168001. G5-A60 HPD42S17800LG5-A60 Tom | oh paste TS0° MPD42S17800LG5-A70 (400 mil) PD42S 16800 G5-A80 £ TAS before RAS self refresh TAS before RAS refresh RAS only refresh Hiden ratesh 28.pin lot $01 (400 mil) #PO42S 16800LLE-A80 POD42S17800LLE-A80 HPD4216800.G5-A60 eons PD4217800L.G5-A60 rons 28-pin plastic TSOP il) HPD4217800LG5-A70 (400 mil) ‘HPD4216800LG5-A80 on | e006 Azo TAS befor RAS rersh u Ss RAS only refresh Hidden refresh Jone 28-pin plastic SOs PD 4217B00LLE-A70 (400 mil) QUALITY GRADE STANDARD Please refer to “Quality grade on NEC Semiconductor Devices” (Document number 1E1-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. 244 M™ 6427525 0055074 354

NEC HPD42S16800L, 4216800L, 42S17800L, 4217800L PIN CONFIGURATIONS (Marking Side) 28-pin Plastic TSOP (II) wy, Veco o—41 28 [| GND VO1 042 27 fo 1/08 102 o-—43 26 f-+0 1/07 VO30-44 EER 25 bo 1/06 104 00-45 PESS 24 bo 1/05 WEo—46 = SG3G 23 bo CAS FASO—97 838R 22-0 OE AIINCM™ O—18 = - PBPB 21 bo AD Aloo—49 Apa 20 bo a8 Aootio «= 7 * ig} oa Alo W 18 © AGB A20 12 17 © AS A30 13, 16 OAS Vee © 14 15 © GND 28-pin Plastic SON Cn Vec o—1 O 28 }—o GND O10 2 27 o VO8 102 0-43 26 [+0 1/07 103 0-14 25 +0 1/06 AQ to All : Address inputs VO40--45 Gee 24 +0 1/05 ° se ines Wo 6 Sees 23 o CAS YO1to /O8 —: Data Inputs/Outputs FAS O47 3820 22-0 OE RAS : Row address strobe AIINCMo—18 — 8BSE 21 +0 AS CAS Column address strobe Al0o—49- FSFS 20-0 AB — . nooo MERE ilo a7 we : Write enable Alo Ww 18 ° AB OE : Output enable A20—412 17 bo AS Veo : Supply voltage AS o—113 16 p—o A4 GND : Ground Veo o—4 14 15 |-~o GND NC : No connection Note All --PD42S16800L, 4216800L NC -wPD42S17800L, 4217800L (No connection) 245 MB 4427525 0055075 250

NEC HPD42S16800L, 4216800L, 42S17800L, 4217800L INPUT/OUTPUT PIN FUNCTIONS The uPD42S16800L, 4216800L, 42S17800L, 4217800L have input pins RAS, CAS, WE, OE, AO to A11/A10"™" and inpuvoutput pins 1/01 to /08. RAS RAS activates the sense amplifier by latching a row address and selecting a (Row address corresponding word line. strobe) It refreshes memory cell array of one line selected by the row address. It also selects the following function. + CAS before RAS refresh. CAS CAS activates data input/output circuit by latching column address and {Column address selecting a digit line connected with the sense amplifier. strobe) A0 to AI/A10""" Address bus. ou2 hem (Address input) Input total 21-bit of address signal, upper 12/11" -bit and lower 9/10 bit in sequence (address multiplex method). Therefore, one word is selected from 2 097 152-word by &-bit memory cell array. In actual operation, latch row address by specifying row address and activating RAS. Then, switch the address bus to column address and activate CAS. Each address is taken into the device when RAS and CAS are activated, Therefore, the address input setup time (tas, tasc) and hold time (trax, tcax) are specified for the activation of RAS and CAS. WE Write control signal. (Write enable) Write operation is executed by activating RAS, CAS and WE. OE Read control signal. _ {Output enable) Read operation can be executed by activating RAS, CAS and OE. If WE is activated during read operation, OE is to be ineffective in the device. Therefore, read operation cannot be executed. 01 to YOR Inpuy | 8-bit data bus. {Data inputoutput) | OUtPUt! 110 +9 1/08 are used to input/output data. Notes 1. A11--uPD42S 16800L, 4216800L A10---uPD42S17800L, 4217800. 2. 12--PD42S16800L, 4216800L 11--PD42817800L, 42178001. 3. 9--PD42S16800L, 4216800L 10--pPD42S17800L, 4217800L 247 mB 6427525 0055077 0b3 a

ELECTRICAL SPECIFICATIONS Nott,2 ABSOLUTE MAXIMUM RATINGS [____Peanew | Symbsi | condton [Rainy [ume] [Weep ononrsinnetew eno | wv [id esas |v [suspivvotage | Vee | SSC*dt tee | | ouputcurent |e || er [opeaingempenie | te [| *i| awe | ed [swapetonpersure | tus | +d atop |e Remark Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS [___Paramewr [Sym] onion [wn | we | wax [ var ] Suprvoinge | ve || a0 | aa | ae | v | High el nputvaiage [vm [+ a0 | vena v Low levalingutvotage | va [it oa | | os |v _ (CAPACITANCE (Ts = +25 °C, f = 1 MHz) [—__Pecameter [Syma] Tentconaiton [| wn [ WA | wax | unr ] ee ee 248 M@™ 6427525 0055078 TTT

NEC HPD42S16800L, 4216800L, 42S17800L, 4217800L DC CHARACTERISTICS (Recommended Operating Conditions unless otherwise noted) [uPD42S16800L, 4216800L] [Parameter [Symbol Testconaition |main| Max. Unit_ Notes #98, og [ wentone || oo | VWnuwrame GS tocoma |_| on | sunay [vetavatss GS _tevoma | | ar | sir com | Maw tevoma | | a | D421 —— a [veeaavstas cS _tonoma |_| 05 | FAS cea [meron | [| them tren > com ac (Fast page mode) tees tecamin s se [mcwm To | cx woe BS mova [rom [| | refresh current lo=OmA Standby : Vec-0.2 VS RAS _ _ CAS before RAS Refresh : CAS before RAS 4.096 cycles/128 ms long refresh current RAS, CAS:0VSVn S02V yA (4 096 cycles/128 ms, Vee-02V SVS Von ly for zPD42S 16800L — — only for zPD42S16800L) WE evn Address input : Don't care Output : Open Self refresh current lo=OmA (CAS before RAS self RAS, CAS: 0VSVus02V uA ‘only for #PD42S16800L) Vee-0.2 VS Vin Vinawax ) Input leakage current Vi=0t03.6V 5 {45 | WA all other pins not under test = 0 V Output leakage current | lon | Outputs ae disabled (Hi2) 5 | as | uA Vo=0t036 V ftow wvetouputvotape | vo [o=a0ma SSS wt | | 249 MB 6427525 0055079 936 a

NEC HPD42S16800L, 4216800L, 42S17800L, 4217800L [uPD42S17800L, 4217800L] [Parameter [Symbol Testcondition | MIN | Max.| Unit_[Notes #78, Til came [_meneone [| 0 | Operating current tremtncann | mentors | | 90 | [Wnwni sma Sonoma |_| os | MPD42S17800L, ——= sxancby [veco2vamas. tenon | [awe] sure [vinwn 5S CS tonoma | | 2 | |MPD4217800L. ae [veoavams CS tonoma |_| 8 | Sea [_eertore || | sem eww | fo | a [wertom || mo | (Fast page mode) tre=treamin » tme= 70.08 mA i Pees [Te moms [oceom [| wo refresh current locOmA Standby : Vec-0.2 VS RAS — — CAS before RAS Refresh : CAS before RAS: 2.048 cycles/128 ms long refresh current RAS, CAS: 0V SV S02V WA er Renard renoL) VeeA2¥S Vin ins WE, OE:Vin Address input : Don't care ‘Output : Open Self refresh current lo=0mA (CS pofore RAS self RAS, CAS :0VSVus02V uA only for uPD42S$17800L) Vec-0.2 VS Vin Vincmax > Input leakage current Vin 0to3.6V +5 | 4 | uA all other pins not under test = 0 V Outputs are disabled (Hi-Z) Output leak t HA [Hiontevetouputvotage] vow [es-2ama za | |v || Low level output voliage| Vor [to=s2ama Tow |v | 250 mm b427525 o05s0a0 658 =

NEC UPD42S16800L, 4216800L, 42S17800L, 4217800L AC CHARACTERISTICS (Recommended Operating Conditions unless otherwise noted) Notes 5,6 (12) eres [Rondon FoadorwneGwetine fw [vol [rol [wl |= | 7 | [rasawescyaeTine dime | ooo | | ww | aw [| | | 7 | [Fox Pace Mode GyeeTineiReederwrid ue || [| | so{ | | 7 | [0 | [es 7 ‘Accass Time from CAS (Falling Edge) [rae | | | | wi | 2 | ns | as | Hssentonecmaser fu} [wt [= Top Pes] | Access TimefromOe toms | | w [| | ns | 8 | | RAS toColumn Address DelayTime [to | 15 | 30 | 15 | 35 | 7 | ao | vs | 8 | | ExStoosascwptime tz | 9 | fo | flo | tls | | | GEtodatasouptime to | o | | o | fo | tls | | [output ButterTurn-off Delay Time cas) tor | o | 3 | 0 | 5 | o | 15 | ns | vo | [Geto datadeiytime too | np | | we | fs | | ns || [ouput utter turn-off Detey Time oe ro | o | 1a | o | ws | o | 5 { ns | 10 | | decommentoistine tem | o | | o | fo | fe | | | GE to MAS inecivesetuptime tts | o | [| o | [| o | [ms | | [Trenstion Time Riseandra) (tx | a | so | 3 | so | 3 | so | ns | | | RAS Prochargetime ftw | ao | | so | fo | | ns || | RAS Pulse wisth Random Read, write Gyeie) [tus | 60 | wooo] 70 | wooo] eo [too] ns | | RAS Pulse Width (Fast Page Mode) [tase] 60 | 125000] 70 | 125000| 60 | 12500] ns | | FAS Hold Time [won [is [|e | fo | | || TAS Pulse wiath fof 2 feeet 2 fee] a feel = | ofa left eS {rt tefl [GAStoRAS ProchergeTime ftw | 5 | | s | | || ns | on | | cas rrechargetime item | wo | | wo | Po [fe || | EAS rrecnarge Time Fest rene Moer [te | ro | | wo {| | wo | | ns | | | RAS Precharge caSHorstime ——tmwe | 8 | | 8 [| s Tt ns || [RAS Hold Time trom GAS recharge ftmer| as | | wo | | ws [fos || [Row Acaress SewwpTime tam | 9 | | o | fo [| ns || [RowAdaressHotime tm | wo | | wo | Pe | UP | 251 mm 6427525 0055081 594 a

NEC HPD42S16800L, 4216800L, 42S17800L, 4217800L (22) frm iwc | [Column Addresssetuptime tase | o | To | fo TT | | Couumn AddressHoistine tem [tp | Ts Ts [ts || Column Address Lead Time Referenced to RAS mies fe, je. feed Read Command Setup Time tes | o | fo | fo | fis | Read Command Hold Time ReferencedtoRAS |twm | o | | o | | o | | ns | az | | Read Command Hols Time Reterencediocas [tw | o | [| o | | o | | rs | i | | write Command Hola Time ReterencedtocAs |twx| to | | wo | | ws | | ns | 3 | | write Command Puise with tw | vo | | wo | [we | | ne | aa | | Oate-inserwptime toe fo | | co | flo | oe fe | | OatainHoidtime tem | vo | fs Ts | ns |e | | We commana sewuptime ftw | o [| | o | fo | {ns | as | [CAS toWEDelayTime teow | gp || ws | ws | ns | ts | | RAStoWE Delay Time tm | es || 95 | fos | ne Ts | | CS Prchargs Delay Tne Referenda WE FaxPogeMose)|toro| se | | es [| 70 | [ns | 15 | [ Column Address Delay Time Referenced toe |two| ss | | eo | | es | | ne | 15 | | Write Command Lead Time Referenced toRAS |twm | 20 | | 20 | | 20 | | ns | | | write Command LeedTimeRetorenceatocas tom | 15 | | 5 | [is | | ns | | | GAS SetupTimefor CAS before RAS Refresh tem | 5 | | 5 | | 5 | | ns | | | EAS Hold Time torCAS botoremAS Refresh [tow | 10 | | vo | | io | [ons || [Brune wen GS ete AS Sat twten Celina] a0 | | wo | [wo | | = | | | FAS Precharge Tine CASbefore MAS Sot Fatash Cyclo we | ro | | roo | | 150 | | ns | 16 | [Weseuptime [| | |wewoigtime ftw fs Ps Tf Te | Retrash Time ee L_| [tat fae] Ts | 8? wm Luz7s25 0o0ss082 420 a

NEC uUPD42S16800L, 4216800L, 42S17800L, 4217800L Notes 1. All voltages are referenced to GND. _ __ 2. After power-up, wait more than 100 us and then, execute 8 CAS before RAS refresh cycles or 8 RAS only refresh cycles to initialize the intemal circuit. 3. Icc1, loca, lec, lees, and lece depend on tncand tre. Specified values are obtained with outputs open. 4. Address can be changed once or less while RAS = Vil and CAS = ViH. 5. AC measurements assume tr = 5 ns. 6. AC Characteristics test condition (1) Input timing specification Vet gan = 2.0 V ---0eeeeenenon % Vu wx) #08 Versnneeeesnnf | H t=5ns h=5ns (2) Output timing specification Vow tun) # 2.0 VY --2----2222-: Vor ax) 2 0,8 V =2220202-n0= 7. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (Ts = 0 to 70 °C) is assured. . 8. In random read cycle, the access time is changed by the conditions of trap and taco as follows. [ wos imomaiend wastnowmn | tmcomn | [insmod es Stevan | ws — | [toma cie | tesco | trap (MAX) and taco oaax) indicate the points which the access time changes and are not the limits of operation. 9. Loading conditions are 1 TTL and 100 pF. 10, tor oraxs and toez wax. define the time at which the output achieves the open circuit condition and are not referenced to Von or Vou. 11. tone mins requirement should be applicable for RAS / CAS cycles preceded by any cycles. 12. Either tic aan. or tan onins must be satisfied for a read cycle. 13. tweoans is applicable for late write cycle or read modify write cycle. In early write cycles, twox min should be satisfied. 14. This specification is referenced to CAS falling edge in early write cycles and to WE falling edge in late write or read modify write cycles. 15. If twes 2 twcs aanw, the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle. If tawo 2 trwo win), town Z towo (MN), tao Z taWD MIN, terWo z tcrwo dan, the cycle is a read modify write cycle and the data out will contain date read from the selected cell. If neither of the above conditions is met, the condition of the data out is indeterminate. 16. This specification is applicable only for uPD42S16800L and uPD42S17800L. 253 M@™ 6427525 0055083 367 a

NEC UPD42S16800L, 4216800L, 42S17800L, 4217800L READ CYCLE tre _ {oo to aa ton a eg J | ES reson SX) C= XOX ARERR EO - a we te me | | ANNAN ait mk thom bees as | EARLY WRITE CYCLE nd ee aoe saves $o° SER son KRY ce KR KKK zi il TTT rorwice Y= KXXXKKKKRRK_wasoonran KKK Remark OE = Don't Care 254 WM 6427525 0055084 2eT3

NEC UPD42S16800L, 4216800L, 42S17800L, 4217800L LATE WRITE CYCLE at—{_ dF RAS ya | - {| tw as ae We \\y YY 1 f= snows Yt: SORE KR Sa. KTR RRR KKKRRRRRKKKK = ZZ) = \\ att TTT ANNANANUNNNANARANNT some: KRRKXKKKRRRRKKREKEN aon —KRKKKRRRRKKHK READ MODIFY WRITE CYCLE el a ram: XA HX = RRR ROKER REE EKEKRNE ———= = mit od Vn & t TUN ANNANANANUNT SS joie Yor? | INCRE KOK SE _KRREKKREER 255 6427525 0055085 13T

NEC UPD42S16800L, 4216800L, 42S17800L, 4217800L FAST PAGE MODE READ CYCLE tease te aan VeR p—t mi ao ——— ocr Yoo KR Row KY con. KXXXK cot. XXX cot KXXXKXXKXKK ilies me ZZ] on ty pee HE | caved TOM | ime LITT He el ELL st prove oot SE} DEO op FAST PAGE MODE EARLY WRITE CYCLE - ——ae a a tn ry i ‘—_ — cerns YX) XK cou. XXX) =) AK) KXXXXXXXXXK we Yt ml AA lm worroves YXKXXKXK onan KX omen KXKK oman KEXKKLEKKLK Remark OE = Don't Care emer wn tt hee 256 mm 6427525 0055086 O7b

NEC UPD42S16800L, 4216800L, 42S17800L, 4217800L FAST PAGE MODE LATE WRITE CYCLE FCA | \\— pols fod 8 Pelle pasos Yo RY ROW KE co KKKKK 2 HK 2 KRKKKRKKKKK ZT) LY Ci ry cy = ZIT, | el TA ANNANAANT vortoice Wi KXKKKXKK GH ORO K YH OMAK KAP on AK KX KX Remark eee re cone RS one | modify write cycles are available for each of the consecutive FAST PAGE MODE READ MODIFY WRITE CYCLE Jeli [| jt) saoom YX) CY = HORDE = _ XR eZ |. NT N77 LESS RCANNV\\NYN I 7 6 _ LT wags Ea VO 10108 VO eeceeendeat beeen es) XX sth) soceee +) OK ti) a bot Sueno Remark [a acura Mean” /Modiy wnte cycles are available for each of the consecubve 257 b4e7525 0055087 Toe

NEC HPD42S16800L, 4216800L, 42S17800L, 4217800L CAS BEFORE RAS SELF REFRESH CYCLE (Only for .PD42S16800L, 42S17800L) twos “we " i. tse tea co a Vw as te f a, pas at — Vee wc ZF (AAA, AAA Remark. Address, OE = Don't care VO to VO8 = Hi-Z How to use CAS before RAS self refresh mode CAS before RAS self refresh mode can't be used by itself. It must be used with perfoming one of 3 refreshes below. + When using distributed CAS before RAS refresh Refresh 4 096 times (uPD42S16800L) or 2 048 times (1PD42S17800L) during 128 ms before set into the TAS before RAS self refresh mode and after reset. + When using burst CAS before RAS refresh Refresh 4 096 times during 64 ms (/PD42S16800L) or 2 048 times during 32 ms (PD42S17800L) before set into the CAS before RAS self refresh mode and after reset. + When using RAS only refresh Refresh against all refresh addresses during 64 ms (uPD42S16800L) or during 32 ms (uPD42S17800L) before set into the CAS before RAS self refresh mode and after reset. 258 me b427525 0055088 5

NEC UPD42S16800L, 4216800L, 42S17800L, 4217800L CAS BEFORE RAS REFRESH CYCLE oe ey we YS Z//} WIA Remark Address, OF = Don'tcare O01 to VO8 = Hi-Z RAS ONLY REFRESH CYCLE rewees Vo XXQK PO" KXKKXKKKKOK PO” KXXXXKKXXXXXXXX Remark WE. OE = Don't care 01 to V08 = Hi-Z 259 M@™ 6427525 0055089 885 ml

NEC HPD42S16800L, 4216800L, 42S17800L, 4217800L HIDDEN REFRESH CYCLE _ “os et ae am to aa —, ES [i wt ee wire [| nace "XX Mrowk) KXXXXXXXXXXXKAXXKAXAAXKAKRAAXA fe we vr aie ANUAUAANNY av: TW MITTT1 260 we b4275e5 0055090 ST? =

NEC HPD42S16800L, 4216800L, 42S17800L, 4217800L TEST MODE SET CYCLE (WE AND CAS BEFORE RAS REFRESH CYCLE) i mS [i RAS vy ton ee ae yr | [tm — Ve Remark Address, OE = Don'tcare VO! to WO8 = Hi-Z TEST MODE TEST MODE is fast test function. On using this mode, test time is reduced to 1/2. In this TEST MODE, internal organization is 1 M words by 16 bits apperently. Don't care about the input levels of the CAS input AO. 1. How to enter TEST MODE Through TEST MODE SET CYCLE (WE and CAS before RAS refresh cycle), the device enters TEST MODE. 2. Write / Read in TEST MODE Write date of “1° or *0* through 1/01 to 1/08 by controlling address except for above-mentioned address. Each input data through each V/O write 2 bits at once. And read through 1/01 to /08 to check written data. In case of writing each 2 bits rightly, each /O data is "1°. But wrong, the data is “O° 3. Refresh in TEST MODE Use normal read cycle or WE and CAS before RAS refrash cycle. ‘4, How to exit from TEST MODE Through RAS only refresh cycle or CAS before RAS refresh cycle, the device exits from TEST MODE. 261 W@™ 6427525 0055091 433

NEC UPD42S16800L, 4216800L, 42S17800L, 4217800L ES CPD 42S 16800L, 4216800L, 42S17800L, 4217800L_ PACKAGE DRAWINGS

28 PIN PLASTIC TSOP(I) (400 mil)

D + | l A w Pa a b

1 A 14

H J 9. ik en ee . ° ‘ ole) $28G5-50-7JD2-1 Nore [rrem[—wmuumerers [ incnes | Each lead centerline is located within 021 mm (0,009 inch) of its true postion TP.) at | A | 1881MAX. | 0.741 MAX. _| [0 | oaoso.10 [orate | [| oxse0s o0ve:r0.008 | [| onas8 | oos 38] [io] esior | omzosis | N | 010 [000 262 me 6427525 0055092 37T a

NEC HPD42S16800L, 4216800L, 42S17800L, 4217800L _

28 PIN PLASTIC SOJ (400 mil)

B g 15 | nn a [nil tt , Se 7 a

5 Ff E

NEC HPD42S16800L, 4216800L, 42S17800L, 4217800L RECOMMENDED SOLDERING CONDITIONS Please consult with our sales offices for soldering conditions of the 4PD42S16800L, 4216800L, 42S17800L, 4217800L. TYPE OF SURFACE MOUNT DEVICE MPD42S 16800LG5, 4216800LG5, 42S17800LG5, 4217800LG5 : 28-pin Plastic TSOP (II) (400 mil) MPD42S 16800LLE, 4216800LLE, 42617800LLE, 4217800LLE : 28-pin Plastic SOU (400 mil) 264 me b4e7525 0055094 Lue =

Product Information

4216800L specifications and overview.

Summary

3.3 V OPERATION 16 M-BIT DYNAMIC RAM 2 M-WORD BY 8-BIT, FAST PAGE MODE

Description

3.3 V OPERATION 16 M-BIT DYNAMIC RAM 2 M-WORD BY 8-BIT, FAST PAGE MODE

Source title 4216800L Datasheet(PDF) - NEC

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