4071B

HEF4071B PHILIPS | Alldatasheet

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Technical content

Product specification File under Integrated Circuits, IC04 January 1995 INTEGRATED CIRCUITS HEF4071B gates Quadruple 2-input OR gate For a complete data sheet, please also download:

• The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

Philips Semiconductors Product specification Quadruple 2-input OR gate HEF4071B gates

DESCRIPTION

The HEF4071B is a positive logic quadruple 2-input OR gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance. Fig.1 Functional diagram. HEF4071BP(N): 14-lead DIL; plastic (SOT27-1) HEF4071BD(F): 14-lead DIL; ceramic (cerdip) (SOT73) HEF4071BT(D): 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America Fig.2 Pinning diagram. Fig.3 Logic diagram (one gfate). FAMILY DATA, IDD LIMITS category GATES See Family Specifications

Philips Semiconductors Product specification Quadruple 2-input OR gate HEF4071B gates AC CHARACTERISTICS VSS = 0 V; Tamb =2 5°C; CL = 50 pF; input transition times≤ 20 ns VDD V SYMBOL TYP. MAX. TYPICAL EXTRAPOLATION FORMULA Propagation delays In → O n 5 55 115 ns 28 ns + (0,55 ns/pF) CL HIGH to LOW 10 t PHL 25 50 ns 15 ns + (0,23 ns/pF) CL 15 20 35 ns 12 ns + (0,16 ns/pF) CL 5 45 90 ns 18 ns + (0,55 ns/pF) CL LOW to HIGH 10 t PLH 20 45 ns 9 ns + (0,23 ns/pF) CL 15 15 30 ns 7 ns + (0,16 ns/pF) CL Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) CL HIGH to LOW 10 t THL 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL 5 60 120 ns 10 ns + (1,0 ns/pF) CL LOW to HIGH 10 t TLH 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL VDD V TYPICAL FORMULA FOR P ( µW) Dynamic power 5 1150 f i+∑ (foC L)× VDD 2 where dissipation per 10 4800 f i+∑ (foC L)× VDD 2 fi= input freq. (MHz) package (P) 15 19 700 f i+∑ (foC L)× VDD 2 fo = output freq. (MHz) C L = load capacitance (pF) ∑ (foC L) = sum of outputs VDD = supply voltage (V)