4069UB

CD4069UBC FAIRCHILD | Alldatasheet

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Features

■ Wide supply voltage range: 3.0V to 15V ■ High noise immunity: 0.45 VDD typ. ■ Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS ■ Equivalent to MM74C04 Ordering Code: Device also available in Tape and Reel. Specify by appending suffix “X” to the ordering code. Connection Diagram Pin Assignments for SOIC and DIP Schematic Diagram Order Number Package Number Package Description CD4069UBCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body CD4069UBCSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4069UBCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

www.fairchildsemi.com 2 CD4069UBC Absolute Maximum Ratings(Note 1) (Note 2) Recommended Operating Conditions (Note 2) Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Recom- mended Operating Conditions” and Electrical Characteristics table provide conditions for actual device operation. Note 2: V SS = 0V unless otherwise specified. Note 3: VSS = 0V unless otherwise specified. Note 4: IOH and IOL are tested one output at a time. DC Supply Voltage (VDD ) −0.5V to +18 VDC Input Voltage (VIN) −0.5V to VDD +0.5 VDC Storage Temperature Range (TS) −65°C to +150°C Power Dissipation (PD ) Dual-In-Line 700 mW Small Outline 500 mW Lead Temperature (TL) (Soldering, 10 seconds) 260 °C DC Supply Voltage (VDD ) 3V to 15V DC Input Voltage (VIN)0 V t o V DD VDC Operating Temperature Range (TA) −40°C to +85°C Symbol Parameter Conditions −40°C +25°C +85°C Units Min Max Min Typ Max Min Max IDD Quiescent Device Current V DD = 5V, 1.0 1.0 7.5 µA VIN = VDD or VSS VDD = 10V, 2.0 2.0 15 µA VIN = VDD or VSS VDD = 15V, 4.0 4.0 30 µA VIN = VDD or VSS VOL LOW Level Output Voltage |I O | < 1 µA VDD = 5V 0.05 0 0.05 0.05 V VDD = 10V 0.05 0 0.05 0.05 V VDD = 15V 0.05 0 0.05 0.05 V VOH HIGH Level Output Voltage |I O | < 1 µA VDD = 5V 4.95 4.95 4.95 V VDD = 10V 9.95 9.95 9.95 V VDD = 15V 14.95 14.95 14.95 V VIL LOW Level Input Voltage |I O | < 1 µA VDD = 5V, VO = 4.5V 1.0 1.0 1.0 V VDD = 10V, VO = 9V 2.0 2.0 2.0 V VDD = 15V, VO = 13.5V 3.0 3.0 3.0 V VIH HIGH Level Input Voltage |I O | < 1 µA VDD = 5V, VO = 0.5V 4.0 4.0 4.0 V VDD = 10V, VO = 1V 8.0 8.0 8.0 V VDD = 15V, VO = 1.5V 12.0 12.0 12.0 V IIN Input Current V DD = 15V, VIN = 0V −0.30 −10−5 −0.30 −1.0 µA VDD = 15V, VIN = 15V 0.30 10 −5 0.30 1.0 µA

3 www.fairchildsemi.com CD4069UBC TA = 25°C, CL = 50 pF , RL = 200 kΩ , tr and tf ≤ 20 ns, unless otherwise specified Note 5: AC Parameters are guaranteed by DC correlated testing. Note 6: C PD determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics application note— AN-90. AC Test Circuits and Switching Time Waveforms Symbol Parameter Conditions Min Typ Max Units tPHL or tPLH Propagation Delay Time from V DD = 5V 50 90 ns Input to Output V DD = 10V 30 60 ns VDD = 15V 25 50 ns tTHL or tTLH Transition Time V DD = 5V 80 150 ns VDD = 10V 50 100 ns VDD = 15V 40 80 ns C IN Average Input Capacitance Any Gate 6 15 pF C PD Power Dissipation Capacitance Any Gate (Note 6) 12 pF

www.fairchildsemi.com 4 CD4069UBC Typical Performance Characteristics Gate Transfer Characteristics Power Dissipation vs Frequency Propagation Delay vs Ambient Temperature Propagation Delay vs Ambient Temperature Propagation Delay Time vs Load Capacitance

5 www.fairchildsemi.com CD4069UBC Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body Package Number M14A 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm wide Package Number M14D

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. CD4069UBC Inverter Circuits LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N14A