HEF4066B PHILIPS | Alldatasheet
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Technical content
Product specification File under Integrated Circuits, IC04 January 1995 INTEGRATED CIRCUITS HEF4066B gates Quadruple bilateral switches For a complete data sheet, please also download:
- The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC
- The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
Philips Semiconductors Product specification Quadruple bilateral switches HEF4066B gates
DESCRIPTION
The HEF4066B has four independent bilateral analogue switches (transmission gates). Each switch has two input/output terminals (Y/Z) and an active HIGH enable input (E). When E is connected to V DD a low impedance bidirectional path between Y and Z is established (ON condition). When E is connected to V SS the switch is disabled and a high impedance between Y and Z is established (OFF condition). The HEF4066B is pin compatible with the HEF4016B but exhibits a much lower ON resistance. In addition the ON resistance is relatively constant over the full input signal range. Fig.1 Functional diagram. Fig.2 Pinning diagram. HEF4066BP(N): 14-lead DIL; plastic (SOT27-1) HEF4066BD(F): 14-lead DIL; ceramic (cerdip) (SOT73)) HEF4066BT(D): 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America PINNING
APPLICATION INFORMATION
An example of application for the HEF4066B is:
- Analogue and digital switching E 0 to E3 enable inputs Y0 to Y3 input/output terminals Z0 to Z3 input/output terminals Fig.3 Schematic diagram (one switch).
Philips Semiconductors Product specification Quadruple bilateral switches HEF4066B gates RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) DC CHARACTERISTICS Tamb =2 5°C Power dissipation per switch P max. 100 mW For other RATINGS see Family Specifications VDD V SYMBOL MIN. TYP. MAX. CONDITIONS ON resistance R ON − 350 2500 Ω En at VDD 10 − 80 245 Ω Vis=V SS to VDD 15 − 60 175 Ω see Fig.4 ON resistance R ON − 115 340 Ω En at VDD 10 − 50 160 Ω Vis=V SS 15 − 40 115 Ω see Fig.4 ON resistance R ON − 120 365 Ω En at VDD 10 − 65 200 Ω Vis=V DD 15 − 50 155 Ω see Fig.4 ‘Δ’ ON resistance 5 ΔR ON − 25 −Ω En at VDD between any two 10 − 10 −Ω Vis=V SS to VDD channels 15 − 5 −Ω see Fig.4 OFF state leakage 5 IOZ −− − nA En at VSScurrent, any 10 −− − nA channel OFF 15 −− 200 nA En input voltage 5 VIL − 2,25 1 V Iis=1 0µA see Fig.9LOW 10 − 4,50 2 V 15 − 6,75 2 V VDD V SYMBOL T amb (°c) CONDITIONS −40 +25 +85 MAX. MAX. MAX. Quiescent device 5 IDD 1,0 1,0 7,5 µAV SS = 0; all valid current 10 2,0 2,0 15,0 µA input combinations; 15 4,0 4,0 30,0 µAV I=V SS or VDD Input leakage current at En 15 ± IIN − 300 1000 nA E n at VSS or VDD
Philips Semiconductors Product specification Quadruple bilateral switches HEF4066B gates NOTE To avoid drawing VDD current out of terminal Z, when switch current flows into terminals Y, the voltage drop across the bidirectional switch must not exceed 0,4 V. If the switch current flows into terminal Z, no VDD current will flow out of terminals Y, in this case there is no limit for the voltage drop across the switch, but the voltages at Y and Z may not exceed V DD or VSS . Fig.4 Test set-up for measuring RON . Fig.5 Typical RON as a function of input voltage. En at VDD Iis= 200µA VSS =0V
Philips Semiconductors Product specification Quadruple bilateral switches HEF4066B gates AC CHARACTERISTICS (1),(2) VSS =0V ; Tamb =2 5°C; input transition times≤ 20 ns VDD V SYMBOL TYP. MAX. Propagation delays Vis→ Vos 51 0 2 0 n s note 3HIGH to LOW 10 t PHL 51 0 n s 15 5 10 ns 51 0 2 0 n s note 3LOW to HIGH 10 t PLH 51 0 n s 15 5 10 ns Output disable times En → Vos 5 80 160 ns note 4HIGH 10 t PHZ 65 130 ns 15 60 120 ns 5 80 160 ns note 4LOW 10 t PLZ 70 140 ns 15 70 140 ns Output enable times En → Vos 54 0 8 0 n s note 4HIGH 10 t PZH 20 40 ns 15 15 30 ns 54 5 9 0 n s note 4LOW 10 t PZL 20 40 ns 15 15 30 ns Distortion, sine-wave 5 0,25 % note 5response 10 0,04 % 15 0,04 % Crosstalk between 5 − MHz note 6any two channels 10 1 MHz 15 − MHz Crosstalk; enable 5 − mV note 7input to output 10 50 mV 15 − mV OFF-state 5 − MHz note 8feed-through 10 1 MHz 15 − MHz ON-state frequency 5 − MHz note 9response 10 90 MHz 15 − MHz
Philips Semiconductors Product specification Quadruple bilateral switches HEF4066B gates Notes 1. V isis the input voltage at a Y or Z terminal, whichever is assigned as input. 2. V os is the output voltage at a Y or Z terminal, whichever is assigned as output. 3. R L =1 0kΩ to VSS ; CL = 50 pF to VSS ; En =V DD ;Vis=V DD (square-wave); see Figs 6 and 10. 4. R L =1 0kΩ ;C L = 50 pF to VSS ; En =V DD (square-wave); Vis=V DD and RL to VSS for tPHZ and tPZH ; Vis=V SS and RL to VDD for tPLZ and tPZL ; see Figs 6 and 11. 5. R L =1 0kΩ ; CL = 15 pF; En =V DD ; Vis= 1⁄2 VDD(p-p)(sine-wave, symmetrical about1⁄2 VDD ); fis= 1 kHz; see Fig.7. 6. R L =1k Ω ; Vis= 1⁄2 VDD(p-p)(sine-wave, symmetrical about1⁄2 VDD ); 7. R L =1 0kΩ to VSS ; CL = 15 pF to VSS ; En =V DD (square-wave); crosstalk isVos (peak value); see Fig.6. 8. R L =1k Ω ; CL = 5 pF; En =V SS ; Vis= 1⁄2 VDD(p-p)(sine-wave, symmetrical about1⁄2 VDD ); 9. R L =1k Ω ; CL = 5 pF; En =V DD ; Vis= 1⁄2 VDD(p-p)(sine-wave, symmetrical about1⁄2 VDD ); VDD V TYPICAL FORMULA FOR P ( µW) Dynamic power 5 800 f i+∑ (foC L)× VDD 2 where dissipation per 10 3 500 f i+∑ (foC L)× VDD 2 fi= input freq. (MHz) package (P) 15 10 100 f i+∑ (foC L)× VDD 2 fo = output freq. (MHz) C L = load capacitance (pF) ∑ (foC L) = sum of outputs VDD = supply voltage (V) 20 log V os(B) 20 log V os V is 20 log V os V is Fig.6 Fig.7
Philips Semiconductors Product specification Quadruple bilateral switches HEF4066B gates Fig.8 Fig.9
Philips Semiconductors Product specification Quadruple bilateral switches HEF4066B gates Fig.10 Waveforms showing propagation delays from Visto Vos. Fig.11 Waveforms showing output disable and enable times. (1) Visat VDD (2) Visat VSS .