74VHC4066 FAIRCHILD | Alldatasheet

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■ Typical switch enable time: 15 ns ■ Wide analog input voltage range: 0–12V ■ Low “on” resistance: 30 typ. ('4066) ■ Low quiescent current: 80 µA maximum (74VHC) ■ Matched switch characteristics ■ Individual switch controls ■ Pin and function compatible with the 74HC4066 Ordering Code: Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Top View Schematic Diagram Truth Table Order Number Package Number Package Description 74VHC4066M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74VHC4066MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC4066N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Input Switch CTL I/O–O/I L “OFF” H“ O N ”

www.fairchildsemi.com 2 74VHC4066 Absolute Maximum Ratings(Note 1) (Note 2) Recommended Operating Conditions Note 1: Absolute Maximum Ratings are those values beyond which dam- age to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/ °C from 65°C to 85°C. Note 4: For a power supply of 5V ± 10% the worst case on resistance (RON ) occurs for VHC at 4.5V. Thus the 4.5V values should be used when designing for CMOS at the higher voltage and so the 5.5V values should be used. Note 5: At supply voltages (VCC – GND) approaching 2V the analog switch on resistance becomes extremely non-linear. Therefore it is recommended that these devices be used to transmit digital only when using these supply voltages. Supply Voltage (VCC ) −0.5 to +15V DC Control Input Voltage (VIN) −1.5 to VCC + 1.5V DC Switch I/O Voltage (VIO)V EE − 0.5 to VCC + 0.5V Clamp Diode Current (IIK, IOK ) ±20 mA DC Output Current, per pin (IOUT ) ±25 mA DC V CC or GND Current, per pin (ICC ) ±50 mA Storage Temperature Range (TSTG ) −65°C to +150°C Power Dissipation (PD ) (Note 3) 600 mW S.O. Package only 500 mW Lead Temperature (TL) (Soldering 10 seconds) 260 °C Min Max Units Supply Voltage (VCC )2 1 2 V DC Input or Output Voltage 0 V CC V (VIN, VOUT ) Operating Temperature Range (TA) −40 +85 °C Input Rise or Fall Times (tr, tf) VCC = 2.0V 1000 ns VCC = 4.5V 500 ns VCC = 9.0V 400 ns Symbol Parameter Conditions VCC TA =25°CT A =−40 to 85°C Units Typ Guaranteed Limits VIH Minimum HIGH Level 2.0V 1.5 1.5 V Input Voltage 4.5V 3.15 3.15 V 9.0V 6.3 5.3 V 12.0V 8.4 8.4 V VIL Maximum LOW Level 2.0V 0.5 0.5 V Input Voltage 4.5V 1.35 1.35 V 9.0V 2.7 2.7 V 12.0V 3.6 3.6 V R ON Maximum “ON” Resistance V CTL = VIH, IS = 2.0 mA 4.5V 100 170 200 Ω See (Note 5) V IS = VCC to GND 9.0V 50 85 105 Ω (Figure 1) 12.0V 30 70 85 Ω 2.0V 120 180 215 Ω VCTL = VIH, IS = 2.0 mA 4.5V 50 80 100 Ω VIS = VCC or GND 9.0V 35 60 75 Ω (Figure 1) 12.0V 20 40 60 Ω R ON Maximum “ON” Resistance V CTL = VIH 4.5V 10 15 20 Ω Matching V IS = VCC to GND 9.0V 5 10 15 Ω 12.0V 5 10 15 Ω IIN Maximum Control V IN = VCC or GND ±0.05 ±0.5 µA Input Current V CC = 2 − 6V IIZ Maximum Switch “OFF” V OS = VCC or GND 6.0V 10 ±60 ±600 nA Leakage Current V IS = GND or VCC 9.0V 15 ±80 ±800 nA VCTL = VIL (Figure 2) 12.0V 20 ±100 ±1000 nA IIZ Maximum Switch “ON” V IS = VCC to GND 6.0V 10 ±40 ±150 nA Leakage Current V CTL = VIH 9.0V 15 ±50 ±200 nA VOS = OPEN (Figure 3) 12.0V 20 ±60 ±300 nA ICC Maximum Quiescent V IN = VCC or GND 6.0V 1.0 10 µA Supply Current I OUT = 0 µA 9.0V 2.0 20 µA 12.0V 4.0 40 µA

3 www.fairchildsemi.com 74VHC4066 VCC = 2.0V−6.0V VEE = 0V−12V, CL = 50 pF (unless otherwise specified) Note 6: Adjust 0 dBm for F = 1 kHz (Null RL/RON Attenuation). Note 7: VIS is centered at VCC /2. Note 8: Adjust input for 0 dBm. Symbol Parameter Conditions VCC TA =25°CT A =−40 to 85°C Units Typ Guaranteed Limits tPHL , tPLH Maximum Propagation 3.3V 25 30 20 ns Delay Switch In to Out 4.5V 5 10 13 ns 9.0V 4 8 10 ns 12.0V 3 7 11 ns tPZL , tPZH Maximum Switch Turn R L = 1 kΩ 3.3V 30 58 73 ns “ON” Delay 4.5V 12 20 25 ns 9.0V 6 12 15 ns 12.0V 5 10 13 ns tPHZ , tPLZ Maximum Switch Turn R L = 1 kΩ 3.3V 60 100 125 ns “OFF” Delay 4.5V 25 36 45 ns 9.0V 20 32 40 ns 12.0V 15 30 38 Minimum Frequency R L = 600Ω 4.5V 40 MHz Response (Figure 7)V IS = 2 VPP at (VCC /2) 9.0V 100 MHz 20 log(VO /VI) = −3 dB (Note 6)(Note 7) Crosstalk Between R L = 600Ω , F = 1 MHz any Two Switches (Note 7)(Note 8) 4.5V −52 dB (Figure 8)9 . 0 V −50 dB Peak Control to Switch R L = 600Ω , F = 1 MHz 4.5V 100 mV Feedthrough Noise C L = 50 pF 9.0V 250 mV (Figure 9) Switch OFF Signal R L = 600Ω , F = 1 MHz Feedthrough V (CT) VIL Isolation (Note 7)(Note 8) 4.5V −42 dB (Figure 10)9 . 0 V −44 dB THD Total Harmonic R L = 10 kΩ , CL = 50 pF, Distortion F = 1 kHz (Figure 11)V IS = 4 VPP 4.5V .013 % VIS = 8 VPP 9.0V .008 % C IN Maximum Control 5 10 10 pF Input Capacitance C IN Maximum Switch 20 pF Input Capacitance C IN Maximum Feedthrough V CTL = GND 0.5 pF Capacitance C PD Power Dissipation 15 pF Capacitance

7 www.fairchildsemi.com 74VHC4066 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A

www.fairchildsemi.com 8 74VHC4066 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

9 www.fairchildsemi.com 74VHC4066 Quad Analog Switch Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com