4060EFE

LTC4060 LINEAR | Alldatasheet

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Standalone Linear NiMH/NiCd Fast Battery Charger ■ Complete Fast Charger Controller for Single, 2-, 3- or 4-Series Cell NiMH/NiCd Batteries ■ No Firmware or Microcontroller Required ■ Termination by –∆V, Maximum Voltage or Maximum Time ■ No Sense Resistor or Blocking Diode Required ■ Automatic Recharge Keeps Batteries Charged ■ Programmable Fast Charge Current: 0.4A to 2A ■ Accurate Charge Current: ±5% at 2A ■ Fast Charge Current Programmable Beyond 2A with External Sense Resistor ■ Automatic Detection of Battery ■ Precharge for Heavily Discharged Batteries ■ Optional Temperature Qualified Charging ■ Charge and AC Present Status Outputs Can Drive LED ■ Automatic Sleep Mode with Input Supply Removal ■ Negligible Battery Drain in Sleep Mode: <1µA ■ Manual Shutdown ■ Input Supply Range: 4.5V to 10V ■ Available in 16-Lead DFN and TSSOP Packages ■ Portable Computers, Cellular Phones and PDAs ■ Medical Equipment ■ Charging Docks and Cradles ■ Portable Consumer Electronics , LTC and LT are registered trademarks of Linear Technology Corporation. 2-Cell, 2A Standalone NiMH Fast Charger with Optional Thermistor and Charge Indicator DESCRIPTIO UFEATURES APPLICATIO SU TYPICAL APPLICATIO U The LTC 4060 is a complete fast charging system for NiMH or NiCd batteries. Just a few external components are needed to design a standalone linear charging system. An external PNP transistor provides charge current that is user programmable with a resistor. A small external capaci- tor sets the maximum charge time. No external current sense resistor is needed, and no blocking diode is required. The IC automatically senses the DC input supply and bat- tery insertion or removal. Heavily discharged batteries are initially charged at a C/5 rate before a fast charge is applied. Fast charge is terminated using the –∆V detection method. Backup termination consists of a programmable timer and battery overvoltage detector. An optional external NTC ther- mistor can be used for temperature-based qualification of charging. An optional programmable recharge feature au- tomatically recharges batteries after discharge. Manual shutdown is accomplished with the SHDN pin, while removing input power automatically puts the LTC4060 into sleep mode. During shutdown or sleep mode, battery drain is <1µA. The LTC4060 is available in both low profile (0.75mm) 16- pin 5mm × 3mm DFN and 16-lead TSSOP packages. Both feature exposed metal die mount pads for optimum ther- mal performance. 2-Cell NiMH Charging Profile VCC VIN = 5V LTC4060 GND SHDN CHRG NTC PROG ARCT SEL0 SEL1 ACP SENSE DRIVE BAT TIMER CHEM PAUSE 330Ω 698Ω NTC 1.5nF

4060 TA01

“CHARGE” CHARGE TIME (MINUTES)

3.10 BATTERY VOLTAGE (V)

3.20 3.30 3.40 10 20 30 40

4060 TA01b

–∆V TERMINATION

(Note 1) Input Voltage SHDN, NTC, SEL0, SEL1, PROG, ARCT, CC + 0.3V Output Voltage LTC4060EDHC ABSOLUTE MAXIMUM RATINGSW WW U PACKAGE/ORDER INFORMATIONW UU Consult LTC Marketing for parts specified with wider operating temperature ranges. Operating Ambient Temperature Range Storage Temperature Range Lead Temperature (Soldering, 10 sec) GND CHRG V CC ACP CHEM NTC SEL1 SEL0 DRIVE BAT SENSE TIMER SHDN PAUSE PROG ARCT TOP VIEW DHC16 PACKAGE 16-LEAD (5mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 37°C/W EXPOSED PAD (PIN 17) IS GND MUST BE SOLDERED TO PCB TO OBTAIN θJA = 37°C/W OTHERWISE θJA = 140°C DHC PART MARKING 4060 ORDER PART NUMBER LTC4060EFE FE PART MARKING 4060EFE FE PACKAGE 16-LEAD PLASTIC TSSOP TOP VIEW DRIVE BAT SENSE TIMER SHDN PAUSE PROG ARCT GND CHRG V CC ACP CHEM NTC SEL1 SEL0 TJMAX = 125°C, θJA = 37°C/W EXPOSED PAD (PIN 17) IS GND MUST BE SOLDERED TO PCB TO OBTAIN θJA = 37°C/W OTHERWISE θJA = 135°C The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VBAT = 2.8V, GND = 0V unless otherwise specified. All currents into the device pins are positive and all currents out of the device pins are negative. All voltages are referenced to GND unless otherwise specified.

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC Supply VCC Operating Voltage Range (Note 4) ● 4.50 10 V ICC VCC Supply Current (Note 9) I PROG = 2mA (RPROG = 698Ω), 2.9 4.3 mA PAUSE = VCC ISD VCC Supply Shutdown Current SHDN = 0V 250 325 µA IBSD Battery Pin Leakage Current in Shutdown (Note 5) V BAT = 2.8V, SHDN = 0V –1 0 1 µA IBSL Battery Pin Leakage Current in Sleep (Note 6) V CC = 0V, VBAT = 5.6V –1 0 1 µA VUVI1 Undervoltage Lockout Exit Threshold SEL0 = 0, SEL1 = 0 and SEL0 = V CC, ● 4.25 4.36 4.47 V SEL1 = 0, VCC Increasing VUVD1 Undervoltage Lockout Entry Threshold SEL0 = 0, SEL1 = 0 and SEL0 = V CC, ● 4.15 4.26 4.37 V SEL1 = 0, VCC Decreasing

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VBAT = 2.8V, GND = 0V unless otherwise specified. All currents into the device pins are positive and all currents out of the device pins are negative. All voltages are referenced to GND unless otherwise specified. VUVI2 Undervoltage Lockout Exit Threshold SEL0 = 0, SEL1 = V CC, VCC Increasing ● 6.67 6.81 6.95 V VUVD2 Undervoltage Lockout Entry Threshold SEL0 = 0, SEL1 = V CC, VCC Decreasing ● 6.57 6.71 6.85 V VUVI3 Undervoltage Lockout Exit Threshold SEL0 = V CC, SEL1 = VCC, VCC Increasing ● 8.28 8.47 8.65 V VUVD3 Undervoltage Lockout Entry Threshold SEL0 = V CC, SEL1 = VCC, VCC Decreasing ● 8.18 8.37 8.55 V VUVH Undervoltage Lockout Hysteresis For All SEL0, SEL1 Options 100 mV Charging Performance IFCH High Fast Charge Current (Notes 7, 10) R PROG = 698Ω, 5V < VCC < 10V ● 1.9 2 2.1 A IFCL Low Fast Charge Current (Note 7) R PROG = 3480Ω, 4.5V < VCC < 10V ● 0.35 0.4 0.45 A IPCH High Precharge Current (Note 7) R PROG = 698Ω, 4.5V < VCC < 10V 320 400 480 mA IPCL Low Precharge Current (Note 7) R PROG = 3480Ω, 4.5V < VCC < 10V 40 80 120 mA IBRD Battery Removal Detection Bias Current 4.5V < V CC < 10V, VBAT = VCC – 0.4V ● –450 –300 –160 µA VBR Battery Removal Threshold Voltage (Note 8) V CELL Increasing, 4.5V < VCC < 10V ● 1.95 2.05 2.15 V VBRH Battery Removal Threshold Hysteresis Voltage V CELL Decreasing 50 mV (Note 8) VBOV Battery Overvoltage Threshold (Note 8) V CELL Increasing, 4.5V < VCC < 10V ● 1.85 1.95 2.05 V VBOVH Battery Overvoltage Threshold Hysteresis (Note 8) V CELL Decreasing 50 mV VFCQ Fast Charge Qualification Threshold Voltage V CELL Increasing, 4.5V < VCC < 10V 840 900 960 mV (Note 8) VFCQH Fast Charge Qualification Threshold Hysteresis V CELL Decreasing 50 mV Voltage (Note 8) VIDT Initial Delay Hold-Off Threshold Voltage (Note 8) V CELL Increasing, 4.5V < VCC < 10V 1.24 1.3 1.36 V VIDTH Initial Delay Hold-Off Threshold Hysteresis Voltage V CELL Decreasing 50 mV (Note 8) VMDV –∆V Termination (Note 8) CHEM = V CC (NiCd) ● 11 16 21 mV CHEM = 0V (NiMH) ● 58 1 4 m V VPROG Program Pin Voltage 4.5V < V CC < 10V, RPROG = 635Ω ● 1.45 1.5 1.54 V and 3480Ω VART Automatic Recharge Programmed Threshold V CELL Decreasing, VARCT = 1.1V, ● 1.065 1.1 1.135 V Voltage Accuracy (Note 8) 4.5V < V CC < 10V VARDT Automatic Recharge Default Threshold Voltage V CELL Decreasing, VARCT = VCC, ● 1.235 1.3 1.365 V Accuracy (Note 8) 4.5V < V CC < 10V VARH Automatic Recharge Threshold Voltage Hysteresis V CELL Increasing 50 mV (Note 8) VARDEF Automatic Recharge Pin Default Enable Threshold V CC VCC V Voltage – 0.8 – 0.2 VARDIS Automatic Recharge Pin Disable Threshold 250 650 mV Voltage IARL Automatic Recharge Pin Pull-Down Current V ARCT = 1.3V ● 0.15 1.5 µA VCLD NTC Pin Cold Threshold Voltage V NTC Decreasing, 4.5V < VCC < 10V ● 0.83 • 0.86 • 0.89 • V VCC VCC VCC VCLDH NTC Pin Cold Threshold Hysteresis Voltage V NTC Increasing 150 mV VHTI NTC Pin Hot Charge Initiation Threshold Voltage V NTC Decreasing, 4.5V < VCC < 10V ● 0.47 • 0.5 • 0.53 • V VCC VCC VCC

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VBAT = 2.8V, GND = 0V unless otherwise specified. All currents into the device pins are positive and all currents out of the device pins are negative. All voltages are referenced to GND unless otherwise specified. VHTIH NTC Pin Hot Charge Initiation Hysteresis Voltage V NTC Increasing 100 mV VHTC NTC Pin Hot Charge Cutoff Threshold Voltage V NTC Decreasing, 4.5V ≤ VCC ≤ 10V ● 0.37 • 0.4 • 0.43 • V VCC VCC VCC VHTCH NTC Pin Hot Charge Cutoff Hysteresis Voltage V NTC Increasing 100 mV VNDIS NTC Pin Disable Threshold Voltage 25 250 mV INL NTC Pin Pull-Down Current V NTC = 2.5V ● 0.15 1.5 µA tACC Timer Accuracy R PROG = 698Ω, CTIMER = 1.2nF and –15 0 15 % RPROG = 3480Ω, CTIMER = 470pF Output Drivers IDRV Drive Pin Sink Current V DRIVE = 4V ● 40 70 120 mA RDRV Drive Pin Resistance to VCC VDRIVE = 4V, Not Charging 4700 Ω VOL ACP, CHRG Output Pins Low Voltage I ACP = ICHRG = 10mA 0.8 V IOH ACP, CHRG Output Pins High Leakage Current Outputs Inactive, V CHRG = VACP = VCC –2 2 µA Control Inputs VIT SHDN, SEL0, SEL1, CHEM, PAUSE Pins Digital V CC = 10V 350 650 mV Input Threshold Voltage VITH SHDN, SEL0, SEL1, CHEM, PAUSE Pins Digital 50 mV Input Hysteresis Voltage IIPD SHDN, SEL0, SEL1, CHEM Pins Digital Input V CC = 10V, VIN = VCC 0.4 2 µA Pull-Down Current IIPU PAUSE Pin Digital Input Pull-Up Current V IN = GND –2 –0.4 µA Note 1: Absolute Maximum Ratings only indicate limits for survivability. Operating the device beyond these limits may result in permanent damage. Continuous or extended application of these maximum levels may adversely affect device reliability. Note 2: The LTC4060 is guaranteed to meet performance specifications from 0°C to 70°C ambient temperature range and 0°C to 85°C junction temperature range. Specifications over the –40°C to 85°C operating ambient temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Overtempera- ture protection is activated at a temperature of approximately 145°C, which is above the specified maximum operating junction temperature. Continuous operation above the specified maximum operation temperature may result in device degradation or failure. Operating junction temperature T J (in °C) is calculated from the ambient temperature TA and the average power dissipation PD (in watts) by the formula: TJ = TA + θJA • PD Note 4: Short duration drops below the minimum VCC specification of several microseconds or less are ignored by the undervoltage detection circuit. Note 5: Assumes that the external PNP pass transistor has negligible B-C reverse leakage current when the collector is biased at 2.8V (VBAT for two charged cells in series) and the base is biased at VCC. Note 6: Assumes that the external PNP pass transistor has negligible B-E reverse leakage current when the emitter is biased at 0V (VCC) and the base is biased at 5.6V (VBAT for four charged cells in series). Note 7: The charge current specified is the regulated current through the internal current sense resistor that flows into the external PNP pass transistor’s emitter. Actual battery charging current is slightly less and depends upon PNP alpha. Note 8: Given as a per cell voltage (V BAT/Number of Cells). Note 9: Supply current includes the current programming resistor current of 2mA. The charger is paused and not charging the battery. Note 10: The minimum VCC supply is set at 5V during this test to compensate for voltage drops due to test socket contact resistance and 2A of current. This ensures that the supply voltage delivered to the device under test does not fall below the UVLO entry threshold. Specification at the minimum V CC of 4.5V is assured by design and characterization.

TYPICAL PERFOR A CE CHARACTERISTICS UW NiMH Battery Charging Characteristics at 1C Rate NiCd Battery Charging Characteristics at 1C Rate NiMH Battery Charging Characteristics at C/2 Rate NiCd Battery Charging Characteristics at C/2 Rate IFCH vs Temperature and Supply Voltage IFCL vs Temperature and Supply Voltage IBRD vs Temperature and Supply Voltage VMDV vs Temperature and Supply Voltage tACC vs Temperature and Supply Voltage CHARGE TIME (MINUTES) 1.4 CELL VOLTAGE (V)1.5 1.6 1.7 10 20 30 40

4060 G02

–∆V TERMINATION TA = 25°C CHARGE TIME (MINUTES) 02 0

1.35 CELL VOTLAGE (V)

1.45 1.60 40 80 100

4060 G03

1.40 1.55 1.50 60 120 140 –∆V TERMINATION TA = 25°C CHARGE TIME (MINUTES) 02 0

1.40 CELL VOTLAGE (V)

1.50 1.65 40 80 100

4060 G04

1.45 1.60 1.55 60 120 140 –∆V TERMINATION TEMPERATURE (°C) –50

1.990 IFCH (A)

1.995 2.000 2.005 2.010 –25 0 25 50

4060 G05

VCC = 10V VCC = 4.5V TEMPERATURE (°C) –50 398 IFCL (mA) 399 400 401 402 –25 0 25 50

4060 G06

VCC = 10V VCC = 4.5V TEMPERATURE (°C) –50 –340 IBRD (µA) –300 –260 –25 0 25 50

4060 G07

VCC = 10V VCC = 4.5V TEMPERATURE (°C) –50 25 75

4060 G08

–25 0 50 100 125 VMDV (mV) NiCd 4.5V ≤ VCC ≤ 10V NiMH 4.5V ≤ VCC ≤ 10V TEMPERATURE (°C) –50 0.5 1.0 1.7 25 75

4060 G09

–0.5 –25 0 50 100 125 –1.0 –1.5 1.5 ERROR (%) VCC = 10V VCC = 4.5V RPROG = 3480Ω CTIMER = 470pF RPROG = 698Ω CTIMER = 1.2nF CHARGE TIME (MINUTES) 1.55 CELL VOLTAGE (V)1.60 1.65 1.70 10 20 30 40

4060 G01

–∆V TERMINATION TA = 25°C

DRIVE (Pin 1): Base Drive Output for the External PNP Pass Transistor. Provides a controlled sink current that drives the base of the PNP. This pin has current limit protection for the LTC4060. BAT (Pin 2): Battery Voltage Sense Input Pin. The LTC4060 uses the voltage on this pin to monitor battery voltage and control the battery current during charging. An internal resistor divider is connected to this pin which is discon- nected when in shutdown or when no power is applied to V CC. SENSE (Pin 3): Charge Current Sense Node Input. Current from VCC passes through the internal current sense resis- tor and reappears at the SENSE pin to supply current to the external PNP emitter. The PNP collector provides charge current directly to the battery. TIMER (Pin 4): Charge Timer Input. A capacitor connected between TIMER and GND along with a resistor connected from PROG to GND programs the charge cycle timing limits. SHDN (Pin 5): Active Low Shutdown Control Logic Input. When pulled low, charging stops and the LTC4060 supply current is minimized. PAUSE (Pin 6): Pause Enable Logic Input. The charger can be paused, turning off the charge current, disabling termi- nation and stopping the timer when this pin is high. A low level will resume the charging process. PROG (Pin 7): Charge Current Programming Input. Pro- vides a virtual reference of 1.5V for an external resistor PROG) tied between this pin and GND that programs the battery charge current. The fast charge current will be 930 times the current through this resistor. This voltage is also usable as system voltage reference. ARCT (Pin 8): Autorecharge Threshold Programming Input. When the average cell voltage falls below this threshold, charging is reinitiated. The voltage on this pin is conveniently derived by using two series PROG pin resistors and connecting to their common. Connecting ARCT to V CC invokes a default threshold of 1.3V. Connect- ing ARCT to GND inhibits autorecharge. SEL0, SEL1 (Pins 9, 10): Number of Cells Selection Logic Input. For single cell, connect both pins to GND. For two cells, connect SEL1 to GND and SEL0 to V CC. For three cells, SEL1 connects to V CC and SEL0 to GND. For four cells, connect both pins to VCC. NTC (Pin 11): Battery Temperature Input. An external NTC thermistor network may be connected to NTC to provide temperature-based charge qualification. Connecting NTC to GND inhibits this function. CHEM (Pin 12): Battery Chemistry Selection Logic Input. When connected to a high level NiCd fast charge – ∆V termination parameters are used. A low level selects NiMH parameters. ACP (Pin 13): Open-Drain Power Supply Status Output. When V CC is greater than the undervoltage lockout thresh- old, the ACP pin will pull to ground. Otherwise the pin is high impedance. This output is capable of driving an LED. V CC (Pin 14): Power Input. This pin can be bypassed to ground with a capacitance of 1µF. CHRG (Pin 15): Open-Drain Charge Indicator Status Out- put. The LTC4060 indicates it is providing charge to the battery by driving this pin to GND. If charging is paused or suspended due to abnormal battery temperature, the pin remains pulled to GND. Otherwise the pin is high imped- ance. This output can drive an LED. GND (Pin 16): Ground. This pin provides a ground for the internal voltage reference and other circuits. All voltage thresholds are referenced to this pin. Exposed Pad (Pin 17): Thermal Connection. Internally connected to GND. Solder to PCB ground for optimum thermal performance.

31.5Ω 0.03Ω 1.5V PROG RPROG VCC NTC CUTOFF I I/5 HOT COLD CURRENT DIVIDER VOLTAGE REFERENCE UVLO SUPPLY GOOD SEL0 SEL1 AUTORECHARGE DETECTOR IC OVERTEMPERATURE DETECT OUTPUT DRIVER AND CURRENT LIMIT BATTERY DETECTOR A/D CONVERTER IBRD 4060 BD OSCILLATOR TIMER CTIMER IOSC THERMISTOR INTERFACE CHARGER STATE CONTROL LOGIC VCC I I/5 IOSC – + CHRG15 ACP13 SHDN5 PAUSE6 ARCT SEL0 SEL1 CHEM GND 16, 17 BAT DRIVE SENSE

4060 F01

Figure 1. LTC4060 Basic State Diagram

The charge current is set with an external current pro- gramming resistor connected between the PROG pin and GND. In the Block Diagram, amplifier A1 will cause a virtual 1.5V to appear on the PROG pin and thus, all of the pro- gramming resistor’s current will flow through the N-channel FET to the current divider. The current divider is controlled by the charger state control logic to produce a voltage across R1, appropriate either for precharge (I/5) or for fast charge (I), depending on the cell voltage. The current di- vider also produces a constant current I OSC, that along with an external capacitor tied to the TIMER pin, sets the Oscillator’s clock frequency. During charging, the external PNP transistor’s collector will provide the battery charge current. The PNP’s emitter current flows into the SENSE pin and through the internal current sense resistor R2 (0.03Ω). This current is slightly more than the collector current since it includes the base current. Amplifier A2 and the output driver will drive the base of the external PNP through the DRIVE pin to force the same reference voltage that appears across R1 to appear across the R2. The pre- cision ratio between R1 and R2, along with the current programming resistor, accurately determines the charge current. When charging begins, the charger state control logic will enable precharge of the battery. When the cell voltage exceeds the fast charge qualification threshold, fast charge begins. If the cell voltage exceeds the initial delay hold off threshold voltage just prior to precharge, then the A/D converter immediately monitors for a – ∆V event to terminate charging while in fast charge. Otherwise, the fast charge voltage stabilization hold off period must expire before the A/D converter monitors for a –∆V event from which to terminate charging. The –∆V magnitude for termination is selected for either NiMH or NiCd by the CHEM pin. Should the battery temperature become too hot or too cold, charging will be suspended by the charger state control logic until the temperature enters normal limits. A termination timer puts the charger into shutdown mode if the programmed time has expired. After charging has ended, the optional autorecharge detector function monitors for the battery voltage to drop to either a default or externally programmed cell voltage before automati- cally restarting a charge cycle. The SHDN pin can be used to return the charger to a shutdown and reset state. The PAUSE pin can be used to pause the charge current and internal clocks for any interval desired. Fault conditions, such as overheating of the IC due to excessive PNP base current drive, are monitored and limited by the IC overtemperature detection and output driver and current limit blocks. When either V CC is removed or manual shutdown is entered, the charger will draw only tiny leakage currents from the battery, thus maximizing standby time. With VCC removed, the external PNP’s base is connected to the battery by the charger. In manual shutdown, the base is connected to VCC by the charger. Undervoltage Lockout An internal undervoltage lockout circuit (UVLO) monitors the input voltage and keeps the charger in the inactive sleep mode until V CC rises above the undervoltage exit threshold. The ACP pin is high impedance while in the sleep mode and becomes low impedance to ground when in the active mode. The threshold is dependent upon the number of series cells selected by the SEL0 and SEL1 pins (see V UVI1-3 and VUVD1-3 in the Electrical Characteristics table). The UVLO circuit has a built-in hysteresis of 100mV. The thresholds are chosen to provide a minimum voltage drop of approximately 600mV between minimum VCC and BAT at a battery cell voltage of 1.8V. This helps to protect against excessive saturation in the external power PNP when the supply voltage is near its minimum. While inactive the LTC4060 reduces battery current to just a negligible leakage current (I BSL). Manual Shutdown Control The LTC4060 can be forced into a low quiescent current shutdown while VCC is present by applying a low level to the SHDN pin. In manual shutdown, charging is inhibited, the internal timer is reset and oscillator disabled, CHRG status output is high impedance and ACP continues to provide the correct status. The LTC4060 will draw low cur- rent from the supply (I SD), and only a negligible leakage current is applied to the battery (I BSD). If a high level is OPERATIOU

Table 1. LTC4060 Time Limit Programming Examples high or removing and reapplying power to the charger. will not initiate until these temperature limits are met. FCQ, the LTC4060 remains in precharge. rises above 5°C or falls below 45°C.

charging begins at the maximum current set by the external programming resistor connected between the PROG pin and GND. If an external thermistor indicates sensed temperature is beyond a range of 5°C to 55°C charging is suspended, the charge timer is paused and the CHRG status output remains low. Normal charging resumes from the previous state when the sensed temperature rises above 5°C or falls below 45 °C. Voltage-based termination (– ∆V) is then reset and immediately enabled. If voltage-based termina- tion was imminent when the temperature limits were exceeded, charge termination will occur. Charge Termination Once fast charge begins and after an initial battery voltage stabilization hold-off period shown in Table 1, voltage- based termination (–∆V) is enabled. This period is used to prevent falsely terminating on a –∆V event that can occur almost immediately after initiating charging on some heavily discharged or stored batteries. However, if V CELL was measured to be above 1.3V (VIDT) immediately prior to the precharge cycle, then a mostly charged battery is assumed and voltage-based termination (–∆V) is enabled without delay. An internal 1.5mV resolution A/D converter measures the cell voltage after each battery voltage sampling interval indicated in Table 1. The peak cell voltage is stored and compared to the current cell voltage. When the cell voltage has dropped by at least V MDV (magnitude selected by the CHEM pin) from the peak for four consecutive battery voltage sampling intervals, charging is terminated. Back-up termination is provided by the charge time limiter, whose time limit is indicated in Table 1, and by a battery overvoltage detector. Once terminated by back-up termi- nation, charge qualification can be reinitiated only by remov- ing and replacing the battery or toggling the SHDN pin low to high or removing and reapplying power to the charger. Automatic Recharge Once charging is complete, the optional programmable automatic recharge state can be entered. This state, if enabled, will automatically restart the charger from the charge qualification state without user intervention when- ever the battery cell voltage drops below a set level. With the advent of low memory effect NiMH and improved NiCd cells an automatic recharge feature is practical and elimi- nates the need for very slow trickle charging. The CHRG status output is high impedance in the auto- matic recharge state until charging begins. If the V CELL voltage drops below the voltage set on the ARCT pin for at least the automatic recharge entry delay time as shown in Table 1, the charge qualification state is entered and charging will begin anew in fast charge. An easy way of setting the voltage on the ARCT pin is by using two series current programming resistors and connecting their com- mon to the ARCT pin as shown in Figure 2. The PROG pin will provide a constant 1.5V (V PROG). The programmable voltage range of the ARCT pin is approximately 0.8V to 1.6V. A preprogrammed recharge threshold of 1.3V (VARDT) is selected when the ARCT pin is connected to V CC (VARDEF). Automatic recharge is disabled when the ARCT pin is connected to ground (VARDIS). Pause After charging is initiated, the PAUSE pin may be used to pause operation at any time. Whenever the voltage on the PAUSE pin is a logic high, the charge timer and all other timers pause, charging is stopped and the fast charge ter- mination algorithm is inhibited. The CHRG status output remains at GND. If voltage-based termination was immi- nent before pause, charge termination will occur. Otherwise, when pause ends, the charge timer and all other timers resume timing, charging restarts and voltage-based termi- nation (–∆V) is reset and immediately enabled. If the bat- tery is removed while the PAUSE pin is a logic high, then battery removal is detected and shutdown is entered. If the battery is replaced while the PAUSE pin is a logic high, it will not be detected until pause is turned off. For pause periods or a series of periods where the battery capacity could be significantly depleted, consider using shutdown instead of pause to avoid having the safety timer expire before the battery can be fully charged. Shutdown resets the safety timer.

Table 2. LTC4060 Charging Parameters moval of a battery by monitoring the V CELL pin voltage.

• . •930 15 930 1395 where RPROG is the total resistance from the PROG pin to ground. For example, if 1A of fast charge current is required: R A kPROG ==1395 1 14. 1% Resistor Under precharge conditions, the current is reduced to 20% of the fast charge value (I MAX).The LTC4060 is designed for a maximum current of 2A. This translates to a maximum PROG pin current of 2.15mA and a minimum program resistor of 698 Ω. Reduced accuracy at low current limits the useful fast charge current to a minimum of approximately 200mA. Errors in the charge current can be statistically approximated as follows: One Sigma Error ≅ 7mA For best stability over temperature and time, 1% metal- film resistors are recommended. Capacitance on the PROG pin should be limited to about 75pF to insure adequate AC phase margin for its amplifier. Different charge currents can be programmed by various means such as by switching in different program resis- tors. A voltage DAC connected through a resistor to the PROG pin or a current DAC connected in parallel with a

resistor to the PROG pin can also be used to program current. Note that this will alter the timer periods unless alternate TIMER pin capacitors are also programmed through an analog switch. The PROG pin provides a reference voltage of 1.5V (V PROG) that may be tapped for system use. Current loading on PROG is multiplied by 930 and appears as increased I MAX. This may be compensated by adjustment of RPROG. Total PROG pin current must be limited to 2.3mA otherwise absolute maximum ratings will be exceeded. When the LTC4060 is in the shutdown mode, the PROG pin is forced to ground potential to save power. Programming the Timer All LTC4060 internal timing is derived from the internal oscillator that is programmed with an external capacitor at the TIMER pin. The time periods shown in Table 1 scale directly with the timer period. The programmable safety timer is used to put a time limit on the entire charge cycle for the case when charging has not otherwise terminated. The time limit is programmed by an external capacitor at the TIMER pin and is also dependent on the current set by the programming resistor connected to the PROG pin. The time limit is determined by the following equation: t MAX (Hours) = 1.567 • 106 • RPROG (Ω) • CTIMER (F) CF t Hours RTIMER MAX PROG () () .• • ( ) Ω1 567 10 6 Some typical timing values are detailed in Table 1. The timer begins at the start of a charge cycle. After the time- out occurs, the charge current stops and the CHRG output assumes a high impedance state to indicate that the charging has stopped. Excessively short time-out periods may not allow enough time for the battery to receive full charge or may result in premature – ∆V termination due to too short a battery voltage stabilization hold-off period. Excessively long time- out periods may indicate too low a charge current which may not allow voltage-based termination (– ∆V) to work properly. Time-out limits of less than 0.75 hour for faster 2C charge rates, or more than 3.5 hours for slower C/2 APPLICATIO S I FOR ATIOWU UU charge rates, are generally not recommended. Consult the battery manufacturer for recommended periods. An external timing source can also be used to drive the TIMER pin for precise or programmed control. The high level must be between 2.5V and VCC and the low level must be between 0V and 0.25V. Also, the driving source must be able to overdrive the internal current source and sink which is 5% of the current through R PROG. Battery Temperature Sensing Temperature sensing is optional in LTC4060 applications. To disable temperature qualification of all charging opera- tions, the NTC pin must be wired to ground. A circuit for temperature sensing using a thermistor with a negative temperature coefficient (NTC) is shown in Figure 2. Inter- nally derived VCC proportional voltages (VCLD, VHTI, VHTC) are compared to the voltage on the NTC input pin to test the temperature thresholds. The battery temperature is mea- sured by placing the thermistor close to the battery pack. In Figure 2, a common 10k NTC thermistor such as a Murata NTH4G series NTH4G39A103F can be used. R HOT should be a 1% resistor with a value equal to the value of the chosen NTC thermistor at 45°C (VNTC = VHTI = 0.5 • VCC typ). Another temperature may be chosen to suit the battery requirements. The LTC4060 will not initiate a charge cycle or continue with a precharge if the value of the thermistor falls below 4.42k which is a temperature rising to approximately 45°C. However, once fast charging is in progress, it will not be stopped until the thermistor drops below 3k which is a temperature rising to approximately 55°C (V NTC = VHTC = 0.4 • V CC typ). Once reaching this charge cutoff threshold, charging is suspended until the value of the thermistor rises above approximately 4.8k (falling temperature) or approximately 43°C (45°C – 2°C hysteresis at V CC = 5V) and then charging is resumed. Hysteresis avoids possible oscillation about the trip points. Note that the comparator hysteresis voltages are constant and when V CC increases the signal level from the ther- mistor increases thus making the temperature hysteresis look smaller. During suspension the charge current is turned off and the safety timer is frozen. The LTC4060 is also designed to suspend when the thermistor rises above 34k (falling

temperature) at approximately 0°C (5°C – 5°C hysteresis at VCC = 5V) and then resume when the thermistor falls below 27k (rising temperature) which will be approxi- mately 5°C (V NTC = VCLD = 0.86 • VCC typ). Many thermistors with an RCOLD to RHOT ratio of approxi- mately 7 will work. For lower power dissipation higher values of thermistor resistance can be used. The Murata NTH4G series offers resistances of up to 100k at 25°C. It is important that the thermistor be placed in close contact with the battery and away from the external PNP pass transistor to avoid excessive temperature errors on the sensed battery temperature. Furthermore, since V CC is a high current path into the LTC4060, it is essential to minimize voltage drops between the V CC supply pin and the top of RHOT by Kelvin connecting RHOT directly to the VCC pin. Power Requirements The DC power input to the VCC pin must always be within proper limits while charging a battery. Voltages beyond the absolute maximum ratings may damage the charger and voltages falling below the UVLO entry thresholds, as programmed by the SEL0 and SEL1 pins, will likely cause the charger to enter the shutdown state (when the UVLO exit threshold is exceeded charging will begin anew). While the LTC4060 is designed to reject 60Hz or 120Hz supply ripple, certain precautions are required. The instantaneous ripple voltage must always be within the above mentioned limits. Ripple voltage seen across the collector-base junc- tion of the external PNP pass transistor will slightly modu- late its beta and hence its base current. Since the emitter current is precisely regulated by the LTC4060, any modu- lation of base current will appear at the collector. This slightly modulated battery charge current into a battery will usually produce an insignificant modulation voltage at the battery. However, if excessive wire impedance to the battery from the PNP exists, then it may be helpful to Kelvin connect the BAT pin to a convenient point closest to the battery to reduce ripple magnitude entering the LTC4060’s battery monitoring circuits. The battery ground imped- ance should also be managed to limit ripple voltage at the BAT pin. Excessive ripple into the BAT pin may cause the charger to deviate from specified performance. APPLICATIO S I FOR ATIOWU UU VCC Bypass Capacitor A 1µF capacitor located close to the LTC4060 will usually provide adequate input bypassing. However, caution must be exercised when using multilayer ceramic capacitors. Because of the self-resonance and high Q characteristics of some types of ceramic capacitors, along with wiring inductance, high voltage transients can be generated under some conditions such as connecting or disconnect- ing a supply input to a hot power source. To reduce the Q and prevent these transients from exceeding the absolute maximum voltage rating, consider adding about 1 Ω of resistance in series with the ceramic input capacitor. BAT Bypass Capacitor This optional capacitor, connected between BAT and GND, can be used to help filter excessive contact bounce during the battery monitoring or charging process. The value will depend upon the contact bounce open duration, but is typi- cally 10µF. Another purpose of this capacitor is to bypass transient battery load events that might otherwise disrupt monitoring or charging. Should the battery connections not be subject to excessive contact bounce or excessive bat- tery voltage transients, then no BAT pin capacitor is re- quired. The same caution mentioned above for the V CC by- pass capacitor applies. External PNP Transistor The external PNP pass transistor must have adequate beta and breakdown voltages, low saturation voltage and suf- ficient power dissipation capability that may include heat sinking. To provide 2A of charge current with the minimum avail- able base current drive of 40mA (I DRV min) requires a minimum PNP beta of 50. The transistor’s collector to emitter breakdown voltage must be high enough to withstand the difference between the maximum supply voltage and minimum battery volt- age. Almost any transistor will meet this requirement. Additionally, when no power is supplied to the charger IN = 0V and VSENSE = 0V), the transistor’s emitter to base breakdown voltage must be high enough to prevent a leakage path at the maximum battery voltage while not

APPLICATIO S I FOR ATIOWU UU charging (the DRIVE pin is internally switched to the BAT pin). Most transistors will meet this requirement as well. With low supply voltages, the PNP saturation voltage (VCESAT) becomes important. The V CESAT must be less than the minimum supply voltage minus the maximum voltage drop across the internal current sense resistor and bond wires (approximately 0.08Ω) and maximum battery voltage presented to the charger accounting for wire I • R drops. V CESAT (V) < VDD(MIN) – (IBAT(MAX) • 0.08Ω + VBAT(MAX)) For example, if it were desired to have a programmed charge current of 2A with a minimum supply voltage of 4.75V and a maximum battery voltage of 3.6V (2 series cells at 1.8V each), then the minimum operating V CESAT is: If the PNP transistor cannot achieve the saturation voltage required, base current will dramatically increase. This is to be avoided for a number of reasons: DRIVE pin current may reach current limit resulting in the LTC4060 charac- teristics going out of specifications, excessive power dissipation may force the IC into thermal shutdown, or the battery could discharge because some of the current from the DRIVE pin could be pulled from the battery through the forward biased PNP collector base junction. The actual battery fast charge current (I BAT) is slightly less than the regulated charge current because the charger senses the emitter current and the battery charge current will be reduced by the base current. In terms of β (I C/IB) IBAT can be calculated as follows: IA IBAT PROG() • = + ⎠⎟930 1 β β If β = 100 then IBAT is 1% low. The 1% loss can be easily compensated for by increasing IPROG by 1%. Another important factor to consider when choosing the PNP pass transistor is its power handling capability. The transistor’s data sheet will usually give the maximum rated power dissipation at a given ambient temperature with a power derating for elevated temperature operation. The maximum power dissipation of the PNP when charging is: P D(MAX) (W) = IMAX(VDD(MAX) – VBAT(MIN)) VDD(MAX) is the maximum supply voltage and VBAT(MIN) is the minimum battery voltage when discharged, but not less than 0.9V/cell since less than 0.9V/cell invokes precharge current levels. Thermal Considerations Internal overtemperature protection is provided to prevent excessive LTC4060 die temperature during a fault condi- tion. If the internal die temperature exceeds approximately 145°C, charging stops and the part enters the shutdown state. The faults can be generated from insuffient heat sinking, a shorted DRIVE pin or from excessive DRIVE pin current to the base of an external PNP transistor if it’s in deep saturation from a very low V CE. Once in the shutdown state, charge qualification can be reinitiated only by re- moving and replacing the battery or toggling the SHDN pin low to high or removing and reapplying power to the charger. This protection is not designed to prevent over- heating of the PNP pass transistor. Indirectly though, self- heating of the PNP thermally conducting to the LTC4060 can result in the IC’s junction temperature rising above 145°C, thus cutting off the PNP’s base current. This action will limit the PNP’s junction temperature to some tempera- ture well above 145 °C. The user should insure that the maximum rated junction temperature is not exceeded under any normal operating condition. See Package/Order Information for the θ JA of the LTC4060 Exposed Pad packages. The actual thermal resistance in the application will vary depending on forced air cooling, use of the Exposed Pad and other heat sinking means, especially the amount of copper on the PCB to which the LTC4060 is attached. The majority of the power dissipated within the LTC4060 is in the current sense resitor and DRIVE pin driver as given below: P D = (IBAT)2 • 0.08 + IDRIVE (VCC – VEB) TJ = TA + θJA • PD VEB is the emitter to base voltage of the external PNP.

voltage falls below this automatic recharge will begin. BAT filters excessive contact bounce. C/2 rate simply by doubling the CTIMER capacitance.

4060 F02

4060 F03

Figure 2. Full Featured 2A Charger Application Figure 3. 1A Charger Application with Power Path Control

and the resistor sets the trickle current. Figure 5. Bond wire, lead frame and PCB interconnect for RISET = 0.16Ω and RPROG = 698Ω. require additional heat sinking.

4060 F04

4060 F05

Figure 4. Adding Trickle Charge Figure 5. Extended Charge Current Operation

as shown in Figure 6 can be used.

4060 F06

Figure 6. Low Loss Reverse Input Voltage Protection

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. UPACKAGE DESCRIPTIO 16-Lead Plastic DFN (5mm × 3mm) (Reference LTC DWG # 05-08-1706) 3.00 ±0.10 (2 SIDES) 5.00 ±0.10 (2 SIDES) NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.40 ± 0.10 BOTTOM VIEW—EXPOSED PAD 1.65 ± 0.10 (2 SIDES) 0.75 ±0.05 R = 0.115 TYP R = 0.20 TYP 4.40 ±0.10 (2 SIDES) 169 PIN 1 TOP MARK (SEE NOTE 6)

0.200 REF

0.00 – 0.05 (DHC16) DFN 1103 0.25 ± 0.05 PIN 1 NOTCH

0.50 BSC

4.40 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 1.65 ±0.05 (2 SIDES)2.20 ±0.05 0.65 ±0.05 3.50 ±0.05 PACKAGE OUTLINE 0.25 ± 0.05

© LINEAR TECHNOLOGY CORPORATION 2004 LT/TP 0904 1K • PRINTED IN THE USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com UPACKAGE DESCRIPTIO 16-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation BC FE16 (BC) TSSOP 0204 0.09 – 0.20 (.0035 – .0079) 0° – 8° 0.25 REF 0.50 – 0.75 (.020 – .030) 4.30 – 4.50* (.169 – .177) 13 4 5 6 7 8 10 9 4.90 – 5.10* (.193 – .201) 16 1514 13 12 11 1.10 (.0433) MAX 0.05 – 0.15 (.002 – .006) 0.65 (.0256) BSC 2.94 (.116) 0.195 – 0.30 (.0077 – .0118) TYP 2RECOMMENDED SOLDER PAD LAYOUT 0.45 ±0.05

0.65 BSC

4.50 ±0.10 6.60 ±0.10 1.05 ±0.10 2.94 (.116) 3.58 (.141) 3.58 (.141) MILLIMETERS (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE SEE NOTE 4 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT 6.40 (.252) BSC PART NUMBER DESCRIPTION COMMENTS LTC1732 Lithium-Ion Linear Battery Charger Controller Simple Charger uses External FET, Features Preset Voltages, C/10 Charger Detection and Programmable Timer, Input Power Good Indication LTC1733 Monolithic Lithium-Ion Linear Battery Charger Standalone Charger with Programmable Timer, Up to 1.5A Charge Current LTC1734 Lithium-Ion Linear Battery Charger in ThinSOT TM Simple ThinSOT Charger, No Blocking Diode, No Sense Resistor Needed LTC1734L Lithium-Ion Linear Battery Charger in ThinSOT Low Current Version of LTC1734; 50mA ≤ ICHRG ≤ 180mA LTC1998 Lithium-Ion Low Battery Detector 1% Accurate 2.5 µA Quiescent Current, SOT-23 LTC4006/LTC4007 4A Multicell Li-Ion Battery Chargers Standalone Charger, 6V ≤ VIN ≤ 28V, Up to 96% Efficiency, ±0.8% Charging Voltage Accuracy LTC4008 4A Multichemistry Battery Charger Synchronous Operation for High Efficiency, AC Adapter Current Limit LTC4052 Monolithic Lithium-Ion Battery Pulse Charger No Blocking Diode or External Power FET Required, ≤1.5A Charge Current LTC4053 USB Compatible Monolithic Li-Ion Battery Charger Standalone Charger with Programmable Timer, Up to 1.25A Charge Current LTC4054 Standalone Linear Li-Ion Battery Charger Thermal Regulation Prevents Overheating, C/10 Termination, in ThinSOT C/10 Indicator, Up to 800mA Charge Current LTC4055 USB Power Controller and Li-Ion Battery Charger Charges Directly from USB or Wall Adapter, New Topology Charges Faster an d More Efficiently LTC4058 Standalone Li-Ion Linear Charger in DFN Up to 950mA Charge Current, Kelvin Sense for High Accuracy, LTC4058X C/10 Charge Termination LTC4411 Low Loss PowerPath TM Controller in ThinSOT Automatic Switching Between DC Sources, Load Sharing, LTC4412 Replaces ORing Diodes ThinSOT and PowerPath are trademarks of Linear Technology Corporation. RELATED PARTS