UTC4052 UTC | Alldatasheet
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UTC UNISONIC TECHNOLOGIES CO., LTD. 1 QW-R502-013,A ANALOG MULTIPLEXERS /DEMULTIPLEXERS
DESCRIPTION
The UTC 4052 analog multiplexers is digitally –controlled analog switch. The device feature low ON impedance and very low OFF leakage current. Control of analog signals up to the complete supply voltage range can be achieved.
FEATURES
*Triple Diode Protection on Control Inputs *Switch Function is Break Before Make *Supply Voltage Range=3.0 Vdc to 18 Vdc *Analog Voltage Range(VDD-VEE)=3.0 to 18V *Note:VEE must be≤Vss *Linearized Transfer Characterisstics *Low-noise-12nV/√Cycle ,f ≥1.0kHz Typical DIP-16 SOP-16 ABSOLUTE MAXIMUM RATINGS*1 PARAMETER SYMBOL RATING UNIT DC Supply Voltage (Referenced to VEE,Vss≥VEE) VDD -0.5 ~ +18.0 V Input or Output Voltage (DC or Transient) (Referenced to Vss for Control Inputs and VEE for switch I/O) Vin,Vout -0.5 ~ V DD+0.5 V Input Current (DC or Transient) per Control Pin Iin ±10 mA Switch Through Current I SW ±25 mA Power Dissipation *2 D I P - 1 6 SOP-16 PD 700 500 mW Ambient Temperature Range T A -55 ~ +125 °C Storage Temperature Range Tstg -65 ~ +150 °C Lead Temperature (8-Second Soldering) T LEAD 260 °C *1. Maximum Ratings are those values beyond which damage to the device may occur. *2. Temperature Derating : 7.0 mW/℃ From 65 ℃ ~ 125 ℃
UTC UNISONIC TECHNOLOGIES CO., LTD. 2 QW-R502-013,A INHIBIT A B X Y Dual 4-Channel Analog Multiplexer/Demultiplexer CONTROLS SWITCHES IN/OUT COMMONS OUT/IN VDD=PIN16, VSS=PIN8, VEE=PIN7 Y INH VEE Vss 9
16 VDD
X A B PIN ASSIGMENT Note: Control Inputs referenced to Vss. Analog Inputs and Outputs reference to VEE. VEE must be <Vss.
ELECTRICAL CHARACTERISTICS
-55°C 25 °C 125 °C PARAMETER SYMBOL TEST CONDITIONS MIN MAX MIN TYP *3 MAX MIN MAX UNIT SUPPLY REQUIREMENTS (Voltages Referenced to VEE) Power Current Per Range VDD VDD-3.0≥Vss≥VEE 3.0 18 3.0 18 3.0 18 V Quiescent Current Per Package IDD Control Inputs: Vin=Vss or VDD,Switch I/O : VEE≤VI/O≤≤VDD, and△Vswitch≤500mV *4 VDD=5.0V VDD=10V VDD=15V 5.0 0.005 0.010 0.015 5.0 150 300 600 µA Total Supply Current (Dynamic Plus Quiescent, Per Package ID(AV) TA=25℃only (The channel component, (Vin-Vout) /Ron, is not included.) VDD=5.0V VDD=10V VDD=15V ( 0 . 0 7 µ A / k H z ) f + IDD Typical (0.20µA/kHz)f+I DD ( 0 . 3 6 µ A / k H z ) f + IDD µA CONTROL INPUTS-INHIBIT, A, B, C (Voltages Referenced to Vss) Low-Level Input Voltage VIL Ron=per spec, Ioff=per spec VDD=5.0V VDD=10V VDD=15V 1.5 3.0 4.0 2.25 4.50 6.75 1.5 3.0 4.0 1.5 3.0 4.0 V High-Level Input Voltage VIH Ron=per spec, Ioff=per spec VDD=5.0V VDD=10V VDD=15V 3.5 7.0 3.5 7.0 2.75 5.50 8.25 3.5 7.0 V
UTC UNISONIC TECHNOLOGIES CO., LTD. 3 QW-R502-013,A -55°C 25 °C 125 °C PARAMETER SYMBOL TEST CONDITIONS MIN MAX MIN TYP *3 MAX MIN MAX UNIT Input Leakage Current Iin VDD=15V ,Vin=0 or VDD ±0.1 ±10-5 ±0.1 1.0 µA Input Capacitance Cin 5.0 7.5 pF SWITCHES IN/OUT AND COMMONS OUT/IN –X,Y,Z(Voltages Referenced to VEE) Recommended Peak-to-Peak Voltage Into or Out of the Switch VI/O Channel On or Off 0 V DD 0 V DD 0 V DD Vpp Recommended Static or Dynamic Voltage Across the Switch * (Figure 3) △Vswitch Channel On 0 600 0 600 0 300 mV Output Offset Voltage Voo Vin=0V,No Load 10 µV ON Resistance Ron △Vswitch≤500mV *4 Vin=VIL or VIH (Control), and Vin=0 to VDD(Switch) VDD=5.0V VDD=10V VDD=15V 800 400 220 250 120 1050 500 280 1200 520 300 Ω △ON Resistance Between Any Two Channels in the Same Package △Ron VDD=5.0V VDD=10V VDD=15V 135 65 Ω Off-Channel Leakage Current(Figure 8) Ioff VDD=15V ,Vin=VIL or VIH (Control) Channel to Channel or Any One Channel ±100 ±0.05 ±100 ±1000 nA Capacitance, Switch I/O CI/O Inhibit=V DD 10 pF Capacitance, Common O/I CO/I Inhibit=V DD 32 pF Capacitance, Feedthrough (Channel Off) C I/O Pins Not Adjacent Pins Adjacent 0.15 0.47 p F *3. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential *performance. *4. For voltage drops across the switch (△Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD *current may be drawn, i.e. the current out of the switch may contain both V DD and switch input components. The *reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data *sheet.)
UTC UNISONIC TECHNOLOGIES CO., LTD. 4 QW-R502-013,A ELECTRICAL CHARACTERISTICS *5 (CL = 50 pF, TA = 25℃) (VEE ≤VSS unless otherwise indicated) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Propagation Delay Times(Figure 4) Switch Input to Switch Output t PLH,tPHL RL=10kΩ VDD-VEE= 5.0, tPLH,tPHL=(0.17 ns/pF) CL+21.5 ns VDD-VEE=10, tPLH,tPHL=(0.08 ns/pF) CL+8.0 ns VDD-VEE=15, tPLH,tPHL=(0.06 ns/pF) CL+7.0 ns ns Propagation Delay Times(Figure 4) Inhibit to Output t PHZ,tPLZ tPZH,tPZL RL=10kΩ,VEE=Vss Output”1” or “0” to High Impedance, or High Impedance to”1” or “0” Level VDD-VEE= 5.0 VDD-VEE=10 VDD-VEE=15 300 155 125 600 310 250 ns Propagation Delay Times(Figure 4) Control Input to Output tPLN,tPHL RL=10kΩ,VEE=Vss VDD-VEE= 5.0 VDD-VEE=10 VDD-VEE=15 325 130 650 260 180 ns Second Harmonic Distortion RL=10kΩ, f=1kHz, Vin=5Vpp, VDD-VEE=10 0.07 % Bandwidth (Figure 5) BW RL=1kΩ, Vin=1/2(VDD-VEE)p-p, CL=50pF,
20 Log (Vout/Vin)=-3dB, VDD-VEE=10
17 MHz
(Figure 5) R L=1kΩ, Vin=1/2(VDD-VEE)p-p, Fin=30MHz, VDD-VEE=10 -50 dB Channel Separation (Figure 6) RL=1kΩ, Vin=1/2(V DD-VEE)p-p, fin=3.0MHz, VDD-VEE=10 -50 dB Crosstalk ,Control Input to Common O/I (Figure R1=1kΩ, R L=10kΩ, Control tTLH=tTHL=20ns ,Inhibit=Vss), VDD-VEE=10 mV *5. The formulas given are for the typical characteristics only at 25 ℃. *6. Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential *performance.
1 XX None
Figure 2. Functional Diagram
16 V DD
UTC UNISONIC TECHNOLOGIES CO., LTD. 8 QW-R502-013,A 700 300 500 600 -10 Vin,INPUT VOLTAGE (VOLTS) RON,"ON" RESISTANCE (OHMS) -8.0 0 0.2 6.04.0 400 100 200 Figure12.VDD=2.5V,VEE=-2.5V TA=125℃ 25℃ -55℃ 350 150 250 300 -10 Vin, INPUT VOLTAGE (VOLTS) -8.0 0 0.2 6.04.0 200 100 Figure13 Comparison at 25℃,VDD=-VEE TA=25℃ RON,"ON" RESISTANCE (OHMS) VDD=2.5V 5.0V 7.5V Figure A illustrates use of the on–chip level converter detailed in Figures 2. The 0 ~ 5 V Digital Control signal is used to directly control a 9 Vp–p analog signal. The digital control logic levels are determined by VDD and VSS. The VDD voltage is the logic high voltage; the VSS voltage is logic low. For the example, VDD = + 5 V = logic high at the control inputs; VSS = GND = 0 V = logic low. The maximum analog signal level is determined by VDD and VEE. The VDD voltage determines the maximum recommended peak above VSS. The VEE voltage determines the maximum swing below VSS. For the example, VDD – VSS = 5 V maximum swing above VSS; VSS – VEE = 5 V maximum swing below VSS. The example shows a ± 4.5 V signal which allows a 1/2 volt margin at each peak. If voltage transients above V DD and/or below VEE are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure B. These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping. The absolute maximum potential difference between VDD and VEE is 18.0 V. Most parameters are specified up to 15 V which is the recommended maximum difference between VDD and VEE. Balanced supplies are not required. However, VSS must be greater than or equal to VEE. For example, VDD = + 10 V, VSS = + 5 V, and VEE – 3 V is acceptable. See the Table below. EXTERNAL CMOS DIGITAL CIRCUITRY 0 ~ 5V DIGITAL CONTROL SIGNALS ANALOG SIGNAL
9 Vp-p SWITCH
INHIBIT, A,B,C COMMON O/I VDD Vss VEE +5V -5V ANALOG SIGNAL
9 Vp-p
-4.5V +4.5V GND +5V Figure A. Application Example 4052
UTC UNISONIC TECHNOLOGIES CO., LTD. 9 QW-R502-013,A VDD Dx Dx VEE VDD Dx Dx VEE ANALOG I/O COMMON O/I Figure B.External Germanium or Schottky Clipping Diodes POSSIBLE SUPPLY CONNECTIONS VDD IN VOLTS VSS IN VOLTS VEE IN VOITS CONTROL INPUTS LOGIC HIGH/LOGIC LOW IN VOLTS MAXIMUM ANALOG SIGNAL RANGE IN VOLTS