4042B

HEF4042B PHILIPS | Alldatasheet

Document overview

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Technical content

Product specification File under Integrated Circuits, IC04 January 1995 INTEGRATED CIRCUITS HEF4042B MSI Quadruple D-latch For a complete data sheet, please also download:

• The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

Philips Semiconductors Product specification Quadruple D-latch HEF4042B MSI

DESCRIPTION

The HEF4042B is a 4-bit latch with four data inputs (D0 to D 3), four buffered latch outputs (O0 to O3), four buffered complementary latch outputs (O 0 toO 3) and two common enable inputs (E0 and E1). Information on D0 to D3 is transferred to O0 to O3 while both E0 and E1 are in the same state, either HIGH or LOW. O0 to O3 follow D0 to D 3 as long as both E0 and E1 remain in the same state. When E 0 and E1 are different, D0 to D3 do not affect O0 to O 3 and the information in the latch is stored. O 0 toO 3 are always the complement of O0 to O3. The exclusive-OR input structure allows the choice of either polarity for E 0 and E1. With one enable input HIGH, the other enable input is active HIGH; with one enable input LOW, the other enable input is active LOW. Fig.1 Functional diagram. PINNING

APPLICATION INFORMATION

Some examples of applications for the HEF4042B are:

• Buffer storage
• Holding register FAMILY DATA, IDD LIMITS category MSI See Family Specifications HEF4042BP(N): 16-lead DIL; plastic (SOT38-1) HEF4042BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4042BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America D 0 to D3 data inputs E0 and E1 enable inputs O 0 to O3 parallel latch outputs O 0 toO 3 complementary parallel latch outputs Fig.2 Pinning diagram.

Philips Semiconductors Product specification Quadruple D-latch HEF4042B MSI Fig.3 Logic diagram. Fig.4 Logic diagram (one latch). FUNCTION TABLE Note 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage). E0 E1 OUTPUT O n LL D n L H latched H L latched HH D n

Philips Semiconductors Product specification Quadruple D-latch HEF4042B MSI AC CHARACTERISTICS VSS = 0 V; Tamb =2 5°C; CL = 50 pF; input transition times≤ 20 ns VDD V SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA Propagation delays D → O, O 5 95 190 ns 67 ns + (0,55 ns/pF) CL HIGH to LOW 10 t PHL 40 80 ns 28 ns + (0,23 ns/pF) CL 15 30 55 ns 22 ns + (0,16 ns/pF) CL 5 85 175 ns 57 ns + (0,55 ns/pF) CL LOW to HIGH 10 t PLH 40 75 ns 28 ns + (0,23 ns/pF) CL 15 30 60 ns 22 ns + (0,16 ns/pF) CL E → O, O 5 130 260 ns 102 ns + (0,55 ns/pF) CL HIGH to LOW 10 t PHL 50 105 ns 38 ns + (0,23 ns/pF) CL 15 35 75 ns 27 ns + (0,16 ns/pF) CL 5 120 245 ns 92 ns + (0,55 ns/pF) CL LOW to HIGH 10 t PLH 50 105 ns 38 ns + (0,23 ns/pF) CL 15 35 75 ns 27 ns + (0,16 ns/pF) CL Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) CL HIGH to LOW 10 t THL 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL 5 60 120 ns 10 ns + (1,0 ns/pF) CL LOW to HIGH 10 t TLH 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL Set-up time 5 30 10 ns see also waveforms Figs 5 and 6 D → E1 0 t su 20 5 ns 15 20 5 ns Hold time 5 15 −5n s D → E1 0 t hold 15 0 ns 15 15 0 ns Minimum enable 5 90 45 ns pulse width 10 t WE 40 20 ns 15 30 15 ns VDD V TYPICAL FORMULA FOR P (W) Dynamic power 5 3800 f i+∑ (foC L)× VDD 2 where dissipation per 10 15 700 f i+∑ (foC L)× VDD 2 fi= input freq. (MHz) package (P) 15 41 100 f i+∑ (foC L)× VDD 2 fo = output freq. (MHz) C L = load capacitance (pF) ∑ (foC L) = sum of outputs VDD = supply voltage (V)

Philips Semiconductors Product specification Quadruple D-latch HEF4042B MSI Fig.5 Waveforms showing propagation delays for D to O, with latch enabled. Either E0 or E1 is held HIGH or LOW while the other enable input is pulsed as the function table shows.

Philips Semiconductors Product specification Quadruple D-latch HEF4042B MSI Fig.6 Waveforms showing minimum enable pulse width, set-up time and hold time for E and D. Set-up and hold-times are shown as positive values but may be specified as negative values.